arch/arm/mach-omap2/prm3xxx.c

   1 /*
   2  * OMAP3xxx PRM module functions
   3  *
   4  * Copyright (C) 2010-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2010 Nokia Corporation
   6  * Benoît Cousson
   7  * Paul Walmsley
   8  * Rajendra Nayak <rnayak@ti.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/errno.h>
  17 #include <linux/err.h>
  18 #include <linux/io.h>
  19 #include <linux/irq.h>
  20 #include <linux/of_irq.h>
  21
  22 #include "soc.h"
  23 #include "common.h"
  24 #include "vp.h"
  25 #include "powerdomain.h"
  26 #include "prm3xxx.h"
  27 #include "prm2xxx_3xxx.h"
  28 #include "cm2xxx_3xxx.h"
  29 #include "prm-regbits-34xx.h"
  30 #include "cm3xxx.h"
  31 #include "cm-regbits-34xx.h"
  32
  33 static const struct omap_prcm_irq omap3_prcm_irqs[] = {
  34         OMAP_PRCM_IRQ("wkup",   0,      0),
  35         OMAP_PRCM_IRQ("io",     9,      1),
  36 };
  37
  38 static struct omap_prcm_irq_setup omap3_prcm_irq_setup = {
  39         .ack                    = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
  40         .mask                   = OMAP3_PRM_IRQENABLE_MPU_OFFSET,
  41         .nr_regs                = 1,
  42         .irqs                   = omap3_prcm_irqs,
  43         .nr_irqs                = ARRAY_SIZE(omap3_prcm_irqs),
  44         .irq                    = 11 + OMAP_INTC_START,
  45         .read_pending_irqs      = &omap3xxx_prm_read_pending_irqs,
  46         .ocp_barrier            = &omap3xxx_prm_ocp_barrier,
  47         .save_and_clear_irqen   = &omap3xxx_prm_save_and_clear_irqen,
  48         .restore_irqen          = &omap3xxx_prm_restore_irqen,
  49         .reconfigure_io_chain   = NULL,
  50 };
  51
  52 /*
  53  * omap3_prm_reset_src_map - map from bits in the PRM_RSTST hardware
  54  *   register (which are specific to OMAP3xxx SoCs) to reset source ID
  55  *   bit shifts (which is an OMAP SoC-independent enumeration)
  56  */
  57 static struct prm_reset_src_map omap3xxx_prm_reset_src_map[] = {
  58         { OMAP3430_GLOBAL_COLD_RST_SHIFT, OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT },
  59         { OMAP3430_GLOBAL_SW_RST_SHIFT, OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT },
  60         { OMAP3430_SECURITY_VIOL_RST_SHIFT, OMAP_SECU_VIOL_RST_SRC_ID_SHIFT },
  61         { OMAP3430_MPU_WD_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT },
  62         { OMAP3430_SECURE_WD_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT },
  63         { OMAP3430_EXTERNAL_WARM_RST_SHIFT, OMAP_EXTWARM_RST_SRC_ID_SHIFT },
  64         { OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT,
  65           OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT },
  66         { OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT,
  67           OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT },
  68         { OMAP3430_ICEPICK_RST_SHIFT, OMAP_ICEPICK_RST_SRC_ID_SHIFT },
  69         { OMAP3430_ICECRUSHER_RST_SHIFT, OMAP_ICECRUSHER_RST_SRC_ID_SHIFT },
  70         { -1, -1 },
  71 };
  72
  73 /* PRM VP */
  74
  75 /*
  76  * struct omap3_vp - OMAP3 VP register access description.
  77  * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
  78  */
  79 struct omap3_vp {
  80         u32 tranxdone_status;
  81 };
  82
  83 static struct omap3_vp omap3_vp[] = {
  84         [OMAP3_VP_VDD_MPU_ID] = {
  85                 .tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK,
  86         },
  87         [OMAP3_VP_VDD_CORE_ID] = {
  88                 .tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK,
  89         },
  90 };
  91
  92 #define MAX_VP_ID ARRAY_SIZE(omap3_vp);
  93
  94 u32 omap3_prm_vp_check_txdone(u8 vp_id)
  95 {
  96         struct omap3_vp *vp = &omap3_vp[vp_id];
  97         u32 irqstatus;
  98
  99         irqstatus = omap2_prm_read_mod_reg(OCP_MOD,
 100                                            OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 101         return irqstatus & vp->tranxdone_status;
 102 }
 103
 104 void omap3_prm_vp_clear_txdone(u8 vp_id)
 105 {
 106         struct omap3_vp *vp = &omap3_vp[vp_id];
 107
 108         omap2_prm_write_mod_reg(vp->tranxdone_status,
 109                                 OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 110 }
 111
 112 u32 omap3_prm_vcvp_read(u8 offset)
 113 {
 114         return omap2_prm_read_mod_reg(OMAP3430_GR_MOD, offset);
 115 }
 116
 117 void omap3_prm_vcvp_write(u32 val, u8 offset)
 118 {
 119         omap2_prm_write_mod_reg(val, OMAP3430_GR_MOD, offset);
 120 }
 121
 122 u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
 123 {
 124         return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset);
 125 }
 126
 127 /**
 128  * omap3xxx_prm_dpll3_reset - use DPLL3 reset to reboot the OMAP SoC
 129  *
 130  * Set the DPLL3 reset bit, which should reboot the SoC.  This is the
 131  * recommended way to restart the SoC, considering Errata i520.  No
 132  * return value.
 133  */
 134 void omap3xxx_prm_dpll3_reset(void)
 135 {
 136         omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, OMAP3430_GR_MOD,
 137                                    OMAP2_RM_RSTCTRL);
 138         /* OCP barrier */
 139         omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP2_RM_RSTCTRL);
 140 }
 141
 142 /**
 143  * omap3xxx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
 144  * @events: ptr to a u32, preallocated by caller
 145  *
 146  * Read PRM_IRQSTATUS_MPU bits, AND'ed with the currently-enabled PRM
 147  * MPU IRQs, and store the result into the u32 pointed to by @events.
 148  * No return value.
 149  */
 150 void omap3xxx_prm_read_pending_irqs(unsigned long *events)
 151 {
 152         u32 mask, st;
 153
 154         /* XXX Can the mask read be avoided (e.g., can it come from RAM?) */
 155         mask = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 156         st = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 157
 158         events[0] = mask & st;
 159 }
 160
 161 /**
 162  * omap3xxx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
 163  *
 164  * Force any buffered writes to the PRM IP block to complete.  Needed
 165  * by the PRM IRQ handler, which reads and writes directly to the IP
 166  * block, to avoid race conditions after acknowledging or clearing IRQ
 167  * bits.  No return value.
 168  */
 169 void omap3xxx_prm_ocp_barrier(void)
 170 {
 171         omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
 172 }
 173
 174 /**
 175  * omap3xxx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU reg
 176  * @saved_mask: ptr to a u32 array to save IRQENABLE bits
 177  *
 178  * Save the PRM_IRQENABLE_MPU register to @saved_mask.  @saved_mask
 179  * must be allocated by the caller.  Intended to be used in the PRM
 180  * interrupt handler suspend callback.  The OCP barrier is needed to
 181  * ensure the write to disable PRM interrupts reaches the PRM before
 182  * returning; otherwise, spurious interrupts might occur.  No return
 183  * value.
 184  */
 185 void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask)
 186 {
 187         saved_mask[0] = omap2_prm_read_mod_reg(OCP_MOD,
 188                                                OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 189         omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 190
 191         /* OCP barrier */
 192         omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
 193 }
 194
 195 /**
 196  * omap3xxx_prm_restore_irqen - set PRM_IRQENABLE_MPU register from args
 197  * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
 198  *
 199  * Restore the PRM_IRQENABLE_MPU register from @saved_mask.  Intended
 200  * to be used in the PRM interrupt handler resume callback to restore
 201  * values saved by omap3xxx_prm_save_and_clear_irqen().  No OCP
 202  * barrier should be needed here; any pending PRM interrupts will fire
 203  * once the writes reach the PRM.  No return value.
 204  */
 205 void omap3xxx_prm_restore_irqen(u32 *saved_mask)
 206 {
 207         omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD,
 208                                 OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 209 }
 210
 211 /**
 212  * omap3xxx_prm_clear_mod_irqs - clear wake-up events from PRCM interrupt
 213  * @module: PRM module to clear wakeups from
 214  * @regs: register set to clear, 1 or 3
 215  * @ignore_bits: wakeup status bits to ignore
 216  *
 217  * The purpose of this function is to clear any wake-up events latched
 218  * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
 219  * may occur whilst attempting to clear a PM_WKST_x register and thus
 220  * set another bit in this register. A while loop is used to ensure
 221  * that any peripheral wake-up events occurring while attempting to
 222  * clear the PM_WKST_x are detected and cleared.
 223  */
 224 int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
 225 {
 226         u32 wkst, fclk, iclk, clken;
 227         u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
 228         u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
 229         u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
 230         u16 grpsel_off = (regs == 3) ?
 231                 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
 232         int c = 0;
 233
 234         wkst = omap2_prm_read_mod_reg(module, wkst_off);
 235         wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
 236         wkst &= ~ignore_bits;
 237         if (wkst) {
 238                 iclk = omap2_cm_read_mod_reg(module, iclk_off);
 239                 fclk = omap2_cm_read_mod_reg(module, fclk_off);
 240                 while (wkst) {
 241                         clken = wkst;
 242                         omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
 243                         /*
 244                          * For USBHOST, we don't know whether HOST1 or
 245                          * HOST2 woke us up, so enable both f-clocks
 246                          */
 247                         if (module == OMAP3430ES2_USBHOST_MOD)
 248                                 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
 249                         omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
 250                         omap2_prm_write_mod_reg(wkst, module, wkst_off);
 251                         wkst = omap2_prm_read_mod_reg(module, wkst_off);
 252                         wkst &= ~ignore_bits;
 253                         c++;
 254                 }
 255                 omap2_cm_write_mod_reg(iclk, module, iclk_off);
 256                 omap2_cm_write_mod_reg(fclk, module, fclk_off);
 257         }
 258
 259         return c;
 260 }
 261
 262 /**
 263  * omap3_prm_reset_modem - toggle reset signal for modem
 264  *
 265  * Toggles the reset signal to modem IP block. Required to allow
 266  * OMAP3430 without stacked modem to idle properly.
 267  */
 268 void __init omap3_prm_reset_modem(void)
 269 {
 270         omap2_prm_write_mod_reg(
 271                 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
 272                 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
 273                                 CORE_MOD, OMAP2_RM_RSTCTRL);
 274         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
 275 }
 276
 277 /**
 278  * omap3_prm_init_pm - initialize PM related registers for PRM
 279  * @has_uart4: SoC has UART4
 280  * @has_iva: SoC has IVA
 281  *
 282  * Initializes PRM registers for PM use. Called from PM init.
 283  */
 284 void __init omap3_prm_init_pm(bool has_uart4, bool has_iva)
 285 {
 286         u32 en_uart4_mask;
 287         u32 grpsel_uart4_mask;
 288
 289         /*
 290          * Enable control of expternal oscillator through
 291          * sys_clkreq. In the long run clock framework should
 292          * take care of this.
 293          */
 294         omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
 295                                    1 << OMAP_AUTOEXTCLKMODE_SHIFT,
 296                                    OMAP3430_GR_MOD,
 297                                    OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 298
 299         /* setup wakup source */
 300         omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
 301                                 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
 302                                 WKUP_MOD, PM_WKEN);
 303         /* No need to write EN_IO, that is always enabled */
 304         omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
 305                                 OMAP3430_GRPSEL_GPT1_MASK |
 306                                 OMAP3430_GRPSEL_GPT12_MASK,
 307                                 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
 308
 309         /* Enable PM_WKEN to support DSS LPR */
 310         omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
 311                                 OMAP3430_DSS_MOD, PM_WKEN);
 312
 313         if (has_uart4) {
 314                 en_uart4_mask = OMAP3630_EN_UART4_MASK;
 315                 grpsel_uart4_mask = OMAP3630_GRPSEL_UART4_MASK;
 316         }
 317
 318         /* Enable wakeups in PER */
 319         omap2_prm_write_mod_reg(en_uart4_mask |
 320                                 OMAP3430_EN_GPIO2_MASK |
 321                                 OMAP3430_EN_GPIO3_MASK |
 322                                 OMAP3430_EN_GPIO4_MASK |
 323                                 OMAP3430_EN_GPIO5_MASK |
 324                                 OMAP3430_EN_GPIO6_MASK |
 325                                 OMAP3430_EN_UART3_MASK |
 326                                 OMAP3430_EN_MCBSP2_MASK |
 327                                 OMAP3430_EN_MCBSP3_MASK |
 328                                 OMAP3430_EN_MCBSP4_MASK,
 329                                 OMAP3430_PER_MOD, PM_WKEN);
 330
 331         /* and allow them to wake up MPU */
 332         omap2_prm_write_mod_reg(grpsel_uart4_mask |
 333                                 OMAP3430_GRPSEL_GPIO2_MASK |
 334                                 OMAP3430_GRPSEL_GPIO3_MASK |
 335                                 OMAP3430_GRPSEL_GPIO4_MASK |
 336                                 OMAP3430_GRPSEL_GPIO5_MASK |
 337                                 OMAP3430_GRPSEL_GPIO6_MASK |
 338                                 OMAP3430_GRPSEL_UART3_MASK |
 339                                 OMAP3430_GRPSEL_MCBSP2_MASK |
 340                                 OMAP3430_GRPSEL_MCBSP3_MASK |
 341                                 OMAP3430_GRPSEL_MCBSP4_MASK,
 342                                 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 343
 344         /* Don't attach IVA interrupts */
 345         if (has_iva) {
 346                 omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 347                 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 348                 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 349                 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD,
 350                                         OMAP3430_PM_IVAGRPSEL);
 351         }
 352
 353         /* Clear any pending 'reset' flags */
 354         omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
 355         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
 356         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
 357         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
 358         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
 359         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
 360         omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD,
 361                                 OMAP2_RM_RSTST);
 362
 363         /* Clear any pending PRCM interrupts */
 364         omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 365
 366         /* We need to idle iva2_pwrdm even on am3703 with no iva2. */
 367         omap3xxx_prm_iva_idle();
 368
 369         omap3_prm_reset_modem();
 370 }
 371
 372 /**
 373  * omap3430_pre_es3_1_reconfigure_io_chain - restart wake-up daisy chain
 374  *
 375  * The ST_IO_CHAIN bit does not exist in 3430 before es3.1. The only
 376  * thing we can do is toggle EN_IO bit for earlier omaps.
 377  */
 378 void omap3430_pre_es3_1_reconfigure_io_chain(void)
 379 {
 380         omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
 381                                      PM_WKEN);
 382         omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
 383                                    PM_WKEN);
 384         omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 385 }
 386
 387 /**
 388  * omap3_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
 389  *
 390  * Clear any previously-latched I/O wakeup events and ensure that the
 391  * I/O wakeup gates are aligned with the current mux settings.  Works
 392  * by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then
 393  * deasserting WUCLKIN and clearing the ST_IO_CHAIN WKST bit.  No
 394  * return value. These registers are only available in 3430 es3.1 and later.
 395  */
 396 void omap3_prm_reconfigure_io_chain(void)
 397 {
 398         int i = 0;
 399
 400         omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
 401                                    PM_WKEN);
 402
 403         omap_test_timeout(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) &
 404                           OMAP3430_ST_IO_CHAIN_MASK,
 405                           MAX_IOPAD_LATCH_TIME, i);
 406         if (i == MAX_IOPAD_LATCH_TIME)
 407                 pr_warn("PRM: I/O chain clock line assertion timed out\n");
 408
 409         omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
 410                                      PM_WKEN);
 411
 412         omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, WKUP_MOD,
 413                                    PM_WKST);
 414
 415         omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST);
 416 }
 417
 418 /**
 419  * omap3xxx_prm_reconfigure_io_chain - reconfigure I/O chain
 420  */
 421 void omap3xxx_prm_reconfigure_io_chain(void)
 422 {
 423         if (omap3_prcm_irq_setup.reconfigure_io_chain)
 424                 omap3_prcm_irq_setup.reconfigure_io_chain();
 425 }
 426
 427 /**
 428  * omap3xxx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches
 429  *
 430  * Activates the I/O wakeup event latches and allows events logged by
 431  * those latches to signal a wakeup event to the PRCM.  For I/O
 432  * wakeups to occur, WAKEUPENABLE bits must be set in the pad mux
 433  * registers, and omap3xxx_prm_reconfigure_io_chain() must be called.
 434  * No return value.
 435  */
 436 static void __init omap3xxx_prm_enable_io_wakeup(void)
 437 {
 438         if (prm_features & PRM_HAS_IO_WAKEUP)
 439                 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
 440                                            PM_WKEN);
 441 }
 442
 443 /**
 444  * omap3xxx_prm_read_reset_sources - return the last SoC reset source
 445  *
 446  * Return a u32 representing the last reset sources of the SoC.  The
 447  * returned reset source bits are standardized across OMAP SoCs.
 448  */
 449 static u32 omap3xxx_prm_read_reset_sources(void)
 450 {
 451         struct prm_reset_src_map *p;
 452         u32 r = 0;
 453         u32 v;
 454
 455         v = omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST);
 456
 457         p = omap3xxx_prm_reset_src_map;
 458         while (p->reg_shift >= 0 && p->std_shift >= 0) {
 459                 if (v & (1 << p->reg_shift))
 460                         r |= 1 << p->std_shift;
 461                 p++;
 462         }
 463
 464         return r;
 465 }
 466
 467 /**
 468  * omap3xxx_prm_iva_idle - ensure IVA is in idle so it can be put into retention
 469  *
 470  * In cases where IVA2 is activated by bootcode, it may prevent
 471  * full-chip retention or off-mode because it is not idle.  This
 472  * function forces the IVA2 into idle state so it can go
 473  * into retention/off and thus allow full-chip retention/off.
 474  */
 475 void omap3xxx_prm_iva_idle(void)
 476 {
 477         /* ensure IVA2 clock is disabled */
 478         omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 479
 480         /* if no clock activity, nothing else to do */
 481         if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
 482               OMAP3430_CLKACTIVITY_IVA2_MASK))
 483                 return;
 484
 485         /* Reset IVA2 */
 486         omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 487                                 OMAP3430_RST2_IVA2_MASK |
 488                                 OMAP3430_RST3_IVA2_MASK,
 489                                 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 490
 491         /* Enable IVA2 clock */
 492         omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
 493                                OMAP3430_IVA2_MOD, CM_FCLKEN);
 494
 495         /* Un-reset IVA2 */
 496         omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 497
 498         /* Disable IVA2 clock */
 499         omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 500
 501         /* Reset IVA2 */
 502         omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 503                                 OMAP3430_RST2_IVA2_MASK |
 504                                 OMAP3430_RST3_IVA2_MASK,
 505                                 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 506 }
 507
 508 /**
 509  * omap3xxx_prm_clear_global_cold_reset - checks the global cold reset status
 510  *                                        and clears it if asserted
 511  *
 512  * Checks if cold-reset has occurred and clears the status bit if yes. Returns
 513  * 1 if cold-reset has occurred, 0 otherwise.
 514  */
 515 int omap3xxx_prm_clear_global_cold_reset(void)
 516 {
 517         if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
 518             OMAP3430_GLOBAL_COLD_RST_MASK) {
 519                 omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
 520                                            OMAP3430_GR_MOD,
 521                                            OMAP3_PRM_RSTST_OFFSET);
 522                 return 1;
 523         }
 524
 525         return 0;
 526 }
 527
 528 void omap3_prm_save_scratchpad_contents(u32 *ptr)
 529 {
 530         *ptr++ = omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
 531                                         OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 532
 533         *ptr++ = omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
 534                                         OMAP3_PRM_CLKSEL_OFFSET);
 535 }
 536
 537 /* Powerdomain low-level functions */
 538
 539 static int omap3_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
 540 {
 541         omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
 542                                    (pwrst << OMAP_POWERSTATE_SHIFT),
 543                                    pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
 544         return 0;
 545 }
 546
 547 static int omap3_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
 548 {
 549         return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
 550                                              OMAP2_PM_PWSTCTRL,
 551                                              OMAP_POWERSTATE_MASK);
 552 }
 553
 554 static int omap3_pwrdm_read_pwrst(struct powerdomain *pwrdm)
 555 {
 556         return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
 557                                              OMAP2_PM_PWSTST,
 558                                              OMAP_POWERSTATEST_MASK);
 559 }
 560
 561 /* Applicable only for OMAP3. Not supported on OMAP2 */
 562 static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
 563 {
 564         return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
 565                                              OMAP3430_PM_PREPWSTST,
 566                                              OMAP3430_LASTPOWERSTATEENTERED_MASK);
 567 }
 568
 569 static int omap3_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
 570 {
 571         return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
 572                                              OMAP2_PM_PWSTST,
 573                                              OMAP3430_LOGICSTATEST_MASK);
 574 }
 575
 576 static int omap3_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
 577 {
 578         return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
 579                                              OMAP2_PM_PWSTCTRL,
 580                                              OMAP3430_LOGICSTATEST_MASK);
 581 }
 582
 583 static int omap3_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
 584 {
 585         return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
 586                                              OMAP3430_PM_PREPWSTST,
 587                                              OMAP3430_LASTLOGICSTATEENTERED_MASK);
 588 }
 589
 590 static int omap3_get_mem_bank_lastmemst_mask(u8 bank)
 591 {
 592         switch (bank) {
 593         case 0:
 594                 return OMAP3430_LASTMEM1STATEENTERED_MASK;
 595         case 1:
 596                 return OMAP3430_LASTMEM2STATEENTERED_MASK;
 597         case 2:
 598                 return OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK;
 599         case 3:
 600                 return OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK;
 601         default:
 602                 WARN_ON(1); /* should never happen */
 603                 return -EEXIST;
 604         }
 605         return 0;
 606 }
 607
 608 static int omap3_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
 609 {
 610         u32 m;
 611
 612         m = omap3_get_mem_bank_lastmemst_mask(bank);
 613
 614         return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
 615                                 OMAP3430_PM_PREPWSTST, m);
 616 }
 617
 618 static int omap3_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
 619 {
 620         omap2_prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST);
 621         return 0;
 622 }
 623
 624 static int omap3_pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
 625 {
 626         return omap2_prm_rmw_mod_reg_bits(0,
 627                                           1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
 628                                           pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
 629 }
 630
 631 static int omap3_pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
 632 {
 633         return omap2_prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
 634                                           0, pwrdm->prcm_offs,
 635                                           OMAP2_PM_PWSTCTRL);
 636 }
 637
 638 struct pwrdm_ops omap3_pwrdm_operations = {
 639         .pwrdm_set_next_pwrst   = omap3_pwrdm_set_next_pwrst,
 640         .pwrdm_read_next_pwrst  = omap3_pwrdm_read_next_pwrst,
 641         .pwrdm_read_pwrst       = omap3_pwrdm_read_pwrst,
 642         .pwrdm_read_prev_pwrst  = omap3_pwrdm_read_prev_pwrst,
 643         .pwrdm_set_logic_retst  = omap2_pwrdm_set_logic_retst,
 644         .pwrdm_read_logic_pwrst = omap3_pwrdm_read_logic_pwrst,
 645         .pwrdm_read_logic_retst = omap3_pwrdm_read_logic_retst,
 646         .pwrdm_read_prev_logic_pwrst    = omap3_pwrdm_read_prev_logic_pwrst,
 647         .pwrdm_set_mem_onst     = omap2_pwrdm_set_mem_onst,
 648         .pwrdm_set_mem_retst    = omap2_pwrdm_set_mem_retst,
 649         .pwrdm_read_mem_pwrst   = omap2_pwrdm_read_mem_pwrst,
 650         .pwrdm_read_mem_retst   = omap2_pwrdm_read_mem_retst,
 651         .pwrdm_read_prev_mem_pwrst      = omap3_pwrdm_read_prev_mem_pwrst,
 652         .pwrdm_clear_all_prev_pwrst     = omap3_pwrdm_clear_all_prev_pwrst,
 653         .pwrdm_enable_hdwr_sar  = omap3_pwrdm_enable_hdwr_sar,
 654         .pwrdm_disable_hdwr_sar = omap3_pwrdm_disable_hdwr_sar,
 655         .pwrdm_wait_transition  = omap2_pwrdm_wait_transition,
 656 };
 657
 658 /*
 659  *
 660  */
 661
 662 static int omap3xxx_prm_late_init(void);
 663
 664 static struct prm_ll_data omap3xxx_prm_ll_data = {
 665         .read_reset_sources = &omap3xxx_prm_read_reset_sources,
 666         .late_init = &omap3xxx_prm_late_init,
 667 };
 668
 669 int __init omap3xxx_prm_init(void)
 670 {
 671         if (omap3_has_io_wakeup())
 672                 prm_features |= PRM_HAS_IO_WAKEUP;
 673
 674         return prm_register(&omap3xxx_prm_ll_data);
 675 }
 676
 677 static struct of_device_id omap3_prm_dt_match_table[] = {
 678         { .compatible = "ti,omap3-prm" },
 679         { }
 680 };
 681
 682 static int omap3xxx_prm_late_init(void)
 683 {
 684         int ret;
 685
 686         if (!(prm_features & PRM_HAS_IO_WAKEUP))
 687                 return 0;
 688
 689         if (omap3_has_io_chain_ctrl())
 690                 omap3_prcm_irq_setup.reconfigure_io_chain =
 691                         omap3_prm_reconfigure_io_chain;
 692         else
 693                 omap3_prcm_irq_setup.reconfigure_io_chain =
 694                         omap3430_pre_es3_1_reconfigure_io_chain;
 695
 696         if (of_have_populated_dt()) {
 697                 struct device_node *np;
 698                 int irq_num;
 699
 700                 np = of_find_matching_node(NULL, omap3_prm_dt_match_table);
 701                 if (np) {
 702                         irq_num = of_irq_get(np, 0);
 703                         if (irq_num >= 0)
 704                                 omap3_prcm_irq_setup.irq = irq_num;
 705                 }
 706         }
 707
 708         omap3xxx_prm_enable_io_wakeup();
 709         ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
 710         if (!ret)
 711                 irq_set_status_flags(omap_prcm_event_to_irq("io"),
 712                                      IRQ_NOAUTOEN);
 713
 714         return ret;
 715 }
 716
 717 static void __exit omap3xxx_prm_exit(void)
 718 {
 719         prm_unregister(&omap3xxx_prm_ll_data);
 720 }
 721 __exitcall(omap3xxx_prm_exit);