arch/arm/mach-omap2/prcm.c

   1 /*
   2  * linux/arch/arm/mach-omap2/prcm.c
   3  *
   4  * OMAP 24xx Power Reset and Clock Management (PRCM) functions
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  *
   8  * Written by Tony Lindgren <tony.lindgren@nokia.com>
   9  *
  10  * Copyright (C) 2007 Texas Instruments, Inc.
  11  * Rajendra Nayak <rnayak@ti.com>
  12  *
  13  * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/clk.h>
  22 #include <linux/io.h>
  23 #include <linux/delay.h>
  24
  25 #include <plat/common.h>
  26 #include <plat/prcm.h>
  27 #include <plat/irqs.h>
  28 #include <plat/control.h>
  29
  30 #include "clock.h"
  31 #include "cm.h"
  32 #include "prm.h"
  33 #include "prm-regbits-24xx.h"
  34
  35 static void __iomem *prm_base;
  36 static void __iomem *cm_base;
  37 static void __iomem *cm2_base;
  38
  39 #define MAX_MODULE_ENABLE_WAIT          100000
  40
  41 struct omap3_prcm_regs {
  42         u32 control_padconf_sys_nirq;
  43         u32 iva2_cm_clksel1;
  44         u32 iva2_cm_clksel2;
  45         u32 cm_sysconfig;
  46         u32 sgx_cm_clksel;
  47         u32 dss_cm_clksel;
  48         u32 cam_cm_clksel;
  49         u32 per_cm_clksel;
  50         u32 emu_cm_clksel;
  51         u32 emu_cm_clkstctrl;
  52         u32 pll_cm_autoidle2;
  53         u32 pll_cm_clksel4;
  54         u32 pll_cm_clksel5;
  55         u32 pll_cm_clken2;
  56         u32 cm_polctrl;
  57         u32 iva2_cm_fclken;
  58         u32 iva2_cm_clken_pll;
  59         u32 core_cm_fclken1;
  60         u32 core_cm_fclken3;
  61         u32 sgx_cm_fclken;
  62         u32 wkup_cm_fclken;
  63         u32 dss_cm_fclken;
  64         u32 cam_cm_fclken;
  65         u32 per_cm_fclken;
  66         u32 usbhost_cm_fclken;
  67         u32 core_cm_iclken1;
  68         u32 core_cm_iclken2;
  69         u32 core_cm_iclken3;
  70         u32 sgx_cm_iclken;
  71         u32 wkup_cm_iclken;
  72         u32 dss_cm_iclken;
  73         u32 cam_cm_iclken;
  74         u32 per_cm_iclken;
  75         u32 usbhost_cm_iclken;
  76         u32 iva2_cm_autiidle2;
  77         u32 mpu_cm_autoidle2;
  78         u32 iva2_cm_clkstctrl;
  79         u32 mpu_cm_clkstctrl;
  80         u32 core_cm_clkstctrl;
  81         u32 sgx_cm_clkstctrl;
  82         u32 dss_cm_clkstctrl;
  83         u32 cam_cm_clkstctrl;
  84         u32 per_cm_clkstctrl;
  85         u32 neon_cm_clkstctrl;
  86         u32 usbhost_cm_clkstctrl;
  87         u32 core_cm_autoidle1;
  88         u32 core_cm_autoidle2;
  89         u32 core_cm_autoidle3;
  90         u32 wkup_cm_autoidle;
  91         u32 dss_cm_autoidle;
  92         u32 cam_cm_autoidle;
  93         u32 per_cm_autoidle;
  94         u32 usbhost_cm_autoidle;
  95         u32 sgx_cm_sleepdep;
  96         u32 dss_cm_sleepdep;
  97         u32 cam_cm_sleepdep;
  98         u32 per_cm_sleepdep;
  99         u32 usbhost_cm_sleepdep;
 100         u32 cm_clkout_ctrl;
 101         u32 prm_clkout_ctrl;
 102         u32 sgx_pm_wkdep;
 103         u32 dss_pm_wkdep;
 104         u32 cam_pm_wkdep;
 105         u32 per_pm_wkdep;
 106         u32 neon_pm_wkdep;
 107         u32 usbhost_pm_wkdep;
 108         u32 core_pm_mpugrpsel1;
 109         u32 iva2_pm_ivagrpsel1;
 110         u32 core_pm_mpugrpsel3;
 111         u32 core_pm_ivagrpsel3;
 112         u32 wkup_pm_mpugrpsel;
 113         u32 wkup_pm_ivagrpsel;
 114         u32 per_pm_mpugrpsel;
 115         u32 per_pm_ivagrpsel;
 116         u32 wkup_pm_wken;
 117 };
 118
 119 struct omap3_prcm_regs prcm_context;
 120
 121 u32 omap_prcm_get_reset_sources(void)
 122 {
 123         /* XXX This presumably needs modification for 34XX */
 124         return prm_read_mod_reg(WKUP_MOD, RM_RSTST) & 0x7f;
 125 }
 126 EXPORT_SYMBOL(omap_prcm_get_reset_sources);
 127
 128 /* Resets clock rates and reboots the system. Only called from system.h */
 129 void omap_prcm_arch_reset(char mode)
 130 {
 131         s16 prcm_offs;
 132         omap2_clk_prepare_for_reboot();
 133
 134         if (cpu_is_omap24xx())
 135                 prcm_offs = WKUP_MOD;
 136         else if (cpu_is_omap34xx()) {
 137                 u32 l;
 138
 139                 prcm_offs = OMAP3430_GR_MOD;
 140                 l = ('B' << 24) | ('M' << 16) | mode;
 141                 /* Reserve the first word in scratchpad for communicating
 142                  * with the boot ROM. A pointer to a data structure
 143                  * describing the boot process can be stored there,
 144                  * cf. OMAP34xx TRM, Initialization / Software Booting
 145                  * Configuration. */
 146                 omap_writel(l, OMAP343X_SCRATCHPAD + 4);
 147         } else
 148                 WARN_ON(1);
 149
 150         prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, RM_RSTCTRL);
 151 }
 152
 153 static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg)
 154 {
 155         BUG_ON(!base);
 156         return __raw_readl(base + module + reg);
 157 }
 158
 159 static inline void __omap_prcm_write(u32 value, void __iomem *base,
 160                                                 s16 module, u16 reg)
 161 {
 162         BUG_ON(!base);
 163         __raw_writel(value, base + module + reg);
 164 }
 165
 166 /* Read a register in a PRM module */
 167 u32 prm_read_mod_reg(s16 module, u16 idx)
 168 {
 169         return __omap_prcm_read(prm_base, module, idx);
 170 }
 171
 172 /* Write into a register in a PRM module */
 173 void prm_write_mod_reg(u32 val, s16 module, u16 idx)
 174 {
 175         __omap_prcm_write(val, prm_base, module, idx);
 176 }
 177
 178 /* Read-modify-write a register in a PRM module. Caller must lock */
 179 u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
 180 {
 181         u32 v;
 182
 183         v = prm_read_mod_reg(module, idx);
 184         v &= ~mask;
 185         v |= bits;
 186         prm_write_mod_reg(v, module, idx);
 187
 188         return v;
 189 }
 190
 191 /* Read a register in a CM module */
 192 u32 cm_read_mod_reg(s16 module, u16 idx)
 193 {
 194         return __omap_prcm_read(cm_base, module, idx);
 195 }
 196
 197 /* Write into a register in a CM module */
 198 void cm_write_mod_reg(u32 val, s16 module, u16 idx)
 199 {
 200         __omap_prcm_write(val, cm_base, module, idx);
 201 }
 202
 203 /* Read-modify-write a register in a CM module. Caller must lock */
 204 u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
 205 {
 206         u32 v;
 207
 208         v = cm_read_mod_reg(module, idx);
 209         v &= ~mask;
 210         v |= bits;
 211         cm_write_mod_reg(v, module, idx);
 212
 213         return v;
 214 }
 215
 216 /**
 217  * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
 218  * @reg: physical address of module IDLEST register
 219  * @mask: value to mask against to determine if the module is active
 220  * @name: name of the clock (for printk)
 221  *
 222  * Returns 1 if the module indicated readiness in time, or 0 if it
 223  * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
 224  */
 225 int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name)
 226 {
 227         int i = 0;
 228         int ena = 0;
 229
 230         /*
 231          * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
 232          * 34xx reverses this, just to keep us on our toes
 233          */
 234         if (cpu_is_omap24xx())
 235                 ena = mask;
 236         else if (cpu_is_omap34xx())
 237                 ena = 0;
 238         else
 239                 BUG();
 240
 241         /* Wait for lock */
 242         omap_test_timeout(((__raw_readl(reg) & mask) == ena),
 243                           MAX_MODULE_ENABLE_WAIT, i);
 244
 245         if (i < MAX_MODULE_ENABLE_WAIT)
 246                 pr_debug("cm: Module associated with clock %s ready after %d "
 247                          "loops\n", name, i);
 248         else
 249                 pr_err("cm: Module associated with clock %s didn't enable in "
 250                        "%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
 251
 252         return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
 253 };
 254
 255 void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
 256 {
 257         prm_base = omap2_globals->prm;
 258         cm_base = omap2_globals->cm;
 259         cm2_base = omap2_globals->cm2;
 260 }
 261
 262 #ifdef CONFIG_ARCH_OMAP3
 263 void omap3_prcm_save_context(void)
 264 {
 265         prcm_context.control_padconf_sys_nirq =
 266                          omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
 267         prcm_context.iva2_cm_clksel1 =
 268                          cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
 269         prcm_context.iva2_cm_clksel2 =
 270                          cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
 271         prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
 272         prcm_context.sgx_cm_clksel =
 273                          cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
 274         prcm_context.dss_cm_clksel =
 275                          cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
 276         prcm_context.cam_cm_clksel =
 277                          cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
 278         prcm_context.per_cm_clksel =
 279                          cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
 280         prcm_context.emu_cm_clksel =
 281                          cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
 282         prcm_context.emu_cm_clkstctrl =
 283                          cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSTCTRL);
 284         prcm_context.pll_cm_autoidle2 =
 285                          cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
 286         prcm_context.pll_cm_clksel4 =
 287                         cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
 288         prcm_context.pll_cm_clksel5 =
 289                          cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
 290         prcm_context.pll_cm_clken2 =
 291                         cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
 292         prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
 293         prcm_context.iva2_cm_fclken =
 294                          cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
 295         prcm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD,
 296                         OMAP3430_CM_CLKEN_PLL);
 297         prcm_context.core_cm_fclken1 =
 298                          cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 299         prcm_context.core_cm_fclken3 =
 300                          cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
 301         prcm_context.sgx_cm_fclken =
 302                          cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
 303         prcm_context.wkup_cm_fclken =
 304                          cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
 305         prcm_context.dss_cm_fclken =
 306                          cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
 307         prcm_context.cam_cm_fclken =
 308                          cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
 309         prcm_context.per_cm_fclken =
 310                          cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
 311         prcm_context.usbhost_cm_fclken =
 312                          cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
 313         prcm_context.core_cm_iclken1 =
 314                          cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
 315         prcm_context.core_cm_iclken2 =
 316                          cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
 317         prcm_context.core_cm_iclken3 =
 318                          cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
 319         prcm_context.sgx_cm_iclken =
 320                          cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
 321         prcm_context.wkup_cm_iclken =
 322                          cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
 323         prcm_context.dss_cm_iclken =
 324                          cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
 325         prcm_context.cam_cm_iclken =
 326                          cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
 327         prcm_context.per_cm_iclken =
 328                          cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
 329         prcm_context.usbhost_cm_iclken =
 330                          cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
 331         prcm_context.iva2_cm_autiidle2 =
 332                          cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
 333         prcm_context.mpu_cm_autoidle2 =
 334                          cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
 335         prcm_context.iva2_cm_clkstctrl =
 336                          cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSTCTRL);
 337         prcm_context.mpu_cm_clkstctrl =
 338                          cm_read_mod_reg(MPU_MOD, CM_CLKSTCTRL);
 339         prcm_context.core_cm_clkstctrl =
 340                          cm_read_mod_reg(CORE_MOD, CM_CLKSTCTRL);
 341         prcm_context.sgx_cm_clkstctrl =
 342                          cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSTCTRL);
 343         prcm_context.dss_cm_clkstctrl =
 344                          cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSTCTRL);
 345         prcm_context.cam_cm_clkstctrl =
 346                          cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSTCTRL);
 347         prcm_context.per_cm_clkstctrl =
 348                          cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSTCTRL);
 349         prcm_context.neon_cm_clkstctrl =
 350                          cm_read_mod_reg(OMAP3430_NEON_MOD, CM_CLKSTCTRL);
 351         prcm_context.usbhost_cm_clkstctrl =
 352                          cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL);
 353         prcm_context.core_cm_autoidle1 =
 354                          cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
 355         prcm_context.core_cm_autoidle2 =
 356                          cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
 357         prcm_context.core_cm_autoidle3 =
 358                          cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
 359         prcm_context.wkup_cm_autoidle =
 360                          cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
 361         prcm_context.dss_cm_autoidle =
 362                          cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
 363         prcm_context.cam_cm_autoidle =
 364                          cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
 365         prcm_context.per_cm_autoidle =
 366                          cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
 367         prcm_context.usbhost_cm_autoidle =
 368                          cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
 369         prcm_context.sgx_cm_sleepdep =
 370                  cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP3430_CM_SLEEPDEP);
 371         prcm_context.dss_cm_sleepdep =
 372                  cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
 373         prcm_context.cam_cm_sleepdep =
 374                  cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
 375         prcm_context.per_cm_sleepdep =
 376                  cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
 377         prcm_context.usbhost_cm_sleepdep =
 378                  cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
 379         prcm_context.cm_clkout_ctrl = cm_read_mod_reg(OMAP3430_CCR_MOD,
 380                  OMAP3_CM_CLKOUT_CTRL_OFFSET);
 381         prcm_context.prm_clkout_ctrl = prm_read_mod_reg(OMAP3430_CCR_MOD,
 382                 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
 383         prcm_context.sgx_pm_wkdep =
 384                  prm_read_mod_reg(OMAP3430ES2_SGX_MOD, PM_WKDEP);
 385         prcm_context.dss_pm_wkdep =
 386                  prm_read_mod_reg(OMAP3430_DSS_MOD, PM_WKDEP);
 387         prcm_context.cam_pm_wkdep =
 388                  prm_read_mod_reg(OMAP3430_CAM_MOD, PM_WKDEP);
 389         prcm_context.per_pm_wkdep =
 390                  prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKDEP);
 391         prcm_context.neon_pm_wkdep =
 392                  prm_read_mod_reg(OMAP3430_NEON_MOD, PM_WKDEP);
 393         prcm_context.usbhost_pm_wkdep =
 394                  prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
 395         prcm_context.core_pm_mpugrpsel1 =
 396                  prm_read_mod_reg(CORE_MOD, OMAP3430_PM_MPUGRPSEL1);
 397         prcm_context.iva2_pm_ivagrpsel1 =
 398                  prm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_PM_IVAGRPSEL1);
 399         prcm_context.core_pm_mpugrpsel3 =
 400                  prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_MPUGRPSEL3);
 401         prcm_context.core_pm_ivagrpsel3 =
 402                  prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 403         prcm_context.wkup_pm_mpugrpsel =
 404                  prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
 405         prcm_context.wkup_pm_ivagrpsel =
 406                  prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 407         prcm_context.per_pm_mpugrpsel =
 408                  prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 409         prcm_context.per_pm_ivagrpsel =
 410                  prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 411         prcm_context.wkup_pm_wken = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 412         return;
 413 }
 414
 415 void omap3_prcm_restore_context(void)
 416 {
 417         omap_ctrl_writel(prcm_context.control_padconf_sys_nirq,
 418                                          OMAP343X_CONTROL_PADCONF_SYSNIRQ);
 419         cm_write_mod_reg(prcm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
 420                                          CM_CLKSEL1);
 421         cm_write_mod_reg(prcm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
 422                                          CM_CLKSEL2);
 423         __raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
 424         cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
 425                                          CM_CLKSEL);
 426         cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
 427                                          CM_CLKSEL);
 428         cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
 429                                          CM_CLKSEL);
 430         cm_write_mod_reg(prcm_context.per_cm_clksel, OMAP3430_PER_MOD,
 431                                          CM_CLKSEL);
 432         cm_write_mod_reg(prcm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
 433                                          CM_CLKSEL1);
 434         cm_write_mod_reg(prcm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
 435                                          CM_CLKSTCTRL);
 436         cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD,
 437                                          CM_AUTOIDLE2);
 438         cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD,
 439                                         OMAP3430ES2_CM_CLKSEL4);
 440         cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD,
 441                                          OMAP3430ES2_CM_CLKSEL5);
 442         cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD,
 443                                         OMAP3430ES2_CM_CLKEN2);
 444         __raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
 445         cm_write_mod_reg(prcm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
 446                                          CM_FCLKEN);
 447         cm_write_mod_reg(prcm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
 448                                         OMAP3430_CM_CLKEN_PLL);
 449         cm_write_mod_reg(prcm_context.core_cm_fclken1, CORE_MOD, CM_FCLKEN1);
 450         cm_write_mod_reg(prcm_context.core_cm_fclken3, CORE_MOD,
 451                                          OMAP3430ES2_CM_FCLKEN3);
 452         cm_write_mod_reg(prcm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
 453                                          CM_FCLKEN);
 454         cm_write_mod_reg(prcm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
 455         cm_write_mod_reg(prcm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
 456                                          CM_FCLKEN);
 457         cm_write_mod_reg(prcm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
 458                                          CM_FCLKEN);
 459         cm_write_mod_reg(prcm_context.per_cm_fclken, OMAP3430_PER_MOD,
 460                                          CM_FCLKEN);
 461         cm_write_mod_reg(prcm_context.usbhost_cm_fclken,
 462                                          OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
 463         cm_write_mod_reg(prcm_context.core_cm_iclken1, CORE_MOD, CM_ICLKEN1);
 464         cm_write_mod_reg(prcm_context.core_cm_iclken2, CORE_MOD, CM_ICLKEN2);
 465         cm_write_mod_reg(prcm_context.core_cm_iclken3, CORE_MOD, CM_ICLKEN3);
 466         cm_write_mod_reg(prcm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
 467                                         CM_ICLKEN);
 468         cm_write_mod_reg(prcm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
 469         cm_write_mod_reg(prcm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
 470                                         CM_ICLKEN);
 471         cm_write_mod_reg(prcm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
 472                                         CM_ICLKEN);
 473         cm_write_mod_reg(prcm_context.per_cm_iclken, OMAP3430_PER_MOD,
 474                                         CM_ICLKEN);
 475         cm_write_mod_reg(prcm_context.usbhost_cm_iclken,
 476                                         OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
 477         cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD,
 478                                         CM_AUTOIDLE2);
 479         cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2);
 480         cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
 481                                         CM_CLKSTCTRL);
 482         cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD, CM_CLKSTCTRL);
 483         cm_write_mod_reg(prcm_context.core_cm_clkstctrl, CORE_MOD,
 484                                         CM_CLKSTCTRL);
 485         cm_write_mod_reg(prcm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
 486                                         CM_CLKSTCTRL);
 487         cm_write_mod_reg(prcm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
 488                                         CM_CLKSTCTRL);
 489         cm_write_mod_reg(prcm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
 490                                         CM_CLKSTCTRL);
 491         cm_write_mod_reg(prcm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
 492                                         CM_CLKSTCTRL);
 493         cm_write_mod_reg(prcm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
 494                                         CM_CLKSTCTRL);
 495         cm_write_mod_reg(prcm_context.usbhost_cm_clkstctrl,
 496                                         OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL);
 497         cm_write_mod_reg(prcm_context.core_cm_autoidle1, CORE_MOD,
 498                                         CM_AUTOIDLE1);
 499         cm_write_mod_reg(prcm_context.core_cm_autoidle2, CORE_MOD,
 500                                         CM_AUTOIDLE2);
 501         cm_write_mod_reg(prcm_context.core_cm_autoidle3, CORE_MOD,
 502                                         CM_AUTOIDLE3);
 503         cm_write_mod_reg(prcm_context.wkup_cm_autoidle, WKUP_MOD, CM_AUTOIDLE);
 504         cm_write_mod_reg(prcm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
 505                                         CM_AUTOIDLE);
 506         cm_write_mod_reg(prcm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
 507                                         CM_AUTOIDLE);
 508         cm_write_mod_reg(prcm_context.per_cm_autoidle, OMAP3430_PER_MOD,
 509                                         CM_AUTOIDLE);
 510         cm_write_mod_reg(prcm_context.usbhost_cm_autoidle,
 511                                         OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
 512         cm_write_mod_reg(prcm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
 513                                         OMAP3430_CM_SLEEPDEP);
 514         cm_write_mod_reg(prcm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
 515                                         OMAP3430_CM_SLEEPDEP);
 516         cm_write_mod_reg(prcm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
 517                                         OMAP3430_CM_SLEEPDEP);
 518         cm_write_mod_reg(prcm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
 519                                         OMAP3430_CM_SLEEPDEP);
 520         cm_write_mod_reg(prcm_context.usbhost_cm_sleepdep,
 521                                 OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
 522         cm_write_mod_reg(prcm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
 523                                         OMAP3_CM_CLKOUT_CTRL_OFFSET);
 524         prm_write_mod_reg(prcm_context.prm_clkout_ctrl, OMAP3430_CCR_MOD,
 525                                         OMAP3_PRM_CLKOUT_CTRL_OFFSET);
 526         prm_write_mod_reg(prcm_context.sgx_pm_wkdep, OMAP3430ES2_SGX_MOD,
 527                                         PM_WKDEP);
 528         prm_write_mod_reg(prcm_context.dss_pm_wkdep, OMAP3430_DSS_MOD,
 529                                         PM_WKDEP);
 530         prm_write_mod_reg(prcm_context.cam_pm_wkdep, OMAP3430_CAM_MOD,
 531                                         PM_WKDEP);
 532         prm_write_mod_reg(prcm_context.per_pm_wkdep, OMAP3430_PER_MOD,
 533                                         PM_WKDEP);
 534         prm_write_mod_reg(prcm_context.neon_pm_wkdep, OMAP3430_NEON_MOD,
 535                                         PM_WKDEP);
 536         prm_write_mod_reg(prcm_context.usbhost_pm_wkdep,
 537                                         OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
 538         prm_write_mod_reg(prcm_context.core_pm_mpugrpsel1, CORE_MOD,
 539                                         OMAP3430_PM_MPUGRPSEL1);
 540         prm_write_mod_reg(prcm_context.iva2_pm_ivagrpsel1, OMAP3430_IVA2_MOD,
 541                                         OMAP3430_PM_IVAGRPSEL1);
 542         prm_write_mod_reg(prcm_context.core_pm_mpugrpsel3, CORE_MOD,
 543                                         OMAP3430ES2_PM_MPUGRPSEL3);
 544         prm_write_mod_reg(prcm_context.core_pm_ivagrpsel3, CORE_MOD,
 545                                         OMAP3430ES2_PM_IVAGRPSEL3);
 546         prm_write_mod_reg(prcm_context.wkup_pm_mpugrpsel, WKUP_MOD,
 547                                         OMAP3430_PM_MPUGRPSEL);
 548         prm_write_mod_reg(prcm_context.wkup_pm_ivagrpsel, WKUP_MOD,
 549                                         OMAP3430_PM_IVAGRPSEL);
 550         prm_write_mod_reg(prcm_context.per_pm_mpugrpsel, OMAP3430_PER_MOD,
 551                                         OMAP3430_PM_MPUGRPSEL);
 552         prm_write_mod_reg(prcm_context.per_pm_ivagrpsel, OMAP3430_PER_MOD,
 553                                          OMAP3430_PM_IVAGRPSEL);
 554         prm_write_mod_reg(prcm_context.wkup_pm_wken, WKUP_MOD, PM_WKEN);
 555         return;
 556 }
 557 #endif