arch/arm/mach-omap2/pm34xx.c

   1 /*
   2  * OMAP3 Power Management Routines
   3  *
   4  * Copyright (C) 2006-2008 Nokia Corporation
   5  * Tony Lindgren <tony@atomide.com>
   6  * Jouni Hogander
   7  *
   8  * Copyright (C) 2007 Texas Instruments, Inc.
   9  * Rajendra Nayak <rnayak@ti.com>
  10  *
  11  * Copyright (C) 2005 Texas Instruments, Inc.
  12  * Richard Woodruff <r-woodruff2@ti.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/pm.h>
  22 #include <linux/suspend.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/module.h>
  25 #include <linux/list.h>
  26 #include <linux/err.h>
  27 #include <linux/gpio.h>
  28 #include <linux/clk.h>
  29 #include <linux/delay.h>
  30 #include <linux/slab.h>
  31 #include <linux/platform_data/gpio-omap.h>
  32
  33 #include <trace/events/power.h>
  34
  35 #include <asm/suspend.h>
  36 #include <asm/system_misc.h>
  37
  38 #include <plat/sram.h>
  39 #include "clockdomain.h"
  40 #include "powerdomain.h"
  41 #include <plat/sdrc.h>
  42 #include <plat/prcm.h>
  43 #include <plat/gpmc.h>
  44 #include <plat/dma.h>
  45
  46 #include "common.h"
  47 #include "cm2xxx_3xxx.h"
  48 #include "cm-regbits-34xx.h"
  49 #include "prm-regbits-34xx.h"
  50
  51 #include "prm2xxx_3xxx.h"
  52 #include "pm.h"
  53 #include "sdrc.h"
  54 #include "control.h"
  55
  56 /* pm34xx errata defined in pm.h */
  57 u16 pm34xx_errata;
  58
  59 struct power_state {
  60         struct powerdomain *pwrdm;
  61         u32 next_state;
  62 #ifdef CONFIG_SUSPEND
  63         u32 saved_state;
  64 #endif
  65         struct list_head node;
  66 };
  67
  68 static LIST_HEAD(pwrst_list);
  69
  70 static int (*_omap_save_secure_sram)(u32 *addr);
  71 void (*omap3_do_wfi_sram)(void);
  72
  73 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
  74 static struct powerdomain *core_pwrdm, *per_pwrdm;
  75
  76 static void omap3_core_save_context(void)
  77 {
  78         omap3_ctrl_save_padconf();
  79
  80         /*
  81          * Force write last pad into memory, as this can fail in some
  82          * cases according to errata 1.157, 1.185
  83          */
  84         omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
  85                 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
  86
  87         /* Save the Interrupt controller context */
  88         omap_intc_save_context();
  89         /* Save the GPMC context */
  90         omap3_gpmc_save_context();
  91         /* Save the system control module context, padconf already save above*/
  92         omap3_control_save_context();
  93         omap_dma_global_context_save();
  94 }
  95
  96 static void omap3_core_restore_context(void)
  97 {
  98         /* Restore the control module context, padconf restored by h/w */
  99         omap3_control_restore_context();
 100         /* Restore the GPMC context */
 101         omap3_gpmc_restore_context();
 102         /* Restore the interrupt controller context */
 103         omap_intc_restore_context();
 104         omap_dma_global_context_restore();
 105 }
 106
 107 /*
 108  * FIXME: This function should be called before entering off-mode after
 109  * OMAP3 secure services have been accessed. Currently it is only called
 110  * once during boot sequence, but this works as we are not using secure
 111  * services.
 112  */
 113 static void omap3_save_secure_ram_context(void)
 114 {
 115         u32 ret;
 116         int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 117
 118         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 119                 /*
 120                  * MPU next state must be set to POWER_ON temporarily,
 121                  * otherwise the WFI executed inside the ROM code
 122                  * will hang the system.
 123                  */
 124                 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
 125                 ret = _omap_save_secure_sram((u32 *)
 126                                 __pa(omap3_secure_ram_storage));
 127                 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
 128                 /* Following is for error tracking, it should not happen */
 129                 if (ret) {
 130                         pr_err("save_secure_sram() returns %08x\n", ret);
 131                         while (1)
 132                                 ;
 133                 }
 134         }
 135 }
 136
 137 /*
 138  * PRCM Interrupt Handler Helper Function
 139  *
 140  * The purpose of this function is to clear any wake-up events latched
 141  * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
 142  * may occur whilst attempting to clear a PM_WKST_x register and thus
 143  * set another bit in this register. A while loop is used to ensure
 144  * that any peripheral wake-up events occurring while attempting to
 145  * clear the PM_WKST_x are detected and cleared.
 146  */
 147 static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
 148 {
 149         u32 wkst, fclk, iclk, clken;
 150         u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
 151         u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
 152         u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
 153         u16 grpsel_off = (regs == 3) ?
 154                 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
 155         int c = 0;
 156
 157         wkst = omap2_prm_read_mod_reg(module, wkst_off);
 158         wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
 159         wkst &= ~ignore_bits;
 160         if (wkst) {
 161                 iclk = omap2_cm_read_mod_reg(module, iclk_off);
 162                 fclk = omap2_cm_read_mod_reg(module, fclk_off);
 163                 while (wkst) {
 164                         clken = wkst;
 165                         omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
 166                         /*
 167                          * For USBHOST, we don't know whether HOST1 or
 168                          * HOST2 woke us up, so enable both f-clocks
 169                          */
 170                         if (module == OMAP3430ES2_USBHOST_MOD)
 171                                 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
 172                         omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
 173                         omap2_prm_write_mod_reg(wkst, module, wkst_off);
 174                         wkst = omap2_prm_read_mod_reg(module, wkst_off);
 175                         wkst &= ~ignore_bits;
 176                         c++;
 177                 }
 178                 omap2_cm_write_mod_reg(iclk, module, iclk_off);
 179                 omap2_cm_write_mod_reg(fclk, module, fclk_off);
 180         }
 181
 182         return c;
 183 }
 184
 185 static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
 186 {
 187         int c;
 188
 189         c = prcm_clear_mod_irqs(WKUP_MOD, 1,
 190                 ~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK));
 191
 192         return c ? IRQ_HANDLED : IRQ_NONE;
 193 }
 194
 195 static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
 196 {
 197         int c;
 198
 199         /*
 200          * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
 201          * these are handled in a separate handler to avoid acking
 202          * IO events before parsing in mux code
 203          */
 204         c = prcm_clear_mod_irqs(WKUP_MOD, 1,
 205                 OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK);
 206         c += prcm_clear_mod_irqs(CORE_MOD, 1, 0);
 207         c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
 208         if (omap_rev() > OMAP3430_REV_ES1_0) {
 209                 c += prcm_clear_mod_irqs(CORE_MOD, 3, 0);
 210                 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
 211         }
 212
 213         return c ? IRQ_HANDLED : IRQ_NONE;
 214 }
 215
 216 static void omap34xx_save_context(u32 *save)
 217 {
 218         u32 val;
 219
 220         /* Read Auxiliary Control Register */
 221         asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
 222         *save++ = 1;
 223         *save++ = val;
 224
 225         /* Read L2 AUX ctrl register */
 226         asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
 227         *save++ = 1;
 228         *save++ = val;
 229 }
 230
 231 static int omap34xx_do_sram_idle(unsigned long save_state)
 232 {
 233         omap34xx_cpu_suspend(save_state);
 234         return 0;
 235 }
 236
 237 void omap_sram_idle(void)
 238 {
 239         /* Variable to tell what needs to be saved and restored
 240          * in omap_sram_idle*/
 241         /* save_state = 0 => Nothing to save and restored */
 242         /* save_state = 1 => Only L1 and logic lost */
 243         /* save_state = 2 => Only L2 lost */
 244         /* save_state = 3 => L1, L2 and logic lost */
 245         int save_state = 0;
 246         int mpu_next_state = PWRDM_POWER_ON;
 247         int per_next_state = PWRDM_POWER_ON;
 248         int core_next_state = PWRDM_POWER_ON;
 249         int per_going_off;
 250         int core_prev_state;
 251         u32 sdrc_pwr = 0;
 252
 253         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 254         switch (mpu_next_state) {
 255         case PWRDM_POWER_ON:
 256         case PWRDM_POWER_RET:
 257                 /* No need to save context */
 258                 save_state = 0;
 259                 break;
 260         case PWRDM_POWER_OFF:
 261                 save_state = 3;
 262                 break;
 263         default:
 264                 /* Invalid state */
 265                 pr_err("Invalid mpu state in sram_idle\n");
 266                 return;
 267         }
 268
 269         /* NEON control */
 270         if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
 271                 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
 272
 273         /* Enable IO-PAD and IO-CHAIN wakeups */
 274         per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
 275         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
 276
 277         pwrdm_pre_transition(NULL);
 278
 279         /* PER */
 280         if (per_next_state < PWRDM_POWER_ON) {
 281                 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
 282                 omap2_gpio_prepare_for_idle(per_going_off);
 283         }
 284
 285         /* CORE */
 286         if (core_next_state < PWRDM_POWER_ON) {
 287                 if (core_next_state == PWRDM_POWER_OFF) {
 288                         omap3_core_save_context();
 289                         omap3_cm_save_context();
 290                 }
 291         }
 292
 293         omap3_intc_prepare_idle();
 294
 295         /*
 296          * On EMU/HS devices ROM code restores a SRDC value
 297          * from scratchpad which has automatic self refresh on timeout
 298          * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
 299          * Hence store/restore the SDRC_POWER register here.
 300          */
 301         if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
 302             (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
 303              omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
 304             core_next_state == PWRDM_POWER_OFF)
 305                 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
 306
 307         /*
 308          * omap3_arm_context is the location where some ARM context
 309          * get saved. The rest is placed on the stack, and restored
 310          * from there before resuming.
 311          */
 312         if (save_state)
 313                 omap34xx_save_context(omap3_arm_context);
 314         if (save_state == 1 || save_state == 3)
 315                 cpu_suspend(save_state, omap34xx_do_sram_idle);
 316         else
 317                 omap34xx_do_sram_idle(save_state);
 318
 319         /* Restore normal SDRC POWER settings */
 320         if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
 321             (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
 322              omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
 323             core_next_state == PWRDM_POWER_OFF)
 324                 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
 325
 326         /* CORE */
 327         if (core_next_state < PWRDM_POWER_ON) {
 328                 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
 329                 if (core_prev_state == PWRDM_POWER_OFF) {
 330                         omap3_core_restore_context();
 331                         omap3_cm_restore_context();
 332                         omap3_sram_restore_context();
 333                         omap2_sms_restore_context();
 334                 }
 335                 if (core_next_state == PWRDM_POWER_OFF)
 336                         omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
 337                                                OMAP3430_GR_MOD,
 338                                                OMAP3_PRM_VOLTCTRL_OFFSET);
 339         }
 340         omap3_intc_resume_idle();
 341
 342         pwrdm_post_transition(NULL);
 343
 344         /* PER */
 345         if (per_next_state < PWRDM_POWER_ON)
 346                 omap2_gpio_resume_after_idle();
 347 }
 348
 349 static void omap3_pm_idle(void)
 350 {
 351         local_fiq_disable();
 352
 353         if (omap_irq_pending())
 354                 goto out;
 355
 356         trace_power_start(POWER_CSTATE, 1, smp_processor_id());
 357         trace_cpu_idle(1, smp_processor_id());
 358
 359         omap_sram_idle();
 360
 361         trace_power_end(smp_processor_id());
 362         trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
 363
 364 out:
 365         local_fiq_enable();
 366 }
 367
 368 #ifdef CONFIG_SUSPEND
 369 static int omap3_pm_suspend(void)
 370 {
 371         struct power_state *pwrst;
 372         int state, ret = 0;
 373
 374         /* Read current next_pwrsts */
 375         list_for_each_entry(pwrst, &pwrst_list, node)
 376                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
 377         /* Set ones wanted by suspend */
 378         list_for_each_entry(pwrst, &pwrst_list, node) {
 379                 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
 380                         goto restore;
 381                 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
 382                         goto restore;
 383         }
 384
 385         omap3_intc_suspend();
 386
 387         omap_sram_idle();
 388
 389 restore:
 390         /* Restore next_pwrsts */
 391         list_for_each_entry(pwrst, &pwrst_list, node) {
 392                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 393                 if (state > pwrst->next_state) {
 394                         pr_info("Powerdomain (%s) didn't enter target state %d\n",
 395                                 pwrst->pwrdm->name, pwrst->next_state);
 396                         ret = -1;
 397                 }
 398                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
 399         }
 400         if (ret)
 401                 pr_err("Could not enter target state in pm_suspend\n");
 402         else
 403                 pr_info("Successfully put all powerdomains to target state\n");
 404
 405         return ret;
 406 }
 407
 408 #endif /* CONFIG_SUSPEND */
 409
 410
 411 /**
 412  * omap3_iva_idle(): ensure IVA is in idle so it can be put into
 413  *                   retention
 414  *
 415  * In cases where IVA2 is activated by bootcode, it may prevent
 416  * full-chip retention or off-mode because it is not idle.  This
 417  * function forces the IVA2 into idle state so it can go
 418  * into retention/off and thus allow full-chip retention/off.
 419  *
 420  **/
 421 static void __init omap3_iva_idle(void)
 422 {
 423         /* ensure IVA2 clock is disabled */
 424         omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 425
 426         /* if no clock activity, nothing else to do */
 427         if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
 428               OMAP3430_CLKACTIVITY_IVA2_MASK))
 429                 return;
 430
 431         /* Reset IVA2 */
 432         omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 433                           OMAP3430_RST2_IVA2_MASK |
 434                           OMAP3430_RST3_IVA2_MASK,
 435                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 436
 437         /* Enable IVA2 clock */
 438         omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
 439                          OMAP3430_IVA2_MOD, CM_FCLKEN);
 440
 441         /* Set IVA2 boot mode to 'idle' */
 442         omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
 443                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 444
 445         /* Un-reset IVA2 */
 446         omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 447
 448         /* Disable IVA2 clock */
 449         omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 450
 451         /* Reset IVA2 */
 452         omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 453                           OMAP3430_RST2_IVA2_MASK |
 454                           OMAP3430_RST3_IVA2_MASK,
 455                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 456 }
 457
 458 static void __init omap3_d2d_idle(void)
 459 {
 460         u16 mask, padconf;
 461
 462         /* In a stand alone OMAP3430 where there is not a stacked
 463          * modem for the D2D Idle Ack and D2D MStandby must be pulled
 464          * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
 465          * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
 466         mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
 467         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
 468         padconf |= mask;
 469         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
 470
 471         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
 472         padconf |= mask;
 473         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
 474
 475         /* reset modem */
 476         omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
 477                           OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
 478                           CORE_MOD, OMAP2_RM_RSTCTRL);
 479         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
 480 }
 481
 482 static void __init prcm_setup_regs(void)
 483 {
 484         u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
 485                                         OMAP3630_EN_UART4_MASK : 0;
 486         u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
 487                                         OMAP3630_GRPSEL_UART4_MASK : 0;
 488
 489         /* XXX This should be handled by hwmod code or SCM init code */
 490         omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
 491
 492         /*
 493          * Enable control of expternal oscillator through
 494          * sys_clkreq. In the long run clock framework should
 495          * take care of this.
 496          */
 497         omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
 498                              1 << OMAP_AUTOEXTCLKMODE_SHIFT,
 499                              OMAP3430_GR_MOD,
 500                              OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 501
 502         /* setup wakup source */
 503         omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
 504                           OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
 505                           WKUP_MOD, PM_WKEN);
 506         /* No need to write EN_IO, that is always enabled */
 507         omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
 508                           OMAP3430_GRPSEL_GPT1_MASK |
 509                           OMAP3430_GRPSEL_GPT12_MASK,
 510                           WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
 511
 512         /* Enable PM_WKEN to support DSS LPR */
 513         omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
 514                                 OMAP3430_DSS_MOD, PM_WKEN);
 515
 516         /* Enable wakeups in PER */
 517         omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
 518                           OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
 519                           OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
 520                           OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
 521                           OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
 522                           OMAP3430_EN_MCBSP4_MASK,
 523                           OMAP3430_PER_MOD, PM_WKEN);
 524         /* and allow them to wake up MPU */
 525         omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
 526                           OMAP3430_GRPSEL_GPIO2_MASK |
 527                           OMAP3430_GRPSEL_GPIO3_MASK |
 528                           OMAP3430_GRPSEL_GPIO4_MASK |
 529                           OMAP3430_GRPSEL_GPIO5_MASK |
 530                           OMAP3430_GRPSEL_GPIO6_MASK |
 531                           OMAP3430_GRPSEL_UART3_MASK |
 532                           OMAP3430_GRPSEL_MCBSP2_MASK |
 533                           OMAP3430_GRPSEL_MCBSP3_MASK |
 534                           OMAP3430_GRPSEL_MCBSP4_MASK,
 535                           OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 536
 537         /* Don't attach IVA interrupts */
 538         if (omap3_has_iva()) {
 539                 omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 540                 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 541                 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 542                 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD,
 543                                         OMAP3430_PM_IVAGRPSEL);
 544         }
 545
 546         /* Clear any pending 'reset' flags */
 547         omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
 548         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
 549         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
 550         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
 551         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
 552         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
 553         omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
 554
 555         /* Clear any pending PRCM interrupts */
 556         omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 557
 558         if (omap3_has_iva())
 559                 omap3_iva_idle();
 560
 561         omap3_d2d_idle();
 562 }
 563
 564 void omap3_pm_off_mode_enable(int enable)
 565 {
 566         struct power_state *pwrst;
 567         u32 state;
 568
 569         if (enable)
 570                 state = PWRDM_POWER_OFF;
 571         else
 572                 state = PWRDM_POWER_RET;
 573
 574         list_for_each_entry(pwrst, &pwrst_list, node) {
 575                 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
 576                                 pwrst->pwrdm == core_pwrdm &&
 577                                 state == PWRDM_POWER_OFF) {
 578                         pwrst->next_state = PWRDM_POWER_RET;
 579                         pr_warn("%s: Core OFF disabled due to errata i583\n",
 580                                 __func__);
 581                 } else {
 582                         pwrst->next_state = state;
 583                 }
 584                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 585         }
 586 }
 587
 588 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
 589 {
 590         struct power_state *pwrst;
 591
 592         list_for_each_entry(pwrst, &pwrst_list, node) {
 593                 if (pwrst->pwrdm == pwrdm)
 594                         return pwrst->next_state;
 595         }
 596         return -EINVAL;
 597 }
 598
 599 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
 600 {
 601         struct power_state *pwrst;
 602
 603         list_for_each_entry(pwrst, &pwrst_list, node) {
 604                 if (pwrst->pwrdm == pwrdm) {
 605                         pwrst->next_state = state;
 606                         return 0;
 607                 }
 608         }
 609         return -EINVAL;
 610 }
 611
 612 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 613 {
 614         struct power_state *pwrst;
 615
 616         if (!pwrdm->pwrsts)
 617                 return 0;
 618
 619         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
 620         if (!pwrst)
 621                 return -ENOMEM;
 622         pwrst->pwrdm = pwrdm;
 623         pwrst->next_state = PWRDM_POWER_RET;
 624         list_add(&pwrst->node, &pwrst_list);
 625
 626         if (pwrdm_has_hdwr_sar(pwrdm))
 627                 pwrdm_enable_hdwr_sar(pwrdm);
 628
 629         return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 630 }
 631
 632 /*
 633  * Push functions to SRAM
 634  *
 635  * The minimum set of functions is pushed to SRAM for execution:
 636  * - omap3_do_wfi for erratum i581 WA,
 637  * - save_secure_ram_context for security extensions.
 638  */
 639 void omap_push_sram_idle(void)
 640 {
 641         omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
 642
 643         if (omap_type() != OMAP2_DEVICE_TYPE_GP)
 644                 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
 645                                 save_secure_ram_context_sz);
 646 }
 647
 648 static void __init pm_errata_configure(void)
 649 {
 650         if (cpu_is_omap3630()) {
 651                 pm34xx_errata |= PM_RTA_ERRATUM_i608;
 652                 /* Enable the l2 cache toggling in sleep logic */
 653                 enable_omap3630_toggle_l2_on_restore();
 654                 if (omap_rev() < OMAP3630_REV_ES1_2)
 655                         pm34xx_errata |= (PM_SDRC_WAKEUP_ERRATUM_i583 |
 656                                           PM_PER_MEMORIES_ERRATUM_i582);
 657         } else if (cpu_is_omap34xx()) {
 658                 pm34xx_errata |= PM_PER_MEMORIES_ERRATUM_i582;
 659         }
 660 }
 661
 662 int __init omap3_pm_init(void)
 663 {
 664         struct power_state *pwrst, *tmp;
 665         struct clockdomain *neon_clkdm, *mpu_clkdm, *per_clkdm, *wkup_clkdm;
 666         int ret;
 667
 668         if (!omap3_has_io_chain_ctrl())
 669                 pr_warning("PM: no software I/O chain control; some wakeups may be lost\n");
 670
 671         pm_errata_configure();
 672
 673         /* XXX prcm_setup_regs needs to be before enabling hw
 674          * supervised mode for powerdomains */
 675         prcm_setup_regs();
 676
 677         ret = request_irq(omap_prcm_event_to_irq("wkup"),
 678                 _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);
 679
 680         if (ret) {
 681                 pr_err("pm: Failed to request pm_wkup irq\n");
 682                 goto err1;
 683         }
 684
 685         /* IO interrupt is shared with mux code */
 686         ret = request_irq(omap_prcm_event_to_irq("io"),
 687                 _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
 688                 omap3_pm_init);
 689         enable_irq(omap_prcm_event_to_irq("io"));
 690
 691         if (ret) {
 692                 pr_err("pm: Failed to request pm_io irq\n");
 693                 goto err2;
 694         }
 695
 696         ret = pwrdm_for_each(pwrdms_setup, NULL);
 697         if (ret) {
 698                 pr_err("Failed to setup powerdomains\n");
 699                 goto err3;
 700         }
 701
 702         (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
 703
 704         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 705         if (mpu_pwrdm == NULL) {
 706                 pr_err("Failed to get mpu_pwrdm\n");
 707                 ret = -EINVAL;
 708                 goto err3;
 709         }
 710
 711         neon_pwrdm = pwrdm_lookup("neon_pwrdm");
 712         per_pwrdm = pwrdm_lookup("per_pwrdm");
 713         core_pwrdm = pwrdm_lookup("core_pwrdm");
 714
 715         neon_clkdm = clkdm_lookup("neon_clkdm");
 716         mpu_clkdm = clkdm_lookup("mpu_clkdm");
 717         per_clkdm = clkdm_lookup("per_clkdm");
 718         wkup_clkdm = clkdm_lookup("wkup_clkdm");
 719
 720 #ifdef CONFIG_SUSPEND
 721         omap_pm_suspend = omap3_pm_suspend;
 722 #endif
 723
 724         arm_pm_idle = omap3_pm_idle;
 725         omap3_idle_init();
 726
 727         /*
 728          * RTA is disabled during initialization as per erratum i608
 729          * it is safer to disable RTA by the bootloader, but we would like
 730          * to be doubly sure here and prevent any mishaps.
 731          */
 732         if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
 733                 omap3630_ctrl_disable_rta();
 734
 735         /*
 736          * The UART3/4 FIFO and the sidetone memory in McBSP2/3 are
 737          * not correctly reset when the PER powerdomain comes back
 738          * from OFF or OSWR when the CORE powerdomain is kept active.
 739          * See OMAP36xx Erratum i582 "PER Domain reset issue after
 740          * Domain-OFF/OSWR Wakeup".  This wakeup dependency is not a
 741          * complete workaround.  The kernel must also prevent the PER
 742          * powerdomain from going to OSWR/OFF while the CORE
 743          * powerdomain is not going to OSWR/OFF.  And if PER last
 744          * power state was off while CORE last power state was ON, the
 745          * UART3/4 and McBSP2/3 SIDETONE devices need to run a
 746          * self-test using their loopback tests; if that fails, those
 747          * devices are unusable until the PER/CORE can complete a transition
 748          * from ON to OSWR/OFF and then back to ON.
 749          *
 750          * XXX Technically this workaround is only needed if off-mode
 751          * or OSWR is enabled.
 752          */
 753         if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582))
 754                 clkdm_add_wkdep(per_clkdm, wkup_clkdm);
 755
 756         clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
 757         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 758                 omap3_secure_ram_storage =
 759                         kmalloc(0x803F, GFP_KERNEL);
 760                 if (!omap3_secure_ram_storage)
 761                         pr_err("Memory allocation failed when allocating for secure sram context\n");
 762
 763                 local_irq_disable();
 764                 local_fiq_disable();
 765
 766                 omap_dma_global_context_save();
 767                 omap3_save_secure_ram_context();
 768                 omap_dma_global_context_restore();
 769
 770                 local_irq_enable();
 771                 local_fiq_enable();
 772         }
 773
 774         omap3_save_scratchpad_contents();
 775         return ret;
 776
 777 err3:
 778         list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
 779                 list_del(&pwrst->node);
 780                 kfree(pwrst);
 781         }
 782         free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init);
 783 err2:
 784         free_irq(omap_prcm_event_to_irq("wkup"), NULL);
 785 err1:
 786         return ret;
 787 }