arch/arm/mach-omap2/pm34xx.c

   1 /*
   2  * OMAP3 Power Management Routines
   3  *
   4  * Copyright (C) 2006-2008 Nokia Corporation
   5  * Tony Lindgren <tony@atomide.com>
   6  * Jouni Hogander
   7  *
   8  * Copyright (C) 2007 Texas Instruments, Inc.
   9  * Rajendra Nayak <rnayak@ti.com>
  10  *
  11  * Copyright (C) 2005 Texas Instruments, Inc.
  12  * Richard Woodruff <r-woodruff2@ti.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/cpu_pm.h>
  22 #include <linux/pm.h>
  23 #include <linux/suspend.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/module.h>
  26 #include <linux/list.h>
  27 #include <linux/err.h>
  28 #include <linux/clk.h>
  29 #include <linux/delay.h>
  30 #include <linux/slab.h>
  31 #include <linux/omap-dma.h>
  32 #include <linux/omap-gpmc.h>
  33
  34 #include <trace/events/power.h>
  35
  36 #include <asm/fncpy.h>
  37 #include <asm/suspend.h>
  38 #include <asm/system_misc.h>
  39
  40 #include "clockdomain.h"
  41 #include "powerdomain.h"
  42 #include "soc.h"
  43 #include "common.h"
  44 #include "cm3xxx.h"
  45 #include "cm-regbits-34xx.h"
  46 #include "prm-regbits-34xx.h"
  47 #include "prm3xxx.h"
  48 #include "pm.h"
  49 #include "sdrc.h"
  50 #include "omap-secure.h"
  51 #include "sram.h"
  52 #include "control.h"
  53 #include "vc.h"
  54
  55 /* pm34xx errata defined in pm.h */
  56 u16 pm34xx_errata;
  57
  58 struct power_state {
  59         struct powerdomain *pwrdm;
  60         u32 next_state;
  61 #ifdef CONFIG_SUSPEND
  62         u32 saved_state;
  63 #endif
  64         struct list_head node;
  65 };
  66
  67 static LIST_HEAD(pwrst_list);
  68
  69 void (*omap3_do_wfi_sram)(void);
  70
  71 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
  72 static struct powerdomain *core_pwrdm, *per_pwrdm;
  73
  74 static void omap3_core_save_context(void)
  75 {
  76         omap3_ctrl_save_padconf();
  77
  78         /*
  79          * Force write last pad into memory, as this can fail in some
  80          * cases according to errata 1.157, 1.185
  81          */
  82         omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
  83                 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
  84
  85         /* Save the Interrupt controller context */
  86         omap_intc_save_context();
  87         /* Save the GPMC context */
  88         omap3_gpmc_save_context();
  89         /* Save the system control module context, padconf already save above*/
  90         omap3_control_save_context();
  91         omap_dma_global_context_save();
  92 }
  93
  94 static void omap3_core_restore_context(void)
  95 {
  96         /* Restore the control module context, padconf restored by h/w */
  97         omap3_control_restore_context();
  98         /* Restore the GPMC context */
  99         omap3_gpmc_restore_context();
 100         /* Restore the interrupt controller context */
 101         omap_intc_restore_context();
 102         omap_dma_global_context_restore();
 103 }
 104
 105 /*
 106  * FIXME: This function should be called before entering off-mode after
 107  * OMAP3 secure services have been accessed. Currently it is only called
 108  * once during boot sequence, but this works as we are not using secure
 109  * services.
 110  */
 111 static void omap3_save_secure_ram_context(void)
 112 {
 113         u32 ret;
 114         int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 115
 116         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 117                 /*
 118                  * MPU next state must be set to POWER_ON temporarily,
 119                  * otherwise the WFI executed inside the ROM code
 120                  * will hang the system.
 121                  */
 122                 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
 123                 ret = omap3_save_secure_ram(omap3_secure_ram_storage,
 124                                             OMAP3_SAVE_SECURE_RAM_SZ);
 125                 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
 126                 /* Following is for error tracking, it should not happen */
 127                 if (ret) {
 128                         pr_err("save_secure_sram() returns %08x\n", ret);
 129                         while (1)
 130                                 ;
 131                 }
 132         }
 133 }
 134
 135 static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
 136 {
 137         int c;
 138
 139         c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, OMAP3430_ST_IO_MASK |
 140                                     OMAP3430_ST_IO_CHAIN_MASK);
 141
 142         return c ? IRQ_HANDLED : IRQ_NONE;
 143 }
 144
 145 static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
 146 {
 147         int c;
 148
 149         /*
 150          * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
 151          * these are handled in a separate handler to avoid acking
 152          * IO events before parsing in mux code
 153          */
 154         c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, ~(OMAP3430_ST_IO_MASK |
 155                                                    OMAP3430_ST_IO_CHAIN_MASK));
 156         c += omap_prm_clear_mod_irqs(CORE_MOD, 1, ~0);
 157         c += omap_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, ~0);
 158         if (omap_rev() > OMAP3430_REV_ES1_0) {
 159                 c += omap_prm_clear_mod_irqs(CORE_MOD, 3, ~0);
 160                 c += omap_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, ~0);
 161         }
 162
 163         return c ? IRQ_HANDLED : IRQ_NONE;
 164 }
 165
 166 static void omap34xx_save_context(u32 *save)
 167 {
 168         u32 val;
 169
 170         /* Read Auxiliary Control Register */
 171         asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
 172         *save++ = 1;
 173         *save++ = val;
 174
 175         /* Read L2 AUX ctrl register */
 176         asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
 177         *save++ = 1;
 178         *save++ = val;
 179 }
 180
 181 static int omap34xx_do_sram_idle(unsigned long save_state)
 182 {
 183         omap34xx_cpu_suspend(save_state);
 184         return 0;
 185 }
 186
 187 void omap_sram_idle(void)
 188 {
 189         /* Variable to tell what needs to be saved and restored
 190          * in omap_sram_idle*/
 191         /* save_state = 0 => Nothing to save and restored */
 192         /* save_state = 1 => Only L1 and logic lost */
 193         /* save_state = 2 => Only L2 lost */
 194         /* save_state = 3 => L1, L2 and logic lost */
 195         int save_state = 0;
 196         int mpu_next_state = PWRDM_POWER_ON;
 197         int per_next_state = PWRDM_POWER_ON;
 198         int core_next_state = PWRDM_POWER_ON;
 199         u32 sdrc_pwr = 0;
 200
 201         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 202         switch (mpu_next_state) {
 203         case PWRDM_POWER_ON:
 204         case PWRDM_POWER_RET:
 205                 /* No need to save context */
 206                 save_state = 0;
 207                 break;
 208         case PWRDM_POWER_OFF:
 209                 save_state = 3;
 210                 break;
 211         default:
 212                 /* Invalid state */
 213                 pr_err("Invalid mpu state in sram_idle\n");
 214                 return;
 215         }
 216
 217         /* NEON control */
 218         if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
 219                 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
 220
 221         /* Enable IO-PAD and IO-CHAIN wakeups */
 222         per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
 223         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
 224
 225         pwrdm_pre_transition(NULL);
 226
 227         /* PER */
 228         if (per_next_state == PWRDM_POWER_OFF)
 229                 cpu_cluster_pm_enter();
 230
 231         /* CORE */
 232         if (core_next_state < PWRDM_POWER_ON) {
 233                 if (core_next_state == PWRDM_POWER_OFF) {
 234                         omap3_core_save_context();
 235                         omap3_cm_save_context();
 236                 }
 237         }
 238
 239         /* Configure PMIC signaling for I2C4 or sys_off_mode */
 240         omap3_vc_set_pmic_signaling(core_next_state);
 241
 242         omap3_intc_prepare_idle();
 243
 244         /*
 245          * On EMU/HS devices ROM code restores a SRDC value
 246          * from scratchpad which has automatic self refresh on timeout
 247          * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
 248          * Hence store/restore the SDRC_POWER register here.
 249          */
 250         if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
 251             (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
 252              omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
 253             core_next_state == PWRDM_POWER_OFF)
 254                 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
 255
 256         /*
 257          * omap3_arm_context is the location where some ARM context
 258          * get saved. The rest is placed on the stack, and restored
 259          * from there before resuming.
 260          */
 261         if (save_state)
 262                 omap34xx_save_context(omap3_arm_context);
 263         if (save_state == 1 || save_state == 3)
 264                 cpu_suspend(save_state, omap34xx_do_sram_idle);
 265         else
 266                 omap34xx_do_sram_idle(save_state);
 267
 268         /* Restore normal SDRC POWER settings */
 269         if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
 270             (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
 271              omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
 272             core_next_state == PWRDM_POWER_OFF)
 273                 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
 274
 275         /* CORE */
 276         if (core_next_state < PWRDM_POWER_ON &&
 277             pwrdm_read_prev_pwrst(core_pwrdm) == PWRDM_POWER_OFF) {
 278                 omap3_core_restore_context();
 279                 omap3_cm_restore_context();
 280                 omap3_sram_restore_context();
 281                 omap2_sms_restore_context();
 282         } else {
 283                 /*
 284                  * In off-mode resume path above, omap3_core_restore_context
 285                  * also handles the INTC autoidle restore done here so limit
 286                  * this to non-off mode resume paths so we don't do it twice.
 287                  */
 288                 omap3_intc_resume_idle();
 289         }
 290
 291         pwrdm_post_transition(NULL);
 292
 293         /* PER */
 294         if (per_next_state == PWRDM_POWER_OFF)
 295                 cpu_cluster_pm_exit();
 296 }
 297
 298 static void omap3_pm_idle(void)
 299 {
 300         if (omap_irq_pending())
 301                 return;
 302
 303         trace_cpu_idle_rcuidle(1, smp_processor_id());
 304
 305         omap_sram_idle();
 306
 307         trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
 308 }
 309
 310 #ifdef CONFIG_SUSPEND
 311 static int omap3_pm_suspend(void)
 312 {
 313         struct power_state *pwrst;
 314         int state, ret = 0;
 315
 316         /* Read current next_pwrsts */
 317         list_for_each_entry(pwrst, &pwrst_list, node)
 318                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
 319         /* Set ones wanted by suspend */
 320         list_for_each_entry(pwrst, &pwrst_list, node) {
 321                 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
 322                         goto restore;
 323                 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
 324                         goto restore;
 325         }
 326
 327         omap3_intc_suspend();
 328
 329         omap_sram_idle();
 330
 331 restore:
 332         /* Restore next_pwrsts */
 333         list_for_each_entry(pwrst, &pwrst_list, node) {
 334                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 335                 if (state > pwrst->next_state) {
 336                         pr_info("Powerdomain (%s) didn't enter target state %d\n",
 337                                 pwrst->pwrdm->name, pwrst->next_state);
 338                         ret = -1;
 339                 }
 340                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
 341         }
 342         if (ret)
 343                 pr_err("Could not enter target state in pm_suspend\n");
 344         else
 345                 pr_info("Successfully put all powerdomains to target state\n");
 346
 347         return ret;
 348 }
 349 #else
 350 #define omap3_pm_suspend NULL
 351 #endif /* CONFIG_SUSPEND */
 352
 353 static void __init prcm_setup_regs(void)
 354 {
 355         omap3_ctrl_init();
 356
 357         omap3_prm_init_pm(cpu_is_omap3630(), omap3_has_iva());
 358 }
 359
 360 void omap3_pm_off_mode_enable(int enable)
 361 {
 362         struct power_state *pwrst;
 363         u32 state;
 364
 365         if (enable)
 366                 state = PWRDM_POWER_OFF;
 367         else
 368                 state = PWRDM_POWER_RET;
 369
 370         list_for_each_entry(pwrst, &pwrst_list, node) {
 371                 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
 372                                 pwrst->pwrdm == core_pwrdm &&
 373                                 state == PWRDM_POWER_OFF) {
 374                         pwrst->next_state = PWRDM_POWER_RET;
 375                         pr_warn("%s: Core OFF disabled due to errata i583\n",
 376                                 __func__);
 377                 } else {
 378                         pwrst->next_state = state;
 379                 }
 380                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 381         }
 382 }
 383
 384 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
 385 {
 386         struct power_state *pwrst;
 387
 388         list_for_each_entry(pwrst, &pwrst_list, node) {
 389                 if (pwrst->pwrdm == pwrdm)
 390                         return pwrst->next_state;
 391         }
 392         return -EINVAL;
 393 }
 394
 395 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
 396 {
 397         struct power_state *pwrst;
 398
 399         list_for_each_entry(pwrst, &pwrst_list, node) {
 400                 if (pwrst->pwrdm == pwrdm) {
 401                         pwrst->next_state = state;
 402                         return 0;
 403                 }
 404         }
 405         return -EINVAL;
 406 }
 407
 408 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 409 {
 410         struct power_state *pwrst;
 411
 412         if (!pwrdm->pwrsts)
 413                 return 0;
 414
 415         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
 416         if (!pwrst)
 417                 return -ENOMEM;
 418         pwrst->pwrdm = pwrdm;
 419         pwrst->next_state = PWRDM_POWER_RET;
 420         list_add(&pwrst->node, &pwrst_list);
 421
 422         if (pwrdm_has_hdwr_sar(pwrdm))
 423                 pwrdm_enable_hdwr_sar(pwrdm);
 424
 425         return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 426 }
 427
 428 /*
 429  * Push functions to SRAM
 430  *
 431  * The minimum set of functions is pushed to SRAM for execution:
 432  * - omap3_do_wfi for erratum i581 WA,
 433  */
 434 void omap_push_sram_idle(void)
 435 {
 436         omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
 437 }
 438
 439 static void __init pm_errata_configure(void)
 440 {
 441         if (cpu_is_omap3630()) {
 442                 pm34xx_errata |= PM_RTA_ERRATUM_i608;
 443                 /* Enable the l2 cache toggling in sleep logic */
 444                 enable_omap3630_toggle_l2_on_restore();
 445                 if (omap_rev() < OMAP3630_REV_ES1_2)
 446                         pm34xx_errata |= (PM_SDRC_WAKEUP_ERRATUM_i583 |
 447                                           PM_PER_MEMORIES_ERRATUM_i582);
 448         } else if (cpu_is_omap34xx()) {
 449                 pm34xx_errata |= PM_PER_MEMORIES_ERRATUM_i582;
 450         }
 451 }
 452
 453 int __init omap3_pm_init(void)
 454 {
 455         struct power_state *pwrst, *tmp;
 456         struct clockdomain *neon_clkdm, *mpu_clkdm, *per_clkdm, *wkup_clkdm;
 457         int ret;
 458
 459         if (!omap3_has_io_chain_ctrl())
 460                 pr_warn("PM: no software I/O chain control; some wakeups may be lost\n");
 461
 462         pm_errata_configure();
 463
 464         /* XXX prcm_setup_regs needs to be before enabling hw
 465          * supervised mode for powerdomains */
 466         prcm_setup_regs();
 467
 468         ret = request_irq(omap_prcm_event_to_irq("wkup"),
 469                 _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);
 470
 471         if (ret) {
 472                 pr_err("pm: Failed to request pm_wkup irq\n");
 473                 goto err1;
 474         }
 475
 476         /* IO interrupt is shared with mux code */
 477         ret = request_irq(omap_prcm_event_to_irq("io"),
 478                 _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
 479                 omap3_pm_init);
 480
 481         if (ret) {
 482                 pr_err("pm: Failed to request pm_io irq\n");
 483                 goto err2;
 484         }
 485
 486         ret = pwrdm_for_each(pwrdms_setup, NULL);
 487         if (ret) {
 488                 pr_err("Failed to setup powerdomains\n");
 489                 goto err3;
 490         }
 491
 492         (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
 493
 494         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 495         if (mpu_pwrdm == NULL) {
 496                 pr_err("Failed to get mpu_pwrdm\n");
 497                 ret = -EINVAL;
 498                 goto err3;
 499         }
 500
 501         neon_pwrdm = pwrdm_lookup("neon_pwrdm");
 502         per_pwrdm = pwrdm_lookup("per_pwrdm");
 503         core_pwrdm = pwrdm_lookup("core_pwrdm");
 504
 505         neon_clkdm = clkdm_lookup("neon_clkdm");
 506         mpu_clkdm = clkdm_lookup("mpu_clkdm");
 507         per_clkdm = clkdm_lookup("per_clkdm");
 508         wkup_clkdm = clkdm_lookup("wkup_clkdm");
 509
 510         omap_common_suspend_init(omap3_pm_suspend);
 511
 512         arm_pm_idle = omap3_pm_idle;
 513         omap3_idle_init();
 514
 515         /*
 516          * RTA is disabled during initialization as per erratum i608
 517          * it is safer to disable RTA by the bootloader, but we would like
 518          * to be doubly sure here and prevent any mishaps.
 519          */
 520         if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
 521                 omap3630_ctrl_disable_rta();
 522
 523         /*
 524          * The UART3/4 FIFO and the sidetone memory in McBSP2/3 are
 525          * not correctly reset when the PER powerdomain comes back
 526          * from OFF or OSWR when the CORE powerdomain is kept active.
 527          * See OMAP36xx Erratum i582 "PER Domain reset issue after
 528          * Domain-OFF/OSWR Wakeup".  This wakeup dependency is not a
 529          * complete workaround.  The kernel must also prevent the PER
 530          * powerdomain from going to OSWR/OFF while the CORE
 531          * powerdomain is not going to OSWR/OFF.  And if PER last
 532          * power state was off while CORE last power state was ON, the
 533          * UART3/4 and McBSP2/3 SIDETONE devices need to run a
 534          * self-test using their loopback tests; if that fails, those
 535          * devices are unusable until the PER/CORE can complete a transition
 536          * from ON to OSWR/OFF and then back to ON.
 537          *
 538          * XXX Technically this workaround is only needed if off-mode
 539          * or OSWR is enabled.
 540          */
 541         if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582))
 542                 clkdm_add_wkdep(per_clkdm, wkup_clkdm);
 543
 544         clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
 545         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 546                 omap3_secure_ram_storage =
 547                         kmalloc(OMAP3_SAVE_SECURE_RAM_SZ, GFP_KERNEL);
 548                 if (!omap3_secure_ram_storage)
 549                         pr_err("Memory allocation failed when allocating for secure sram context\n");
 550
 551                 local_irq_disable();
 552
 553                 omap_dma_global_context_save();
 554                 omap3_save_secure_ram_context();
 555                 omap_dma_global_context_restore();
 556
 557                 local_irq_enable();
 558         }
 559
 560         omap3_save_scratchpad_contents();
 561         return ret;
 562
 563 err3:
 564         list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
 565                 list_del(&pwrst->node);
 566                 kfree(pwrst);
 567         }
 568         free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init);
 569 err2:
 570         free_irq(omap_prcm_event_to_irq("wkup"), NULL);
 571 err1:
 572         return ret;
 573 }