arch/arm/mach-omap2/omap_hwmod_81xx_data.c

   1 /*
   2  * DM81xx hwmod data.
   3  *
   4  * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
   5  * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/types.h>
  19
  20 #include <linux/platform_data/hsmmc-omap.h>
  21
  22 #include "omap_hwmod_common_data.h"
  23 #include "cm81xx.h"
  24 #include "ti81xx.h"
  25 #include "wd_timer.h"
  26
  27 /*
  28  * DM816X hardware modules integration data
  29  *
  30  * Note: This is incomplete and at present, not generated from h/w database.
  31  */
  32
  33 /*
  34  * Common alwon .clkctrl_offs from dm814x TRM "Table 2-278. CM_ALWON REGISTERS"
  35  * also dm816x TRM 18.7.17 CM_ALWON device register values minus 0x1400.
  36  */
  37 #define DM81XX_CM_ALWON_MCASP0_CLKCTRL          0x140
  38 #define DM81XX_CM_ALWON_MCASP1_CLKCTRL          0x144
  39 #define DM81XX_CM_ALWON_MCASP2_CLKCTRL          0x148
  40 #define DM81XX_CM_ALWON_MCBSP_CLKCTRL           0x14c
  41 #define DM81XX_CM_ALWON_UART_0_CLKCTRL          0x150
  42 #define DM81XX_CM_ALWON_UART_1_CLKCTRL          0x154
  43 #define DM81XX_CM_ALWON_UART_2_CLKCTRL          0x158
  44 #define DM81XX_CM_ALWON_GPIO_0_CLKCTRL          0x15c
  45 #define DM81XX_CM_ALWON_GPIO_1_CLKCTRL          0x160
  46 #define DM81XX_CM_ALWON_I2C_0_CLKCTRL           0x164
  47 #define DM81XX_CM_ALWON_I2C_1_CLKCTRL           0x168
  48 #define DM81XX_CM_ALWON_WDTIMER_CLKCTRL         0x18c
  49 #define DM81XX_CM_ALWON_SPI_CLKCTRL             0x190
  50 #define DM81XX_CM_ALWON_MAILBOX_CLKCTRL         0x194
  51 #define DM81XX_CM_ALWON_SPINBOX_CLKCTRL         0x198
  52 #define DM81XX_CM_ALWON_MMUDATA_CLKCTRL         0x19c
  53 #define DM81XX_CM_ALWON_MMUCFG_CLKCTRL          0x1a8
  54 #define DM81XX_CM_ALWON_CONTROL_CLKCTRL         0x1c4
  55 #define DM81XX_CM_ALWON_GPMC_CLKCTRL            0x1d0
  56 #define DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL      0x1d4
  57 #define DM81XX_CM_ALWON_L3_CLKCTRL              0x1e4
  58 #define DM81XX_CM_ALWON_L4HS_CLKCTRL            0x1e8
  59 #define DM81XX_CM_ALWON_L4LS_CLKCTRL            0x1ec
  60 #define DM81XX_CM_ALWON_RTC_CLKCTRL             0x1f0
  61 #define DM81XX_CM_ALWON_TPCC_CLKCTRL            0x1f4
  62 #define DM81XX_CM_ALWON_TPTC0_CLKCTRL           0x1f8
  63 #define DM81XX_CM_ALWON_TPTC1_CLKCTRL           0x1fc
  64 #define DM81XX_CM_ALWON_TPTC2_CLKCTRL           0x200
  65 #define DM81XX_CM_ALWON_TPTC3_CLKCTRL           0x204
  66
  67 /* Registers specific to dm814x */
  68 #define DM814X_CM_ALWON_MCASP_3_4_5_CLKCTRL     0x16c
  69 #define DM814X_CM_ALWON_ATL_CLKCTRL             0x170
  70 #define DM814X_CM_ALWON_MLB_CLKCTRL             0x174
  71 #define DM814X_CM_ALWON_PATA_CLKCTRL            0x178
  72 #define DM814X_CM_ALWON_UART_3_CLKCTRL          0x180
  73 #define DM814X_CM_ALWON_UART_4_CLKCTRL          0x184
  74 #define DM814X_CM_ALWON_UART_5_CLKCTRL          0x188
  75 #define DM814X_CM_ALWON_OCM_0_CLKCTRL           0x1b4
  76 #define DM814X_CM_ALWON_VCP_CLKCTRL             0x1b8
  77 #define DM814X_CM_ALWON_MPU_CLKCTRL             0x1dc
  78 #define DM814X_CM_ALWON_DEBUGSS_CLKCTRL         0x1e0
  79 #define DM814X_CM_ALWON_DCAN_0_1_CLKCTRL        0x218
  80 #define DM814X_CM_ALWON_MMCHS_0_CLKCTRL         0x21c
  81 #define DM814X_CM_ALWON_MMCHS_1_CLKCTRL         0x220
  82 #define DM814X_CM_ALWON_MMCHS_2_CLKCTRL         0x224
  83 #define DM814X_CM_ALWON_CUST_EFUSE_CLKCTRL      0x228
  84
  85 /* Registers specific to dm816x */
  86 #define DM816X_DM_ALWON_BASE            0x1400
  87 #define DM816X_CM_ALWON_TIMER_1_CLKCTRL (0x1570 - DM816X_DM_ALWON_BASE)
  88 #define DM816X_CM_ALWON_TIMER_2_CLKCTRL (0x1574 - DM816X_DM_ALWON_BASE)
  89 #define DM816X_CM_ALWON_TIMER_3_CLKCTRL (0x1578 - DM816X_DM_ALWON_BASE)
  90 #define DM816X_CM_ALWON_TIMER_4_CLKCTRL (0x157c - DM816X_DM_ALWON_BASE)
  91 #define DM816X_CM_ALWON_TIMER_5_CLKCTRL (0x1580 - DM816X_DM_ALWON_BASE)
  92 #define DM816X_CM_ALWON_TIMER_6_CLKCTRL (0x1584 - DM816X_DM_ALWON_BASE)
  93 #define DM816X_CM_ALWON_TIMER_7_CLKCTRL (0x1588 - DM816X_DM_ALWON_BASE)
  94 #define DM816X_CM_ALWON_SDIO_CLKCTRL    (0x15b0 - DM816X_DM_ALWON_BASE)
  95 #define DM816X_CM_ALWON_OCMC_0_CLKCTRL  (0x15b4 - DM816X_DM_ALWON_BASE)
  96 #define DM816X_CM_ALWON_OCMC_1_CLKCTRL  (0x15b8 - DM816X_DM_ALWON_BASE)
  97 #define DM816X_CM_ALWON_ETHERNET_1_CLKCTRL (0x15d8 - DM816X_DM_ALWON_BASE)
  98 #define DM816X_CM_ALWON_MPU_CLKCTRL     (0x15dc - DM816X_DM_ALWON_BASE)
  99 #define DM816X_CM_ALWON_SR_0_CLKCTRL    (0x1608 - DM816X_DM_ALWON_BASE)
 100 #define DM816X_CM_ALWON_SR_1_CLKCTRL    (0x160c - DM816X_DM_ALWON_BASE)
 101
 102 /*
 103  * The default .clkctrl_offs field is offset from CM_DEFAULT, that's
 104  * TRM 18.7.6 CM_DEFAULT device register values minus 0x500
 105  */
 106 #define DM81XX_CM_DEFAULT_OFFSET        0x500
 107 #define DM81XX_CM_DEFAULT_USB_CLKCTRL   (0x558 - DM81XX_CM_DEFAULT_OFFSET)
 108 #define DM81XX_CM_DEFAULT_SATA_CLKCTRL  (0x560 - DM81XX_CM_DEFAULT_OFFSET)
 109
 110 /* L3 Interconnect entries clocked at 125, 250 and 500MHz */
 111 static struct omap_hwmod dm81xx_alwon_l3_slow_hwmod = {
 112         .name           = "alwon_l3_slow",
 113         .clkdm_name     = "alwon_l3s_clkdm",
 114         .class          = &l3_hwmod_class,
 115         .flags          = HWMOD_NO_IDLEST,
 116 };
 117
 118 static struct omap_hwmod dm81xx_default_l3_slow_hwmod = {
 119         .name           = "default_l3_slow",
 120         .clkdm_name     = "default_l3_slow_clkdm",
 121         .class          = &l3_hwmod_class,
 122         .flags          = HWMOD_NO_IDLEST,
 123 };
 124
 125 static struct omap_hwmod dm81xx_alwon_l3_med_hwmod = {
 126         .name           = "l3_med",
 127         .clkdm_name     = "alwon_l3_med_clkdm",
 128         .class          = &l3_hwmod_class,
 129         .flags          = HWMOD_NO_IDLEST,
 130 };
 131
 132 static struct omap_hwmod dm81xx_alwon_l3_fast_hwmod = {
 133         .name           = "l3_fast",
 134         .clkdm_name     = "alwon_l3_fast_clkdm",
 135         .class          = &l3_hwmod_class,
 136         .flags          = HWMOD_NO_IDLEST,
 137 };
 138
 139 /*
 140  * L4 standard peripherals, see TRM table 1-12 for devices using this.
 141  * See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock.
 142  */
 143 static struct omap_hwmod dm81xx_l4_ls_hwmod = {
 144         .name           = "l4_ls",
 145         .clkdm_name     = "alwon_l3s_clkdm",
 146         .class          = &l4_hwmod_class,
 147         .flags          = HWMOD_NO_IDLEST,
 148 };
 149
 150 /*
 151  * L4 high-speed peripherals. For devices using this, please see the TRM
 152  * table 1-13. On dm816x, only EMAC, MDIO and SATA use this. See also TRM
 153  * table 1-73 for devices using 250MHz SYSCLK5 clock.
 154  */
 155 static struct omap_hwmod dm81xx_l4_hs_hwmod = {
 156         .name           = "l4_hs",
 157         .clkdm_name     = "alwon_l3_med_clkdm",
 158         .class          = &l4_hwmod_class,
 159         .flags          = HWMOD_NO_IDLEST,
 160 };
 161
 162 /* L3 slow -> L4 ls peripheral interface running at 125MHz */
 163 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_ls = {
 164         .master = &dm81xx_alwon_l3_slow_hwmod,
 165         .slave  = &dm81xx_l4_ls_hwmod,
 166         .user   = OCP_USER_MPU,
 167 };
 168
 169 /* L3 med -> L4 fast peripheral interface running at 250MHz */
 170 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_hs = {
 171         .master = &dm81xx_alwon_l3_med_hwmod,
 172         .slave  = &dm81xx_l4_hs_hwmod,
 173         .user   = OCP_USER_MPU,
 174 };
 175
 176 /* MPU */
 177 static struct omap_hwmod dm814x_mpu_hwmod = {
 178         .name           = "mpu",
 179         .clkdm_name     = "alwon_l3s_clkdm",
 180         .class          = &mpu_hwmod_class,
 181         .flags          = HWMOD_INIT_NO_IDLE,
 182         .main_clk       = "mpu_ck",
 183         .prcm           = {
 184                 .omap4 = {
 185                         .clkctrl_offs = DM814X_CM_ALWON_MPU_CLKCTRL,
 186                         .modulemode = MODULEMODE_SWCTRL,
 187                 },
 188         },
 189 };
 190
 191 static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_slow = {
 192         .master         = &dm814x_mpu_hwmod,
 193         .slave          = &dm81xx_alwon_l3_slow_hwmod,
 194         .user           = OCP_USER_MPU,
 195 };
 196
 197 /* L3 med peripheral interface running at 200MHz */
 198 static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_med = {
 199         .master = &dm814x_mpu_hwmod,
 200         .slave  = &dm81xx_alwon_l3_med_hwmod,
 201         .user   = OCP_USER_MPU,
 202 };
 203
 204 static struct omap_hwmod dm816x_mpu_hwmod = {
 205         .name           = "mpu",
 206         .clkdm_name     = "alwon_mpu_clkdm",
 207         .class          = &mpu_hwmod_class,
 208         .flags          = HWMOD_INIT_NO_IDLE,
 209         .main_clk       = "mpu_ck",
 210         .prcm           = {
 211                 .omap4 = {
 212                         .clkctrl_offs = DM816X_CM_ALWON_MPU_CLKCTRL,
 213                         .modulemode = MODULEMODE_SWCTRL,
 214                 },
 215         },
 216 };
 217
 218 static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_slow = {
 219         .master         = &dm816x_mpu_hwmod,
 220         .slave          = &dm81xx_alwon_l3_slow_hwmod,
 221         .user           = OCP_USER_MPU,
 222 };
 223
 224 /* L3 med peripheral interface running at 250MHz */
 225 static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_med = {
 226         .master = &dm816x_mpu_hwmod,
 227         .slave  = &dm81xx_alwon_l3_med_hwmod,
 228         .user   = OCP_USER_MPU,
 229 };
 230
 231 /* RTC */
 232 static struct omap_hwmod_class_sysconfig ti81xx_rtc_sysc = {
 233         .rev_offs       = 0x74,
 234         .sysc_offs      = 0x78,
 235         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 236         .idlemodes      = SIDLE_FORCE | SIDLE_NO |
 237                           SIDLE_SMART | SIDLE_SMART_WKUP,
 238         .sysc_fields    = &omap_hwmod_sysc_type3,
 239 };
 240
 241 static struct omap_hwmod_class ti81xx_rtc_hwmod_class = {
 242         .name           = "rtc",
 243         .sysc           = &ti81xx_rtc_sysc,
 244 };
 245
 246 static struct omap_hwmod ti81xx_rtc_hwmod = {
 247         .name           = "rtc",
 248         .class          = &ti81xx_rtc_hwmod_class,
 249         .clkdm_name     = "alwon_l3s_clkdm",
 250         .flags          = HWMOD_NO_IDLEST,
 251         .main_clk       = "sysclk18_ck",
 252         .prcm           = {
 253                 .omap4  = {
 254                         .clkctrl_offs = DM81XX_CM_ALWON_RTC_CLKCTRL,
 255                         .modulemode = MODULEMODE_SWCTRL,
 256                 },
 257         },
 258 };
 259
 260 static struct omap_hwmod_ocp_if ti81xx_l4_ls__rtc = {
 261         .master         = &dm81xx_l4_ls_hwmod,
 262         .slave          = &ti81xx_rtc_hwmod,
 263         .clk            = "sysclk6_ck",
 264         .user           = OCP_USER_MPU,
 265 };
 266
 267 /* UART common */
 268 static struct omap_hwmod_class_sysconfig uart_sysc = {
 269         .rev_offs       = 0x50,
 270         .sysc_offs      = 0x54,
 271         .syss_offs      = 0x58,
 272         .sysc_flags     = SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 273                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 274                                 SYSS_HAS_RESET_STATUS,
 275         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 276                                 MSTANDBY_SMART_WKUP,
 277         .sysc_fields    = &omap_hwmod_sysc_type1,
 278 };
 279
 280 static struct omap_hwmod_class uart_class = {
 281         .name = "uart",
 282         .sysc = &uart_sysc,
 283 };
 284
 285 static struct omap_hwmod dm81xx_uart1_hwmod = {
 286         .name           = "uart1",
 287         .clkdm_name     = "alwon_l3s_clkdm",
 288         .main_clk       = "sysclk10_ck",
 289         .prcm           = {
 290                 .omap4 = {
 291                         .clkctrl_offs = DM81XX_CM_ALWON_UART_0_CLKCTRL,
 292                         .modulemode = MODULEMODE_SWCTRL,
 293                 },
 294         },
 295         .class          = &uart_class,
 296         .flags          = DEBUG_TI81XXUART1_FLAGS,
 297 };
 298
 299 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart1 = {
 300         .master         = &dm81xx_l4_ls_hwmod,
 301         .slave          = &dm81xx_uart1_hwmod,
 302         .clk            = "sysclk6_ck",
 303         .user           = OCP_USER_MPU,
 304 };
 305
 306 static struct omap_hwmod dm81xx_uart2_hwmod = {
 307         .name           = "uart2",
 308         .clkdm_name     = "alwon_l3s_clkdm",
 309         .main_clk       = "sysclk10_ck",
 310         .prcm           = {
 311                 .omap4 = {
 312                         .clkctrl_offs = DM81XX_CM_ALWON_UART_1_CLKCTRL,
 313                         .modulemode = MODULEMODE_SWCTRL,
 314                 },
 315         },
 316         .class          = &uart_class,
 317         .flags          = DEBUG_TI81XXUART2_FLAGS,
 318 };
 319
 320 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart2 = {
 321         .master         = &dm81xx_l4_ls_hwmod,
 322         .slave          = &dm81xx_uart2_hwmod,
 323         .clk            = "sysclk6_ck",
 324         .user           = OCP_USER_MPU,
 325 };
 326
 327 static struct omap_hwmod dm81xx_uart3_hwmod = {
 328         .name           = "uart3",
 329         .clkdm_name     = "alwon_l3s_clkdm",
 330         .main_clk       = "sysclk10_ck",
 331         .prcm           = {
 332                 .omap4 = {
 333                         .clkctrl_offs = DM81XX_CM_ALWON_UART_2_CLKCTRL,
 334                         .modulemode = MODULEMODE_SWCTRL,
 335                 },
 336         },
 337         .class          = &uart_class,
 338         .flags          = DEBUG_TI81XXUART3_FLAGS,
 339 };
 340
 341 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart3 = {
 342         .master         = &dm81xx_l4_ls_hwmod,
 343         .slave          = &dm81xx_uart3_hwmod,
 344         .clk            = "sysclk6_ck",
 345         .user           = OCP_USER_MPU,
 346 };
 347
 348 static struct omap_hwmod_class_sysconfig wd_timer_sysc = {
 349         .rev_offs       = 0x0,
 350         .sysc_offs      = 0x10,
 351         .syss_offs      = 0x14,
 352         .sysc_flags     = SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
 353                                 SYSS_HAS_RESET_STATUS,
 354         .sysc_fields    = &omap_hwmod_sysc_type1,
 355 };
 356
 357 static struct omap_hwmod_class wd_timer_class = {
 358         .name           = "wd_timer",
 359         .sysc           = &wd_timer_sysc,
 360         .pre_shutdown   = &omap2_wd_timer_disable,
 361         .reset          = &omap2_wd_timer_reset,
 362 };
 363
 364 static struct omap_hwmod dm81xx_wd_timer_hwmod = {
 365         .name           = "wd_timer",
 366         .clkdm_name     = "alwon_l3s_clkdm",
 367         .main_clk       = "sysclk18_ck",
 368         .flags          = HWMOD_NO_IDLEST,
 369         .prcm           = {
 370                 .omap4 = {
 371                         .clkctrl_offs = DM81XX_CM_ALWON_WDTIMER_CLKCTRL,
 372                         .modulemode = MODULEMODE_SWCTRL,
 373                 },
 374         },
 375         .class          = &wd_timer_class,
 376 };
 377
 378 static struct omap_hwmod_ocp_if dm81xx_l4_ls__wd_timer1 = {
 379         .master         = &dm81xx_l4_ls_hwmod,
 380         .slave          = &dm81xx_wd_timer_hwmod,
 381         .clk            = "sysclk6_ck",
 382         .user           = OCP_USER_MPU,
 383 };
 384
 385 /* I2C common */
 386 static struct omap_hwmod_class_sysconfig i2c_sysc = {
 387         .rev_offs       = 0x0,
 388         .sysc_offs      = 0x10,
 389         .syss_offs      = 0x90,
 390         .sysc_flags     = SYSC_HAS_SIDLEMODE |
 391                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 392                                 SYSC_HAS_AUTOIDLE,
 393         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
 394         .sysc_fields    = &omap_hwmod_sysc_type1,
 395 };
 396
 397 static struct omap_hwmod_class i2c_class = {
 398         .name = "i2c",
 399         .sysc = &i2c_sysc,
 400 };
 401
 402 static struct omap_hwmod dm81xx_i2c1_hwmod = {
 403         .name           = "i2c1",
 404         .clkdm_name     = "alwon_l3s_clkdm",
 405         .main_clk       = "sysclk10_ck",
 406         .prcm           = {
 407                 .omap4 = {
 408                         .clkctrl_offs = DM81XX_CM_ALWON_I2C_0_CLKCTRL,
 409                         .modulemode = MODULEMODE_SWCTRL,
 410                 },
 411         },
 412         .class          = &i2c_class,
 413 };
 414
 415 static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c1 = {
 416         .master         = &dm81xx_l4_ls_hwmod,
 417         .slave          = &dm81xx_i2c1_hwmod,
 418         .clk            = "sysclk6_ck",
 419         .user           = OCP_USER_MPU,
 420 };
 421
 422 static struct omap_hwmod dm81xx_i2c2_hwmod = {
 423         .name           = "i2c2",
 424         .clkdm_name     = "alwon_l3s_clkdm",
 425         .main_clk       = "sysclk10_ck",
 426         .prcm           = {
 427                 .omap4 = {
 428                         .clkctrl_offs = DM81XX_CM_ALWON_I2C_1_CLKCTRL,
 429                         .modulemode = MODULEMODE_SWCTRL,
 430                 },
 431         },
 432         .class          = &i2c_class,
 433 };
 434
 435 static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c2 = {
 436         .master         = &dm81xx_l4_ls_hwmod,
 437         .slave          = &dm81xx_i2c2_hwmod,
 438         .clk            = "sysclk6_ck",
 439         .user           = OCP_USER_MPU,
 440 };
 441
 442 static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = {
 443         .rev_offs       = 0x0000,
 444         .sysc_offs      = 0x0010,
 445         .syss_offs      = 0x0014,
 446         .sysc_flags     = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 447                                 SYSC_HAS_SOFTRESET |
 448                                 SYSS_HAS_RESET_STATUS,
 449         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
 450         .sysc_fields    = &omap_hwmod_sysc_type1,
 451 };
 452
 453 static struct omap_hwmod_class dm81xx_elm_hwmod_class = {
 454         .name = "elm",
 455         .sysc = &dm81xx_elm_sysc,
 456 };
 457
 458 static struct omap_hwmod dm81xx_elm_hwmod = {
 459         .name           = "elm",
 460         .clkdm_name     = "alwon_l3s_clkdm",
 461         .class          = &dm81xx_elm_hwmod_class,
 462         .main_clk       = "sysclk6_ck",
 463 };
 464
 465 static struct omap_hwmod_ocp_if dm81xx_l4_ls__elm = {
 466         .master         = &dm81xx_l4_ls_hwmod,
 467         .slave          = &dm81xx_elm_hwmod,
 468         .clk            = "sysclk6_ck",
 469         .user           = OCP_USER_MPU,
 470 };
 471
 472 static struct omap_hwmod_class_sysconfig dm81xx_gpio_sysc = {
 473         .rev_offs       = 0x0000,
 474         .sysc_offs      = 0x0010,
 475         .syss_offs      = 0x0114,
 476         .sysc_flags     = SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 477                                 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 478                                 SYSS_HAS_RESET_STATUS,
 479         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 480                                 SIDLE_SMART_WKUP,
 481         .sysc_fields    = &omap_hwmod_sysc_type1,
 482 };
 483
 484 static struct omap_hwmod_class dm81xx_gpio_hwmod_class = {
 485         .name   = "gpio",
 486         .sysc   = &dm81xx_gpio_sysc,
 487         .rev    = 2,
 488 };
 489
 490 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 491         { .role = "dbclk", .clk = "sysclk18_ck" },
 492 };
 493
 494 static struct omap_hwmod dm81xx_gpio1_hwmod = {
 495         .name           = "gpio1",
 496         .clkdm_name     = "alwon_l3s_clkdm",
 497         .class          = &dm81xx_gpio_hwmod_class,
 498         .main_clk       = "sysclk6_ck",
 499         .prcm = {
 500                 .omap4 = {
 501                         .clkctrl_offs = DM81XX_CM_ALWON_GPIO_0_CLKCTRL,
 502                         .modulemode = MODULEMODE_SWCTRL,
 503                 },
 504         },
 505         .opt_clks       = gpio1_opt_clks,
 506         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 507 };
 508
 509 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio1 = {
 510         .master         = &dm81xx_l4_ls_hwmod,
 511         .slave          = &dm81xx_gpio1_hwmod,
 512         .clk            = "sysclk6_ck",
 513         .user           = OCP_USER_MPU,
 514 };
 515
 516 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 517         { .role = "dbclk", .clk = "sysclk18_ck" },
 518 };
 519
 520 static struct omap_hwmod dm81xx_gpio2_hwmod = {
 521         .name           = "gpio2",
 522         .clkdm_name     = "alwon_l3s_clkdm",
 523         .class          = &dm81xx_gpio_hwmod_class,
 524         .main_clk       = "sysclk6_ck",
 525         .prcm = {
 526                 .omap4 = {
 527                         .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL,
 528                         .modulemode = MODULEMODE_SWCTRL,
 529                 },
 530         },
 531         .opt_clks       = gpio2_opt_clks,
 532         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 533 };
 534
 535 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = {
 536         .master         = &dm81xx_l4_ls_hwmod,
 537         .slave          = &dm81xx_gpio2_hwmod,
 538         .clk            = "sysclk6_ck",
 539         .user           = OCP_USER_MPU,
 540 };
 541
 542 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 543         { .role = "dbclk", .clk = "sysclk18_ck" },
 544 };
 545
 546 static struct omap_hwmod dm81xx_gpio3_hwmod = {
 547         .name           = "gpio3",
 548         .clkdm_name     = "alwon_l3s_clkdm",
 549         .class          = &dm81xx_gpio_hwmod_class,
 550         .main_clk       = "sysclk6_ck",
 551         .prcm = {
 552                 .omap4 = {
 553                         .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL,
 554                         .modulemode = MODULEMODE_SWCTRL,
 555                 },
 556         },
 557         .opt_clks       = gpio3_opt_clks,
 558         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 559 };
 560
 561 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio3 = {
 562         .master         = &dm81xx_l4_ls_hwmod,
 563         .slave          = &dm81xx_gpio3_hwmod,
 564         .clk            = "sysclk6_ck",
 565         .user           = OCP_USER_MPU,
 566 };
 567
 568 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 569         { .role = "dbclk", .clk = "sysclk18_ck" },
 570 };
 571
 572 static struct omap_hwmod dm81xx_gpio4_hwmod = {
 573         .name           = "gpio4",
 574         .clkdm_name     = "alwon_l3s_clkdm",
 575         .class          = &dm81xx_gpio_hwmod_class,
 576         .main_clk       = "sysclk6_ck",
 577         .prcm = {
 578                 .omap4 = {
 579                         .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL,
 580                         .modulemode = MODULEMODE_SWCTRL,
 581                 },
 582         },
 583         .opt_clks       = gpio4_opt_clks,
 584         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 585 };
 586
 587 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio4 = {
 588         .master         = &dm81xx_l4_ls_hwmod,
 589         .slave          = &dm81xx_gpio4_hwmod,
 590         .clk            = "sysclk6_ck",
 591         .user           = OCP_USER_MPU,
 592 };
 593
 594 static struct omap_hwmod_class_sysconfig dm81xx_gpmc_sysc = {
 595         .rev_offs       = 0x0,
 596         .sysc_offs      = 0x10,
 597         .syss_offs      = 0x14,
 598         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 599                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
 600         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
 601         .sysc_fields    = &omap_hwmod_sysc_type1,
 602 };
 603
 604 static struct omap_hwmod_class dm81xx_gpmc_hwmod_class = {
 605         .name   = "gpmc",
 606         .sysc   = &dm81xx_gpmc_sysc,
 607 };
 608
 609 static struct omap_hwmod dm81xx_gpmc_hwmod = {
 610         .name           = "gpmc",
 611         .clkdm_name     = "alwon_l3s_clkdm",
 612         .class          = &dm81xx_gpmc_hwmod_class,
 613         .main_clk       = "sysclk6_ck",
 614         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
 615         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
 616         .prcm = {
 617                 .omap4 = {
 618                         .clkctrl_offs = DM81XX_CM_ALWON_GPMC_CLKCTRL,
 619                         .modulemode = MODULEMODE_SWCTRL,
 620                 },
 621         },
 622 };
 623
 624 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__gpmc = {
 625         .master         = &dm81xx_alwon_l3_slow_hwmod,
 626         .slave          = &dm81xx_gpmc_hwmod,
 627         .user           = OCP_USER_MPU,
 628 };
 629
 630 /* USB needs udelay 1 after reset at least on hp t410, use 2 for margin */
 631 static struct omap_hwmod_class_sysconfig dm81xx_usbhsotg_sysc = {
 632         .rev_offs       = 0x0,
 633         .sysc_offs      = 0x10,
 634         .srst_udelay    = 2,
 635         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 636                                 SYSC_HAS_SOFTRESET,
 637         .idlemodes      = SIDLE_SMART | MSTANDBY_FORCE | MSTANDBY_SMART,
 638         .sysc_fields    = &omap_hwmod_sysc_type2,
 639 };
 640
 641 static struct omap_hwmod_class dm81xx_usbotg_class = {
 642         .name = "usbotg",
 643         .sysc = &dm81xx_usbhsotg_sysc,
 644 };
 645
 646 static struct omap_hwmod dm814x_usbss_hwmod = {
 647         .name           = "usb_otg_hs",
 648         .clkdm_name     = "default_l3_slow_clkdm",
 649         .main_clk       = "pll260dcoclkldo",    /* 481c5260.adpll.dcoclkldo */
 650         .prcm           = {
 651                 .omap4 = {
 652                         .clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL,
 653                         .modulemode = MODULEMODE_SWCTRL,
 654                 },
 655         },
 656         .class          = &dm81xx_usbotg_class,
 657 };
 658
 659 static struct omap_hwmod_ocp_if dm814x_default_l3_slow__usbss = {
 660         .master         = &dm81xx_default_l3_slow_hwmod,
 661         .slave          = &dm814x_usbss_hwmod,
 662         .clk            = "sysclk6_ck",
 663         .user           = OCP_USER_MPU,
 664 };
 665
 666 static struct omap_hwmod dm816x_usbss_hwmod = {
 667         .name           = "usb_otg_hs",
 668         .clkdm_name     = "default_l3_slow_clkdm",
 669         .main_clk       = "sysclk6_ck",
 670         .prcm           = {
 671                 .omap4 = {
 672                         .clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL,
 673                         .modulemode = MODULEMODE_SWCTRL,
 674                 },
 675         },
 676         .class          = &dm81xx_usbotg_class,
 677 };
 678
 679 static struct omap_hwmod_ocp_if dm816x_default_l3_slow__usbss = {
 680         .master         = &dm81xx_default_l3_slow_hwmod,
 681         .slave          = &dm816x_usbss_hwmod,
 682         .clk            = "sysclk6_ck",
 683         .user           = OCP_USER_MPU,
 684 };
 685
 686 static struct omap_hwmod_class_sysconfig dm816x_timer_sysc = {
 687         .rev_offs       = 0x0000,
 688         .sysc_offs      = 0x0010,
 689         .syss_offs      = 0x0014,
 690         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET,
 691         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 692                                 SIDLE_SMART_WKUP,
 693         .sysc_fields    = &omap_hwmod_sysc_type2,
 694 };
 695
 696 static struct omap_hwmod_class dm816x_timer_hwmod_class = {
 697         .name = "timer",
 698         .sysc = &dm816x_timer_sysc,
 699 };
 700
 701 static struct omap_hwmod dm814x_timer1_hwmod = {
 702         .name           = "timer1",
 703         .clkdm_name     = "alwon_l3s_clkdm",
 704         .main_clk       = "timer1_fck",
 705         .class          = &dm816x_timer_hwmod_class,
 706         .flags          = HWMOD_NO_IDLEST,
 707 };
 708
 709 static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = {
 710         .master         = &dm81xx_l4_ls_hwmod,
 711         .slave          = &dm814x_timer1_hwmod,
 712         .clk            = "sysclk6_ck",
 713         .user           = OCP_USER_MPU,
 714 };
 715
 716 static struct omap_hwmod dm816x_timer1_hwmod = {
 717         .name           = "timer1",
 718         .clkdm_name     = "alwon_l3s_clkdm",
 719         .main_clk       = "timer1_fck",
 720         .prcm           = {
 721                 .omap4 = {
 722                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_1_CLKCTRL,
 723                         .modulemode = MODULEMODE_SWCTRL,
 724                 },
 725         },
 726         .class          = &dm816x_timer_hwmod_class,
 727 };
 728
 729 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = {
 730         .master         = &dm81xx_l4_ls_hwmod,
 731         .slave          = &dm816x_timer1_hwmod,
 732         .clk            = "sysclk6_ck",
 733         .user           = OCP_USER_MPU,
 734 };
 735
 736 static struct omap_hwmod dm814x_timer2_hwmod = {
 737         .name           = "timer2",
 738         .clkdm_name     = "alwon_l3s_clkdm",
 739         .main_clk       = "timer2_fck",
 740         .class          = &dm816x_timer_hwmod_class,
 741         .flags          = HWMOD_NO_IDLEST,
 742 };
 743
 744 static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = {
 745         .master         = &dm81xx_l4_ls_hwmod,
 746         .slave          = &dm814x_timer2_hwmod,
 747         .clk            = "sysclk6_ck",
 748         .user           = OCP_USER_MPU,
 749 };
 750
 751 static struct omap_hwmod dm816x_timer2_hwmod = {
 752         .name           = "timer2",
 753         .clkdm_name     = "alwon_l3s_clkdm",
 754         .main_clk       = "timer2_fck",
 755         .prcm           = {
 756                 .omap4 = {
 757                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_2_CLKCTRL,
 758                         .modulemode = MODULEMODE_SWCTRL,
 759                 },
 760         },
 761         .class          = &dm816x_timer_hwmod_class,
 762 };
 763
 764 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer2 = {
 765         .master         = &dm81xx_l4_ls_hwmod,
 766         .slave          = &dm816x_timer2_hwmod,
 767         .clk            = "sysclk6_ck",
 768         .user           = OCP_USER_MPU,
 769 };
 770
 771 static struct omap_hwmod dm816x_timer3_hwmod = {
 772         .name           = "timer3",
 773         .clkdm_name     = "alwon_l3s_clkdm",
 774         .main_clk       = "timer3_fck",
 775         .prcm           = {
 776                 .omap4 = {
 777                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_3_CLKCTRL,
 778                         .modulemode = MODULEMODE_SWCTRL,
 779                 },
 780         },
 781         .class          = &dm816x_timer_hwmod_class,
 782 };
 783
 784 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer3 = {
 785         .master         = &dm81xx_l4_ls_hwmod,
 786         .slave          = &dm816x_timer3_hwmod,
 787         .clk            = "sysclk6_ck",
 788         .user           = OCP_USER_MPU,
 789 };
 790
 791 static struct omap_hwmod dm816x_timer4_hwmod = {
 792         .name           = "timer4",
 793         .clkdm_name     = "alwon_l3s_clkdm",
 794         .main_clk       = "timer4_fck",
 795         .prcm           = {
 796                 .omap4 = {
 797                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_4_CLKCTRL,
 798                         .modulemode = MODULEMODE_SWCTRL,
 799                 },
 800         },
 801         .class          = &dm816x_timer_hwmod_class,
 802 };
 803
 804 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer4 = {
 805         .master         = &dm81xx_l4_ls_hwmod,
 806         .slave          = &dm816x_timer4_hwmod,
 807         .clk            = "sysclk6_ck",
 808         .user           = OCP_USER_MPU,
 809 };
 810
 811 static struct omap_hwmod dm816x_timer5_hwmod = {
 812         .name           = "timer5",
 813         .clkdm_name     = "alwon_l3s_clkdm",
 814         .main_clk       = "timer5_fck",
 815         .prcm           = {
 816                 .omap4 = {
 817                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_5_CLKCTRL,
 818                         .modulemode = MODULEMODE_SWCTRL,
 819                 },
 820         },
 821         .class          = &dm816x_timer_hwmod_class,
 822 };
 823
 824 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer5 = {
 825         .master         = &dm81xx_l4_ls_hwmod,
 826         .slave          = &dm816x_timer5_hwmod,
 827         .clk            = "sysclk6_ck",
 828         .user           = OCP_USER_MPU,
 829 };
 830
 831 static struct omap_hwmod dm816x_timer6_hwmod = {
 832         .name           = "timer6",
 833         .clkdm_name     = "alwon_l3s_clkdm",
 834         .main_clk       = "timer6_fck",
 835         .prcm           = {
 836                 .omap4 = {
 837                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_6_CLKCTRL,
 838                         .modulemode = MODULEMODE_SWCTRL,
 839                 },
 840         },
 841         .class          = &dm816x_timer_hwmod_class,
 842 };
 843
 844 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer6 = {
 845         .master         = &dm81xx_l4_ls_hwmod,
 846         .slave          = &dm816x_timer6_hwmod,
 847         .clk            = "sysclk6_ck",
 848         .user           = OCP_USER_MPU,
 849 };
 850
 851 static struct omap_hwmod dm816x_timer7_hwmod = {
 852         .name           = "timer7",
 853         .clkdm_name     = "alwon_l3s_clkdm",
 854         .main_clk       = "timer7_fck",
 855         .prcm           = {
 856                 .omap4 = {
 857                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_7_CLKCTRL,
 858                         .modulemode = MODULEMODE_SWCTRL,
 859                 },
 860         },
 861         .class          = &dm816x_timer_hwmod_class,
 862 };
 863
 864 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer7 = {
 865         .master         = &dm81xx_l4_ls_hwmod,
 866         .slave          = &dm816x_timer7_hwmod,
 867         .clk            = "sysclk6_ck",
 868         .user           = OCP_USER_MPU,
 869 };
 870
 871 /* CPSW on dm814x */
 872 static struct omap_hwmod_class_sysconfig dm814x_cpgmac_sysc = {
 873         .rev_offs       = 0x0,
 874         .sysc_offs      = 0x8,
 875         .syss_offs      = 0x4,
 876         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 877                           SYSS_HAS_RESET_STATUS,
 878         .idlemodes      = SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
 879                           MSTANDBY_NO,
 880         .sysc_fields    = &omap_hwmod_sysc_type3,
 881 };
 882
 883 static struct omap_hwmod_class dm814x_cpgmac0_hwmod_class = {
 884         .name           = "cpgmac0",
 885         .sysc           = &dm814x_cpgmac_sysc,
 886 };
 887
 888 static struct omap_hwmod dm814x_cpgmac0_hwmod = {
 889         .name           = "cpgmac0",
 890         .class          = &dm814x_cpgmac0_hwmod_class,
 891         .clkdm_name     = "alwon_ethernet_clkdm",
 892         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 893         .main_clk       = "cpsw_125mhz_gclk",
 894         .prcm           = {
 895                 .omap4  = {
 896                         .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL,
 897                         .modulemode = MODULEMODE_SWCTRL,
 898                 },
 899         },
 900 };
 901
 902 static struct omap_hwmod_class dm814x_mdio_hwmod_class = {
 903         .name           = "davinci_mdio",
 904 };
 905
 906 static struct omap_hwmod dm814x_mdio_hwmod = {
 907         .name           = "davinci_mdio",
 908         .class          = &dm814x_mdio_hwmod_class,
 909         .clkdm_name     = "alwon_ethernet_clkdm",
 910         .main_clk       = "cpsw_125mhz_gclk",
 911 };
 912
 913 static struct omap_hwmod_ocp_if dm814x_l4_hs__cpgmac0 = {
 914         .master         = &dm81xx_l4_hs_hwmod,
 915         .slave          = &dm814x_cpgmac0_hwmod,
 916         .clk            = "cpsw_125mhz_gclk",
 917         .user           = OCP_USER_MPU,
 918 };
 919
 920 static struct omap_hwmod_ocp_if dm814x_cpgmac0__mdio = {
 921         .master         = &dm814x_cpgmac0_hwmod,
 922         .slave          = &dm814x_mdio_hwmod,
 923         .user           = OCP_USER_MPU,
 924         .flags          = HWMOD_NO_IDLEST,
 925 };
 926
 927 /* EMAC Ethernet */
 928 static struct omap_hwmod_class_sysconfig dm816x_emac_sysc = {
 929         .rev_offs       = 0x0,
 930         .sysc_offs      = 0x4,
 931         .sysc_flags     = SYSC_HAS_SOFTRESET,
 932         .sysc_fields    = &omap_hwmod_sysc_type2,
 933 };
 934
 935 static struct omap_hwmod_class dm816x_emac_hwmod_class = {
 936         .name           = "emac",
 937         .sysc           = &dm816x_emac_sysc,
 938 };
 939
 940 /*
 941  * On dm816x the MDIO is within EMAC0. As the MDIO driver is a separate
 942  * driver probed before EMAC0, we let MDIO do the clock idling.
 943  */
 944 static struct omap_hwmod dm816x_emac0_hwmod = {
 945         .name           = "emac0",
 946         .clkdm_name     = "alwon_ethernet_clkdm",
 947         .class          = &dm816x_emac_hwmod_class,
 948         .flags          = HWMOD_NO_IDLEST,
 949 };
 950
 951 static struct omap_hwmod_ocp_if dm81xx_l4_hs__emac0 = {
 952         .master         = &dm81xx_l4_hs_hwmod,
 953         .slave          = &dm816x_emac0_hwmod,
 954         .clk            = "sysclk5_ck",
 955         .user           = OCP_USER_MPU,
 956 };
 957
 958 static struct omap_hwmod_class dm81xx_mdio_hwmod_class = {
 959         .name           = "davinci_mdio",
 960         .sysc           = &dm816x_emac_sysc,
 961 };
 962
 963 static struct omap_hwmod dm81xx_emac0_mdio_hwmod = {
 964         .name           = "davinci_mdio",
 965         .class          = &dm81xx_mdio_hwmod_class,
 966         .clkdm_name     = "alwon_ethernet_clkdm",
 967         .main_clk       = "sysclk24_ck",
 968         .flags          = HWMOD_NO_IDLEST,
 969         /*
 970          * REVISIT: This should be moved to the emac0_hwmod
 971          * once we have a better way to handle device slaves.
 972          */
 973         .prcm           = {
 974                 .omap4 = {
 975                         .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL,
 976                         .modulemode = MODULEMODE_SWCTRL,
 977                 },
 978         },
 979 };
 980
 981 static struct omap_hwmod_ocp_if dm81xx_emac0__mdio = {
 982         .master         = &dm81xx_l4_hs_hwmod,
 983         .slave          = &dm81xx_emac0_mdio_hwmod,
 984         .user           = OCP_USER_MPU,
 985 };
 986
 987 static struct omap_hwmod dm816x_emac1_hwmod = {
 988         .name           = "emac1",
 989         .clkdm_name     = "alwon_ethernet_clkdm",
 990         .main_clk       = "sysclk24_ck",
 991         .flags          = HWMOD_NO_IDLEST,
 992         .prcm           = {
 993                 .omap4 = {
 994                         .clkctrl_offs = DM816X_CM_ALWON_ETHERNET_1_CLKCTRL,
 995                         .modulemode = MODULEMODE_SWCTRL,
 996                 },
 997         },
 998         .class          = &dm816x_emac_hwmod_class,
 999 };
1000
1001 static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = {
1002         .master         = &dm81xx_l4_hs_hwmod,
1003         .slave          = &dm816x_emac1_hwmod,
1004         .clk            = "sysclk5_ck",
1005         .user           = OCP_USER_MPU,
1006 };
1007
1008 static struct omap_hwmod_class_sysconfig dm81xx_sata_sysc = {
1009         .rev_offs       = 0x00fc,
1010         .sysc_offs      = 0x1100,
1011         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1012         .idlemodes      = SIDLE_FORCE,
1013         .sysc_fields    = &omap_hwmod_sysc_type3,
1014 };
1015
1016 static struct omap_hwmod_class dm81xx_sata_hwmod_class = {
1017         .name   = "sata",
1018         .sysc   = &dm81xx_sata_sysc,
1019 };
1020
1021 static struct omap_hwmod dm81xx_sata_hwmod = {
1022         .name           = "sata",
1023         .clkdm_name     = "default_clkdm",
1024         .flags          = HWMOD_NO_IDLEST,
1025         .prcm = {
1026                 .omap4 = {
1027                         .clkctrl_offs = DM81XX_CM_DEFAULT_SATA_CLKCTRL,
1028                         .modulemode   = MODULEMODE_SWCTRL,
1029                 },
1030         },
1031         .class          = &dm81xx_sata_hwmod_class,
1032 };
1033
1034 static struct omap_hwmod_ocp_if dm81xx_l4_hs__sata = {
1035         .master         = &dm81xx_l4_hs_hwmod,
1036         .slave          = &dm81xx_sata_hwmod,
1037         .clk            = "sysclk5_ck",
1038         .user           = OCP_USER_MPU,
1039 };
1040
1041 static struct omap_hwmod_class_sysconfig dm81xx_mmc_sysc = {
1042         .rev_offs       = 0x0,
1043         .sysc_offs      = 0x110,
1044         .syss_offs      = 0x114,
1045         .sysc_flags     = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1046                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1047                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
1048         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1049         .sysc_fields    = &omap_hwmod_sysc_type1,
1050 };
1051
1052 static struct omap_hwmod_class dm81xx_mmc_class = {
1053         .name = "mmc",
1054         .sysc = &dm81xx_mmc_sysc,
1055 };
1056
1057 static struct omap_hwmod_opt_clk dm81xx_mmc_opt_clks[] = {
1058         { .role = "dbck", .clk = "sysclk18_ck", },
1059 };
1060
1061 static struct omap_hsmmc_dev_attr mmc_dev_attr = {
1062 };
1063
1064 static struct omap_hwmod dm814x_mmc1_hwmod = {
1065         .name           = "mmc1",
1066         .clkdm_name     = "alwon_l3s_clkdm",
1067         .opt_clks       = dm81xx_mmc_opt_clks,
1068         .opt_clks_cnt   = ARRAY_SIZE(dm81xx_mmc_opt_clks),
1069         .main_clk       = "sysclk8_ck",
1070         .prcm           = {
1071                 .omap4 = {
1072                         .clkctrl_offs = DM814X_CM_ALWON_MMCHS_0_CLKCTRL,
1073                         .modulemode = MODULEMODE_SWCTRL,
1074                 },
1075         },
1076         .dev_attr       = &mmc_dev_attr,
1077         .class          = &dm81xx_mmc_class,
1078 };
1079
1080 static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc1 = {
1081         .master         = &dm81xx_l4_ls_hwmod,
1082         .slave          = &dm814x_mmc1_hwmod,
1083         .clk            = "sysclk6_ck",
1084         .user           = OCP_USER_MPU,
1085         .flags          = OMAP_FIREWALL_L4
1086 };
1087
1088 static struct omap_hwmod dm814x_mmc2_hwmod = {
1089         .name           = "mmc2",
1090         .clkdm_name     = "alwon_l3s_clkdm",
1091         .opt_clks       = dm81xx_mmc_opt_clks,
1092         .opt_clks_cnt   = ARRAY_SIZE(dm81xx_mmc_opt_clks),
1093         .main_clk       = "sysclk8_ck",
1094         .prcm           = {
1095                 .omap4 = {
1096                         .clkctrl_offs = DM814X_CM_ALWON_MMCHS_1_CLKCTRL,
1097                         .modulemode = MODULEMODE_SWCTRL,
1098                 },
1099         },
1100         .dev_attr       = &mmc_dev_attr,
1101         .class          = &dm81xx_mmc_class,
1102 };
1103
1104 static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc2 = {
1105         .master         = &dm81xx_l4_ls_hwmod,
1106         .slave          = &dm814x_mmc2_hwmod,
1107         .clk            = "sysclk6_ck",
1108         .user           = OCP_USER_MPU,
1109         .flags          = OMAP_FIREWALL_L4
1110 };
1111
1112 static struct omap_hwmod dm814x_mmc3_hwmod = {
1113         .name           = "mmc3",
1114         .clkdm_name     = "alwon_l3_med_clkdm",
1115         .opt_clks       = dm81xx_mmc_opt_clks,
1116         .opt_clks_cnt   = ARRAY_SIZE(dm81xx_mmc_opt_clks),
1117         .main_clk       = "sysclk8_ck",
1118         .prcm           = {
1119                 .omap4 = {
1120                         .clkctrl_offs = DM814X_CM_ALWON_MMCHS_2_CLKCTRL,
1121                         .modulemode = MODULEMODE_SWCTRL,
1122                 },
1123         },
1124         .dev_attr       = &mmc_dev_attr,
1125         .class          = &dm81xx_mmc_class,
1126 };
1127
1128 static struct omap_hwmod_ocp_if dm814x_alwon_l3_med__mmc3 = {
1129         .master         = &dm81xx_alwon_l3_med_hwmod,
1130         .slave          = &dm814x_mmc3_hwmod,
1131         .clk            = "sysclk4_ck",
1132         .user           = OCP_USER_MPU,
1133 };
1134
1135 static struct omap_hwmod dm816x_mmc1_hwmod = {
1136         .name           = "mmc1",
1137         .clkdm_name     = "alwon_l3s_clkdm",
1138         .opt_clks       = dm81xx_mmc_opt_clks,
1139         .opt_clks_cnt   = ARRAY_SIZE(dm81xx_mmc_opt_clks),
1140         .main_clk       = "sysclk10_ck",
1141         .prcm           = {
1142                 .omap4 = {
1143                         .clkctrl_offs = DM816X_CM_ALWON_SDIO_CLKCTRL,
1144                         .modulemode = MODULEMODE_SWCTRL,
1145                 },
1146         },
1147         .dev_attr       = &mmc_dev_attr,
1148         .class          = &dm81xx_mmc_class,
1149 };
1150
1151 static struct omap_hwmod_ocp_if dm816x_l4_ls__mmc1 = {
1152         .master         = &dm81xx_l4_ls_hwmod,
1153         .slave          = &dm816x_mmc1_hwmod,
1154         .clk            = "sysclk6_ck",
1155         .user           = OCP_USER_MPU,
1156         .flags          = OMAP_FIREWALL_L4
1157 };
1158
1159 static struct omap_hwmod_class_sysconfig dm816x_mcspi_sysc = {
1160         .rev_offs       = 0x0,
1161         .sysc_offs      = 0x110,
1162         .syss_offs      = 0x114,
1163         .sysc_flags     = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1164                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1165                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
1166         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1167         .sysc_fields    = &omap_hwmod_sysc_type1,
1168 };
1169
1170 static struct omap_hwmod_class dm816x_mcspi_class = {
1171         .name = "mcspi",
1172         .sysc = &dm816x_mcspi_sysc,
1173 };
1174
1175 static struct omap_hwmod dm81xx_mcspi1_hwmod = {
1176         .name           = "mcspi1",
1177         .clkdm_name     = "alwon_l3s_clkdm",
1178         .main_clk       = "sysclk10_ck",
1179         .prcm           = {
1180                 .omap4 = {
1181                         .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
1182                         .modulemode = MODULEMODE_SWCTRL,
1183                 },
1184         },
1185         .class          = &dm816x_mcspi_class,
1186 };
1187
1188 static struct omap_hwmod dm81xx_mcspi2_hwmod = {
1189         .name           = "mcspi2",
1190         .clkdm_name     = "alwon_l3s_clkdm",
1191         .main_clk       = "sysclk10_ck",
1192         .prcm           = {
1193                 .omap4 = {
1194                         .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
1195                         .modulemode = MODULEMODE_SWCTRL,
1196                 },
1197         },
1198         .class          = &dm816x_mcspi_class,
1199 };
1200
1201 static struct omap_hwmod dm81xx_mcspi3_hwmod = {
1202         .name           = "mcspi3",
1203         .clkdm_name     = "alwon_l3s_clkdm",
1204         .main_clk       = "sysclk10_ck",
1205         .prcm           = {
1206                 .omap4 = {
1207                         .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
1208                         .modulemode = MODULEMODE_SWCTRL,
1209                 },
1210         },
1211         .class          = &dm816x_mcspi_class,
1212 };
1213
1214 static struct omap_hwmod dm81xx_mcspi4_hwmod = {
1215         .name           = "mcspi4",
1216         .clkdm_name     = "alwon_l3s_clkdm",
1217         .main_clk       = "sysclk10_ck",
1218         .prcm           = {
1219                 .omap4 = {
1220                         .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
1221                         .modulemode = MODULEMODE_SWCTRL,
1222                 },
1223         },
1224         .class          = &dm816x_mcspi_class,
1225 };
1226
1227 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = {
1228         .master         = &dm81xx_l4_ls_hwmod,
1229         .slave          = &dm81xx_mcspi1_hwmod,
1230         .clk            = "sysclk6_ck",
1231         .user           = OCP_USER_MPU,
1232 };
1233
1234 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi2 = {
1235         .master         = &dm81xx_l4_ls_hwmod,
1236         .slave          = &dm81xx_mcspi2_hwmod,
1237         .clk            = "sysclk6_ck",
1238         .user           = OCP_USER_MPU,
1239 };
1240
1241 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi3 = {
1242         .master         = &dm81xx_l4_ls_hwmod,
1243         .slave          = &dm81xx_mcspi3_hwmod,
1244         .clk            = "sysclk6_ck",
1245         .user           = OCP_USER_MPU,
1246 };
1247
1248 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi4 = {
1249         .master         = &dm81xx_l4_ls_hwmod,
1250         .slave          = &dm81xx_mcspi4_hwmod,
1251         .clk            = "sysclk6_ck",
1252         .user           = OCP_USER_MPU,
1253 };
1254
1255 static struct omap_hwmod_class_sysconfig dm81xx_mailbox_sysc = {
1256         .rev_offs       = 0x000,
1257         .sysc_offs      = 0x010,
1258         .syss_offs      = 0x014,
1259         .sysc_flags     = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1260                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE,
1261         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1262         .sysc_fields    = &omap_hwmod_sysc_type1,
1263 };
1264
1265 static struct omap_hwmod_class dm81xx_mailbox_hwmod_class = {
1266         .name = "mailbox",
1267         .sysc = &dm81xx_mailbox_sysc,
1268 };
1269
1270 static struct omap_hwmod dm81xx_mailbox_hwmod = {
1271         .name           = "mailbox",
1272         .clkdm_name     = "alwon_l3s_clkdm",
1273         .class          = &dm81xx_mailbox_hwmod_class,
1274         .main_clk       = "sysclk6_ck",
1275         .prcm           = {
1276                 .omap4 = {
1277                         .clkctrl_offs = DM81XX_CM_ALWON_MAILBOX_CLKCTRL,
1278                         .modulemode = MODULEMODE_SWCTRL,
1279                 },
1280         },
1281 };
1282
1283 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mailbox = {
1284         .master         = &dm81xx_l4_ls_hwmod,
1285         .slave          = &dm81xx_mailbox_hwmod,
1286         .clk            = "sysclk6_ck",
1287         .user           = OCP_USER_MPU,
1288 };
1289
1290 static struct omap_hwmod_class_sysconfig dm81xx_spinbox_sysc = {
1291         .rev_offs       = 0x000,
1292         .sysc_offs      = 0x010,
1293         .syss_offs      = 0x014,
1294         .sysc_flags     = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1295                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE,
1296         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1297         .sysc_fields    = &omap_hwmod_sysc_type1,
1298 };
1299
1300 static struct omap_hwmod_class dm81xx_spinbox_hwmod_class = {
1301         .name = "spinbox",
1302         .sysc = &dm81xx_spinbox_sysc,
1303 };
1304
1305 static struct omap_hwmod dm81xx_spinbox_hwmod = {
1306         .name           = "spinbox",
1307         .clkdm_name     = "alwon_l3s_clkdm",
1308         .class          = &dm81xx_spinbox_hwmod_class,
1309         .main_clk       = "sysclk6_ck",
1310         .prcm           = {
1311                 .omap4 = {
1312                         .clkctrl_offs = DM81XX_CM_ALWON_SPINBOX_CLKCTRL,
1313                         .modulemode = MODULEMODE_SWCTRL,
1314                 },
1315         },
1316 };
1317
1318 static struct omap_hwmod_ocp_if dm81xx_l4_ls__spinbox = {
1319         .master         = &dm81xx_l4_ls_hwmod,
1320         .slave          = &dm81xx_spinbox_hwmod,
1321         .clk            = "sysclk6_ck",
1322         .user           = OCP_USER_MPU,
1323 };
1324
1325 static struct omap_hwmod_class dm81xx_tpcc_hwmod_class = {
1326         .name           = "tpcc",
1327 };
1328
1329 static struct omap_hwmod dm81xx_tpcc_hwmod = {
1330         .name           = "tpcc",
1331         .class          = &dm81xx_tpcc_hwmod_class,
1332         .clkdm_name     = "alwon_l3s_clkdm",
1333         .main_clk       = "sysclk4_ck",
1334         .prcm           = {
1335                 .omap4  = {
1336                         .clkctrl_offs   = DM81XX_CM_ALWON_TPCC_CLKCTRL,
1337                         .modulemode     = MODULEMODE_SWCTRL,
1338                 },
1339         },
1340 };
1341
1342 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tpcc = {
1343         .master         = &dm81xx_alwon_l3_fast_hwmod,
1344         .slave          = &dm81xx_tpcc_hwmod,
1345         .clk            = "sysclk4_ck",
1346         .user           = OCP_USER_MPU,
1347 };
1348
1349 static struct omap_hwmod_class dm81xx_tptc0_hwmod_class = {
1350         .name           = "tptc0",
1351 };
1352
1353 static struct omap_hwmod dm81xx_tptc0_hwmod = {
1354         .name           = "tptc0",
1355         .class          = &dm81xx_tptc0_hwmod_class,
1356         .clkdm_name     = "alwon_l3s_clkdm",
1357         .main_clk       = "sysclk4_ck",
1358         .prcm           = {
1359                 .omap4  = {
1360                         .clkctrl_offs   = DM81XX_CM_ALWON_TPTC0_CLKCTRL,
1361                         .modulemode     = MODULEMODE_SWCTRL,
1362                 },
1363         },
1364 };
1365
1366 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc0 = {
1367         .master         = &dm81xx_alwon_l3_fast_hwmod,
1368         .slave          = &dm81xx_tptc0_hwmod,
1369         .clk            = "sysclk4_ck",
1370         .user           = OCP_USER_MPU,
1371 };
1372
1373 static struct omap_hwmod_ocp_if dm81xx_tptc0__alwon_l3_fast = {
1374         .master         = &dm81xx_tptc0_hwmod,
1375         .slave          = &dm81xx_alwon_l3_fast_hwmod,
1376         .clk            = "sysclk4_ck",
1377         .user           = OCP_USER_MPU,
1378 };
1379
1380 static struct omap_hwmod_class dm81xx_tptc1_hwmod_class = {
1381         .name           = "tptc1",
1382 };
1383
1384 static struct omap_hwmod dm81xx_tptc1_hwmod = {
1385         .name           = "tptc1",
1386         .class          = &dm81xx_tptc1_hwmod_class,
1387         .clkdm_name     = "alwon_l3s_clkdm",
1388         .main_clk       = "sysclk4_ck",
1389         .prcm           = {
1390                 .omap4  = {
1391                         .clkctrl_offs   = DM81XX_CM_ALWON_TPTC1_CLKCTRL,
1392                         .modulemode     = MODULEMODE_SWCTRL,
1393                 },
1394         },
1395 };
1396
1397 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc1 = {
1398         .master         = &dm81xx_alwon_l3_fast_hwmod,
1399         .slave          = &dm81xx_tptc1_hwmod,
1400         .clk            = "sysclk4_ck",
1401         .user           = OCP_USER_MPU,
1402 };
1403
1404 static struct omap_hwmod_ocp_if dm81xx_tptc1__alwon_l3_fast = {
1405         .master         = &dm81xx_tptc1_hwmod,
1406         .slave          = &dm81xx_alwon_l3_fast_hwmod,
1407         .clk            = "sysclk4_ck",
1408         .user           = OCP_USER_MPU,
1409 };
1410
1411 static struct omap_hwmod_class dm81xx_tptc2_hwmod_class = {
1412         .name           = "tptc2",
1413 };
1414
1415 static struct omap_hwmod dm81xx_tptc2_hwmod = {
1416         .name           = "tptc2",
1417         .class          = &dm81xx_tptc2_hwmod_class,
1418         .clkdm_name     = "alwon_l3s_clkdm",
1419         .main_clk       = "sysclk4_ck",
1420         .prcm           = {
1421                 .omap4  = {
1422                         .clkctrl_offs   = DM81XX_CM_ALWON_TPTC2_CLKCTRL,
1423                         .modulemode     = MODULEMODE_SWCTRL,
1424                 },
1425         },
1426 };
1427
1428 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc2 = {
1429         .master         = &dm81xx_alwon_l3_fast_hwmod,
1430         .slave          = &dm81xx_tptc2_hwmod,
1431         .clk            = "sysclk4_ck",
1432         .user           = OCP_USER_MPU,
1433 };
1434
1435 static struct omap_hwmod_ocp_if dm81xx_tptc2__alwon_l3_fast = {
1436         .master         = &dm81xx_tptc2_hwmod,
1437         .slave          = &dm81xx_alwon_l3_fast_hwmod,
1438         .clk            = "sysclk4_ck",
1439         .user           = OCP_USER_MPU,
1440 };
1441
1442 static struct omap_hwmod_class dm81xx_tptc3_hwmod_class = {
1443         .name           = "tptc3",
1444 };
1445
1446 static struct omap_hwmod dm81xx_tptc3_hwmod = {
1447         .name           = "tptc3",
1448         .class          = &dm81xx_tptc3_hwmod_class,
1449         .clkdm_name     = "alwon_l3s_clkdm",
1450         .main_clk       = "sysclk4_ck",
1451         .prcm           = {
1452                 .omap4  = {
1453                         .clkctrl_offs   = DM81XX_CM_ALWON_TPTC3_CLKCTRL,
1454                         .modulemode     = MODULEMODE_SWCTRL,
1455                 },
1456         },
1457 };
1458
1459 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc3 = {
1460         .master         = &dm81xx_alwon_l3_fast_hwmod,
1461         .slave          = &dm81xx_tptc3_hwmod,
1462         .clk            = "sysclk4_ck",
1463         .user           = OCP_USER_MPU,
1464 };
1465
1466 static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = {
1467         .master         = &dm81xx_tptc3_hwmod,
1468         .slave          = &dm81xx_alwon_l3_fast_hwmod,
1469         .clk            = "sysclk4_ck",
1470         .user           = OCP_USER_MPU,
1471 };
1472
1473 /*
1474  * REVISIT: Test and enable the following once clocks work:
1475  * dm81xx_l4_ls__mailbox
1476  *
1477  * Also note that some devices share a single clkctrl_offs..
1478  * For example, i2c1 and 3 share one, and i2c2 and 4 share one.
1479  */
1480 static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = {
1481         &dm814x_mpu__alwon_l3_slow,
1482         &dm814x_mpu__alwon_l3_med,
1483         &dm81xx_alwon_l3_slow__l4_ls,
1484         &dm81xx_alwon_l3_slow__l4_hs,
1485         &dm81xx_l4_ls__uart1,
1486         &dm81xx_l4_ls__uart2,
1487         &dm81xx_l4_ls__uart3,
1488         &dm81xx_l4_ls__wd_timer1,
1489         &dm81xx_l4_ls__i2c1,
1490         &dm81xx_l4_ls__i2c2,
1491         &dm81xx_l4_ls__gpio1,
1492         &dm81xx_l4_ls__gpio2,
1493         &dm81xx_l4_ls__gpio3,
1494         &dm81xx_l4_ls__gpio4,
1495         &dm81xx_l4_ls__elm,
1496         &dm81xx_l4_ls__mcspi1,
1497         &dm81xx_l4_ls__mcspi2,
1498         &dm81xx_l4_ls__mcspi3,
1499         &dm81xx_l4_ls__mcspi4,
1500         &dm814x_l4_ls__mmc1,
1501         &dm814x_l4_ls__mmc2,
1502         &ti81xx_l4_ls__rtc,
1503         &dm81xx_alwon_l3_fast__tpcc,
1504         &dm81xx_alwon_l3_fast__tptc0,
1505         &dm81xx_alwon_l3_fast__tptc1,
1506         &dm81xx_alwon_l3_fast__tptc2,
1507         &dm81xx_alwon_l3_fast__tptc3,
1508         &dm81xx_tptc0__alwon_l3_fast,
1509         &dm81xx_tptc1__alwon_l3_fast,
1510         &dm81xx_tptc2__alwon_l3_fast,
1511         &dm81xx_tptc3__alwon_l3_fast,
1512         &dm814x_l4_ls__timer1,
1513         &dm814x_l4_ls__timer2,
1514         &dm814x_l4_hs__cpgmac0,
1515         &dm814x_cpgmac0__mdio,
1516         &dm81xx_alwon_l3_slow__gpmc,
1517         &dm814x_default_l3_slow__usbss,
1518         &dm814x_alwon_l3_med__mmc3,
1519         NULL,
1520 };
1521
1522 int __init dm814x_hwmod_init(void)
1523 {
1524         omap_hwmod_init();
1525         return omap_hwmod_register_links(dm814x_hwmod_ocp_ifs);
1526 }
1527
1528 static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = {
1529         &dm816x_mpu__alwon_l3_slow,
1530         &dm816x_mpu__alwon_l3_med,
1531         &dm81xx_alwon_l3_slow__l4_ls,
1532         &dm81xx_alwon_l3_slow__l4_hs,
1533         &dm81xx_l4_ls__uart1,
1534         &dm81xx_l4_ls__uart2,
1535         &dm81xx_l4_ls__uart3,
1536         &dm81xx_l4_ls__wd_timer1,
1537         &dm81xx_l4_ls__i2c1,
1538         &dm81xx_l4_ls__i2c2,
1539         &dm81xx_l4_ls__gpio1,
1540         &dm81xx_l4_ls__gpio2,
1541         &dm81xx_l4_ls__elm,
1542         &ti81xx_l4_ls__rtc,
1543         &dm816x_l4_ls__mmc1,
1544         &dm816x_l4_ls__timer1,
1545         &dm816x_l4_ls__timer2,
1546         &dm816x_l4_ls__timer3,
1547         &dm816x_l4_ls__timer4,
1548         &dm816x_l4_ls__timer5,
1549         &dm816x_l4_ls__timer6,
1550         &dm816x_l4_ls__timer7,
1551         &dm81xx_l4_ls__mcspi1,
1552         &dm81xx_l4_ls__mailbox,
1553         &dm81xx_l4_ls__spinbox,
1554         &dm81xx_l4_hs__emac0,
1555         &dm81xx_emac0__mdio,
1556         &dm816x_l4_hs__emac1,
1557         &dm81xx_l4_hs__sata,
1558         &dm81xx_alwon_l3_fast__tpcc,
1559         &dm81xx_alwon_l3_fast__tptc0,
1560         &dm81xx_alwon_l3_fast__tptc1,
1561         &dm81xx_alwon_l3_fast__tptc2,
1562         &dm81xx_alwon_l3_fast__tptc3,
1563         &dm81xx_tptc0__alwon_l3_fast,
1564         &dm81xx_tptc1__alwon_l3_fast,
1565         &dm81xx_tptc2__alwon_l3_fast,
1566         &dm81xx_tptc3__alwon_l3_fast,
1567         &dm81xx_alwon_l3_slow__gpmc,
1568         &dm816x_default_l3_slow__usbss,
1569         NULL,
1570 };
1571
1572 int __init dm816x_hwmod_init(void)
1573 {
1574         omap_hwmod_init();
1575         return omap_hwmod_register_links(dm816x_hwmod_ocp_ifs);
1576 }