4 * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
5 * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #include <linux/types.h>
20 #include <linux/platform_data/hsmmc-omap.h>
22 #include "omap_hwmod_common_data.h"
28 * DM816X hardware modules integration data
30 * Note: This is incomplete and at present, not generated from h/w database.
34 * Common alwon .clkctrl_offs from dm814x TRM "Table 2-278. CM_ALWON REGISTERS"
35 * also dm816x TRM 18.7.17 CM_ALWON device register values minus 0x1400.
37 #define DM81XX_CM_ALWON_MCASP0_CLKCTRL 0x140
38 #define DM81XX_CM_ALWON_MCASP1_CLKCTRL 0x144
39 #define DM81XX_CM_ALWON_MCASP2_CLKCTRL 0x148
40 #define DM81XX_CM_ALWON_MCBSP_CLKCTRL 0x14c
41 #define DM81XX_CM_ALWON_UART_0_CLKCTRL 0x150
42 #define DM81XX_CM_ALWON_UART_1_CLKCTRL 0x154
43 #define DM81XX_CM_ALWON_UART_2_CLKCTRL 0x158
44 #define DM81XX_CM_ALWON_GPIO_0_CLKCTRL 0x15c
45 #define DM81XX_CM_ALWON_GPIO_1_CLKCTRL 0x160
46 #define DM81XX_CM_ALWON_I2C_0_CLKCTRL 0x164
47 #define DM81XX_CM_ALWON_I2C_1_CLKCTRL 0x168
48 #define DM81XX_CM_ALWON_WDTIMER_CLKCTRL 0x18c
49 #define DM81XX_CM_ALWON_SPI_CLKCTRL 0x190
50 #define DM81XX_CM_ALWON_MAILBOX_CLKCTRL 0x194
51 #define DM81XX_CM_ALWON_SPINBOX_CLKCTRL 0x198
52 #define DM81XX_CM_ALWON_MMUDATA_CLKCTRL 0x19c
53 #define DM81XX_CM_ALWON_MMUCFG_CLKCTRL 0x1a8
54 #define DM81XX_CM_ALWON_CONTROL_CLKCTRL 0x1c4
55 #define DM81XX_CM_ALWON_GPMC_CLKCTRL 0x1d0
56 #define DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL 0x1d4
57 #define DM81XX_CM_ALWON_L3_CLKCTRL 0x1e4
58 #define DM81XX_CM_ALWON_L4HS_CLKCTRL 0x1e8
59 #define DM81XX_CM_ALWON_L4LS_CLKCTRL 0x1ec
60 #define DM81XX_CM_ALWON_RTC_CLKCTRL 0x1f0
61 #define DM81XX_CM_ALWON_TPCC_CLKCTRL 0x1f4
62 #define DM81XX_CM_ALWON_TPTC0_CLKCTRL 0x1f8
63 #define DM81XX_CM_ALWON_TPTC1_CLKCTRL 0x1fc
64 #define DM81XX_CM_ALWON_TPTC2_CLKCTRL 0x200
65 #define DM81XX_CM_ALWON_TPTC3_CLKCTRL 0x204
67 /* Registers specific to dm814x */
68 #define DM814X_CM_ALWON_MCASP_3_4_5_CLKCTRL 0x16c
69 #define DM814X_CM_ALWON_ATL_CLKCTRL 0x170
70 #define DM814X_CM_ALWON_MLB_CLKCTRL 0x174
71 #define DM814X_CM_ALWON_PATA_CLKCTRL 0x178
72 #define DM814X_CM_ALWON_UART_3_CLKCTRL 0x180
73 #define DM814X_CM_ALWON_UART_4_CLKCTRL 0x184
74 #define DM814X_CM_ALWON_UART_5_CLKCTRL 0x188
75 #define DM814X_CM_ALWON_OCM_0_CLKCTRL 0x1b4
76 #define DM814X_CM_ALWON_VCP_CLKCTRL 0x1b8
77 #define DM814X_CM_ALWON_MPU_CLKCTRL 0x1dc
78 #define DM814X_CM_ALWON_DEBUGSS_CLKCTRL 0x1e0
79 #define DM814X_CM_ALWON_DCAN_0_1_CLKCTRL 0x218
80 #define DM814X_CM_ALWON_MMCHS_0_CLKCTRL 0x21c
81 #define DM814X_CM_ALWON_MMCHS_1_CLKCTRL 0x220
82 #define DM814X_CM_ALWON_MMCHS_2_CLKCTRL 0x224
83 #define DM814X_CM_ALWON_CUST_EFUSE_CLKCTRL 0x228
85 /* Registers specific to dm816x */
86 #define DM816X_DM_ALWON_BASE 0x1400
87 #define DM816X_CM_ALWON_TIMER_1_CLKCTRL (0x1570 - DM816X_DM_ALWON_BASE)
88 #define DM816X_CM_ALWON_TIMER_2_CLKCTRL (0x1574 - DM816X_DM_ALWON_BASE)
89 #define DM816X_CM_ALWON_TIMER_3_CLKCTRL (0x1578 - DM816X_DM_ALWON_BASE)
90 #define DM816X_CM_ALWON_TIMER_4_CLKCTRL (0x157c - DM816X_DM_ALWON_BASE)
91 #define DM816X_CM_ALWON_TIMER_5_CLKCTRL (0x1580 - DM816X_DM_ALWON_BASE)
92 #define DM816X_CM_ALWON_TIMER_6_CLKCTRL (0x1584 - DM816X_DM_ALWON_BASE)
93 #define DM816X_CM_ALWON_TIMER_7_CLKCTRL (0x1588 - DM816X_DM_ALWON_BASE)
94 #define DM816X_CM_ALWON_SDIO_CLKCTRL (0x15b0 - DM816X_DM_ALWON_BASE)
95 #define DM816X_CM_ALWON_OCMC_0_CLKCTRL (0x15b4 - DM816X_DM_ALWON_BASE)
96 #define DM816X_CM_ALWON_OCMC_1_CLKCTRL (0x15b8 - DM816X_DM_ALWON_BASE)
97 #define DM816X_CM_ALWON_ETHERNET_1_CLKCTRL (0x15d8 - DM816X_DM_ALWON_BASE)
98 #define DM816X_CM_ALWON_MPU_CLKCTRL (0x15dc - DM816X_DM_ALWON_BASE)
99 #define DM816X_CM_ALWON_SR_0_CLKCTRL (0x1608 - DM816X_DM_ALWON_BASE)
100 #define DM816X_CM_ALWON_SR_1_CLKCTRL (0x160c - DM816X_DM_ALWON_BASE)
103 * The default .clkctrl_offs field is offset from CM_DEFAULT, that's
104 * TRM 18.7.6 CM_DEFAULT device register values minus 0x500
106 #define DM81XX_CM_DEFAULT_OFFSET 0x500
107 #define DM81XX_CM_DEFAULT_USB_CLKCTRL (0x558 - DM81XX_CM_DEFAULT_OFFSET)
108 #define DM81XX_CM_DEFAULT_SATA_CLKCTRL (0x560 - DM81XX_CM_DEFAULT_OFFSET)
110 /* L3 Interconnect entries clocked at 125, 250 and 500MHz */
111 static struct omap_hwmod dm81xx_alwon_l3_slow_hwmod = {
112 .name = "alwon_l3_slow",
113 .clkdm_name = "alwon_l3s_clkdm",
114 .class = &l3_hwmod_class,
115 .flags = HWMOD_NO_IDLEST,
118 static struct omap_hwmod dm81xx_default_l3_slow_hwmod = {
119 .name = "default_l3_slow",
120 .clkdm_name = "default_l3_slow_clkdm",
121 .class = &l3_hwmod_class,
122 .flags = HWMOD_NO_IDLEST,
125 static struct omap_hwmod dm81xx_alwon_l3_med_hwmod = {
127 .clkdm_name = "alwon_l3_med_clkdm",
128 .class = &l3_hwmod_class,
129 .flags = HWMOD_NO_IDLEST,
132 static struct omap_hwmod dm81xx_alwon_l3_fast_hwmod = {
134 .clkdm_name = "alwon_l3_fast_clkdm",
135 .class = &l3_hwmod_class,
136 .flags = HWMOD_NO_IDLEST,
140 * L4 standard peripherals, see TRM table 1-12 for devices using this.
141 * See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock.
143 static struct omap_hwmod dm81xx_l4_ls_hwmod = {
145 .clkdm_name = "alwon_l3s_clkdm",
146 .class = &l4_hwmod_class,
147 .flags = HWMOD_NO_IDLEST,
151 * L4 high-speed peripherals. For devices using this, please see the TRM
152 * table 1-13. On dm816x, only EMAC, MDIO and SATA use this. See also TRM
153 * table 1-73 for devices using 250MHz SYSCLK5 clock.
155 static struct omap_hwmod dm81xx_l4_hs_hwmod = {
157 .clkdm_name = "alwon_l3_med_clkdm",
158 .class = &l4_hwmod_class,
159 .flags = HWMOD_NO_IDLEST,
162 /* L3 slow -> L4 ls peripheral interface running at 125MHz */
163 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_ls = {
164 .master = &dm81xx_alwon_l3_slow_hwmod,
165 .slave = &dm81xx_l4_ls_hwmod,
166 .user = OCP_USER_MPU,
169 /* L3 med -> L4 fast peripheral interface running at 250MHz */
170 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_hs = {
171 .master = &dm81xx_alwon_l3_med_hwmod,
172 .slave = &dm81xx_l4_hs_hwmod,
173 .user = OCP_USER_MPU,
177 static struct omap_hwmod dm814x_mpu_hwmod = {
179 .clkdm_name = "alwon_l3s_clkdm",
180 .class = &mpu_hwmod_class,
181 .flags = HWMOD_INIT_NO_IDLE,
182 .main_clk = "mpu_ck",
185 .clkctrl_offs = DM814X_CM_ALWON_MPU_CLKCTRL,
186 .modulemode = MODULEMODE_SWCTRL,
191 static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_slow = {
192 .master = &dm814x_mpu_hwmod,
193 .slave = &dm81xx_alwon_l3_slow_hwmod,
194 .user = OCP_USER_MPU,
197 /* L3 med peripheral interface running at 200MHz */
198 static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_med = {
199 .master = &dm814x_mpu_hwmod,
200 .slave = &dm81xx_alwon_l3_med_hwmod,
201 .user = OCP_USER_MPU,
204 static struct omap_hwmod dm816x_mpu_hwmod = {
206 .clkdm_name = "alwon_mpu_clkdm",
207 .class = &mpu_hwmod_class,
208 .flags = HWMOD_INIT_NO_IDLE,
209 .main_clk = "mpu_ck",
212 .clkctrl_offs = DM816X_CM_ALWON_MPU_CLKCTRL,
213 .modulemode = MODULEMODE_SWCTRL,
218 static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_slow = {
219 .master = &dm816x_mpu_hwmod,
220 .slave = &dm81xx_alwon_l3_slow_hwmod,
221 .user = OCP_USER_MPU,
224 /* L3 med peripheral interface running at 250MHz */
225 static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_med = {
226 .master = &dm816x_mpu_hwmod,
227 .slave = &dm81xx_alwon_l3_med_hwmod,
228 .user = OCP_USER_MPU,
232 static struct omap_hwmod_class_sysconfig ti81xx_rtc_sysc = {
235 .sysc_flags = SYSC_HAS_SIDLEMODE,
236 .idlemodes = SIDLE_FORCE | SIDLE_NO |
237 SIDLE_SMART | SIDLE_SMART_WKUP,
238 .sysc_fields = &omap_hwmod_sysc_type3,
241 static struct omap_hwmod_class ti81xx_rtc_hwmod_class = {
243 .sysc = &ti81xx_rtc_sysc,
246 static struct omap_hwmod ti81xx_rtc_hwmod = {
248 .class = &ti81xx_rtc_hwmod_class,
249 .clkdm_name = "alwon_l3s_clkdm",
250 .flags = HWMOD_NO_IDLEST,
251 .main_clk = "sysclk18_ck",
254 .clkctrl_offs = DM81XX_CM_ALWON_RTC_CLKCTRL,
255 .modulemode = MODULEMODE_SWCTRL,
260 static struct omap_hwmod_ocp_if ti81xx_l4_ls__rtc = {
261 .master = &dm81xx_l4_ls_hwmod,
262 .slave = &ti81xx_rtc_hwmod,
264 .user = OCP_USER_MPU,
268 static struct omap_hwmod_class_sysconfig uart_sysc = {
272 .sysc_flags = SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
273 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
274 SYSS_HAS_RESET_STATUS,
275 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
277 .sysc_fields = &omap_hwmod_sysc_type1,
280 static struct omap_hwmod_class uart_class = {
285 static struct omap_hwmod dm81xx_uart1_hwmod = {
287 .clkdm_name = "alwon_l3s_clkdm",
288 .main_clk = "sysclk10_ck",
291 .clkctrl_offs = DM81XX_CM_ALWON_UART_0_CLKCTRL,
292 .modulemode = MODULEMODE_SWCTRL,
295 .class = &uart_class,
296 .flags = DEBUG_TI81XXUART1_FLAGS,
299 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart1 = {
300 .master = &dm81xx_l4_ls_hwmod,
301 .slave = &dm81xx_uart1_hwmod,
303 .user = OCP_USER_MPU,
306 static struct omap_hwmod dm81xx_uart2_hwmod = {
308 .clkdm_name = "alwon_l3s_clkdm",
309 .main_clk = "sysclk10_ck",
312 .clkctrl_offs = DM81XX_CM_ALWON_UART_1_CLKCTRL,
313 .modulemode = MODULEMODE_SWCTRL,
316 .class = &uart_class,
317 .flags = DEBUG_TI81XXUART2_FLAGS,
320 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart2 = {
321 .master = &dm81xx_l4_ls_hwmod,
322 .slave = &dm81xx_uart2_hwmod,
324 .user = OCP_USER_MPU,
327 static struct omap_hwmod dm81xx_uart3_hwmod = {
329 .clkdm_name = "alwon_l3s_clkdm",
330 .main_clk = "sysclk10_ck",
333 .clkctrl_offs = DM81XX_CM_ALWON_UART_2_CLKCTRL,
334 .modulemode = MODULEMODE_SWCTRL,
337 .class = &uart_class,
338 .flags = DEBUG_TI81XXUART3_FLAGS,
341 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart3 = {
342 .master = &dm81xx_l4_ls_hwmod,
343 .slave = &dm81xx_uart3_hwmod,
345 .user = OCP_USER_MPU,
348 static struct omap_hwmod_class_sysconfig wd_timer_sysc = {
352 .sysc_flags = SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
353 SYSS_HAS_RESET_STATUS,
354 .sysc_fields = &omap_hwmod_sysc_type1,
357 static struct omap_hwmod_class wd_timer_class = {
359 .sysc = &wd_timer_sysc,
360 .pre_shutdown = &omap2_wd_timer_disable,
361 .reset = &omap2_wd_timer_reset,
364 static struct omap_hwmod dm81xx_wd_timer_hwmod = {
366 .clkdm_name = "alwon_l3s_clkdm",
367 .main_clk = "sysclk18_ck",
368 .flags = HWMOD_NO_IDLEST,
371 .clkctrl_offs = DM81XX_CM_ALWON_WDTIMER_CLKCTRL,
372 .modulemode = MODULEMODE_SWCTRL,
375 .class = &wd_timer_class,
378 static struct omap_hwmod_ocp_if dm81xx_l4_ls__wd_timer1 = {
379 .master = &dm81xx_l4_ls_hwmod,
380 .slave = &dm81xx_wd_timer_hwmod,
382 .user = OCP_USER_MPU,
386 static struct omap_hwmod_class_sysconfig i2c_sysc = {
390 .sysc_flags = SYSC_HAS_SIDLEMODE |
391 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
393 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
394 .sysc_fields = &omap_hwmod_sysc_type1,
397 static struct omap_hwmod_class i2c_class = {
402 static struct omap_hwmod dm81xx_i2c1_hwmod = {
404 .clkdm_name = "alwon_l3s_clkdm",
405 .main_clk = "sysclk10_ck",
408 .clkctrl_offs = DM81XX_CM_ALWON_I2C_0_CLKCTRL,
409 .modulemode = MODULEMODE_SWCTRL,
415 static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c1 = {
416 .master = &dm81xx_l4_ls_hwmod,
417 .slave = &dm81xx_i2c1_hwmod,
419 .user = OCP_USER_MPU,
422 static struct omap_hwmod dm81xx_i2c2_hwmod = {
424 .clkdm_name = "alwon_l3s_clkdm",
425 .main_clk = "sysclk10_ck",
428 .clkctrl_offs = DM81XX_CM_ALWON_I2C_1_CLKCTRL,
429 .modulemode = MODULEMODE_SWCTRL,
435 static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c2 = {
436 .master = &dm81xx_l4_ls_hwmod,
437 .slave = &dm81xx_i2c2_hwmod,
439 .user = OCP_USER_MPU,
442 static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = {
446 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
448 SYSS_HAS_RESET_STATUS,
449 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
450 .sysc_fields = &omap_hwmod_sysc_type1,
453 static struct omap_hwmod_class dm81xx_elm_hwmod_class = {
455 .sysc = &dm81xx_elm_sysc,
458 static struct omap_hwmod dm81xx_elm_hwmod = {
460 .clkdm_name = "alwon_l3s_clkdm",
461 .class = &dm81xx_elm_hwmod_class,
462 .main_clk = "sysclk6_ck",
465 static struct omap_hwmod_ocp_if dm81xx_l4_ls__elm = {
466 .master = &dm81xx_l4_ls_hwmod,
467 .slave = &dm81xx_elm_hwmod,
469 .user = OCP_USER_MPU,
472 static struct omap_hwmod_class_sysconfig dm81xx_gpio_sysc = {
476 .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
477 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
478 SYSS_HAS_RESET_STATUS,
479 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
481 .sysc_fields = &omap_hwmod_sysc_type1,
484 static struct omap_hwmod_class dm81xx_gpio_hwmod_class = {
486 .sysc = &dm81xx_gpio_sysc,
490 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
491 { .role = "dbclk", .clk = "sysclk18_ck" },
494 static struct omap_hwmod dm81xx_gpio1_hwmod = {
496 .clkdm_name = "alwon_l3s_clkdm",
497 .class = &dm81xx_gpio_hwmod_class,
498 .main_clk = "sysclk6_ck",
501 .clkctrl_offs = DM81XX_CM_ALWON_GPIO_0_CLKCTRL,
502 .modulemode = MODULEMODE_SWCTRL,
505 .opt_clks = gpio1_opt_clks,
506 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
509 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio1 = {
510 .master = &dm81xx_l4_ls_hwmod,
511 .slave = &dm81xx_gpio1_hwmod,
513 .user = OCP_USER_MPU,
516 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
517 { .role = "dbclk", .clk = "sysclk18_ck" },
520 static struct omap_hwmod dm81xx_gpio2_hwmod = {
522 .clkdm_name = "alwon_l3s_clkdm",
523 .class = &dm81xx_gpio_hwmod_class,
524 .main_clk = "sysclk6_ck",
527 .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL,
528 .modulemode = MODULEMODE_SWCTRL,
531 .opt_clks = gpio2_opt_clks,
532 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
535 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = {
536 .master = &dm81xx_l4_ls_hwmod,
537 .slave = &dm81xx_gpio2_hwmod,
539 .user = OCP_USER_MPU,
542 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
543 { .role = "dbclk", .clk = "sysclk18_ck" },
546 static struct omap_hwmod dm81xx_gpio3_hwmod = {
548 .clkdm_name = "alwon_l3s_clkdm",
549 .class = &dm81xx_gpio_hwmod_class,
550 .main_clk = "sysclk6_ck",
553 .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL,
554 .modulemode = MODULEMODE_SWCTRL,
557 .opt_clks = gpio3_opt_clks,
558 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
561 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio3 = {
562 .master = &dm81xx_l4_ls_hwmod,
563 .slave = &dm81xx_gpio3_hwmod,
565 .user = OCP_USER_MPU,
568 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
569 { .role = "dbclk", .clk = "sysclk18_ck" },
572 static struct omap_hwmod dm81xx_gpio4_hwmod = {
574 .clkdm_name = "alwon_l3s_clkdm",
575 .class = &dm81xx_gpio_hwmod_class,
576 .main_clk = "sysclk6_ck",
579 .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL,
580 .modulemode = MODULEMODE_SWCTRL,
583 .opt_clks = gpio4_opt_clks,
584 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
587 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio4 = {
588 .master = &dm81xx_l4_ls_hwmod,
589 .slave = &dm81xx_gpio4_hwmod,
591 .user = OCP_USER_MPU,
594 static struct omap_hwmod_class_sysconfig dm81xx_gpmc_sysc = {
598 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
599 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
600 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
601 .sysc_fields = &omap_hwmod_sysc_type1,
604 static struct omap_hwmod_class dm81xx_gpmc_hwmod_class = {
606 .sysc = &dm81xx_gpmc_sysc,
609 static struct omap_hwmod dm81xx_gpmc_hwmod = {
611 .clkdm_name = "alwon_l3s_clkdm",
612 .class = &dm81xx_gpmc_hwmod_class,
613 .main_clk = "sysclk6_ck",
614 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
615 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
618 .clkctrl_offs = DM81XX_CM_ALWON_GPMC_CLKCTRL,
619 .modulemode = MODULEMODE_SWCTRL,
624 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__gpmc = {
625 .master = &dm81xx_alwon_l3_slow_hwmod,
626 .slave = &dm81xx_gpmc_hwmod,
627 .user = OCP_USER_MPU,
630 /* USB needs udelay 1 after reset at least on hp t410, use 2 for margin */
631 static struct omap_hwmod_class_sysconfig dm81xx_usbhsotg_sysc = {
635 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
637 .idlemodes = SIDLE_SMART | MSTANDBY_FORCE | MSTANDBY_SMART,
638 .sysc_fields = &omap_hwmod_sysc_type2,
641 static struct omap_hwmod_class dm81xx_usbotg_class = {
643 .sysc = &dm81xx_usbhsotg_sysc,
646 static struct omap_hwmod dm814x_usbss_hwmod = {
647 .name = "usb_otg_hs",
648 .clkdm_name = "default_l3_slow_clkdm",
649 .main_clk = "pll260dcoclkldo", /* 481c5260.adpll.dcoclkldo */
652 .clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL,
653 .modulemode = MODULEMODE_SWCTRL,
656 .class = &dm81xx_usbotg_class,
659 static struct omap_hwmod_ocp_if dm814x_default_l3_slow__usbss = {
660 .master = &dm81xx_default_l3_slow_hwmod,
661 .slave = &dm814x_usbss_hwmod,
663 .user = OCP_USER_MPU,
666 static struct omap_hwmod dm816x_usbss_hwmod = {
667 .name = "usb_otg_hs",
668 .clkdm_name = "default_l3_slow_clkdm",
669 .main_clk = "sysclk6_ck",
672 .clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL,
673 .modulemode = MODULEMODE_SWCTRL,
676 .class = &dm81xx_usbotg_class,
679 static struct omap_hwmod_ocp_if dm816x_default_l3_slow__usbss = {
680 .master = &dm81xx_default_l3_slow_hwmod,
681 .slave = &dm816x_usbss_hwmod,
683 .user = OCP_USER_MPU,
686 static struct omap_hwmod_class_sysconfig dm816x_timer_sysc = {
690 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET,
691 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
693 .sysc_fields = &omap_hwmod_sysc_type2,
696 static struct omap_hwmod_class dm816x_timer_hwmod_class = {
698 .sysc = &dm816x_timer_sysc,
701 static struct omap_hwmod dm814x_timer1_hwmod = {
703 .clkdm_name = "alwon_l3s_clkdm",
704 .main_clk = "timer1_fck",
705 .class = &dm816x_timer_hwmod_class,
706 .flags = HWMOD_NO_IDLEST,
709 static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = {
710 .master = &dm81xx_l4_ls_hwmod,
711 .slave = &dm814x_timer1_hwmod,
713 .user = OCP_USER_MPU,
716 static struct omap_hwmod dm816x_timer1_hwmod = {
718 .clkdm_name = "alwon_l3s_clkdm",
719 .main_clk = "timer1_fck",
722 .clkctrl_offs = DM816X_CM_ALWON_TIMER_1_CLKCTRL,
723 .modulemode = MODULEMODE_SWCTRL,
726 .class = &dm816x_timer_hwmod_class,
729 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = {
730 .master = &dm81xx_l4_ls_hwmod,
731 .slave = &dm816x_timer1_hwmod,
733 .user = OCP_USER_MPU,
736 static struct omap_hwmod dm814x_timer2_hwmod = {
738 .clkdm_name = "alwon_l3s_clkdm",
739 .main_clk = "timer2_fck",
740 .class = &dm816x_timer_hwmod_class,
741 .flags = HWMOD_NO_IDLEST,
744 static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = {
745 .master = &dm81xx_l4_ls_hwmod,
746 .slave = &dm814x_timer2_hwmod,
748 .user = OCP_USER_MPU,
751 static struct omap_hwmod dm816x_timer2_hwmod = {
753 .clkdm_name = "alwon_l3s_clkdm",
754 .main_clk = "timer2_fck",
757 .clkctrl_offs = DM816X_CM_ALWON_TIMER_2_CLKCTRL,
758 .modulemode = MODULEMODE_SWCTRL,
761 .class = &dm816x_timer_hwmod_class,
764 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer2 = {
765 .master = &dm81xx_l4_ls_hwmod,
766 .slave = &dm816x_timer2_hwmod,
768 .user = OCP_USER_MPU,
771 static struct omap_hwmod dm816x_timer3_hwmod = {
773 .clkdm_name = "alwon_l3s_clkdm",
774 .main_clk = "timer3_fck",
777 .clkctrl_offs = DM816X_CM_ALWON_TIMER_3_CLKCTRL,
778 .modulemode = MODULEMODE_SWCTRL,
781 .class = &dm816x_timer_hwmod_class,
784 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer3 = {
785 .master = &dm81xx_l4_ls_hwmod,
786 .slave = &dm816x_timer3_hwmod,
788 .user = OCP_USER_MPU,
791 static struct omap_hwmod dm816x_timer4_hwmod = {
793 .clkdm_name = "alwon_l3s_clkdm",
794 .main_clk = "timer4_fck",
797 .clkctrl_offs = DM816X_CM_ALWON_TIMER_4_CLKCTRL,
798 .modulemode = MODULEMODE_SWCTRL,
801 .class = &dm816x_timer_hwmod_class,
804 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer4 = {
805 .master = &dm81xx_l4_ls_hwmod,
806 .slave = &dm816x_timer4_hwmod,
808 .user = OCP_USER_MPU,
811 static struct omap_hwmod dm816x_timer5_hwmod = {
813 .clkdm_name = "alwon_l3s_clkdm",
814 .main_clk = "timer5_fck",
817 .clkctrl_offs = DM816X_CM_ALWON_TIMER_5_CLKCTRL,
818 .modulemode = MODULEMODE_SWCTRL,
821 .class = &dm816x_timer_hwmod_class,
824 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer5 = {
825 .master = &dm81xx_l4_ls_hwmod,
826 .slave = &dm816x_timer5_hwmod,
828 .user = OCP_USER_MPU,
831 static struct omap_hwmod dm816x_timer6_hwmod = {
833 .clkdm_name = "alwon_l3s_clkdm",
834 .main_clk = "timer6_fck",
837 .clkctrl_offs = DM816X_CM_ALWON_TIMER_6_CLKCTRL,
838 .modulemode = MODULEMODE_SWCTRL,
841 .class = &dm816x_timer_hwmod_class,
844 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer6 = {
845 .master = &dm81xx_l4_ls_hwmod,
846 .slave = &dm816x_timer6_hwmod,
848 .user = OCP_USER_MPU,
851 static struct omap_hwmod dm816x_timer7_hwmod = {
853 .clkdm_name = "alwon_l3s_clkdm",
854 .main_clk = "timer7_fck",
857 .clkctrl_offs = DM816X_CM_ALWON_TIMER_7_CLKCTRL,
858 .modulemode = MODULEMODE_SWCTRL,
861 .class = &dm816x_timer_hwmod_class,
864 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer7 = {
865 .master = &dm81xx_l4_ls_hwmod,
866 .slave = &dm816x_timer7_hwmod,
868 .user = OCP_USER_MPU,
872 static struct omap_hwmod_class_sysconfig dm814x_cpgmac_sysc = {
876 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
877 SYSS_HAS_RESET_STATUS,
878 .idlemodes = SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
880 .sysc_fields = &omap_hwmod_sysc_type3,
883 static struct omap_hwmod_class dm814x_cpgmac0_hwmod_class = {
885 .sysc = &dm814x_cpgmac_sysc,
888 static struct omap_hwmod dm814x_cpgmac0_hwmod = {
890 .class = &dm814x_cpgmac0_hwmod_class,
891 .clkdm_name = "alwon_ethernet_clkdm",
892 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
893 .main_clk = "cpsw_125mhz_gclk",
896 .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL,
897 .modulemode = MODULEMODE_SWCTRL,
902 static struct omap_hwmod_class dm814x_mdio_hwmod_class = {
903 .name = "davinci_mdio",
906 static struct omap_hwmod dm814x_mdio_hwmod = {
907 .name = "davinci_mdio",
908 .class = &dm814x_mdio_hwmod_class,
909 .clkdm_name = "alwon_ethernet_clkdm",
910 .main_clk = "cpsw_125mhz_gclk",
913 static struct omap_hwmod_ocp_if dm814x_l4_hs__cpgmac0 = {
914 .master = &dm81xx_l4_hs_hwmod,
915 .slave = &dm814x_cpgmac0_hwmod,
916 .clk = "cpsw_125mhz_gclk",
917 .user = OCP_USER_MPU,
920 static struct omap_hwmod_ocp_if dm814x_cpgmac0__mdio = {
921 .master = &dm814x_cpgmac0_hwmod,
922 .slave = &dm814x_mdio_hwmod,
923 .user = OCP_USER_MPU,
924 .flags = HWMOD_NO_IDLEST,
928 static struct omap_hwmod_class_sysconfig dm816x_emac_sysc = {
931 .sysc_flags = SYSC_HAS_SOFTRESET,
932 .sysc_fields = &omap_hwmod_sysc_type2,
935 static struct omap_hwmod_class dm816x_emac_hwmod_class = {
937 .sysc = &dm816x_emac_sysc,
941 * On dm816x the MDIO is within EMAC0. As the MDIO driver is a separate
942 * driver probed before EMAC0, we let MDIO do the clock idling.
944 static struct omap_hwmod dm816x_emac0_hwmod = {
946 .clkdm_name = "alwon_ethernet_clkdm",
947 .class = &dm816x_emac_hwmod_class,
948 .flags = HWMOD_NO_IDLEST,
951 static struct omap_hwmod_ocp_if dm81xx_l4_hs__emac0 = {
952 .master = &dm81xx_l4_hs_hwmod,
953 .slave = &dm816x_emac0_hwmod,
955 .user = OCP_USER_MPU,
958 static struct omap_hwmod_class dm81xx_mdio_hwmod_class = {
959 .name = "davinci_mdio",
960 .sysc = &dm816x_emac_sysc,
963 static struct omap_hwmod dm81xx_emac0_mdio_hwmod = {
964 .name = "davinci_mdio",
965 .class = &dm81xx_mdio_hwmod_class,
966 .clkdm_name = "alwon_ethernet_clkdm",
967 .main_clk = "sysclk24_ck",
968 .flags = HWMOD_NO_IDLEST,
970 * REVISIT: This should be moved to the emac0_hwmod
971 * once we have a better way to handle device slaves.
975 .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL,
976 .modulemode = MODULEMODE_SWCTRL,
981 static struct omap_hwmod_ocp_if dm81xx_emac0__mdio = {
982 .master = &dm81xx_l4_hs_hwmod,
983 .slave = &dm81xx_emac0_mdio_hwmod,
984 .user = OCP_USER_MPU,
987 static struct omap_hwmod dm816x_emac1_hwmod = {
989 .clkdm_name = "alwon_ethernet_clkdm",
990 .main_clk = "sysclk24_ck",
991 .flags = HWMOD_NO_IDLEST,
994 .clkctrl_offs = DM816X_CM_ALWON_ETHERNET_1_CLKCTRL,
995 .modulemode = MODULEMODE_SWCTRL,
998 .class = &dm816x_emac_hwmod_class,
1001 static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = {
1002 .master = &dm81xx_l4_hs_hwmod,
1003 .slave = &dm816x_emac1_hwmod,
1004 .clk = "sysclk5_ck",
1005 .user = OCP_USER_MPU,
1008 static struct omap_hwmod_class_sysconfig dm81xx_sata_sysc = {
1010 .sysc_offs = 0x1100,
1011 .sysc_flags = SYSC_HAS_SIDLEMODE,
1012 .idlemodes = SIDLE_FORCE,
1013 .sysc_fields = &omap_hwmod_sysc_type3,
1016 static struct omap_hwmod_class dm81xx_sata_hwmod_class = {
1018 .sysc = &dm81xx_sata_sysc,
1021 static struct omap_hwmod dm81xx_sata_hwmod = {
1023 .clkdm_name = "default_clkdm",
1024 .flags = HWMOD_NO_IDLEST,
1027 .clkctrl_offs = DM81XX_CM_DEFAULT_SATA_CLKCTRL,
1028 .modulemode = MODULEMODE_SWCTRL,
1031 .class = &dm81xx_sata_hwmod_class,
1034 static struct omap_hwmod_ocp_if dm81xx_l4_hs__sata = {
1035 .master = &dm81xx_l4_hs_hwmod,
1036 .slave = &dm81xx_sata_hwmod,
1037 .clk = "sysclk5_ck",
1038 .user = OCP_USER_MPU,
1041 static struct omap_hwmod_class_sysconfig dm81xx_mmc_sysc = {
1045 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1046 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1047 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
1048 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1049 .sysc_fields = &omap_hwmod_sysc_type1,
1052 static struct omap_hwmod_class dm81xx_mmc_class = {
1054 .sysc = &dm81xx_mmc_sysc,
1057 static struct omap_hwmod_opt_clk dm81xx_mmc_opt_clks[] = {
1058 { .role = "dbck", .clk = "sysclk18_ck", },
1061 static struct omap_hsmmc_dev_attr mmc_dev_attr = {
1064 static struct omap_hwmod dm814x_mmc1_hwmod = {
1066 .clkdm_name = "alwon_l3s_clkdm",
1067 .opt_clks = dm81xx_mmc_opt_clks,
1068 .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks),
1069 .main_clk = "sysclk8_ck",
1072 .clkctrl_offs = DM814X_CM_ALWON_MMCHS_0_CLKCTRL,
1073 .modulemode = MODULEMODE_SWCTRL,
1076 .dev_attr = &mmc_dev_attr,
1077 .class = &dm81xx_mmc_class,
1080 static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc1 = {
1081 .master = &dm81xx_l4_ls_hwmod,
1082 .slave = &dm814x_mmc1_hwmod,
1083 .clk = "sysclk6_ck",
1084 .user = OCP_USER_MPU,
1085 .flags = OMAP_FIREWALL_L4
1088 static struct omap_hwmod dm814x_mmc2_hwmod = {
1090 .clkdm_name = "alwon_l3s_clkdm",
1091 .opt_clks = dm81xx_mmc_opt_clks,
1092 .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks),
1093 .main_clk = "sysclk8_ck",
1096 .clkctrl_offs = DM814X_CM_ALWON_MMCHS_1_CLKCTRL,
1097 .modulemode = MODULEMODE_SWCTRL,
1100 .dev_attr = &mmc_dev_attr,
1101 .class = &dm81xx_mmc_class,
1104 static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc2 = {
1105 .master = &dm81xx_l4_ls_hwmod,
1106 .slave = &dm814x_mmc2_hwmod,
1107 .clk = "sysclk6_ck",
1108 .user = OCP_USER_MPU,
1109 .flags = OMAP_FIREWALL_L4
1112 static struct omap_hwmod dm814x_mmc3_hwmod = {
1114 .clkdm_name = "alwon_l3_med_clkdm",
1115 .opt_clks = dm81xx_mmc_opt_clks,
1116 .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks),
1117 .main_clk = "sysclk8_ck",
1120 .clkctrl_offs = DM814X_CM_ALWON_MMCHS_2_CLKCTRL,
1121 .modulemode = MODULEMODE_SWCTRL,
1124 .dev_attr = &mmc_dev_attr,
1125 .class = &dm81xx_mmc_class,
1128 static struct omap_hwmod_ocp_if dm814x_alwon_l3_med__mmc3 = {
1129 .master = &dm81xx_alwon_l3_med_hwmod,
1130 .slave = &dm814x_mmc3_hwmod,
1131 .clk = "sysclk4_ck",
1132 .user = OCP_USER_MPU,
1135 static struct omap_hwmod dm816x_mmc1_hwmod = {
1137 .clkdm_name = "alwon_l3s_clkdm",
1138 .opt_clks = dm81xx_mmc_opt_clks,
1139 .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks),
1140 .main_clk = "sysclk10_ck",
1143 .clkctrl_offs = DM816X_CM_ALWON_SDIO_CLKCTRL,
1144 .modulemode = MODULEMODE_SWCTRL,
1147 .dev_attr = &mmc_dev_attr,
1148 .class = &dm81xx_mmc_class,
1151 static struct omap_hwmod_ocp_if dm816x_l4_ls__mmc1 = {
1152 .master = &dm81xx_l4_ls_hwmod,
1153 .slave = &dm816x_mmc1_hwmod,
1154 .clk = "sysclk6_ck",
1155 .user = OCP_USER_MPU,
1156 .flags = OMAP_FIREWALL_L4
1159 static struct omap_hwmod_class_sysconfig dm816x_mcspi_sysc = {
1163 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1164 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1165 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
1166 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1167 .sysc_fields = &omap_hwmod_sysc_type1,
1170 static struct omap_hwmod_class dm816x_mcspi_class = {
1172 .sysc = &dm816x_mcspi_sysc,
1175 static struct omap_hwmod dm81xx_mcspi1_hwmod = {
1177 .clkdm_name = "alwon_l3s_clkdm",
1178 .main_clk = "sysclk10_ck",
1181 .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
1182 .modulemode = MODULEMODE_SWCTRL,
1185 .class = &dm816x_mcspi_class,
1188 static struct omap_hwmod dm81xx_mcspi2_hwmod = {
1190 .clkdm_name = "alwon_l3s_clkdm",
1191 .main_clk = "sysclk10_ck",
1194 .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
1195 .modulemode = MODULEMODE_SWCTRL,
1198 .class = &dm816x_mcspi_class,
1201 static struct omap_hwmod dm81xx_mcspi3_hwmod = {
1203 .clkdm_name = "alwon_l3s_clkdm",
1204 .main_clk = "sysclk10_ck",
1207 .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
1208 .modulemode = MODULEMODE_SWCTRL,
1211 .class = &dm816x_mcspi_class,
1214 static struct omap_hwmod dm81xx_mcspi4_hwmod = {
1216 .clkdm_name = "alwon_l3s_clkdm",
1217 .main_clk = "sysclk10_ck",
1220 .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
1221 .modulemode = MODULEMODE_SWCTRL,
1224 .class = &dm816x_mcspi_class,
1227 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = {
1228 .master = &dm81xx_l4_ls_hwmod,
1229 .slave = &dm81xx_mcspi1_hwmod,
1230 .clk = "sysclk6_ck",
1231 .user = OCP_USER_MPU,
1234 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi2 = {
1235 .master = &dm81xx_l4_ls_hwmod,
1236 .slave = &dm81xx_mcspi2_hwmod,
1237 .clk = "sysclk6_ck",
1238 .user = OCP_USER_MPU,
1241 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi3 = {
1242 .master = &dm81xx_l4_ls_hwmod,
1243 .slave = &dm81xx_mcspi3_hwmod,
1244 .clk = "sysclk6_ck",
1245 .user = OCP_USER_MPU,
1248 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi4 = {
1249 .master = &dm81xx_l4_ls_hwmod,
1250 .slave = &dm81xx_mcspi4_hwmod,
1251 .clk = "sysclk6_ck",
1252 .user = OCP_USER_MPU,
1255 static struct omap_hwmod_class_sysconfig dm81xx_mailbox_sysc = {
1259 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1260 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE,
1261 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1262 .sysc_fields = &omap_hwmod_sysc_type1,
1265 static struct omap_hwmod_class dm81xx_mailbox_hwmod_class = {
1267 .sysc = &dm81xx_mailbox_sysc,
1270 static struct omap_hwmod dm81xx_mailbox_hwmod = {
1272 .clkdm_name = "alwon_l3s_clkdm",
1273 .class = &dm81xx_mailbox_hwmod_class,
1274 .main_clk = "sysclk6_ck",
1277 .clkctrl_offs = DM81XX_CM_ALWON_MAILBOX_CLKCTRL,
1278 .modulemode = MODULEMODE_SWCTRL,
1283 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mailbox = {
1284 .master = &dm81xx_l4_ls_hwmod,
1285 .slave = &dm81xx_mailbox_hwmod,
1286 .clk = "sysclk6_ck",
1287 .user = OCP_USER_MPU,
1290 static struct omap_hwmod_class_sysconfig dm81xx_spinbox_sysc = {
1294 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1295 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE,
1296 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1297 .sysc_fields = &omap_hwmod_sysc_type1,
1300 static struct omap_hwmod_class dm81xx_spinbox_hwmod_class = {
1302 .sysc = &dm81xx_spinbox_sysc,
1305 static struct omap_hwmod dm81xx_spinbox_hwmod = {
1307 .clkdm_name = "alwon_l3s_clkdm",
1308 .class = &dm81xx_spinbox_hwmod_class,
1309 .main_clk = "sysclk6_ck",
1312 .clkctrl_offs = DM81XX_CM_ALWON_SPINBOX_CLKCTRL,
1313 .modulemode = MODULEMODE_SWCTRL,
1318 static struct omap_hwmod_ocp_if dm81xx_l4_ls__spinbox = {
1319 .master = &dm81xx_l4_ls_hwmod,
1320 .slave = &dm81xx_spinbox_hwmod,
1321 .clk = "sysclk6_ck",
1322 .user = OCP_USER_MPU,
1325 static struct omap_hwmod_class dm81xx_tpcc_hwmod_class = {
1329 static struct omap_hwmod dm81xx_tpcc_hwmod = {
1331 .class = &dm81xx_tpcc_hwmod_class,
1332 .clkdm_name = "alwon_l3s_clkdm",
1333 .main_clk = "sysclk4_ck",
1336 .clkctrl_offs = DM81XX_CM_ALWON_TPCC_CLKCTRL,
1337 .modulemode = MODULEMODE_SWCTRL,
1342 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tpcc = {
1343 .master = &dm81xx_alwon_l3_fast_hwmod,
1344 .slave = &dm81xx_tpcc_hwmod,
1345 .clk = "sysclk4_ck",
1346 .user = OCP_USER_MPU,
1349 static struct omap_hwmod_class dm81xx_tptc0_hwmod_class = {
1353 static struct omap_hwmod dm81xx_tptc0_hwmod = {
1355 .class = &dm81xx_tptc0_hwmod_class,
1356 .clkdm_name = "alwon_l3s_clkdm",
1357 .main_clk = "sysclk4_ck",
1360 .clkctrl_offs = DM81XX_CM_ALWON_TPTC0_CLKCTRL,
1361 .modulemode = MODULEMODE_SWCTRL,
1366 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc0 = {
1367 .master = &dm81xx_alwon_l3_fast_hwmod,
1368 .slave = &dm81xx_tptc0_hwmod,
1369 .clk = "sysclk4_ck",
1370 .user = OCP_USER_MPU,
1373 static struct omap_hwmod_ocp_if dm81xx_tptc0__alwon_l3_fast = {
1374 .master = &dm81xx_tptc0_hwmod,
1375 .slave = &dm81xx_alwon_l3_fast_hwmod,
1376 .clk = "sysclk4_ck",
1377 .user = OCP_USER_MPU,
1380 static struct omap_hwmod_class dm81xx_tptc1_hwmod_class = {
1384 static struct omap_hwmod dm81xx_tptc1_hwmod = {
1386 .class = &dm81xx_tptc1_hwmod_class,
1387 .clkdm_name = "alwon_l3s_clkdm",
1388 .main_clk = "sysclk4_ck",
1391 .clkctrl_offs = DM81XX_CM_ALWON_TPTC1_CLKCTRL,
1392 .modulemode = MODULEMODE_SWCTRL,
1397 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc1 = {
1398 .master = &dm81xx_alwon_l3_fast_hwmod,
1399 .slave = &dm81xx_tptc1_hwmod,
1400 .clk = "sysclk4_ck",
1401 .user = OCP_USER_MPU,
1404 static struct omap_hwmod_ocp_if dm81xx_tptc1__alwon_l3_fast = {
1405 .master = &dm81xx_tptc1_hwmod,
1406 .slave = &dm81xx_alwon_l3_fast_hwmod,
1407 .clk = "sysclk4_ck",
1408 .user = OCP_USER_MPU,
1411 static struct omap_hwmod_class dm81xx_tptc2_hwmod_class = {
1415 static struct omap_hwmod dm81xx_tptc2_hwmod = {
1417 .class = &dm81xx_tptc2_hwmod_class,
1418 .clkdm_name = "alwon_l3s_clkdm",
1419 .main_clk = "sysclk4_ck",
1422 .clkctrl_offs = DM81XX_CM_ALWON_TPTC2_CLKCTRL,
1423 .modulemode = MODULEMODE_SWCTRL,
1428 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc2 = {
1429 .master = &dm81xx_alwon_l3_fast_hwmod,
1430 .slave = &dm81xx_tptc2_hwmod,
1431 .clk = "sysclk4_ck",
1432 .user = OCP_USER_MPU,
1435 static struct omap_hwmod_ocp_if dm81xx_tptc2__alwon_l3_fast = {
1436 .master = &dm81xx_tptc2_hwmod,
1437 .slave = &dm81xx_alwon_l3_fast_hwmod,
1438 .clk = "sysclk4_ck",
1439 .user = OCP_USER_MPU,
1442 static struct omap_hwmod_class dm81xx_tptc3_hwmod_class = {
1446 static struct omap_hwmod dm81xx_tptc3_hwmod = {
1448 .class = &dm81xx_tptc3_hwmod_class,
1449 .clkdm_name = "alwon_l3s_clkdm",
1450 .main_clk = "sysclk4_ck",
1453 .clkctrl_offs = DM81XX_CM_ALWON_TPTC3_CLKCTRL,
1454 .modulemode = MODULEMODE_SWCTRL,
1459 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc3 = {
1460 .master = &dm81xx_alwon_l3_fast_hwmod,
1461 .slave = &dm81xx_tptc3_hwmod,
1462 .clk = "sysclk4_ck",
1463 .user = OCP_USER_MPU,
1466 static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = {
1467 .master = &dm81xx_tptc3_hwmod,
1468 .slave = &dm81xx_alwon_l3_fast_hwmod,
1469 .clk = "sysclk4_ck",
1470 .user = OCP_USER_MPU,
1474 * REVISIT: Test and enable the following once clocks work:
1475 * dm81xx_l4_ls__mailbox
1477 * Also note that some devices share a single clkctrl_offs..
1478 * For example, i2c1 and 3 share one, and i2c2 and 4 share one.
1480 static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = {
1481 &dm814x_mpu__alwon_l3_slow,
1482 &dm814x_mpu__alwon_l3_med,
1483 &dm81xx_alwon_l3_slow__l4_ls,
1484 &dm81xx_alwon_l3_slow__l4_hs,
1485 &dm81xx_l4_ls__uart1,
1486 &dm81xx_l4_ls__uart2,
1487 &dm81xx_l4_ls__uart3,
1488 &dm81xx_l4_ls__wd_timer1,
1489 &dm81xx_l4_ls__i2c1,
1490 &dm81xx_l4_ls__i2c2,
1491 &dm81xx_l4_ls__gpio1,
1492 &dm81xx_l4_ls__gpio2,
1493 &dm81xx_l4_ls__gpio3,
1494 &dm81xx_l4_ls__gpio4,
1496 &dm81xx_l4_ls__mcspi1,
1497 &dm81xx_l4_ls__mcspi2,
1498 &dm81xx_l4_ls__mcspi3,
1499 &dm81xx_l4_ls__mcspi4,
1500 &dm814x_l4_ls__mmc1,
1501 &dm814x_l4_ls__mmc2,
1503 &dm81xx_alwon_l3_fast__tpcc,
1504 &dm81xx_alwon_l3_fast__tptc0,
1505 &dm81xx_alwon_l3_fast__tptc1,
1506 &dm81xx_alwon_l3_fast__tptc2,
1507 &dm81xx_alwon_l3_fast__tptc3,
1508 &dm81xx_tptc0__alwon_l3_fast,
1509 &dm81xx_tptc1__alwon_l3_fast,
1510 &dm81xx_tptc2__alwon_l3_fast,
1511 &dm81xx_tptc3__alwon_l3_fast,
1512 &dm814x_l4_ls__timer1,
1513 &dm814x_l4_ls__timer2,
1514 &dm814x_l4_hs__cpgmac0,
1515 &dm814x_cpgmac0__mdio,
1516 &dm81xx_alwon_l3_slow__gpmc,
1517 &dm814x_default_l3_slow__usbss,
1518 &dm814x_alwon_l3_med__mmc3,
1522 int __init dm814x_hwmod_init(void)
1525 return omap_hwmod_register_links(dm814x_hwmod_ocp_ifs);
1528 static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = {
1529 &dm816x_mpu__alwon_l3_slow,
1530 &dm816x_mpu__alwon_l3_med,
1531 &dm81xx_alwon_l3_slow__l4_ls,
1532 &dm81xx_alwon_l3_slow__l4_hs,
1533 &dm81xx_l4_ls__uart1,
1534 &dm81xx_l4_ls__uart2,
1535 &dm81xx_l4_ls__uart3,
1536 &dm81xx_l4_ls__wd_timer1,
1537 &dm81xx_l4_ls__i2c1,
1538 &dm81xx_l4_ls__i2c2,
1539 &dm81xx_l4_ls__gpio1,
1540 &dm81xx_l4_ls__gpio2,
1543 &dm816x_l4_ls__mmc1,
1544 &dm816x_l4_ls__timer1,
1545 &dm816x_l4_ls__timer2,
1546 &dm816x_l4_ls__timer3,
1547 &dm816x_l4_ls__timer4,
1548 &dm816x_l4_ls__timer5,
1549 &dm816x_l4_ls__timer6,
1550 &dm816x_l4_ls__timer7,
1551 &dm81xx_l4_ls__mcspi1,
1552 &dm81xx_l4_ls__mailbox,
1553 &dm81xx_l4_ls__spinbox,
1554 &dm81xx_l4_hs__emac0,
1555 &dm81xx_emac0__mdio,
1556 &dm816x_l4_hs__emac1,
1557 &dm81xx_l4_hs__sata,
1558 &dm81xx_alwon_l3_fast__tpcc,
1559 &dm81xx_alwon_l3_fast__tptc0,
1560 &dm81xx_alwon_l3_fast__tptc1,
1561 &dm81xx_alwon_l3_fast__tptc2,
1562 &dm81xx_alwon_l3_fast__tptc3,
1563 &dm81xx_tptc0__alwon_l3_fast,
1564 &dm81xx_tptc1__alwon_l3_fast,
1565 &dm81xx_tptc2__alwon_l3_fast,
1566 &dm81xx_tptc3__alwon_l3_fast,
1567 &dm81xx_alwon_l3_slow__gpmc,
1568 &dm816x_default_l3_slow__usbss,
1572 int __init dm816x_hwmod_init(void)
1575 return omap_hwmod_register_links(dm816x_hwmod_ocp_ifs);