arch/arm/mach-omap2/omap_hwmod_81xx_data.c

   1 /*
   2  * DM81xx hwmod data.
   3  *
   4  * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
   5  * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/types.h>
  19
  20 #include <linux/platform_data/hsmmc-omap.h>
  21
  22 #include "omap_hwmod_common_data.h"
  23 #include "cm81xx.h"
  24 #include "ti81xx.h"
  25 #include "wd_timer.h"
  26
  27 /*
  28  * DM816X hardware modules integration data
  29  *
  30  * Note: This is incomplete and at present, not generated from h/w database.
  31  */
  32
  33 /*
  34  * Common alwon .clkctrl_offs from dm814x TRM "Table 2-278. CM_ALWON REGISTERS"
  35  * also dm816x TRM 18.7.17 CM_ALWON device register values minus 0x1400.
  36  */
  37 #define DM81XX_CM_ALWON_MCASP0_CLKCTRL          0x140
  38 #define DM81XX_CM_ALWON_MCASP1_CLKCTRL          0x144
  39 #define DM81XX_CM_ALWON_MCASP2_CLKCTRL          0x148
  40 #define DM81XX_CM_ALWON_MCBSP_CLKCTRL           0x14c
  41 #define DM81XX_CM_ALWON_UART_0_CLKCTRL          0x150
  42 #define DM81XX_CM_ALWON_UART_1_CLKCTRL          0x154
  43 #define DM81XX_CM_ALWON_UART_2_CLKCTRL          0x158
  44 #define DM81XX_CM_ALWON_GPIO_0_CLKCTRL          0x15c
  45 #define DM81XX_CM_ALWON_GPIO_1_CLKCTRL          0x160
  46 #define DM81XX_CM_ALWON_I2C_0_CLKCTRL           0x164
  47 #define DM81XX_CM_ALWON_I2C_1_CLKCTRL           0x168
  48 #define DM81XX_CM_ALWON_WDTIMER_CLKCTRL         0x18c
  49 #define DM81XX_CM_ALWON_SPI_CLKCTRL             0x190
  50 #define DM81XX_CM_ALWON_MAILBOX_CLKCTRL         0x194
  51 #define DM81XX_CM_ALWON_SPINBOX_CLKCTRL         0x198
  52 #define DM81XX_CM_ALWON_MMUDATA_CLKCTRL         0x19c
  53 #define DM81XX_CM_ALWON_MMUCFG_CLKCTRL          0x1a8
  54 #define DM81XX_CM_ALWON_CONTROL_CLKCTRL         0x1c4
  55 #define DM81XX_CM_ALWON_GPMC_CLKCTRL            0x1d0
  56 #define DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL      0x1d4
  57 #define DM81XX_CM_ALWON_L3_CLKCTRL              0x1e4
  58 #define DM81XX_CM_ALWON_L4HS_CLKCTRL            0x1e8
  59 #define DM81XX_CM_ALWON_L4LS_CLKCTRL            0x1ec
  60 #define DM81XX_CM_ALWON_RTC_CLKCTRL             0x1f0
  61 #define DM81XX_CM_ALWON_TPCC_CLKCTRL            0x1f4
  62 #define DM81XX_CM_ALWON_TPTC0_CLKCTRL           0x1f8
  63 #define DM81XX_CM_ALWON_TPTC1_CLKCTRL           0x1fc
  64 #define DM81XX_CM_ALWON_TPTC2_CLKCTRL           0x200
  65 #define DM81XX_CM_ALWON_TPTC3_CLKCTRL           0x204
  66
  67 /* Registers specific to dm814x */
  68 #define DM814X_CM_ALWON_MCASP_3_4_5_CLKCTRL     0x16c
  69 #define DM814X_CM_ALWON_ATL_CLKCTRL             0x170
  70 #define DM814X_CM_ALWON_MLB_CLKCTRL             0x174
  71 #define DM814X_CM_ALWON_PATA_CLKCTRL            0x178
  72 #define DM814X_CM_ALWON_UART_3_CLKCTRL          0x180
  73 #define DM814X_CM_ALWON_UART_4_CLKCTRL          0x184
  74 #define DM814X_CM_ALWON_UART_5_CLKCTRL          0x188
  75 #define DM814X_CM_ALWON_OCM_0_CLKCTRL           0x1b4
  76 #define DM814X_CM_ALWON_VCP_CLKCTRL             0x1b8
  77 #define DM814X_CM_ALWON_MPU_CLKCTRL             0x1dc
  78 #define DM814X_CM_ALWON_DEBUGSS_CLKCTRL         0x1e0
  79 #define DM814X_CM_ALWON_DCAN_0_1_CLKCTRL        0x218
  80 #define DM814X_CM_ALWON_MMCHS_0_CLKCTRL         0x21c
  81 #define DM814X_CM_ALWON_MMCHS_1_CLKCTRL         0x220
  82 #define DM814X_CM_ALWON_MMCHS_2_CLKCTRL         0x224
  83 #define DM814X_CM_ALWON_CUST_EFUSE_CLKCTRL      0x228
  84
  85 /* Registers specific to dm816x */
  86 #define DM816X_DM_ALWON_BASE            0x1400
  87 #define DM816X_CM_ALWON_TIMER_1_CLKCTRL (0x1570 - DM816X_DM_ALWON_BASE)
  88 #define DM816X_CM_ALWON_TIMER_2_CLKCTRL (0x1574 - DM816X_DM_ALWON_BASE)
  89 #define DM816X_CM_ALWON_TIMER_3_CLKCTRL (0x1578 - DM816X_DM_ALWON_BASE)
  90 #define DM816X_CM_ALWON_TIMER_4_CLKCTRL (0x157c - DM816X_DM_ALWON_BASE)
  91 #define DM816X_CM_ALWON_TIMER_5_CLKCTRL (0x1580 - DM816X_DM_ALWON_BASE)
  92 #define DM816X_CM_ALWON_TIMER_6_CLKCTRL (0x1584 - DM816X_DM_ALWON_BASE)
  93 #define DM816X_CM_ALWON_TIMER_7_CLKCTRL (0x1588 - DM816X_DM_ALWON_BASE)
  94 #define DM816X_CM_ALWON_SDIO_CLKCTRL    (0x15b0 - DM816X_DM_ALWON_BASE)
  95 #define DM816X_CM_ALWON_OCMC_0_CLKCTRL  (0x15b4 - DM816X_DM_ALWON_BASE)
  96 #define DM816X_CM_ALWON_OCMC_1_CLKCTRL  (0x15b8 - DM816X_DM_ALWON_BASE)
  97 #define DM816X_CM_ALWON_ETHERNET_1_CLKCTRL (0x15d8 - DM816X_DM_ALWON_BASE)
  98 #define DM816X_CM_ALWON_MPU_CLKCTRL     (0x15dc - DM816X_DM_ALWON_BASE)
  99 #define DM816X_CM_ALWON_SR_0_CLKCTRL    (0x1608 - DM816X_DM_ALWON_BASE)
 100 #define DM816X_CM_ALWON_SR_1_CLKCTRL    (0x160c - DM816X_DM_ALWON_BASE)
 101
 102 /*
 103  * The default .clkctrl_offs field is offset from CM_DEFAULT, that's
 104  * TRM 18.7.6 CM_DEFAULT device register values minus 0x500
 105  */
 106 #define DM81XX_CM_DEFAULT_OFFSET        0x500
 107 #define DM81XX_CM_DEFAULT_USB_CLKCTRL   (0x558 - DM81XX_CM_DEFAULT_OFFSET)
 108 #define DM81XX_CM_DEFAULT_SATA_CLKCTRL  (0x560 - DM81XX_CM_DEFAULT_OFFSET)
 109
 110 /* L3 Interconnect entries clocked at 125, 250 and 500MHz */
 111 static struct omap_hwmod dm81xx_alwon_l3_slow_hwmod = {
 112         .name           = "alwon_l3_slow",
 113         .clkdm_name     = "alwon_l3s_clkdm",
 114         .class          = &l3_hwmod_class,
 115         .flags          = HWMOD_NO_IDLEST,
 116 };
 117
 118 static struct omap_hwmod dm81xx_default_l3_slow_hwmod = {
 119         .name           = "default_l3_slow",
 120         .clkdm_name     = "default_l3_slow_clkdm",
 121         .class          = &l3_hwmod_class,
 122         .flags          = HWMOD_NO_IDLEST,
 123 };
 124
 125 static struct omap_hwmod dm81xx_alwon_l3_med_hwmod = {
 126         .name           = "l3_med",
 127         .clkdm_name     = "alwon_l3_med_clkdm",
 128         .class          = &l3_hwmod_class,
 129         .flags          = HWMOD_NO_IDLEST,
 130 };
 131
 132 static struct omap_hwmod dm81xx_alwon_l3_fast_hwmod = {
 133         .name           = "l3_fast",
 134         .clkdm_name     = "alwon_l3_fast_clkdm",
 135         .class          = &l3_hwmod_class,
 136         .flags          = HWMOD_NO_IDLEST,
 137 };
 138
 139 /*
 140  * L4 standard peripherals, see TRM table 1-12 for devices using this.
 141  * See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock.
 142  */
 143 static struct omap_hwmod dm81xx_l4_ls_hwmod = {
 144         .name           = "l4_ls",
 145         .clkdm_name     = "alwon_l3s_clkdm",
 146         .class          = &l4_hwmod_class,
 147         .flags          = HWMOD_NO_IDLEST,
 148 };
 149
 150 /*
 151  * L4 high-speed peripherals. For devices using this, please see the TRM
 152  * table 1-13. On dm816x, only EMAC, MDIO and SATA use this. See also TRM
 153  * table 1-73 for devices using 250MHz SYSCLK5 clock.
 154  */
 155 static struct omap_hwmod dm81xx_l4_hs_hwmod = {
 156         .name           = "l4_hs",
 157         .clkdm_name     = "alwon_l3_med_clkdm",
 158         .class          = &l4_hwmod_class,
 159         .flags          = HWMOD_NO_IDLEST,
 160 };
 161
 162 /* L3 slow -> L4 ls peripheral interface running at 125MHz */
 163 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_ls = {
 164         .master = &dm81xx_alwon_l3_slow_hwmod,
 165         .slave  = &dm81xx_l4_ls_hwmod,
 166         .user   = OCP_USER_MPU,
 167 };
 168
 169 /* L3 med -> L4 fast peripheral interface running at 250MHz */
 170 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_hs = {
 171         .master = &dm81xx_alwon_l3_med_hwmod,
 172         .slave  = &dm81xx_l4_hs_hwmod,
 173         .user   = OCP_USER_MPU,
 174 };
 175
 176 /* MPU */
 177 static struct omap_hwmod dm814x_mpu_hwmod = {
 178         .name           = "mpu",
 179         .clkdm_name     = "alwon_l3s_clkdm",
 180         .class          = &mpu_hwmod_class,
 181         .flags          = HWMOD_INIT_NO_IDLE,
 182         .main_clk       = "mpu_ck",
 183         .prcm           = {
 184                 .omap4 = {
 185                         .clkctrl_offs = DM814X_CM_ALWON_MPU_CLKCTRL,
 186                         .modulemode = MODULEMODE_SWCTRL,
 187                 },
 188         },
 189 };
 190
 191 static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_slow = {
 192         .master         = &dm814x_mpu_hwmod,
 193         .slave          = &dm81xx_alwon_l3_slow_hwmod,
 194         .user           = OCP_USER_MPU,
 195 };
 196
 197 /* L3 med peripheral interface running at 200MHz */
 198 static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_med = {
 199         .master = &dm814x_mpu_hwmod,
 200         .slave  = &dm81xx_alwon_l3_med_hwmod,
 201         .user   = OCP_USER_MPU,
 202 };
 203
 204 static struct omap_hwmod dm816x_mpu_hwmod = {
 205         .name           = "mpu",
 206         .clkdm_name     = "alwon_mpu_clkdm",
 207         .class          = &mpu_hwmod_class,
 208         .flags          = HWMOD_INIT_NO_IDLE,
 209         .main_clk       = "mpu_ck",
 210         .prcm           = {
 211                 .omap4 = {
 212                         .clkctrl_offs = DM816X_CM_ALWON_MPU_CLKCTRL,
 213                         .modulemode = MODULEMODE_SWCTRL,
 214                 },
 215         },
 216 };
 217
 218 static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_slow = {
 219         .master         = &dm816x_mpu_hwmod,
 220         .slave          = &dm81xx_alwon_l3_slow_hwmod,
 221         .user           = OCP_USER_MPU,
 222 };
 223
 224 /* L3 med peripheral interface running at 250MHz */
 225 static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_med = {
 226         .master = &dm816x_mpu_hwmod,
 227         .slave  = &dm81xx_alwon_l3_med_hwmod,
 228         .user   = OCP_USER_MPU,
 229 };
 230
 231 /* RTC */
 232 static struct omap_hwmod_class_sysconfig ti81xx_rtc_sysc = {
 233         .rev_offs       = 0x74,
 234         .sysc_offs      = 0x78,
 235         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 236         .idlemodes      = SIDLE_FORCE | SIDLE_NO |
 237                           SIDLE_SMART | SIDLE_SMART_WKUP,
 238         .sysc_fields    = &omap_hwmod_sysc_type3,
 239 };
 240
 241 static struct omap_hwmod_class ti81xx_rtc_hwmod_class = {
 242         .name           = "rtc",
 243         .sysc           = &ti81xx_rtc_sysc,
 244 };
 245
 246 static struct omap_hwmod ti81xx_rtc_hwmod = {
 247         .name           = "rtc",
 248         .class          = &ti81xx_rtc_hwmod_class,
 249         .clkdm_name     = "alwon_l3s_clkdm",
 250         .flags          = HWMOD_NO_IDLEST,
 251         .main_clk       = "sysclk18_ck",
 252         .prcm           = {
 253                 .omap4  = {
 254                         .clkctrl_offs = DM81XX_CM_ALWON_RTC_CLKCTRL,
 255                         .modulemode = MODULEMODE_SWCTRL,
 256                 },
 257         },
 258 };
 259
 260 static struct omap_hwmod_ocp_if ti81xx_l4_ls__rtc = {
 261         .master         = &dm81xx_l4_ls_hwmod,
 262         .slave          = &ti81xx_rtc_hwmod,
 263         .clk            = "sysclk6_ck",
 264         .user           = OCP_USER_MPU,
 265 };
 266
 267 /* UART common */
 268 static struct omap_hwmod_class_sysconfig uart_sysc = {
 269         .rev_offs       = 0x50,
 270         .sysc_offs      = 0x54,
 271         .syss_offs      = 0x58,
 272         .sysc_flags     = SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 273                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 274                                 SYSS_HAS_RESET_STATUS,
 275         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 276                                 MSTANDBY_SMART_WKUP,
 277         .sysc_fields    = &omap_hwmod_sysc_type1,
 278 };
 279
 280 static struct omap_hwmod_class uart_class = {
 281         .name = "uart",
 282         .sysc = &uart_sysc,
 283 };
 284
 285 static struct omap_hwmod dm81xx_uart1_hwmod = {
 286         .name           = "uart1",
 287         .clkdm_name     = "alwon_l3s_clkdm",
 288         .main_clk       = "sysclk10_ck",
 289         .prcm           = {
 290                 .omap4 = {
 291                         .clkctrl_offs = DM81XX_CM_ALWON_UART_0_CLKCTRL,
 292                         .modulemode = MODULEMODE_SWCTRL,
 293                 },
 294         },
 295         .class          = &uart_class,
 296         .flags          = DEBUG_TI81XXUART1_FLAGS,
 297 };
 298
 299 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart1 = {
 300         .master         = &dm81xx_l4_ls_hwmod,
 301         .slave          = &dm81xx_uart1_hwmod,
 302         .clk            = "sysclk6_ck",
 303         .user           = OCP_USER_MPU,
 304 };
 305
 306 static struct omap_hwmod dm81xx_uart2_hwmod = {
 307         .name           = "uart2",
 308         .clkdm_name     = "alwon_l3s_clkdm",
 309         .main_clk       = "sysclk10_ck",
 310         .prcm           = {
 311                 .omap4 = {
 312                         .clkctrl_offs = DM81XX_CM_ALWON_UART_1_CLKCTRL,
 313                         .modulemode = MODULEMODE_SWCTRL,
 314                 },
 315         },
 316         .class          = &uart_class,
 317         .flags          = DEBUG_TI81XXUART2_FLAGS,
 318 };
 319
 320 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart2 = {
 321         .master         = &dm81xx_l4_ls_hwmod,
 322         .slave          = &dm81xx_uart2_hwmod,
 323         .clk            = "sysclk6_ck",
 324         .user           = OCP_USER_MPU,
 325 };
 326
 327 static struct omap_hwmod dm81xx_uart3_hwmod = {
 328         .name           = "uart3",
 329         .clkdm_name     = "alwon_l3s_clkdm",
 330         .main_clk       = "sysclk10_ck",
 331         .prcm           = {
 332                 .omap4 = {
 333                         .clkctrl_offs = DM81XX_CM_ALWON_UART_2_CLKCTRL,
 334                         .modulemode = MODULEMODE_SWCTRL,
 335                 },
 336         },
 337         .class          = &uart_class,
 338         .flags          = DEBUG_TI81XXUART3_FLAGS,
 339 };
 340
 341 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart3 = {
 342         .master         = &dm81xx_l4_ls_hwmod,
 343         .slave          = &dm81xx_uart3_hwmod,
 344         .clk            = "sysclk6_ck",
 345         .user           = OCP_USER_MPU,
 346 };
 347
 348 static struct omap_hwmod_class_sysconfig wd_timer_sysc = {
 349         .rev_offs       = 0x0,
 350         .sysc_offs      = 0x10,
 351         .syss_offs      = 0x14,
 352         .sysc_flags     = SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
 353                                 SYSS_HAS_RESET_STATUS,
 354         .sysc_fields    = &omap_hwmod_sysc_type1,
 355 };
 356
 357 static struct omap_hwmod_class wd_timer_class = {
 358         .name           = "wd_timer",
 359         .sysc           = &wd_timer_sysc,
 360         .pre_shutdown   = &omap2_wd_timer_disable,
 361         .reset          = &omap2_wd_timer_reset,
 362 };
 363
 364 static struct omap_hwmod dm81xx_wd_timer_hwmod = {
 365         .name           = "wd_timer",
 366         .clkdm_name     = "alwon_l3s_clkdm",
 367         .main_clk       = "sysclk18_ck",
 368         .flags          = HWMOD_NO_IDLEST,
 369         .prcm           = {
 370                 .omap4 = {
 371                         .clkctrl_offs = DM81XX_CM_ALWON_WDTIMER_CLKCTRL,
 372                         .modulemode = MODULEMODE_SWCTRL,
 373                 },
 374         },
 375         .class          = &wd_timer_class,
 376 };
 377
 378 static struct omap_hwmod_ocp_if dm81xx_l4_ls__wd_timer1 = {
 379         .master         = &dm81xx_l4_ls_hwmod,
 380         .slave          = &dm81xx_wd_timer_hwmod,
 381         .clk            = "sysclk6_ck",
 382         .user           = OCP_USER_MPU,
 383 };
 384
 385 /* I2C common */
 386 static struct omap_hwmod_class_sysconfig i2c_sysc = {
 387         .rev_offs       = 0x0,
 388         .sysc_offs      = 0x10,
 389         .syss_offs      = 0x90,
 390         .sysc_flags     = SYSC_HAS_SIDLEMODE |
 391                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 392                                 SYSC_HAS_AUTOIDLE,
 393         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
 394         .sysc_fields    = &omap_hwmod_sysc_type1,
 395 };
 396
 397 static struct omap_hwmod_class i2c_class = {
 398         .name = "i2c",
 399         .sysc = &i2c_sysc,
 400 };
 401
 402 static struct omap_hwmod dm81xx_i2c1_hwmod = {
 403         .name           = "i2c1",
 404         .clkdm_name     = "alwon_l3s_clkdm",
 405         .main_clk       = "sysclk10_ck",
 406         .prcm           = {
 407                 .omap4 = {
 408                         .clkctrl_offs = DM81XX_CM_ALWON_I2C_0_CLKCTRL,
 409                         .modulemode = MODULEMODE_SWCTRL,
 410                 },
 411         },
 412         .class          = &i2c_class,
 413 };
 414
 415 static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c1 = {
 416         .master         = &dm81xx_l4_ls_hwmod,
 417         .slave          = &dm81xx_i2c1_hwmod,
 418         .clk            = "sysclk6_ck",
 419         .user           = OCP_USER_MPU,
 420 };
 421
 422 static struct omap_hwmod dm81xx_i2c2_hwmod = {
 423         .name           = "i2c2",
 424         .clkdm_name     = "alwon_l3s_clkdm",
 425         .main_clk       = "sysclk10_ck",
 426         .prcm           = {
 427                 .omap4 = {
 428                         .clkctrl_offs = DM81XX_CM_ALWON_I2C_1_CLKCTRL,
 429                         .modulemode = MODULEMODE_SWCTRL,
 430                 },
 431         },
 432         .class          = &i2c_class,
 433 };
 434
 435 static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = {
 436         .rev_offs       = 0x0000,
 437         .sysc_offs      = 0x0010,
 438         .syss_offs      = 0x0014,
 439         .sysc_flags     = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 440                                 SYSC_HAS_SOFTRESET |
 441                                 SYSS_HAS_RESET_STATUS,
 442         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
 443         .sysc_fields    = &omap_hwmod_sysc_type1,
 444 };
 445
 446 static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c2 = {
 447         .master         = &dm81xx_l4_ls_hwmod,
 448         .slave          = &dm81xx_i2c2_hwmod,
 449         .clk            = "sysclk6_ck",
 450         .user           = OCP_USER_MPU,
 451 };
 452
 453 static struct omap_hwmod_class dm81xx_elm_hwmod_class = {
 454         .name = "elm",
 455         .sysc = &dm81xx_elm_sysc,
 456 };
 457
 458 static struct omap_hwmod dm81xx_elm_hwmod = {
 459         .name           = "elm",
 460         .clkdm_name     = "alwon_l3s_clkdm",
 461         .class          = &dm81xx_elm_hwmod_class,
 462         .main_clk       = "sysclk6_ck",
 463 };
 464
 465 static struct omap_hwmod_ocp_if dm81xx_l4_ls__elm = {
 466         .master         = &dm81xx_l4_ls_hwmod,
 467         .slave          = &dm81xx_elm_hwmod,
 468         .clk            = "sysclk6_ck",
 469         .user           = OCP_USER_MPU,
 470 };
 471
 472 static struct omap_hwmod_class_sysconfig dm81xx_gpio_sysc = {
 473         .rev_offs       = 0x0000,
 474         .sysc_offs      = 0x0010,
 475         .syss_offs      = 0x0114,
 476         .sysc_flags     = SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 477                                 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 478                                 SYSS_HAS_RESET_STATUS,
 479         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 480                                 SIDLE_SMART_WKUP,
 481         .sysc_fields    = &omap_hwmod_sysc_type1,
 482 };
 483
 484 static struct omap_hwmod_class dm81xx_gpio_hwmod_class = {
 485         .name   = "gpio",
 486         .sysc   = &dm81xx_gpio_sysc,
 487         .rev    = 2,
 488 };
 489
 490 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 491         { .role = "dbclk", .clk = "sysclk18_ck" },
 492 };
 493
 494 static struct omap_hwmod dm81xx_gpio1_hwmod = {
 495         .name           = "gpio1",
 496         .clkdm_name     = "alwon_l3s_clkdm",
 497         .class          = &dm81xx_gpio_hwmod_class,
 498         .main_clk       = "sysclk6_ck",
 499         .prcm = {
 500                 .omap4 = {
 501                         .clkctrl_offs = DM81XX_CM_ALWON_GPIO_0_CLKCTRL,
 502                         .modulemode = MODULEMODE_SWCTRL,
 503                 },
 504         },
 505         .opt_clks       = gpio1_opt_clks,
 506         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 507 };
 508
 509 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio1 = {
 510         .master         = &dm81xx_l4_ls_hwmod,
 511         .slave          = &dm81xx_gpio1_hwmod,
 512         .clk            = "sysclk6_ck",
 513         .user           = OCP_USER_MPU,
 514 };
 515
 516 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 517         { .role = "dbclk", .clk = "sysclk18_ck" },
 518 };
 519
 520 static struct omap_hwmod dm81xx_gpio2_hwmod = {
 521         .name           = "gpio2",
 522         .clkdm_name     = "alwon_l3s_clkdm",
 523         .class          = &dm81xx_gpio_hwmod_class,
 524         .main_clk       = "sysclk6_ck",
 525         .prcm = {
 526                 .omap4 = {
 527                         .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL,
 528                         .modulemode = MODULEMODE_SWCTRL,
 529                 },
 530         },
 531         .opt_clks       = gpio2_opt_clks,
 532         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 533 };
 534
 535 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = {
 536         .master         = &dm81xx_l4_ls_hwmod,
 537         .slave          = &dm81xx_gpio2_hwmod,
 538         .clk            = "sysclk6_ck",
 539         .user           = OCP_USER_MPU,
 540 };
 541
 542 static struct omap_hwmod_class_sysconfig dm81xx_gpmc_sysc = {
 543         .rev_offs       = 0x0,
 544         .sysc_offs      = 0x10,
 545         .syss_offs      = 0x14,
 546         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 547                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
 548         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
 549         .sysc_fields    = &omap_hwmod_sysc_type1,
 550 };
 551
 552 static struct omap_hwmod_class dm81xx_gpmc_hwmod_class = {
 553         .name   = "gpmc",
 554         .sysc   = &dm81xx_gpmc_sysc,
 555 };
 556
 557 static struct omap_hwmod dm81xx_gpmc_hwmod = {
 558         .name           = "gpmc",
 559         .clkdm_name     = "alwon_l3s_clkdm",
 560         .class          = &dm81xx_gpmc_hwmod_class,
 561         .main_clk       = "sysclk6_ck",
 562         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
 563         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
 564         .prcm = {
 565                 .omap4 = {
 566                         .clkctrl_offs = DM81XX_CM_ALWON_GPMC_CLKCTRL,
 567                         .modulemode = MODULEMODE_SWCTRL,
 568                 },
 569         },
 570 };
 571
 572 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__gpmc = {
 573         .master         = &dm81xx_alwon_l3_slow_hwmod,
 574         .slave          = &dm81xx_gpmc_hwmod,
 575         .user           = OCP_USER_MPU,
 576 };
 577
 578 /* USB needs udelay 1 after reset at least on hp t410, use 2 for margin */
 579 static struct omap_hwmod_class_sysconfig dm81xx_usbhsotg_sysc = {
 580         .rev_offs       = 0x0,
 581         .sysc_offs      = 0x10,
 582         .srst_udelay    = 2,
 583         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 584                                 SYSC_HAS_SOFTRESET,
 585         .idlemodes      = SIDLE_SMART | MSTANDBY_FORCE | MSTANDBY_SMART,
 586         .sysc_fields    = &omap_hwmod_sysc_type2,
 587 };
 588
 589 static struct omap_hwmod_class dm81xx_usbotg_class = {
 590         .name = "usbotg",
 591         .sysc = &dm81xx_usbhsotg_sysc,
 592 };
 593
 594 static struct omap_hwmod dm814x_usbss_hwmod = {
 595         .name           = "usb_otg_hs",
 596         .clkdm_name     = "default_l3_slow_clkdm",
 597         .main_clk       = "pll260dcoclkldo",    /* 481c5260.adpll.dcoclkldo */
 598         .prcm           = {
 599                 .omap4 = {
 600                         .clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL,
 601                         .modulemode = MODULEMODE_SWCTRL,
 602                 },
 603         },
 604         .class          = &dm81xx_usbotg_class,
 605 };
 606
 607 static struct omap_hwmod_ocp_if dm814x_default_l3_slow__usbss = {
 608         .master         = &dm81xx_default_l3_slow_hwmod,
 609         .slave          = &dm814x_usbss_hwmod,
 610         .clk            = "sysclk6_ck",
 611         .user           = OCP_USER_MPU,
 612 };
 613
 614 static struct omap_hwmod dm816x_usbss_hwmod = {
 615         .name           = "usb_otg_hs",
 616         .clkdm_name     = "default_l3_slow_clkdm",
 617         .main_clk       = "sysclk6_ck",
 618         .prcm           = {
 619                 .omap4 = {
 620                         .clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL,
 621                         .modulemode = MODULEMODE_SWCTRL,
 622                 },
 623         },
 624         .class          = &dm81xx_usbotg_class,
 625 };
 626
 627 static struct omap_hwmod_ocp_if dm816x_default_l3_slow__usbss = {
 628         .master         = &dm81xx_default_l3_slow_hwmod,
 629         .slave          = &dm816x_usbss_hwmod,
 630         .clk            = "sysclk6_ck",
 631         .user           = OCP_USER_MPU,
 632 };
 633
 634 static struct omap_hwmod_class_sysconfig dm816x_timer_sysc = {
 635         .rev_offs       = 0x0000,
 636         .sysc_offs      = 0x0010,
 637         .syss_offs      = 0x0014,
 638         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET,
 639         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 640                                 SIDLE_SMART_WKUP,
 641         .sysc_fields    = &omap_hwmod_sysc_type2,
 642 };
 643
 644 static struct omap_hwmod_class dm816x_timer_hwmod_class = {
 645         .name = "timer",
 646         .sysc = &dm816x_timer_sysc,
 647 };
 648
 649 static struct omap_hwmod dm814x_timer1_hwmod = {
 650         .name           = "timer1",
 651         .clkdm_name     = "alwon_l3s_clkdm",
 652         .main_clk       = "timer1_fck",
 653         .class          = &dm816x_timer_hwmod_class,
 654         .flags          = HWMOD_NO_IDLEST,
 655 };
 656
 657 static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = {
 658         .master         = &dm81xx_l4_ls_hwmod,
 659         .slave          = &dm814x_timer1_hwmod,
 660         .clk            = "sysclk6_ck",
 661         .user           = OCP_USER_MPU,
 662 };
 663
 664 static struct omap_hwmod dm816x_timer1_hwmod = {
 665         .name           = "timer1",
 666         .clkdm_name     = "alwon_l3s_clkdm",
 667         .main_clk       = "timer1_fck",
 668         .prcm           = {
 669                 .omap4 = {
 670                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_1_CLKCTRL,
 671                         .modulemode = MODULEMODE_SWCTRL,
 672                 },
 673         },
 674         .class          = &dm816x_timer_hwmod_class,
 675 };
 676
 677 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = {
 678         .master         = &dm81xx_l4_ls_hwmod,
 679         .slave          = &dm816x_timer1_hwmod,
 680         .clk            = "sysclk6_ck",
 681         .user           = OCP_USER_MPU,
 682 };
 683
 684 static struct omap_hwmod dm814x_timer2_hwmod = {
 685         .name           = "timer2",
 686         .clkdm_name     = "alwon_l3s_clkdm",
 687         .main_clk       = "timer2_fck",
 688         .class          = &dm816x_timer_hwmod_class,
 689         .flags          = HWMOD_NO_IDLEST,
 690 };
 691
 692 static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = {
 693         .master         = &dm81xx_l4_ls_hwmod,
 694         .slave          = &dm814x_timer2_hwmod,
 695         .clk            = "sysclk6_ck",
 696         .user           = OCP_USER_MPU,
 697 };
 698
 699 static struct omap_hwmod dm816x_timer2_hwmod = {
 700         .name           = "timer2",
 701         .clkdm_name     = "alwon_l3s_clkdm",
 702         .main_clk       = "timer2_fck",
 703         .prcm           = {
 704                 .omap4 = {
 705                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_2_CLKCTRL,
 706                         .modulemode = MODULEMODE_SWCTRL,
 707                 },
 708         },
 709         .class          = &dm816x_timer_hwmod_class,
 710 };
 711
 712 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer2 = {
 713         .master         = &dm81xx_l4_ls_hwmod,
 714         .slave          = &dm816x_timer2_hwmod,
 715         .clk            = "sysclk6_ck",
 716         .user           = OCP_USER_MPU,
 717 };
 718
 719 static struct omap_hwmod dm816x_timer3_hwmod = {
 720         .name           = "timer3",
 721         .clkdm_name     = "alwon_l3s_clkdm",
 722         .main_clk       = "timer3_fck",
 723         .prcm           = {
 724                 .omap4 = {
 725                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_3_CLKCTRL,
 726                         .modulemode = MODULEMODE_SWCTRL,
 727                 },
 728         },
 729         .class          = &dm816x_timer_hwmod_class,
 730 };
 731
 732 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer3 = {
 733         .master         = &dm81xx_l4_ls_hwmod,
 734         .slave          = &dm816x_timer3_hwmod,
 735         .clk            = "sysclk6_ck",
 736         .user           = OCP_USER_MPU,
 737 };
 738
 739 static struct omap_hwmod dm816x_timer4_hwmod = {
 740         .name           = "timer4",
 741         .clkdm_name     = "alwon_l3s_clkdm",
 742         .main_clk       = "timer4_fck",
 743         .prcm           = {
 744                 .omap4 = {
 745                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_4_CLKCTRL,
 746                         .modulemode = MODULEMODE_SWCTRL,
 747                 },
 748         },
 749         .class          = &dm816x_timer_hwmod_class,
 750 };
 751
 752 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer4 = {
 753         .master         = &dm81xx_l4_ls_hwmod,
 754         .slave          = &dm816x_timer4_hwmod,
 755         .clk            = "sysclk6_ck",
 756         .user           = OCP_USER_MPU,
 757 };
 758
 759 static struct omap_hwmod dm816x_timer5_hwmod = {
 760         .name           = "timer5",
 761         .clkdm_name     = "alwon_l3s_clkdm",
 762         .main_clk       = "timer5_fck",
 763         .prcm           = {
 764                 .omap4 = {
 765                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_5_CLKCTRL,
 766                         .modulemode = MODULEMODE_SWCTRL,
 767                 },
 768         },
 769         .class          = &dm816x_timer_hwmod_class,
 770 };
 771
 772 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer5 = {
 773         .master         = &dm81xx_l4_ls_hwmod,
 774         .slave          = &dm816x_timer5_hwmod,
 775         .clk            = "sysclk6_ck",
 776         .user           = OCP_USER_MPU,
 777 };
 778
 779 static struct omap_hwmod dm816x_timer6_hwmod = {
 780         .name           = "timer6",
 781         .clkdm_name     = "alwon_l3s_clkdm",
 782         .main_clk       = "timer6_fck",
 783         .prcm           = {
 784                 .omap4 = {
 785                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_6_CLKCTRL,
 786                         .modulemode = MODULEMODE_SWCTRL,
 787                 },
 788         },
 789         .class          = &dm816x_timer_hwmod_class,
 790 };
 791
 792 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer6 = {
 793         .master         = &dm81xx_l4_ls_hwmod,
 794         .slave          = &dm816x_timer6_hwmod,
 795         .clk            = "sysclk6_ck",
 796         .user           = OCP_USER_MPU,
 797 };
 798
 799 static struct omap_hwmod dm816x_timer7_hwmod = {
 800         .name           = "timer7",
 801         .clkdm_name     = "alwon_l3s_clkdm",
 802         .main_clk       = "timer7_fck",
 803         .prcm           = {
 804                 .omap4 = {
 805                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_7_CLKCTRL,
 806                         .modulemode = MODULEMODE_SWCTRL,
 807                 },
 808         },
 809         .class          = &dm816x_timer_hwmod_class,
 810 };
 811
 812 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer7 = {
 813         .master         = &dm81xx_l4_ls_hwmod,
 814         .slave          = &dm816x_timer7_hwmod,
 815         .clk            = "sysclk6_ck",
 816         .user           = OCP_USER_MPU,
 817 };
 818
 819 /* CPSW on dm814x */
 820 static struct omap_hwmod_class_sysconfig dm814x_cpgmac_sysc = {
 821         .rev_offs       = 0x0,
 822         .sysc_offs      = 0x8,
 823         .syss_offs      = 0x4,
 824         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 825                           SYSS_HAS_RESET_STATUS,
 826         .idlemodes      = SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
 827                           MSTANDBY_NO,
 828         .sysc_fields    = &omap_hwmod_sysc_type3,
 829 };
 830
 831 static struct omap_hwmod_class dm814x_cpgmac0_hwmod_class = {
 832         .name           = "cpgmac0",
 833         .sysc           = &dm814x_cpgmac_sysc,
 834 };
 835
 836 static struct omap_hwmod dm814x_cpgmac0_hwmod = {
 837         .name           = "cpgmac0",
 838         .class          = &dm814x_cpgmac0_hwmod_class,
 839         .clkdm_name     = "alwon_ethernet_clkdm",
 840         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 841         .main_clk       = "cpsw_125mhz_gclk",
 842         .prcm           = {
 843                 .omap4  = {
 844                         .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL,
 845                         .modulemode = MODULEMODE_SWCTRL,
 846                 },
 847         },
 848 };
 849
 850 static struct omap_hwmod_class dm814x_mdio_hwmod_class = {
 851         .name           = "davinci_mdio",
 852 };
 853
 854 static struct omap_hwmod dm814x_mdio_hwmod = {
 855         .name           = "davinci_mdio",
 856         .class          = &dm814x_mdio_hwmod_class,
 857         .clkdm_name     = "alwon_ethernet_clkdm",
 858         .main_clk       = "cpsw_125mhz_gclk",
 859 };
 860
 861 static struct omap_hwmod_ocp_if dm814x_l4_hs__cpgmac0 = {
 862         .master         = &dm81xx_l4_hs_hwmod,
 863         .slave          = &dm814x_cpgmac0_hwmod,
 864         .clk            = "cpsw_125mhz_gclk",
 865         .user           = OCP_USER_MPU,
 866 };
 867
 868 static struct omap_hwmod_ocp_if dm814x_cpgmac0__mdio = {
 869         .master         = &dm814x_cpgmac0_hwmod,
 870         .slave          = &dm814x_mdio_hwmod,
 871         .user           = OCP_USER_MPU,
 872         .flags          = HWMOD_NO_IDLEST,
 873 };
 874
 875 /* EMAC Ethernet */
 876 static struct omap_hwmod_class_sysconfig dm816x_emac_sysc = {
 877         .rev_offs       = 0x0,
 878         .sysc_offs      = 0x4,
 879         .sysc_flags     = SYSC_HAS_SOFTRESET,
 880         .sysc_fields    = &omap_hwmod_sysc_type2,
 881 };
 882
 883 static struct omap_hwmod_class dm816x_emac_hwmod_class = {
 884         .name           = "emac",
 885         .sysc           = &dm816x_emac_sysc,
 886 };
 887
 888 /*
 889  * On dm816x the MDIO is within EMAC0. As the MDIO driver is a separate
 890  * driver probed before EMAC0, we let MDIO do the clock idling.
 891  */
 892 static struct omap_hwmod dm816x_emac0_hwmod = {
 893         .name           = "emac0",
 894         .clkdm_name     = "alwon_ethernet_clkdm",
 895         .class          = &dm816x_emac_hwmod_class,
 896         .flags          = HWMOD_NO_IDLEST,
 897 };
 898
 899 static struct omap_hwmod_ocp_if dm81xx_l4_hs__emac0 = {
 900         .master         = &dm81xx_l4_hs_hwmod,
 901         .slave          = &dm816x_emac0_hwmod,
 902         .clk            = "sysclk5_ck",
 903         .user           = OCP_USER_MPU,
 904 };
 905
 906 static struct omap_hwmod_class dm81xx_mdio_hwmod_class = {
 907         .name           = "davinci_mdio",
 908         .sysc           = &dm816x_emac_sysc,
 909 };
 910
 911 static struct omap_hwmod dm81xx_emac0_mdio_hwmod = {
 912         .name           = "davinci_mdio",
 913         .class          = &dm81xx_mdio_hwmod_class,
 914         .clkdm_name     = "alwon_ethernet_clkdm",
 915         .main_clk       = "sysclk24_ck",
 916         .flags          = HWMOD_NO_IDLEST,
 917         /*
 918          * REVISIT: This should be moved to the emac0_hwmod
 919          * once we have a better way to handle device slaves.
 920          */
 921         .prcm           = {
 922                 .omap4 = {
 923                         .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL,
 924                         .modulemode = MODULEMODE_SWCTRL,
 925                 },
 926         },
 927 };
 928
 929 static struct omap_hwmod_ocp_if dm81xx_emac0__mdio = {
 930         .master         = &dm81xx_l4_hs_hwmod,
 931         .slave          = &dm81xx_emac0_mdio_hwmod,
 932         .user           = OCP_USER_MPU,
 933 };
 934
 935 static struct omap_hwmod dm816x_emac1_hwmod = {
 936         .name           = "emac1",
 937         .clkdm_name     = "alwon_ethernet_clkdm",
 938         .main_clk       = "sysclk24_ck",
 939         .flags          = HWMOD_NO_IDLEST,
 940         .prcm           = {
 941                 .omap4 = {
 942                         .clkctrl_offs = DM816X_CM_ALWON_ETHERNET_1_CLKCTRL,
 943                         .modulemode = MODULEMODE_SWCTRL,
 944                 },
 945         },
 946         .class          = &dm816x_emac_hwmod_class,
 947 };
 948
 949 static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = {
 950         .master         = &dm81xx_l4_hs_hwmod,
 951         .slave          = &dm816x_emac1_hwmod,
 952         .clk            = "sysclk5_ck",
 953         .user           = OCP_USER_MPU,
 954 };
 955
 956 static struct omap_hwmod_class_sysconfig dm81xx_sata_sysc = {
 957         .sysc_offs      = 0x1100,
 958         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 959         .idlemodes      = SIDLE_FORCE,
 960         .sysc_fields    = &omap_hwmod_sysc_type3,
 961 };
 962
 963 static struct omap_hwmod_class dm81xx_sata_hwmod_class = {
 964         .name   = "sata",
 965         .sysc   = &dm81xx_sata_sysc,
 966 };
 967
 968 static struct omap_hwmod dm81xx_sata_hwmod = {
 969         .name           = "sata",
 970         .clkdm_name     = "default_clkdm",
 971         .flags          = HWMOD_NO_IDLEST,
 972         .prcm = {
 973                 .omap4 = {
 974                         .clkctrl_offs = DM81XX_CM_DEFAULT_SATA_CLKCTRL,
 975                         .modulemode   = MODULEMODE_SWCTRL,
 976                 },
 977         },
 978         .class          = &dm81xx_sata_hwmod_class,
 979 };
 980
 981 static struct omap_hwmod_ocp_if dm81xx_l4_hs__sata = {
 982         .master         = &dm81xx_l4_hs_hwmod,
 983         .slave          = &dm81xx_sata_hwmod,
 984         .clk            = "sysclk5_ck",
 985         .user           = OCP_USER_MPU,
 986 };
 987
 988 static struct omap_hwmod_class_sysconfig dm81xx_mmc_sysc = {
 989         .rev_offs       = 0x0,
 990         .sysc_offs      = 0x110,
 991         .syss_offs      = 0x114,
 992         .sysc_flags     = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 993                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 994                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
 995         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
 996         .sysc_fields    = &omap_hwmod_sysc_type1,
 997 };
 998
 999 static struct omap_hwmod_class dm81xx_mmc_class = {
1000         .name = "mmc",
1001         .sysc = &dm81xx_mmc_sysc,
1002 };
1003
1004 static struct omap_hwmod_opt_clk dm81xx_mmc_opt_clks[] = {
1005         { .role = "dbck", .clk = "sysclk18_ck", },
1006 };
1007
1008 static struct omap_hsmmc_dev_attr mmc_dev_attr = {
1009 };
1010
1011 static struct omap_hwmod dm814x_mmc1_hwmod = {
1012         .name           = "mmc1",
1013         .clkdm_name     = "alwon_l3s_clkdm",
1014         .opt_clks       = dm81xx_mmc_opt_clks,
1015         .opt_clks_cnt   = ARRAY_SIZE(dm81xx_mmc_opt_clks),
1016         .main_clk       = "sysclk8_ck",
1017         .prcm           = {
1018                 .omap4 = {
1019                         .clkctrl_offs = DM814X_CM_ALWON_MMCHS_0_CLKCTRL,
1020                         .modulemode = MODULEMODE_SWCTRL,
1021                 },
1022         },
1023         .dev_attr       = &mmc_dev_attr,
1024         .class          = &dm81xx_mmc_class,
1025 };
1026
1027 static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc1 = {
1028         .master         = &dm81xx_l4_ls_hwmod,
1029         .slave          = &dm814x_mmc1_hwmod,
1030         .clk            = "sysclk6_ck",
1031         .user           = OCP_USER_MPU,
1032         .flags          = OMAP_FIREWALL_L4
1033 };
1034
1035 static struct omap_hwmod dm814x_mmc2_hwmod = {
1036         .name           = "mmc2",
1037         .clkdm_name     = "alwon_l3s_clkdm",
1038         .opt_clks       = dm81xx_mmc_opt_clks,
1039         .opt_clks_cnt   = ARRAY_SIZE(dm81xx_mmc_opt_clks),
1040         .main_clk       = "sysclk8_ck",
1041         .prcm           = {
1042                 .omap4 = {
1043                         .clkctrl_offs = DM814X_CM_ALWON_MMCHS_1_CLKCTRL,
1044                         .modulemode = MODULEMODE_SWCTRL,
1045                 },
1046         },
1047         .dev_attr       = &mmc_dev_attr,
1048         .class          = &dm81xx_mmc_class,
1049 };
1050
1051 static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc2 = {
1052         .master         = &dm81xx_l4_ls_hwmod,
1053         .slave          = &dm814x_mmc2_hwmod,
1054         .clk            = "sysclk6_ck",
1055         .user           = OCP_USER_MPU,
1056         .flags          = OMAP_FIREWALL_L4
1057 };
1058
1059 static struct omap_hwmod dm814x_mmc3_hwmod = {
1060         .name           = "mmc3",
1061         .clkdm_name     = "alwon_l3_med_clkdm",
1062         .opt_clks       = dm81xx_mmc_opt_clks,
1063         .opt_clks_cnt   = ARRAY_SIZE(dm81xx_mmc_opt_clks),
1064         .main_clk       = "sysclk8_ck",
1065         .prcm           = {
1066                 .omap4 = {
1067                         .clkctrl_offs = DM814X_CM_ALWON_MMCHS_2_CLKCTRL,
1068                         .modulemode = MODULEMODE_SWCTRL,
1069                 },
1070         },
1071         .dev_attr       = &mmc_dev_attr,
1072         .class          = &dm81xx_mmc_class,
1073 };
1074
1075 static struct omap_hwmod_ocp_if dm814x_alwon_l3_med__mmc3 = {
1076         .master         = &dm81xx_alwon_l3_med_hwmod,
1077         .slave          = &dm814x_mmc3_hwmod,
1078         .clk            = "sysclk4_ck",
1079         .user           = OCP_USER_MPU,
1080 };
1081
1082 static struct omap_hwmod dm816x_mmc1_hwmod = {
1083         .name           = "mmc1",
1084         .clkdm_name     = "alwon_l3s_clkdm",
1085         .opt_clks       = dm81xx_mmc_opt_clks,
1086         .opt_clks_cnt   = ARRAY_SIZE(dm81xx_mmc_opt_clks),
1087         .main_clk       = "sysclk10_ck",
1088         .prcm           = {
1089                 .omap4 = {
1090                         .clkctrl_offs = DM816X_CM_ALWON_SDIO_CLKCTRL,
1091                         .modulemode = MODULEMODE_SWCTRL,
1092                 },
1093         },
1094         .dev_attr       = &mmc_dev_attr,
1095         .class          = &dm81xx_mmc_class,
1096 };
1097
1098 static struct omap_hwmod_ocp_if dm816x_l4_ls__mmc1 = {
1099         .master         = &dm81xx_l4_ls_hwmod,
1100         .slave          = &dm816x_mmc1_hwmod,
1101         .clk            = "sysclk6_ck",
1102         .user           = OCP_USER_MPU,
1103         .flags          = OMAP_FIREWALL_L4
1104 };
1105
1106 static struct omap_hwmod_class_sysconfig dm816x_mcspi_sysc = {
1107         .rev_offs       = 0x0,
1108         .sysc_offs      = 0x110,
1109         .syss_offs      = 0x114,
1110         .sysc_flags     = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1111                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1112                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
1113         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1114         .sysc_fields    = &omap_hwmod_sysc_type1,
1115 };
1116
1117 static struct omap_hwmod_class dm816x_mcspi_class = {
1118         .name = "mcspi",
1119         .sysc = &dm816x_mcspi_sysc,
1120 };
1121
1122 static struct omap_hwmod dm81xx_mcspi1_hwmod = {
1123         .name           = "mcspi1",
1124         .clkdm_name     = "alwon_l3s_clkdm",
1125         .main_clk       = "sysclk10_ck",
1126         .prcm           = {
1127                 .omap4 = {
1128                         .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
1129                         .modulemode = MODULEMODE_SWCTRL,
1130                 },
1131         },
1132         .class          = &dm816x_mcspi_class,
1133 };
1134
1135 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = {
1136         .master         = &dm81xx_l4_ls_hwmod,
1137         .slave          = &dm81xx_mcspi1_hwmod,
1138         .clk            = "sysclk6_ck",
1139         .user           = OCP_USER_MPU,
1140 };
1141
1142 static struct omap_hwmod_class_sysconfig dm81xx_mailbox_sysc = {
1143         .rev_offs       = 0x000,
1144         .sysc_offs      = 0x010,
1145         .syss_offs      = 0x014,
1146         .sysc_flags     = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1147                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE,
1148         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1149         .sysc_fields    = &omap_hwmod_sysc_type1,
1150 };
1151
1152 static struct omap_hwmod_class dm81xx_mailbox_hwmod_class = {
1153         .name = "mailbox",
1154         .sysc = &dm81xx_mailbox_sysc,
1155 };
1156
1157 static struct omap_hwmod dm81xx_mailbox_hwmod = {
1158         .name           = "mailbox",
1159         .clkdm_name     = "alwon_l3s_clkdm",
1160         .class          = &dm81xx_mailbox_hwmod_class,
1161         .main_clk       = "sysclk6_ck",
1162         .prcm           = {
1163                 .omap4 = {
1164                         .clkctrl_offs = DM81XX_CM_ALWON_MAILBOX_CLKCTRL,
1165                         .modulemode = MODULEMODE_SWCTRL,
1166                 },
1167         },
1168 };
1169
1170 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mailbox = {
1171         .master         = &dm81xx_l4_ls_hwmod,
1172         .slave          = &dm81xx_mailbox_hwmod,
1173         .clk            = "sysclk6_ck",
1174         .user           = OCP_USER_MPU,
1175 };
1176
1177 static struct omap_hwmod_class_sysconfig dm81xx_spinbox_sysc = {
1178         .rev_offs       = 0x000,
1179         .sysc_offs      = 0x010,
1180         .syss_offs      = 0x014,
1181         .sysc_flags     = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1182                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE,
1183         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1184         .sysc_fields    = &omap_hwmod_sysc_type1,
1185 };
1186
1187 static struct omap_hwmod_class dm81xx_spinbox_hwmod_class = {
1188         .name = "spinbox",
1189         .sysc = &dm81xx_spinbox_sysc,
1190 };
1191
1192 static struct omap_hwmod dm81xx_spinbox_hwmod = {
1193         .name           = "spinbox",
1194         .clkdm_name     = "alwon_l3s_clkdm",
1195         .class          = &dm81xx_spinbox_hwmod_class,
1196         .main_clk       = "sysclk6_ck",
1197         .prcm           = {
1198                 .omap4 = {
1199                         .clkctrl_offs = DM81XX_CM_ALWON_SPINBOX_CLKCTRL,
1200                         .modulemode = MODULEMODE_SWCTRL,
1201                 },
1202         },
1203 };
1204
1205 static struct omap_hwmod_ocp_if dm81xx_l4_ls__spinbox = {
1206         .master         = &dm81xx_l4_ls_hwmod,
1207         .slave          = &dm81xx_spinbox_hwmod,
1208         .clk            = "sysclk6_ck",
1209         .user           = OCP_USER_MPU,
1210 };
1211
1212 static struct omap_hwmod_class dm81xx_tpcc_hwmod_class = {
1213         .name           = "tpcc",
1214 };
1215
1216 static struct omap_hwmod dm81xx_tpcc_hwmod = {
1217         .name           = "tpcc",
1218         .class          = &dm81xx_tpcc_hwmod_class,
1219         .clkdm_name     = "alwon_l3s_clkdm",
1220         .main_clk       = "sysclk4_ck",
1221         .prcm           = {
1222                 .omap4  = {
1223                         .clkctrl_offs   = DM81XX_CM_ALWON_TPCC_CLKCTRL,
1224                         .modulemode     = MODULEMODE_SWCTRL,
1225                 },
1226         },
1227 };
1228
1229 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tpcc = {
1230         .master         = &dm81xx_alwon_l3_fast_hwmod,
1231         .slave          = &dm81xx_tpcc_hwmod,
1232         .clk            = "sysclk4_ck",
1233         .user           = OCP_USER_MPU,
1234 };
1235
1236 static struct omap_hwmod_class dm81xx_tptc0_hwmod_class = {
1237         .name           = "tptc0",
1238 };
1239
1240 static struct omap_hwmod dm81xx_tptc0_hwmod = {
1241         .name           = "tptc0",
1242         .class          = &dm81xx_tptc0_hwmod_class,
1243         .clkdm_name     = "alwon_l3s_clkdm",
1244         .main_clk       = "sysclk4_ck",
1245         .prcm           = {
1246                 .omap4  = {
1247                         .clkctrl_offs   = DM81XX_CM_ALWON_TPTC0_CLKCTRL,
1248                         .modulemode     = MODULEMODE_SWCTRL,
1249                 },
1250         },
1251 };
1252
1253 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc0 = {
1254         .master         = &dm81xx_alwon_l3_fast_hwmod,
1255         .slave          = &dm81xx_tptc0_hwmod,
1256         .clk            = "sysclk4_ck",
1257         .user           = OCP_USER_MPU,
1258 };
1259
1260 static struct omap_hwmod_ocp_if dm81xx_tptc0__alwon_l3_fast = {
1261         .master         = &dm81xx_tptc0_hwmod,
1262         .slave          = &dm81xx_alwon_l3_fast_hwmod,
1263         .clk            = "sysclk4_ck",
1264         .user           = OCP_USER_MPU,
1265 };
1266
1267 static struct omap_hwmod_class dm81xx_tptc1_hwmod_class = {
1268         .name           = "tptc1",
1269 };
1270
1271 static struct omap_hwmod dm81xx_tptc1_hwmod = {
1272         .name           = "tptc1",
1273         .class          = &dm81xx_tptc1_hwmod_class,
1274         .clkdm_name     = "alwon_l3s_clkdm",
1275         .main_clk       = "sysclk4_ck",
1276         .prcm           = {
1277                 .omap4  = {
1278                         .clkctrl_offs   = DM81XX_CM_ALWON_TPTC1_CLKCTRL,
1279                         .modulemode     = MODULEMODE_SWCTRL,
1280                 },
1281         },
1282 };
1283
1284 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc1 = {
1285         .master         = &dm81xx_alwon_l3_fast_hwmod,
1286         .slave          = &dm81xx_tptc1_hwmod,
1287         .clk            = "sysclk4_ck",
1288         .user           = OCP_USER_MPU,
1289 };
1290
1291 static struct omap_hwmod_ocp_if dm81xx_tptc1__alwon_l3_fast = {
1292         .master         = &dm81xx_tptc1_hwmod,
1293         .slave          = &dm81xx_alwon_l3_fast_hwmod,
1294         .clk            = "sysclk4_ck",
1295         .user           = OCP_USER_MPU,
1296 };
1297
1298 static struct omap_hwmod_class dm81xx_tptc2_hwmod_class = {
1299         .name           = "tptc2",
1300 };
1301
1302 static struct omap_hwmod dm81xx_tptc2_hwmod = {
1303         .name           = "tptc2",
1304         .class          = &dm81xx_tptc2_hwmod_class,
1305         .clkdm_name     = "alwon_l3s_clkdm",
1306         .main_clk       = "sysclk4_ck",
1307         .prcm           = {
1308                 .omap4  = {
1309                         .clkctrl_offs   = DM81XX_CM_ALWON_TPTC2_CLKCTRL,
1310                         .modulemode     = MODULEMODE_SWCTRL,
1311                 },
1312         },
1313 };
1314
1315 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc2 = {
1316         .master         = &dm81xx_alwon_l3_fast_hwmod,
1317         .slave          = &dm81xx_tptc2_hwmod,
1318         .clk            = "sysclk4_ck",
1319         .user           = OCP_USER_MPU,
1320 };
1321
1322 static struct omap_hwmod_ocp_if dm81xx_tptc2__alwon_l3_fast = {
1323         .master         = &dm81xx_tptc2_hwmod,
1324         .slave          = &dm81xx_alwon_l3_fast_hwmod,
1325         .clk            = "sysclk4_ck",
1326         .user           = OCP_USER_MPU,
1327 };
1328
1329 static struct omap_hwmod_class dm81xx_tptc3_hwmod_class = {
1330         .name           = "tptc3",
1331 };
1332
1333 static struct omap_hwmod dm81xx_tptc3_hwmod = {
1334         .name           = "tptc3",
1335         .class          = &dm81xx_tptc3_hwmod_class,
1336         .clkdm_name     = "alwon_l3s_clkdm",
1337         .main_clk       = "sysclk4_ck",
1338         .prcm           = {
1339                 .omap4  = {
1340                         .clkctrl_offs   = DM81XX_CM_ALWON_TPTC3_CLKCTRL,
1341                         .modulemode     = MODULEMODE_SWCTRL,
1342                 },
1343         },
1344 };
1345
1346 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc3 = {
1347         .master         = &dm81xx_alwon_l3_fast_hwmod,
1348         .slave          = &dm81xx_tptc3_hwmod,
1349         .clk            = "sysclk4_ck",
1350         .user           = OCP_USER_MPU,
1351 };
1352
1353 static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = {
1354         .master         = &dm81xx_tptc3_hwmod,
1355         .slave          = &dm81xx_alwon_l3_fast_hwmod,
1356         .clk            = "sysclk4_ck",
1357         .user           = OCP_USER_MPU,
1358 };
1359
1360 /*
1361  * REVISIT: Test and enable the following once clocks work:
1362  * dm81xx_l4_ls__mailbox
1363  *
1364  * Also note that some devices share a single clkctrl_offs..
1365  * For example, i2c1 and 3 share one, and i2c2 and 4 share one.
1366  */
1367 static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = {
1368         &dm814x_mpu__alwon_l3_slow,
1369         &dm814x_mpu__alwon_l3_med,
1370         &dm81xx_alwon_l3_slow__l4_ls,
1371         &dm81xx_alwon_l3_slow__l4_hs,
1372         &dm81xx_l4_ls__uart1,
1373         &dm81xx_l4_ls__uart2,
1374         &dm81xx_l4_ls__uart3,
1375         &dm81xx_l4_ls__wd_timer1,
1376         &dm81xx_l4_ls__i2c1,
1377         &dm81xx_l4_ls__i2c2,
1378         &dm81xx_l4_ls__gpio1,
1379         &dm81xx_l4_ls__gpio2,
1380         &dm81xx_l4_ls__elm,
1381         &dm81xx_l4_ls__mcspi1,
1382         &dm814x_l4_ls__mmc1,
1383         &dm814x_l4_ls__mmc2,
1384         &ti81xx_l4_ls__rtc,
1385         &dm81xx_alwon_l3_fast__tpcc,
1386         &dm81xx_alwon_l3_fast__tptc0,
1387         &dm81xx_alwon_l3_fast__tptc1,
1388         &dm81xx_alwon_l3_fast__tptc2,
1389         &dm81xx_alwon_l3_fast__tptc3,
1390         &dm81xx_tptc0__alwon_l3_fast,
1391         &dm81xx_tptc1__alwon_l3_fast,
1392         &dm81xx_tptc2__alwon_l3_fast,
1393         &dm81xx_tptc3__alwon_l3_fast,
1394         &dm814x_l4_ls__timer1,
1395         &dm814x_l4_ls__timer2,
1396         &dm814x_l4_hs__cpgmac0,
1397         &dm814x_cpgmac0__mdio,
1398         &dm81xx_alwon_l3_slow__gpmc,
1399         &dm814x_default_l3_slow__usbss,
1400         &dm814x_alwon_l3_med__mmc3,
1401         NULL,
1402 };
1403
1404 int __init dm814x_hwmod_init(void)
1405 {
1406         omap_hwmod_init();
1407         return omap_hwmod_register_links(dm814x_hwmod_ocp_ifs);
1408 }
1409
1410 static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = {
1411         &dm816x_mpu__alwon_l3_slow,
1412         &dm816x_mpu__alwon_l3_med,
1413         &dm81xx_alwon_l3_slow__l4_ls,
1414         &dm81xx_alwon_l3_slow__l4_hs,
1415         &dm81xx_l4_ls__uart1,
1416         &dm81xx_l4_ls__uart2,
1417         &dm81xx_l4_ls__uart3,
1418         &dm81xx_l4_ls__wd_timer1,
1419         &dm81xx_l4_ls__i2c1,
1420         &dm81xx_l4_ls__i2c2,
1421         &dm81xx_l4_ls__gpio1,
1422         &dm81xx_l4_ls__gpio2,
1423         &dm81xx_l4_ls__elm,
1424         &ti81xx_l4_ls__rtc,
1425         &dm816x_l4_ls__mmc1,
1426         &dm816x_l4_ls__timer1,
1427         &dm816x_l4_ls__timer2,
1428         &dm816x_l4_ls__timer3,
1429         &dm816x_l4_ls__timer4,
1430         &dm816x_l4_ls__timer5,
1431         &dm816x_l4_ls__timer6,
1432         &dm816x_l4_ls__timer7,
1433         &dm81xx_l4_ls__mcspi1,
1434         &dm81xx_l4_ls__mailbox,
1435         &dm81xx_l4_ls__spinbox,
1436         &dm81xx_l4_hs__emac0,
1437         &dm81xx_emac0__mdio,
1438         &dm816x_l4_hs__emac1,
1439         &dm81xx_l4_hs__sata,
1440         &dm81xx_alwon_l3_fast__tpcc,
1441         &dm81xx_alwon_l3_fast__tptc0,
1442         &dm81xx_alwon_l3_fast__tptc1,
1443         &dm81xx_alwon_l3_fast__tptc2,
1444         &dm81xx_alwon_l3_fast__tptc3,
1445         &dm81xx_tptc0__alwon_l3_fast,
1446         &dm81xx_tptc1__alwon_l3_fast,
1447         &dm81xx_tptc2__alwon_l3_fast,
1448         &dm81xx_tptc3__alwon_l3_fast,
1449         &dm81xx_alwon_l3_slow__gpmc,
1450         &dm816x_default_l3_slow__usbss,
1451         NULL,
1452 };
1453
1454 int __init dm816x_hwmod_init(void)
1455 {
1456         omap_hwmod_init();
1457         return omap_hwmod_register_links(dm816x_hwmod_ocp_ifs);
1458 }