arch/arm/mach-omap2/omap_hwmod_7xx_data.c

   1 /*
   2  * Hardware modules present on the DRA7xx chips
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Paul Walmsley
   7  * Benoit Cousson
   8  *
   9  * This file is automatically generated from the OMAP hardware databases.
  10  * We respectfully ask that any modifications to this file be coordinated
  11  * with the public linux-omap@vger.kernel.org mailing list and the
  12  * authors above to ensure that the autogeneration scripts are kept
  13  * up-to-date with the file contents.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include <linux/io.h>
  21 #include <linux/platform_data/gpio-omap.h>
  22 #include <linux/platform_data/hsmmc-omap.h>
  23 #include <linux/power/smartreflex.h>
  24 #include <linux/i2c-omap.h>
  25
  26 #include <linux/omap-dma.h>
  27 #include <linux/platform_data/spi-omap2-mcspi.h>
  28 #include <linux/platform_data/asoc-ti-mcbsp.h>
  29 #include <plat/dmtimer.h>
  30
  31 #include "omap_hwmod.h"
  32 #include "omap_hwmod_common_data.h"
  33 #include "cm1_7xx.h"
  34 #include "cm2_7xx.h"
  35 #include "prm7xx.h"
  36 #include "i2c.h"
  37 #include "wd_timer.h"
  38 #include "soc.h"
  39
  40 /* Base offset for all DRA7XX interrupts external to MPUSS */
  41 #define DRA7XX_IRQ_GIC_START    32
  42
  43 /* Base offset for all DRA7XX dma requests */
  44 #define DRA7XX_DMA_REQ_START    1
  45
  46
  47 /*
  48  * IP blocks
  49  */
  50
  51 /*
  52  * 'dmm' class
  53  * instance(s): dmm
  54  */
  55 static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
  56         .name   = "dmm",
  57 };
  58
  59 /* dmm */
  60 static struct omap_hwmod dra7xx_dmm_hwmod = {
  61         .name           = "dmm",
  62         .class          = &dra7xx_dmm_hwmod_class,
  63         .clkdm_name     = "emif_clkdm",
  64         .prcm = {
  65                 .omap4 = {
  66                         .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
  67                         .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
  68                 },
  69         },
  70 };
  71
  72 /*
  73  * 'l3' class
  74  * instance(s): l3_instr, l3_main_1, l3_main_2
  75  */
  76 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
  77         .name   = "l3",
  78 };
  79
  80 /* l3_instr */
  81 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
  82         .name           = "l3_instr",
  83         .class          = &dra7xx_l3_hwmod_class,
  84         .clkdm_name     = "l3instr_clkdm",
  85         .prcm = {
  86                 .omap4 = {
  87                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  88                         .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  89                         .modulemode   = MODULEMODE_HWCTRL,
  90                 },
  91         },
  92 };
  93
  94 /* l3_main_1 */
  95 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
  96         .name           = "l3_main_1",
  97         .class          = &dra7xx_l3_hwmod_class,
  98         .clkdm_name     = "l3main1_clkdm",
  99         .prcm = {
 100                 .omap4 = {
 101                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
 102                         .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
 103                 },
 104         },
 105 };
 106
 107 /* l3_main_2 */
 108 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
 109         .name           = "l3_main_2",
 110         .class          = &dra7xx_l3_hwmod_class,
 111         .clkdm_name     = "l3instr_clkdm",
 112         .prcm = {
 113                 .omap4 = {
 114                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
 115                         .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
 116                         .modulemode   = MODULEMODE_HWCTRL,
 117                 },
 118         },
 119 };
 120
 121 /*
 122  * 'l4' class
 123  * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
 124  */
 125 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
 126         .name   = "l4",
 127 };
 128
 129 /* l4_cfg */
 130 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
 131         .name           = "l4_cfg",
 132         .class          = &dra7xx_l4_hwmod_class,
 133         .clkdm_name     = "l4cfg_clkdm",
 134         .prcm = {
 135                 .omap4 = {
 136                         .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 137                         .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 138                 },
 139         },
 140 };
 141
 142 /* l4_per1 */
 143 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
 144         .name           = "l4_per1",
 145         .class          = &dra7xx_l4_hwmod_class,
 146         .clkdm_name     = "l4per_clkdm",
 147         .prcm = {
 148                 .omap4 = {
 149                         .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
 150                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 151                 },
 152         },
 153 };
 154
 155 /* l4_per2 */
 156 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
 157         .name           = "l4_per2",
 158         .class          = &dra7xx_l4_hwmod_class,
 159         .clkdm_name     = "l4per2_clkdm",
 160         .prcm = {
 161                 .omap4 = {
 162                         .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
 163                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 164                 },
 165         },
 166 };
 167
 168 /* l4_per3 */
 169 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
 170         .name           = "l4_per3",
 171         .class          = &dra7xx_l4_hwmod_class,
 172         .clkdm_name     = "l4per3_clkdm",
 173         .prcm = {
 174                 .omap4 = {
 175                         .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
 176                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 177                 },
 178         },
 179 };
 180
 181 /* l4_wkup */
 182 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
 183         .name           = "l4_wkup",
 184         .class          = &dra7xx_l4_hwmod_class,
 185         .clkdm_name     = "wkupaon_clkdm",
 186         .prcm = {
 187                 .omap4 = {
 188                         .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
 189                         .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
 190                 },
 191         },
 192 };
 193
 194 /*
 195  * 'atl' class
 196  *
 197  */
 198
 199 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
 200         .name   = "atl",
 201 };
 202
 203 /* atl */
 204 static struct omap_hwmod dra7xx_atl_hwmod = {
 205         .name           = "atl",
 206         .class          = &dra7xx_atl_hwmod_class,
 207         .clkdm_name     = "atl_clkdm",
 208         .main_clk       = "atl_gfclk_mux",
 209         .prcm = {
 210                 .omap4 = {
 211                         .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
 212                         .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
 213                         .modulemode   = MODULEMODE_SWCTRL,
 214                 },
 215         },
 216 };
 217
 218 /*
 219  * 'bb2d' class
 220  *
 221  */
 222
 223 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
 224         .name   = "bb2d",
 225 };
 226
 227 /* bb2d */
 228 static struct omap_hwmod dra7xx_bb2d_hwmod = {
 229         .name           = "bb2d",
 230         .class          = &dra7xx_bb2d_hwmod_class,
 231         .clkdm_name     = "dss_clkdm",
 232         .main_clk       = "dpll_core_h24x2_ck",
 233         .prcm = {
 234                 .omap4 = {
 235                         .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
 236                         .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
 237                         .modulemode   = MODULEMODE_SWCTRL,
 238                 },
 239         },
 240 };
 241
 242 /*
 243  * 'counter' class
 244  *
 245  */
 246
 247 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
 248         .rev_offs       = 0x0000,
 249         .sysc_offs      = 0x0010,
 250         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 251         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 252                            SIDLE_SMART_WKUP),
 253         .sysc_fields    = &omap_hwmod_sysc_type1,
 254 };
 255
 256 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
 257         .name   = "counter",
 258         .sysc   = &dra7xx_counter_sysc,
 259 };
 260
 261 /* counter_32k */
 262 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
 263         .name           = "counter_32k",
 264         .class          = &dra7xx_counter_hwmod_class,
 265         .clkdm_name     = "wkupaon_clkdm",
 266         .flags          = HWMOD_SWSUP_SIDLE,
 267         .main_clk       = "wkupaon_iclk_mux",
 268         .prcm = {
 269                 .omap4 = {
 270                         .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
 271                         .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
 272                 },
 273         },
 274 };
 275
 276 /*
 277  * 'ctrl_module' class
 278  *
 279  */
 280
 281 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
 282         .name   = "ctrl_module",
 283 };
 284
 285 /* ctrl_module_wkup */
 286 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
 287         .name           = "ctrl_module_wkup",
 288         .class          = &dra7xx_ctrl_module_hwmod_class,
 289         .clkdm_name     = "wkupaon_clkdm",
 290         .prcm = {
 291                 .omap4 = {
 292                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 293                 },
 294         },
 295 };
 296
 297 /*
 298  * 'gmac' class
 299  * cpsw/gmac sub system
 300  */
 301 static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
 302         .rev_offs       = 0x0,
 303         .sysc_offs      = 0x8,
 304         .syss_offs      = 0x4,
 305         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 306                            SYSS_HAS_RESET_STATUS),
 307         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
 308                            MSTANDBY_NO),
 309         .sysc_fields    = &omap_hwmod_sysc_type3,
 310 };
 311
 312 static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
 313         .name           = "gmac",
 314         .sysc           = &dra7xx_gmac_sysc,
 315 };
 316
 317 static struct omap_hwmod dra7xx_gmac_hwmod = {
 318         .name           = "gmac",
 319         .class          = &dra7xx_gmac_hwmod_class,
 320         .clkdm_name     = "gmac_clkdm",
 321         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 322         .main_clk       = "dpll_gmac_ck",
 323         .mpu_rt_idx     = 1,
 324         .prcm           = {
 325                 .omap4  = {
 326                         .clkctrl_offs   = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
 327                         .context_offs   = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
 328                         .modulemode     = MODULEMODE_SWCTRL,
 329                 },
 330         },
 331 };
 332
 333 /*
 334  * 'mdio' class
 335  */
 336 static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
 337         .name           = "davinci_mdio",
 338 };
 339
 340 static struct omap_hwmod dra7xx_mdio_hwmod = {
 341         .name           = "davinci_mdio",
 342         .class          = &dra7xx_mdio_hwmod_class,
 343         .clkdm_name     = "gmac_clkdm",
 344         .main_clk       = "dpll_gmac_ck",
 345 };
 346
 347 /*
 348  * 'dcan' class
 349  *
 350  */
 351
 352 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
 353         .name   = "dcan",
 354 };
 355
 356 /* dcan1 */
 357 static struct omap_hwmod dra7xx_dcan1_hwmod = {
 358         .name           = "dcan1",
 359         .class          = &dra7xx_dcan_hwmod_class,
 360         .clkdm_name     = "wkupaon_clkdm",
 361         .main_clk       = "dcan1_sys_clk_mux",
 362         .flags          = HWMOD_CLKDM_NOAUTO,
 363         .prcm = {
 364                 .omap4 = {
 365                         .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
 366                         .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
 367                         .modulemode   = MODULEMODE_SWCTRL,
 368                 },
 369         },
 370 };
 371
 372 /* dcan2 */
 373 static struct omap_hwmod dra7xx_dcan2_hwmod = {
 374         .name           = "dcan2",
 375         .class          = &dra7xx_dcan_hwmod_class,
 376         .clkdm_name     = "l4per2_clkdm",
 377         .main_clk       = "sys_clkin1",
 378         .flags          = HWMOD_CLKDM_NOAUTO,
 379         .prcm = {
 380                 .omap4 = {
 381                         .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
 382                         .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
 383                         .modulemode   = MODULEMODE_SWCTRL,
 384                 },
 385         },
 386 };
 387
 388 /* pwmss  */
 389 static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = {
 390         .rev_offs       = 0x0,
 391         .sysc_offs      = 0x4,
 392         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET,
 393         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 394         .sysc_fields    = &omap_hwmod_sysc_type2,
 395 };
 396
 397 /*
 398  * epwmss class
 399  */
 400 static struct omap_hwmod_class dra7xx_epwmss_hwmod_class = {
 401         .name           = "epwmss",
 402         .sysc           = &dra7xx_epwmss_sysc,
 403 };
 404
 405 /* epwmss0 */
 406 static struct omap_hwmod dra7xx_epwmss0_hwmod = {
 407         .name           = "epwmss0",
 408         .class          = &dra7xx_epwmss_hwmod_class,
 409         .clkdm_name     = "l4per2_clkdm",
 410         .main_clk       = "l4_root_clk_div",
 411         .prcm           = {
 412                 .omap4  = {
 413                         .modulemode     = MODULEMODE_SWCTRL,
 414                         .clkctrl_offs   = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,
 415                         .context_offs   = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
 416                 },
 417         },
 418 };
 419
 420 /* epwmss1 */
 421 static struct omap_hwmod dra7xx_epwmss1_hwmod = {
 422         .name           = "epwmss1",
 423         .class          = &dra7xx_epwmss_hwmod_class,
 424         .clkdm_name     = "l4per2_clkdm",
 425         .main_clk       = "l4_root_clk_div",
 426         .prcm           = {
 427                 .omap4  = {
 428                         .modulemode     = MODULEMODE_SWCTRL,
 429                         .clkctrl_offs   = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,
 430                         .context_offs   = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
 431                 },
 432         },
 433 };
 434
 435 /* epwmss2 */
 436 static struct omap_hwmod dra7xx_epwmss2_hwmod = {
 437         .name           = "epwmss2",
 438         .class          = &dra7xx_epwmss_hwmod_class,
 439         .clkdm_name     = "l4per2_clkdm",
 440         .main_clk       = "l4_root_clk_div",
 441         .prcm           = {
 442                 .omap4  = {
 443                         .modulemode     = MODULEMODE_SWCTRL,
 444                         .clkctrl_offs   = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,
 445                         .context_offs   = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
 446                 },
 447         },
 448 };
 449
 450 /*
 451  * 'dma' class
 452  *
 453  */
 454
 455 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
 456         .rev_offs       = 0x0000,
 457         .sysc_offs      = 0x002c,
 458         .syss_offs      = 0x0028,
 459         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 460                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 461                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 462                            SYSS_HAS_RESET_STATUS),
 463         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 464                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 465                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 466         .sysc_fields    = &omap_hwmod_sysc_type1,
 467 };
 468
 469 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
 470         .name   = "dma",
 471         .sysc   = &dra7xx_dma_sysc,
 472 };
 473
 474 /* dma dev_attr */
 475 static struct omap_dma_dev_attr dma_dev_attr = {
 476         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 477                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 478         .lch_count      = 32,
 479 };
 480
 481 /* dma_system */
 482 static struct omap_hwmod dra7xx_dma_system_hwmod = {
 483         .name           = "dma_system",
 484         .class          = &dra7xx_dma_hwmod_class,
 485         .clkdm_name     = "dma_clkdm",
 486         .main_clk       = "l3_iclk_div",
 487         .prcm = {
 488                 .omap4 = {
 489                         .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
 490                         .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
 491                 },
 492         },
 493         .dev_attr       = &dma_dev_attr,
 494 };
 495
 496 /*
 497  * 'tpcc' class
 498  *
 499  */
 500 static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
 501         .name           = "tpcc",
 502 };
 503
 504 static struct omap_hwmod dra7xx_tpcc_hwmod = {
 505         .name           = "tpcc",
 506         .class          = &dra7xx_tpcc_hwmod_class,
 507         .clkdm_name     = "l3main1_clkdm",
 508         .main_clk       = "l3_iclk_div",
 509         .prcm           = {
 510                 .omap4  = {
 511                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET,
 512                         .context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
 513                 },
 514         },
 515 };
 516
 517 /*
 518  * 'tptc' class
 519  *
 520  */
 521 static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
 522         .name           = "tptc",
 523 };
 524
 525 /* tptc0 */
 526 static struct omap_hwmod dra7xx_tptc0_hwmod = {
 527         .name           = "tptc0",
 528         .class          = &dra7xx_tptc_hwmod_class,
 529         .clkdm_name     = "l3main1_clkdm",
 530         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 531         .main_clk       = "l3_iclk_div",
 532         .prcm           = {
 533                 .omap4  = {
 534                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET,
 535                         .context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
 536                         .modulemode   = MODULEMODE_HWCTRL,
 537                 },
 538         },
 539 };
 540
 541 /* tptc1 */
 542 static struct omap_hwmod dra7xx_tptc1_hwmod = {
 543         .name           = "tptc1",
 544         .class          = &dra7xx_tptc_hwmod_class,
 545         .clkdm_name     = "l3main1_clkdm",
 546         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 547         .main_clk       = "l3_iclk_div",
 548         .prcm           = {
 549                 .omap4  = {
 550                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET,
 551                         .context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
 552                         .modulemode   = MODULEMODE_HWCTRL,
 553                 },
 554         },
 555 };
 556
 557 /*
 558  * 'dss' class
 559  *
 560  */
 561
 562 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
 563         .rev_offs       = 0x0000,
 564         .syss_offs      = 0x0014,
 565         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 566 };
 567
 568 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
 569         .name   = "dss",
 570         .sysc   = &dra7xx_dss_sysc,
 571         .reset  = omap_dss_reset,
 572 };
 573
 574 /* dss */
 575 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 576         { .role = "dss_clk", .clk = "dss_dss_clk" },
 577         { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
 578         { .role = "32khz_clk", .clk = "dss_32khz_clk" },
 579         { .role = "video2_clk", .clk = "dss_video2_clk" },
 580         { .role = "video1_clk", .clk = "dss_video1_clk" },
 581         { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
 582         { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
 583 };
 584
 585 static struct omap_hwmod dra7xx_dss_hwmod = {
 586         .name           = "dss_core",
 587         .class          = &dra7xx_dss_hwmod_class,
 588         .clkdm_name     = "dss_clkdm",
 589         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 590         .main_clk       = "dss_dss_clk",
 591         .prcm = {
 592                 .omap4 = {
 593                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 594                         .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
 595                         .modulemode   = MODULEMODE_SWCTRL,
 596                 },
 597         },
 598         .opt_clks       = dss_opt_clks,
 599         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 600 };
 601
 602 /*
 603  * 'dispc' class
 604  * display controller
 605  */
 606
 607 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
 608         .rev_offs       = 0x0000,
 609         .sysc_offs      = 0x0010,
 610         .syss_offs      = 0x0014,
 611         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 612                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 613                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 614                            SYSS_HAS_RESET_STATUS),
 615         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 616                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 617         .sysc_fields    = &omap_hwmod_sysc_type1,
 618 };
 619
 620 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
 621         .name   = "dispc",
 622         .sysc   = &dra7xx_dispc_sysc,
 623 };
 624
 625 /* dss_dispc */
 626 /* dss_dispc dev_attr */
 627 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
 628         .has_framedonetv_irq    = 1,
 629         .manager_count          = 4,
 630 };
 631
 632 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
 633         .name           = "dss_dispc",
 634         .class          = &dra7xx_dispc_hwmod_class,
 635         .clkdm_name     = "dss_clkdm",
 636         .main_clk       = "dss_dss_clk",
 637         .prcm = {
 638                 .omap4 = {
 639                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 640                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 641                 },
 642         },
 643         .dev_attr       = &dss_dispc_dev_attr,
 644         .parent_hwmod   = &dra7xx_dss_hwmod,
 645 };
 646
 647 /*
 648  * 'hdmi' class
 649  * hdmi controller
 650  */
 651
 652 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
 653         .rev_offs       = 0x0000,
 654         .sysc_offs      = 0x0010,
 655         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 656                            SYSC_HAS_SOFTRESET),
 657         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 658                            SIDLE_SMART_WKUP),
 659         .sysc_fields    = &omap_hwmod_sysc_type2,
 660 };
 661
 662 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
 663         .name   = "hdmi",
 664         .sysc   = &dra7xx_hdmi_sysc,
 665 };
 666
 667 /* dss_hdmi */
 668
 669 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 670         { .role = "sys_clk", .clk = "dss_hdmi_clk" },
 671 };
 672
 673 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
 674         .name           = "dss_hdmi",
 675         .class          = &dra7xx_hdmi_hwmod_class,
 676         .clkdm_name     = "dss_clkdm",
 677         .main_clk       = "dss_48mhz_clk",
 678         .prcm = {
 679                 .omap4 = {
 680                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 681                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 682                 },
 683         },
 684         .opt_clks       = dss_hdmi_opt_clks,
 685         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 686         .parent_hwmod   = &dra7xx_dss_hwmod,
 687 };
 688
 689 /* AES (the 'P' (public) device) */
 690 static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = {
 691         .rev_offs       = 0x0080,
 692         .sysc_offs      = 0x0084,
 693         .syss_offs      = 0x0088,
 694         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 695 };
 696
 697 static struct omap_hwmod_class dra7xx_aes_hwmod_class = {
 698         .name   = "aes",
 699         .sysc   = &dra7xx_aes_sysc,
 700         .rev    = 2,
 701 };
 702
 703 /* AES1 */
 704 static struct omap_hwmod dra7xx_aes1_hwmod = {
 705         .name           = "aes1",
 706         .class          = &dra7xx_aes_hwmod_class,
 707         .clkdm_name     = "l4sec_clkdm",
 708         .main_clk       = "l3_iclk_div",
 709         .prcm = {
 710                 .omap4 = {
 711                         .clkctrl_offs = DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET,
 712                         .context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET,
 713                         .modulemode   = MODULEMODE_HWCTRL,
 714                 },
 715         },
 716 };
 717
 718 /* AES2 */
 719 static struct omap_hwmod dra7xx_aes2_hwmod = {
 720         .name           = "aes2",
 721         .class          = &dra7xx_aes_hwmod_class,
 722         .clkdm_name     = "l4sec_clkdm",
 723         .main_clk       = "l3_iclk_div",
 724         .prcm = {
 725                 .omap4 = {
 726                         .clkctrl_offs = DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET,
 727                         .context_offs = DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET,
 728                         .modulemode   = MODULEMODE_HWCTRL,
 729                 },
 730         },
 731 };
 732
 733 /* sha0 HIB2 (the 'P' (public) device) */
 734 static struct omap_hwmod_class_sysconfig dra7xx_sha0_sysc = {
 735         .rev_offs       = 0x100,
 736         .sysc_offs      = 0x110,
 737         .syss_offs      = 0x114,
 738         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 739 };
 740
 741 static struct omap_hwmod_class dra7xx_sha0_hwmod_class = {
 742         .name           = "sham",
 743         .sysc           = &dra7xx_sha0_sysc,
 744         .rev            = 2,
 745 };
 746
 747 struct omap_hwmod dra7xx_sha0_hwmod = {
 748         .name           = "sham",
 749         .class          = &dra7xx_sha0_hwmod_class,
 750         .clkdm_name     = "l4sec_clkdm",
 751         .main_clk       = "l3_iclk_div",
 752         .prcm           = {
 753                 .omap4 = {
 754                         .clkctrl_offs = DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
 755                         .context_offs = DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
 756                         .modulemode   = MODULEMODE_HWCTRL,
 757                 },
 758         },
 759 };
 760
 761 /*
 762  * 'elm' class
 763  *
 764  */
 765
 766 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
 767         .rev_offs       = 0x0000,
 768         .sysc_offs      = 0x0010,
 769         .syss_offs      = 0x0014,
 770         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 771                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 772                            SYSS_HAS_RESET_STATUS),
 773         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 774                            SIDLE_SMART_WKUP),
 775         .sysc_fields    = &omap_hwmod_sysc_type1,
 776 };
 777
 778 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
 779         .name   = "elm",
 780         .sysc   = &dra7xx_elm_sysc,
 781 };
 782
 783 /* elm */
 784
 785 static struct omap_hwmod dra7xx_elm_hwmod = {
 786         .name           = "elm",
 787         .class          = &dra7xx_elm_hwmod_class,
 788         .clkdm_name     = "l4per_clkdm",
 789         .main_clk       = "l3_iclk_div",
 790         .prcm = {
 791                 .omap4 = {
 792                         .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
 793                         .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
 794                 },
 795         },
 796 };
 797
 798 /*
 799  * 'gpio' class
 800  *
 801  */
 802
 803 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
 804         .rev_offs       = 0x0000,
 805         .sysc_offs      = 0x0010,
 806         .syss_offs      = 0x0114,
 807         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 808                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 809                            SYSS_HAS_RESET_STATUS),
 810         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 811                            SIDLE_SMART_WKUP),
 812         .sysc_fields    = &omap_hwmod_sysc_type1,
 813 };
 814
 815 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
 816         .name   = "gpio",
 817         .sysc   = &dra7xx_gpio_sysc,
 818         .rev    = 2,
 819 };
 820
 821 /* gpio dev_attr */
 822 static struct omap_gpio_dev_attr gpio_dev_attr = {
 823         .bank_width     = 32,
 824         .dbck_flag      = true,
 825 };
 826
 827 /* gpio1 */
 828 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 829         { .role = "dbclk", .clk = "gpio1_dbclk" },
 830 };
 831
 832 static struct omap_hwmod dra7xx_gpio1_hwmod = {
 833         .name           = "gpio1",
 834         .class          = &dra7xx_gpio_hwmod_class,
 835         .clkdm_name     = "wkupaon_clkdm",
 836         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 837         .main_clk       = "wkupaon_iclk_mux",
 838         .prcm = {
 839                 .omap4 = {
 840                         .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
 841                         .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
 842                         .modulemode   = MODULEMODE_HWCTRL,
 843                 },
 844         },
 845         .opt_clks       = gpio1_opt_clks,
 846         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 847         .dev_attr       = &gpio_dev_attr,
 848 };
 849
 850 /* gpio2 */
 851 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 852         { .role = "dbclk", .clk = "gpio2_dbclk" },
 853 };
 854
 855 static struct omap_hwmod dra7xx_gpio2_hwmod = {
 856         .name           = "gpio2",
 857         .class          = &dra7xx_gpio_hwmod_class,
 858         .clkdm_name     = "l4per_clkdm",
 859         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 860         .main_clk       = "l3_iclk_div",
 861         .prcm = {
 862                 .omap4 = {
 863                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
 864                         .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
 865                         .modulemode   = MODULEMODE_HWCTRL,
 866                 },
 867         },
 868         .opt_clks       = gpio2_opt_clks,
 869         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 870         .dev_attr       = &gpio_dev_attr,
 871 };
 872
 873 /* gpio3 */
 874 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 875         { .role = "dbclk", .clk = "gpio3_dbclk" },
 876 };
 877
 878 static struct omap_hwmod dra7xx_gpio3_hwmod = {
 879         .name           = "gpio3",
 880         .class          = &dra7xx_gpio_hwmod_class,
 881         .clkdm_name     = "l4per_clkdm",
 882         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 883         .main_clk       = "l3_iclk_div",
 884         .prcm = {
 885                 .omap4 = {
 886                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
 887                         .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
 888                         .modulemode   = MODULEMODE_HWCTRL,
 889                 },
 890         },
 891         .opt_clks       = gpio3_opt_clks,
 892         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 893         .dev_attr       = &gpio_dev_attr,
 894 };
 895
 896 /* gpio4 */
 897 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 898         { .role = "dbclk", .clk = "gpio4_dbclk" },
 899 };
 900
 901 static struct omap_hwmod dra7xx_gpio4_hwmod = {
 902         .name           = "gpio4",
 903         .class          = &dra7xx_gpio_hwmod_class,
 904         .clkdm_name     = "l4per_clkdm",
 905         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 906         .main_clk       = "l3_iclk_div",
 907         .prcm = {
 908                 .omap4 = {
 909                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
 910                         .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
 911                         .modulemode   = MODULEMODE_HWCTRL,
 912                 },
 913         },
 914         .opt_clks       = gpio4_opt_clks,
 915         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 916         .dev_attr       = &gpio_dev_attr,
 917 };
 918
 919 /* gpio5 */
 920 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 921         { .role = "dbclk", .clk = "gpio5_dbclk" },
 922 };
 923
 924 static struct omap_hwmod dra7xx_gpio5_hwmod = {
 925         .name           = "gpio5",
 926         .class          = &dra7xx_gpio_hwmod_class,
 927         .clkdm_name     = "l4per_clkdm",
 928         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 929         .main_clk       = "l3_iclk_div",
 930         .prcm = {
 931                 .omap4 = {
 932                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
 933                         .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
 934                         .modulemode   = MODULEMODE_HWCTRL,
 935                 },
 936         },
 937         .opt_clks       = gpio5_opt_clks,
 938         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
 939         .dev_attr       = &gpio_dev_attr,
 940 };
 941
 942 /* gpio6 */
 943 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
 944         { .role = "dbclk", .clk = "gpio6_dbclk" },
 945 };
 946
 947 static struct omap_hwmod dra7xx_gpio6_hwmod = {
 948         .name           = "gpio6",
 949         .class          = &dra7xx_gpio_hwmod_class,
 950         .clkdm_name     = "l4per_clkdm",
 951         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 952         .main_clk       = "l3_iclk_div",
 953         .prcm = {
 954                 .omap4 = {
 955                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
 956                         .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
 957                         .modulemode   = MODULEMODE_HWCTRL,
 958                 },
 959         },
 960         .opt_clks       = gpio6_opt_clks,
 961         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
 962         .dev_attr       = &gpio_dev_attr,
 963 };
 964
 965 /* gpio7 */
 966 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
 967         { .role = "dbclk", .clk = "gpio7_dbclk" },
 968 };
 969
 970 static struct omap_hwmod dra7xx_gpio7_hwmod = {
 971         .name           = "gpio7",
 972         .class          = &dra7xx_gpio_hwmod_class,
 973         .clkdm_name     = "l4per_clkdm",
 974         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 975         .main_clk       = "l3_iclk_div",
 976         .prcm = {
 977                 .omap4 = {
 978                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
 979                         .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
 980                         .modulemode   = MODULEMODE_HWCTRL,
 981                 },
 982         },
 983         .opt_clks       = gpio7_opt_clks,
 984         .opt_clks_cnt   = ARRAY_SIZE(gpio7_opt_clks),
 985         .dev_attr       = &gpio_dev_attr,
 986 };
 987
 988 /* gpio8 */
 989 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
 990         { .role = "dbclk", .clk = "gpio8_dbclk" },
 991 };
 992
 993 static struct omap_hwmod dra7xx_gpio8_hwmod = {
 994         .name           = "gpio8",
 995         .class          = &dra7xx_gpio_hwmod_class,
 996         .clkdm_name     = "l4per_clkdm",
 997         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 998         .main_clk       = "l3_iclk_div",
 999         .prcm = {
1000                 .omap4 = {
1001                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
1002                         .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
1003                         .modulemode   = MODULEMODE_HWCTRL,
1004                 },
1005         },
1006         .opt_clks       = gpio8_opt_clks,
1007         .opt_clks_cnt   = ARRAY_SIZE(gpio8_opt_clks),
1008         .dev_attr       = &gpio_dev_attr,
1009 };
1010
1011 /*
1012  * 'gpmc' class
1013  *
1014  */
1015
1016 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
1017         .rev_offs       = 0x0000,
1018         .sysc_offs      = 0x0010,
1019         .syss_offs      = 0x0014,
1020         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1021                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1022         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1023         .sysc_fields    = &omap_hwmod_sysc_type1,
1024 };
1025
1026 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
1027         .name   = "gpmc",
1028         .sysc   = &dra7xx_gpmc_sysc,
1029 };
1030
1031 /* gpmc */
1032
1033 static struct omap_hwmod dra7xx_gpmc_hwmod = {
1034         .name           = "gpmc",
1035         .class          = &dra7xx_gpmc_hwmod_class,
1036         .clkdm_name     = "l3main1_clkdm",
1037         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
1038         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
1039         .main_clk       = "l3_iclk_div",
1040         .prcm = {
1041                 .omap4 = {
1042                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
1043                         .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
1044                         .modulemode   = MODULEMODE_HWCTRL,
1045                 },
1046         },
1047 };
1048
1049 /*
1050  * 'hdq1w' class
1051  *
1052  */
1053
1054 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
1055         .rev_offs       = 0x0000,
1056         .sysc_offs      = 0x0014,
1057         .syss_offs      = 0x0018,
1058         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1059                            SYSS_HAS_RESET_STATUS),
1060         .sysc_fields    = &omap_hwmod_sysc_type1,
1061 };
1062
1063 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
1064         .name   = "hdq1w",
1065         .sysc   = &dra7xx_hdq1w_sysc,
1066 };
1067
1068 /* hdq1w */
1069
1070 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
1071         .name           = "hdq1w",
1072         .class          = &dra7xx_hdq1w_hwmod_class,
1073         .clkdm_name     = "l4per_clkdm",
1074         .flags          = HWMOD_INIT_NO_RESET,
1075         .main_clk       = "func_12m_fclk",
1076         .prcm = {
1077                 .omap4 = {
1078                         .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1079                         .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1080                         .modulemode   = MODULEMODE_SWCTRL,
1081                 },
1082         },
1083 };
1084
1085 /*
1086  * 'i2c' class
1087  *
1088  */
1089
1090 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
1091         .sysc_offs      = 0x0010,
1092         .syss_offs      = 0x0090,
1093         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1094                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1095                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1096         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1097                            SIDLE_SMART_WKUP),
1098         .sysc_fields    = &omap_hwmod_sysc_type1,
1099 };
1100
1101 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
1102         .name   = "i2c",
1103         .sysc   = &dra7xx_i2c_sysc,
1104         .reset  = &omap_i2c_reset,
1105         .rev    = OMAP_I2C_IP_VERSION_2,
1106 };
1107
1108 /* i2c dev_attr */
1109 static struct omap_i2c_dev_attr i2c_dev_attr = {
1110         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1111 };
1112
1113 /* i2c1 */
1114 static struct omap_hwmod dra7xx_i2c1_hwmod = {
1115         .name           = "i2c1",
1116         .class          = &dra7xx_i2c_hwmod_class,
1117         .clkdm_name     = "l4per_clkdm",
1118         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1119         .main_clk       = "func_96m_fclk",
1120         .prcm = {
1121                 .omap4 = {
1122                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1123                         .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
1124                         .modulemode   = MODULEMODE_SWCTRL,
1125                 },
1126         },
1127         .dev_attr       = &i2c_dev_attr,
1128 };
1129
1130 /* i2c2 */
1131 static struct omap_hwmod dra7xx_i2c2_hwmod = {
1132         .name           = "i2c2",
1133         .class          = &dra7xx_i2c_hwmod_class,
1134         .clkdm_name     = "l4per_clkdm",
1135         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1136         .main_clk       = "func_96m_fclk",
1137         .prcm = {
1138                 .omap4 = {
1139                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1140                         .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
1141                         .modulemode   = MODULEMODE_SWCTRL,
1142                 },
1143         },
1144         .dev_attr       = &i2c_dev_attr,
1145 };
1146
1147 /* i2c3 */
1148 static struct omap_hwmod dra7xx_i2c3_hwmod = {
1149         .name           = "i2c3",
1150         .class          = &dra7xx_i2c_hwmod_class,
1151         .clkdm_name     = "l4per_clkdm",
1152         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1153         .main_clk       = "func_96m_fclk",
1154         .prcm = {
1155                 .omap4 = {
1156                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1157                         .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
1158                         .modulemode   = MODULEMODE_SWCTRL,
1159                 },
1160         },
1161         .dev_attr       = &i2c_dev_attr,
1162 };
1163
1164 /* i2c4 */
1165 static struct omap_hwmod dra7xx_i2c4_hwmod = {
1166         .name           = "i2c4",
1167         .class          = &dra7xx_i2c_hwmod_class,
1168         .clkdm_name     = "l4per_clkdm",
1169         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1170         .main_clk       = "func_96m_fclk",
1171         .prcm = {
1172                 .omap4 = {
1173                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1174                         .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
1175                         .modulemode   = MODULEMODE_SWCTRL,
1176                 },
1177         },
1178         .dev_attr       = &i2c_dev_attr,
1179 };
1180
1181 /* i2c5 */
1182 static struct omap_hwmod dra7xx_i2c5_hwmod = {
1183         .name           = "i2c5",
1184         .class          = &dra7xx_i2c_hwmod_class,
1185         .clkdm_name     = "ipu_clkdm",
1186         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1187         .main_clk       = "func_96m_fclk",
1188         .prcm = {
1189                 .omap4 = {
1190                         .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
1191                         .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1192                         .modulemode   = MODULEMODE_SWCTRL,
1193                 },
1194         },
1195         .dev_attr       = &i2c_dev_attr,
1196 };
1197
1198 /*
1199  * 'mailbox' class
1200  *
1201  */
1202
1203 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
1204         .rev_offs       = 0x0000,
1205         .sysc_offs      = 0x0010,
1206         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1207                            SYSC_HAS_SOFTRESET),
1208         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1209         .sysc_fields    = &omap_hwmod_sysc_type2,
1210 };
1211
1212 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1213         .name   = "mailbox",
1214         .sysc   = &dra7xx_mailbox_sysc,
1215 };
1216
1217 /* mailbox1 */
1218 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1219         .name           = "mailbox1",
1220         .class          = &dra7xx_mailbox_hwmod_class,
1221         .clkdm_name     = "l4cfg_clkdm",
1222         .prcm = {
1223                 .omap4 = {
1224                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1225                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1226                 },
1227         },
1228 };
1229
1230 /* mailbox2 */
1231 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1232         .name           = "mailbox2",
1233         .class          = &dra7xx_mailbox_hwmod_class,
1234         .clkdm_name     = "l4cfg_clkdm",
1235         .prcm = {
1236                 .omap4 = {
1237                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1238                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1239                 },
1240         },
1241 };
1242
1243 /* mailbox3 */
1244 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1245         .name           = "mailbox3",
1246         .class          = &dra7xx_mailbox_hwmod_class,
1247         .clkdm_name     = "l4cfg_clkdm",
1248         .prcm = {
1249                 .omap4 = {
1250                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1251                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1252                 },
1253         },
1254 };
1255
1256 /* mailbox4 */
1257 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1258         .name           = "mailbox4",
1259         .class          = &dra7xx_mailbox_hwmod_class,
1260         .clkdm_name     = "l4cfg_clkdm",
1261         .prcm = {
1262                 .omap4 = {
1263                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1264                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1265                 },
1266         },
1267 };
1268
1269 /* mailbox5 */
1270 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1271         .name           = "mailbox5",
1272         .class          = &dra7xx_mailbox_hwmod_class,
1273         .clkdm_name     = "l4cfg_clkdm",
1274         .prcm = {
1275                 .omap4 = {
1276                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1277                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1278                 },
1279         },
1280 };
1281
1282 /* mailbox6 */
1283 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1284         .name           = "mailbox6",
1285         .class          = &dra7xx_mailbox_hwmod_class,
1286         .clkdm_name     = "l4cfg_clkdm",
1287         .prcm = {
1288                 .omap4 = {
1289                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1290                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1291                 },
1292         },
1293 };
1294
1295 /* mailbox7 */
1296 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1297         .name           = "mailbox7",
1298         .class          = &dra7xx_mailbox_hwmod_class,
1299         .clkdm_name     = "l4cfg_clkdm",
1300         .prcm = {
1301                 .omap4 = {
1302                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1303                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1304                 },
1305         },
1306 };
1307
1308 /* mailbox8 */
1309 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1310         .name           = "mailbox8",
1311         .class          = &dra7xx_mailbox_hwmod_class,
1312         .clkdm_name     = "l4cfg_clkdm",
1313         .prcm = {
1314                 .omap4 = {
1315                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1316                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1317                 },
1318         },
1319 };
1320
1321 /* mailbox9 */
1322 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1323         .name           = "mailbox9",
1324         .class          = &dra7xx_mailbox_hwmod_class,
1325         .clkdm_name     = "l4cfg_clkdm",
1326         .prcm = {
1327                 .omap4 = {
1328                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1329                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1330                 },
1331         },
1332 };
1333
1334 /* mailbox10 */
1335 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1336         .name           = "mailbox10",
1337         .class          = &dra7xx_mailbox_hwmod_class,
1338         .clkdm_name     = "l4cfg_clkdm",
1339         .prcm = {
1340                 .omap4 = {
1341                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1342                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1343                 },
1344         },
1345 };
1346
1347 /* mailbox11 */
1348 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1349         .name           = "mailbox11",
1350         .class          = &dra7xx_mailbox_hwmod_class,
1351         .clkdm_name     = "l4cfg_clkdm",
1352         .prcm = {
1353                 .omap4 = {
1354                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1355                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1356                 },
1357         },
1358 };
1359
1360 /* mailbox12 */
1361 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1362         .name           = "mailbox12",
1363         .class          = &dra7xx_mailbox_hwmod_class,
1364         .clkdm_name     = "l4cfg_clkdm",
1365         .prcm = {
1366                 .omap4 = {
1367                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1368                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1369                 },
1370         },
1371 };
1372
1373 /* mailbox13 */
1374 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1375         .name           = "mailbox13",
1376         .class          = &dra7xx_mailbox_hwmod_class,
1377         .clkdm_name     = "l4cfg_clkdm",
1378         .prcm = {
1379                 .omap4 = {
1380                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1381                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1382                 },
1383         },
1384 };
1385
1386 /*
1387  * 'mcspi' class
1388  *
1389  */
1390
1391 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1392         .rev_offs       = 0x0000,
1393         .sysc_offs      = 0x0010,
1394         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1395                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1396         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1397                            SIDLE_SMART_WKUP),
1398         .sysc_fields    = &omap_hwmod_sysc_type2,
1399 };
1400
1401 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1402         .name   = "mcspi",
1403         .sysc   = &dra7xx_mcspi_sysc,
1404         .rev    = OMAP4_MCSPI_REV,
1405 };
1406
1407 /* mcspi1 */
1408 /* mcspi1 dev_attr */
1409 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1410         .num_chipselect = 4,
1411 };
1412
1413 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1414         .name           = "mcspi1",
1415         .class          = &dra7xx_mcspi_hwmod_class,
1416         .clkdm_name     = "l4per_clkdm",
1417         .main_clk       = "func_48m_fclk",
1418         .prcm = {
1419                 .omap4 = {
1420                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1421                         .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1422                         .modulemode   = MODULEMODE_SWCTRL,
1423                 },
1424         },
1425         .dev_attr       = &mcspi1_dev_attr,
1426 };
1427
1428 /* mcspi2 */
1429 /* mcspi2 dev_attr */
1430 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1431         .num_chipselect = 2,
1432 };
1433
1434 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1435         .name           = "mcspi2",
1436         .class          = &dra7xx_mcspi_hwmod_class,
1437         .clkdm_name     = "l4per_clkdm",
1438         .main_clk       = "func_48m_fclk",
1439         .prcm = {
1440                 .omap4 = {
1441                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1442                         .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1443                         .modulemode   = MODULEMODE_SWCTRL,
1444                 },
1445         },
1446         .dev_attr       = &mcspi2_dev_attr,
1447 };
1448
1449 /* mcspi3 */
1450 /* mcspi3 dev_attr */
1451 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1452         .num_chipselect = 2,
1453 };
1454
1455 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1456         .name           = "mcspi3",
1457         .class          = &dra7xx_mcspi_hwmod_class,
1458         .clkdm_name     = "l4per_clkdm",
1459         .main_clk       = "func_48m_fclk",
1460         .prcm = {
1461                 .omap4 = {
1462                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1463                         .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1464                         .modulemode   = MODULEMODE_SWCTRL,
1465                 },
1466         },
1467         .dev_attr       = &mcspi3_dev_attr,
1468 };
1469
1470 /* mcspi4 */
1471 /* mcspi4 dev_attr */
1472 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1473         .num_chipselect = 1,
1474 };
1475
1476 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1477         .name           = "mcspi4",
1478         .class          = &dra7xx_mcspi_hwmod_class,
1479         .clkdm_name     = "l4per_clkdm",
1480         .main_clk       = "func_48m_fclk",
1481         .prcm = {
1482                 .omap4 = {
1483                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1484                         .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1485                         .modulemode   = MODULEMODE_SWCTRL,
1486                 },
1487         },
1488         .dev_attr       = &mcspi4_dev_attr,
1489 };
1490
1491 /*
1492  * 'mcasp' class
1493  *
1494  */
1495 static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
1496         .sysc_offs      = 0x0004,
1497         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1498         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1499         .sysc_fields    = &omap_hwmod_sysc_type3,
1500 };
1501
1502 static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
1503         .name   = "mcasp",
1504         .sysc   = &dra7xx_mcasp_sysc,
1505 };
1506
1507 /* mcasp1 */
1508 static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = {
1509         { .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" },
1510         { .role = "ahclkr", .clk = "mcasp1_ahclkr_mux" },
1511 };
1512
1513 static struct omap_hwmod dra7xx_mcasp1_hwmod = {
1514         .name           = "mcasp1",
1515         .class          = &dra7xx_mcasp_hwmod_class,
1516         .clkdm_name     = "ipu_clkdm",
1517         .main_clk       = "mcasp1_aux_gfclk_mux",
1518         .flags          = HWMOD_OPT_CLKS_NEEDED,
1519         .prcm = {
1520                 .omap4 = {
1521                         .clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
1522                         .context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
1523                         .modulemode   = MODULEMODE_SWCTRL,
1524                 },
1525         },
1526         .opt_clks       = mcasp1_opt_clks,
1527         .opt_clks_cnt   = ARRAY_SIZE(mcasp1_opt_clks),
1528 };
1529
1530 /* mcasp2 */
1531 static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = {
1532         { .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" },
1533         { .role = "ahclkr", .clk = "mcasp2_ahclkr_mux" },
1534 };
1535
1536 static struct omap_hwmod dra7xx_mcasp2_hwmod = {
1537         .name           = "mcasp2",
1538         .class          = &dra7xx_mcasp_hwmod_class,
1539         .clkdm_name     = "l4per2_clkdm",
1540         .main_clk       = "mcasp2_aux_gfclk_mux",
1541         .flags          = HWMOD_OPT_CLKS_NEEDED,
1542         .prcm = {
1543                 .omap4 = {
1544                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
1545                         .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
1546                         .modulemode   = MODULEMODE_SWCTRL,
1547                 },
1548         },
1549         .opt_clks       = mcasp2_opt_clks,
1550         .opt_clks_cnt   = ARRAY_SIZE(mcasp2_opt_clks),
1551 };
1552
1553 /* mcasp3 */
1554 static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = {
1555         { .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" },
1556 };
1557
1558 static struct omap_hwmod dra7xx_mcasp3_hwmod = {
1559         .name           = "mcasp3",
1560         .class          = &dra7xx_mcasp_hwmod_class,
1561         .clkdm_name     = "l4per2_clkdm",
1562         .main_clk       = "mcasp3_aux_gfclk_mux",
1563         .flags          = HWMOD_OPT_CLKS_NEEDED,
1564         .prcm = {
1565                 .omap4 = {
1566                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
1567                         .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
1568                         .modulemode   = MODULEMODE_SWCTRL,
1569                 },
1570         },
1571         .opt_clks       = mcasp3_opt_clks,
1572         .opt_clks_cnt   = ARRAY_SIZE(mcasp3_opt_clks),
1573 };
1574
1575 /* mcasp4 */
1576 static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = {
1577         { .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" },
1578 };
1579
1580 static struct omap_hwmod dra7xx_mcasp4_hwmod = {
1581         .name           = "mcasp4",
1582         .class          = &dra7xx_mcasp_hwmod_class,
1583         .clkdm_name     = "l4per2_clkdm",
1584         .main_clk       = "mcasp4_aux_gfclk_mux",
1585         .flags          = HWMOD_OPT_CLKS_NEEDED,
1586         .prcm = {
1587                 .omap4 = {
1588                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
1589                         .context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
1590                         .modulemode   = MODULEMODE_SWCTRL,
1591                 },
1592         },
1593         .opt_clks       = mcasp4_opt_clks,
1594         .opt_clks_cnt   = ARRAY_SIZE(mcasp4_opt_clks),
1595 };
1596
1597 /* mcasp5 */
1598 static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = {
1599         { .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" },
1600 };
1601
1602 static struct omap_hwmod dra7xx_mcasp5_hwmod = {
1603         .name           = "mcasp5",
1604         .class          = &dra7xx_mcasp_hwmod_class,
1605         .clkdm_name     = "l4per2_clkdm",
1606         .main_clk       = "mcasp5_aux_gfclk_mux",
1607         .flags          = HWMOD_OPT_CLKS_NEEDED,
1608         .prcm = {
1609                 .omap4 = {
1610                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
1611                         .context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
1612                         .modulemode   = MODULEMODE_SWCTRL,
1613                 },
1614         },
1615         .opt_clks       = mcasp5_opt_clks,
1616         .opt_clks_cnt   = ARRAY_SIZE(mcasp5_opt_clks),
1617 };
1618
1619 /* mcasp6 */
1620 static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = {
1621         { .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" },
1622 };
1623
1624 static struct omap_hwmod dra7xx_mcasp6_hwmod = {
1625         .name           = "mcasp6",
1626         .class          = &dra7xx_mcasp_hwmod_class,
1627         .clkdm_name     = "l4per2_clkdm",
1628         .main_clk       = "mcasp6_aux_gfclk_mux",
1629         .flags          = HWMOD_OPT_CLKS_NEEDED,
1630         .prcm = {
1631                 .omap4 = {
1632                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
1633                         .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
1634                         .modulemode   = MODULEMODE_SWCTRL,
1635                 },
1636         },
1637         .opt_clks       = mcasp6_opt_clks,
1638         .opt_clks_cnt   = ARRAY_SIZE(mcasp6_opt_clks),
1639 };
1640
1641 /* mcasp7 */
1642 static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = {
1643         { .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" },
1644 };
1645
1646 static struct omap_hwmod dra7xx_mcasp7_hwmod = {
1647         .name           = "mcasp7",
1648         .class          = &dra7xx_mcasp_hwmod_class,
1649         .clkdm_name     = "l4per2_clkdm",
1650         .main_clk       = "mcasp7_aux_gfclk_mux",
1651         .flags          = HWMOD_OPT_CLKS_NEEDED,
1652         .prcm = {
1653                 .omap4 = {
1654                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
1655                         .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
1656                         .modulemode   = MODULEMODE_SWCTRL,
1657                 },
1658         },
1659         .opt_clks       = mcasp7_opt_clks,
1660         .opt_clks_cnt   = ARRAY_SIZE(mcasp7_opt_clks),
1661 };
1662
1663 /* mcasp8 */
1664 static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = {
1665         { .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" },
1666 };
1667
1668 static struct omap_hwmod dra7xx_mcasp8_hwmod = {
1669         .name           = "mcasp8",
1670         .class          = &dra7xx_mcasp_hwmod_class,
1671         .clkdm_name     = "l4per2_clkdm",
1672         .main_clk       = "mcasp8_aux_gfclk_mux",
1673         .flags          = HWMOD_OPT_CLKS_NEEDED,
1674         .prcm = {
1675                 .omap4 = {
1676                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
1677                         .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
1678                         .modulemode   = MODULEMODE_SWCTRL,
1679                 },
1680         },
1681         .opt_clks       = mcasp8_opt_clks,
1682         .opt_clks_cnt   = ARRAY_SIZE(mcasp8_opt_clks),
1683 };
1684
1685 /*
1686  * 'mmc' class
1687  *
1688  */
1689
1690 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1691         .rev_offs       = 0x0000,
1692         .sysc_offs      = 0x0010,
1693         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1694                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1695                            SYSC_HAS_SOFTRESET),
1696         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1697                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1698                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1699         .sysc_fields    = &omap_hwmod_sysc_type2,
1700 };
1701
1702 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1703         .name   = "mmc",
1704         .sysc   = &dra7xx_mmc_sysc,
1705 };
1706
1707 /* mmc1 */
1708 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1709         { .role = "clk32k", .clk = "mmc1_clk32k" },
1710 };
1711
1712 /* mmc1 dev_attr */
1713 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1714         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1715 };
1716
1717 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1718         .name           = "mmc1",
1719         .class          = &dra7xx_mmc_hwmod_class,
1720         .clkdm_name     = "l3init_clkdm",
1721         .main_clk       = "mmc1_fclk_div",
1722         .prcm = {
1723                 .omap4 = {
1724                         .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1725                         .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1726                         .modulemode   = MODULEMODE_SWCTRL,
1727                 },
1728         },
1729         .opt_clks       = mmc1_opt_clks,
1730         .opt_clks_cnt   = ARRAY_SIZE(mmc1_opt_clks),
1731         .dev_attr       = &mmc1_dev_attr,
1732 };
1733
1734 /* mmc2 */
1735 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1736         { .role = "clk32k", .clk = "mmc2_clk32k" },
1737 };
1738
1739 static struct omap_hwmod dra7xx_mmc2_hwmod = {
1740         .name           = "mmc2",
1741         .class          = &dra7xx_mmc_hwmod_class,
1742         .clkdm_name     = "l3init_clkdm",
1743         .main_clk       = "mmc2_fclk_div",
1744         .prcm = {
1745                 .omap4 = {
1746                         .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1747                         .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1748                         .modulemode   = MODULEMODE_SWCTRL,
1749                 },
1750         },
1751         .opt_clks       = mmc2_opt_clks,
1752         .opt_clks_cnt   = ARRAY_SIZE(mmc2_opt_clks),
1753 };
1754
1755 /* mmc3 */
1756 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1757         { .role = "clk32k", .clk = "mmc3_clk32k" },
1758 };
1759
1760 static struct omap_hwmod dra7xx_mmc3_hwmod = {
1761         .name           = "mmc3",
1762         .class          = &dra7xx_mmc_hwmod_class,
1763         .clkdm_name     = "l4per_clkdm",
1764         .main_clk       = "mmc3_gfclk_div",
1765         .prcm = {
1766                 .omap4 = {
1767                         .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1768                         .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1769                         .modulemode   = MODULEMODE_SWCTRL,
1770                 },
1771         },
1772         .opt_clks       = mmc3_opt_clks,
1773         .opt_clks_cnt   = ARRAY_SIZE(mmc3_opt_clks),
1774 };
1775
1776 /* mmc4 */
1777 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1778         { .role = "clk32k", .clk = "mmc4_clk32k" },
1779 };
1780
1781 static struct omap_hwmod dra7xx_mmc4_hwmod = {
1782         .name           = "mmc4",
1783         .class          = &dra7xx_mmc_hwmod_class,
1784         .clkdm_name     = "l4per_clkdm",
1785         .main_clk       = "mmc4_gfclk_div",
1786         .prcm = {
1787                 .omap4 = {
1788                         .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1789                         .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1790                         .modulemode   = MODULEMODE_SWCTRL,
1791                 },
1792         },
1793         .opt_clks       = mmc4_opt_clks,
1794         .opt_clks_cnt   = ARRAY_SIZE(mmc4_opt_clks),
1795 };
1796
1797 /*
1798  * 'mpu' class
1799  *
1800  */
1801
1802 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1803         .name   = "mpu",
1804 };
1805
1806 /* mpu */
1807 static struct omap_hwmod dra7xx_mpu_hwmod = {
1808         .name           = "mpu",
1809         .class          = &dra7xx_mpu_hwmod_class,
1810         .clkdm_name     = "mpu_clkdm",
1811         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1812         .main_clk       = "dpll_mpu_m2_ck",
1813         .prcm = {
1814                 .omap4 = {
1815                         .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1816                         .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1817                 },
1818         },
1819 };
1820
1821 /*
1822  * 'ocp2scp' class
1823  *
1824  */
1825
1826 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1827         .rev_offs       = 0x0000,
1828         .sysc_offs      = 0x0010,
1829         .syss_offs      = 0x0014,
1830         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1831                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1832         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1833         .sysc_fields    = &omap_hwmod_sysc_type1,
1834 };
1835
1836 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1837         .name   = "ocp2scp",
1838         .sysc   = &dra7xx_ocp2scp_sysc,
1839 };
1840
1841 /* ocp2scp1 */
1842 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1843         .name           = "ocp2scp1",
1844         .class          = &dra7xx_ocp2scp_hwmod_class,
1845         .clkdm_name     = "l3init_clkdm",
1846         .main_clk       = "l4_root_clk_div",
1847         .prcm = {
1848                 .omap4 = {
1849                         .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1850                         .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1851                         .modulemode   = MODULEMODE_HWCTRL,
1852                 },
1853         },
1854 };
1855
1856 /* ocp2scp3 */
1857 static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1858         .name           = "ocp2scp3",
1859         .class          = &dra7xx_ocp2scp_hwmod_class,
1860         .clkdm_name     = "l3init_clkdm",
1861         .main_clk       = "l4_root_clk_div",
1862         .prcm = {
1863                 .omap4 = {
1864                         .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1865                         .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1866                         .modulemode   = MODULEMODE_HWCTRL,
1867                 },
1868         },
1869 };
1870
1871 /*
1872  * 'PCIE' class
1873  *
1874  */
1875
1876 /*
1877  * As noted in documentation for _reset() in omap_hwmod.c, the stock reset
1878  * functionality of OMAP HWMOD layer does not deassert the hardreset lines
1879  * associated with an IP automatically leaving the driver to handle that
1880  * by itself. This does not work for PCIeSS which needs the reset lines
1881  * deasserted for the driver to start accessing registers.
1882  *
1883  * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
1884  * lines after asserting them.
1885  */
1886 static int dra7xx_pciess_reset(struct omap_hwmod *oh)
1887 {
1888         int i;
1889
1890         for (i = 0; i < oh->rst_lines_cnt; i++) {
1891                 omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name);
1892                 omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name);
1893         }
1894
1895         return 0;
1896 }
1897
1898 static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
1899         .name   = "pcie",
1900         .reset  = dra7xx_pciess_reset,
1901 };
1902
1903 /* pcie1 */
1904 static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
1905         { .name = "pcie", .rst_shift = 0 },
1906 };
1907
1908 static struct omap_hwmod dra7xx_pciess1_hwmod = {
1909         .name           = "pcie1",
1910         .class          = &dra7xx_pciess_hwmod_class,
1911         .clkdm_name     = "pcie_clkdm",
1912         .rst_lines      = dra7xx_pciess1_resets,
1913         .rst_lines_cnt  = ARRAY_SIZE(dra7xx_pciess1_resets),
1914         .main_clk       = "l4_root_clk_div",
1915         .prcm = {
1916                 .omap4 = {
1917                         .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1918                         .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1919                         .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1920                         .modulemode   = MODULEMODE_SWCTRL,
1921                 },
1922         },
1923 };
1924
1925 /* pcie2 */
1926 static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
1927         { .name = "pcie", .rst_shift = 1 },
1928 };
1929
1930 /* pcie2 */
1931 static struct omap_hwmod dra7xx_pciess2_hwmod = {
1932         .name           = "pcie2",
1933         .class          = &dra7xx_pciess_hwmod_class,
1934         .clkdm_name     = "pcie_clkdm",
1935         .rst_lines      = dra7xx_pciess2_resets,
1936         .rst_lines_cnt  = ARRAY_SIZE(dra7xx_pciess2_resets),
1937         .main_clk       = "l4_root_clk_div",
1938         .prcm = {
1939                 .omap4 = {
1940                         .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1941                         .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1942                         .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1943                         .modulemode   = MODULEMODE_SWCTRL,
1944                 },
1945         },
1946 };
1947
1948 /*
1949  * 'qspi' class
1950  *
1951  */
1952
1953 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1954         .sysc_offs      = 0x0010,
1955         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1956         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1957                            SIDLE_SMART_WKUP),
1958         .sysc_fields    = &omap_hwmod_sysc_type2,
1959 };
1960
1961 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1962         .name   = "qspi",
1963         .sysc   = &dra7xx_qspi_sysc,
1964 };
1965
1966 /* qspi */
1967 static struct omap_hwmod dra7xx_qspi_hwmod = {
1968         .name           = "qspi",
1969         .class          = &dra7xx_qspi_hwmod_class,
1970         .clkdm_name     = "l4per2_clkdm",
1971         .main_clk       = "qspi_gfclk_div",
1972         .prcm = {
1973                 .omap4 = {
1974                         .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1975                         .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1976                         .modulemode   = MODULEMODE_SWCTRL,
1977                 },
1978         },
1979 };
1980
1981 /*
1982  * 'rtcss' class
1983  *
1984  */
1985 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1986         .sysc_offs      = 0x0078,
1987         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1988         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1989                            SIDLE_SMART_WKUP),
1990         .sysc_fields    = &omap_hwmod_sysc_type3,
1991 };
1992
1993 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1994         .name   = "rtcss",
1995         .sysc   = &dra7xx_rtcss_sysc,
1996         .unlock = &omap_hwmod_rtc_unlock,
1997         .lock   = &omap_hwmod_rtc_lock,
1998 };
1999
2000 /* rtcss */
2001 static struct omap_hwmod dra7xx_rtcss_hwmod = {
2002         .name           = "rtcss",
2003         .class          = &dra7xx_rtcss_hwmod_class,
2004         .clkdm_name     = "rtc_clkdm",
2005         .main_clk       = "sys_32k_ck",
2006         .prcm = {
2007                 .omap4 = {
2008                         .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
2009                         .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
2010                         .modulemode   = MODULEMODE_SWCTRL,
2011                 },
2012         },
2013 };
2014
2015 /*
2016  * 'sata' class
2017  *
2018  */
2019
2020 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
2021         .sysc_offs      = 0x0000,
2022         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
2023         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2024                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2025                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2026         .sysc_fields    = &omap_hwmod_sysc_type2,
2027 };
2028
2029 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
2030         .name   = "sata",
2031         .sysc   = &dra7xx_sata_sysc,
2032 };
2033
2034 /* sata */
2035
2036 static struct omap_hwmod dra7xx_sata_hwmod = {
2037         .name           = "sata",
2038         .class          = &dra7xx_sata_hwmod_class,
2039         .clkdm_name     = "l3init_clkdm",
2040         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2041         .main_clk       = "func_48m_fclk",
2042         .mpu_rt_idx     = 1,
2043         .prcm = {
2044                 .omap4 = {
2045                         .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
2046                         .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
2047                         .modulemode   = MODULEMODE_SWCTRL,
2048                 },
2049         },
2050 };
2051
2052 /*
2053  * 'smartreflex' class
2054  *
2055  */
2056
2057 /* The IP is not compliant to type1 / type2 scheme */
2058 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
2059         .sysc_offs      = 0x0038,
2060         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2061         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2062                            SIDLE_SMART_WKUP),
2063         .sysc_fields    = &omap36xx_sr_sysc_fields,
2064 };
2065
2066 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
2067         .name   = "smartreflex",
2068         .sysc   = &dra7xx_smartreflex_sysc,
2069         .rev    = 2,
2070 };
2071
2072 /* smartreflex_core */
2073 /* smartreflex_core dev_attr */
2074 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2075         .sensor_voltdm_name     = "core",
2076 };
2077
2078 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
2079         .name           = "smartreflex_core",
2080         .class          = &dra7xx_smartreflex_hwmod_class,
2081         .clkdm_name     = "coreaon_clkdm",
2082         .main_clk       = "wkupaon_iclk_mux",
2083         .prcm = {
2084                 .omap4 = {
2085                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
2086                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
2087                         .modulemode   = MODULEMODE_SWCTRL,
2088                 },
2089         },
2090         .dev_attr       = &smartreflex_core_dev_attr,
2091 };
2092
2093 /* smartreflex_mpu */
2094 /* smartreflex_mpu dev_attr */
2095 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2096         .sensor_voltdm_name     = "mpu",
2097 };
2098
2099 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
2100         .name           = "smartreflex_mpu",
2101         .class          = &dra7xx_smartreflex_hwmod_class,
2102         .clkdm_name     = "coreaon_clkdm",
2103         .main_clk       = "wkupaon_iclk_mux",
2104         .prcm = {
2105                 .omap4 = {
2106                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
2107                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
2108                         .modulemode   = MODULEMODE_SWCTRL,
2109                 },
2110         },
2111         .dev_attr       = &smartreflex_mpu_dev_attr,
2112 };
2113
2114 /*
2115  * 'spinlock' class
2116  *
2117  */
2118
2119 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
2120         .rev_offs       = 0x0000,
2121         .sysc_offs      = 0x0010,
2122         .syss_offs      = 0x0014,
2123         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2124                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2125                            SYSS_HAS_RESET_STATUS),
2126         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2127         .sysc_fields    = &omap_hwmod_sysc_type1,
2128 };
2129
2130 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
2131         .name   = "spinlock",
2132         .sysc   = &dra7xx_spinlock_sysc,
2133 };
2134
2135 /* spinlock */
2136 static struct omap_hwmod dra7xx_spinlock_hwmod = {
2137         .name           = "spinlock",
2138         .class          = &dra7xx_spinlock_hwmod_class,
2139         .clkdm_name     = "l4cfg_clkdm",
2140         .main_clk       = "l3_iclk_div",
2141         .prcm = {
2142                 .omap4 = {
2143                         .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
2144                         .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
2145                 },
2146         },
2147 };
2148
2149 /*
2150  * 'timer' class
2151  *
2152  * This class contains several variants: ['timer_1ms', 'timer_secure',
2153  * 'timer']
2154  */
2155
2156 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
2157         .rev_offs       = 0x0000,
2158         .sysc_offs      = 0x0010,
2159         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2160                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2161         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2162                            SIDLE_SMART_WKUP),
2163         .sysc_fields    = &omap_hwmod_sysc_type2,
2164 };
2165
2166 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
2167         .name   = "timer",
2168         .sysc   = &dra7xx_timer_1ms_sysc,
2169 };
2170
2171 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
2172         .rev_offs       = 0x0000,
2173         .sysc_offs      = 0x0010,
2174         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2175                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2176         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2177                            SIDLE_SMART_WKUP),
2178         .sysc_fields    = &omap_hwmod_sysc_type2,
2179 };
2180
2181 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
2182         .name   = "timer",
2183         .sysc   = &dra7xx_timer_sysc,
2184 };
2185
2186 /* timer1 */
2187 static struct omap_hwmod dra7xx_timer1_hwmod = {
2188         .name           = "timer1",
2189         .class          = &dra7xx_timer_1ms_hwmod_class,
2190         .clkdm_name     = "wkupaon_clkdm",
2191         .main_clk       = "timer1_gfclk_mux",
2192         .prcm = {
2193                 .omap4 = {
2194                         .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
2195                         .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
2196                         .modulemode   = MODULEMODE_SWCTRL,
2197                 },
2198         },
2199 };
2200
2201 /* timer2 */
2202 static struct omap_hwmod dra7xx_timer2_hwmod = {
2203         .name           = "timer2",
2204         .class          = &dra7xx_timer_1ms_hwmod_class,
2205         .clkdm_name     = "l4per_clkdm",
2206         .main_clk       = "timer2_gfclk_mux",
2207         .prcm = {
2208                 .omap4 = {
2209                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
2210                         .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
2211                         .modulemode   = MODULEMODE_SWCTRL,
2212                 },
2213         },
2214 };
2215
2216 /* timer3 */
2217 static struct omap_hwmod dra7xx_timer3_hwmod = {
2218         .name           = "timer3",
2219         .class          = &dra7xx_timer_hwmod_class,
2220         .clkdm_name     = "l4per_clkdm",
2221         .main_clk       = "timer3_gfclk_mux",
2222         .prcm = {
2223                 .omap4 = {
2224                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
2225                         .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
2226                         .modulemode   = MODULEMODE_SWCTRL,
2227                 },
2228         },
2229 };
2230
2231 /* timer4 */
2232 static struct omap_hwmod dra7xx_timer4_hwmod = {
2233         .name           = "timer4",
2234         .class          = &dra7xx_timer_hwmod_class,
2235         .clkdm_name     = "l4per_clkdm",
2236         .main_clk       = "timer4_gfclk_mux",
2237         .prcm = {
2238                 .omap4 = {
2239                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
2240                         .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
2241                         .modulemode   = MODULEMODE_SWCTRL,
2242                 },
2243         },
2244 };
2245
2246 /* timer5 */
2247 static struct omap_hwmod dra7xx_timer5_hwmod = {
2248         .name           = "timer5",
2249         .class          = &dra7xx_timer_hwmod_class,
2250         .clkdm_name     = "ipu_clkdm",
2251         .main_clk       = "timer5_gfclk_mux",
2252         .prcm = {
2253                 .omap4 = {
2254                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
2255                         .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
2256                         .modulemode   = MODULEMODE_SWCTRL,
2257                 },
2258         },
2259 };
2260
2261 /* timer6 */
2262 static struct omap_hwmod dra7xx_timer6_hwmod = {
2263         .name           = "timer6",
2264         .class          = &dra7xx_timer_hwmod_class,
2265         .clkdm_name     = "ipu_clkdm",
2266         .main_clk       = "timer6_gfclk_mux",
2267         .prcm = {
2268                 .omap4 = {
2269                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
2270                         .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
2271                         .modulemode   = MODULEMODE_SWCTRL,
2272                 },
2273         },
2274 };
2275
2276 /* timer7 */
2277 static struct omap_hwmod dra7xx_timer7_hwmod = {
2278         .name           = "timer7",
2279         .class          = &dra7xx_timer_hwmod_class,
2280         .clkdm_name     = "ipu_clkdm",
2281         .main_clk       = "timer7_gfclk_mux",
2282         .prcm = {
2283                 .omap4 = {
2284                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
2285                         .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
2286                         .modulemode   = MODULEMODE_SWCTRL,
2287                 },
2288         },
2289 };
2290
2291 /* timer8 */
2292 static struct omap_hwmod dra7xx_timer8_hwmod = {
2293         .name           = "timer8",
2294         .class          = &dra7xx_timer_hwmod_class,
2295         .clkdm_name     = "ipu_clkdm",
2296         .main_clk       = "timer8_gfclk_mux",
2297         .prcm = {
2298                 .omap4 = {
2299                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
2300                         .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
2301                         .modulemode   = MODULEMODE_SWCTRL,
2302                 },
2303         },
2304 };
2305
2306 /* timer9 */
2307 static struct omap_hwmod dra7xx_timer9_hwmod = {
2308         .name           = "timer9",
2309         .class          = &dra7xx_timer_hwmod_class,
2310         .clkdm_name     = "l4per_clkdm",
2311         .main_clk       = "timer9_gfclk_mux",
2312         .prcm = {
2313                 .omap4 = {
2314                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
2315                         .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
2316                         .modulemode   = MODULEMODE_SWCTRL,
2317                 },
2318         },
2319 };
2320
2321 /* timer10 */
2322 static struct omap_hwmod dra7xx_timer10_hwmod = {
2323         .name           = "timer10",
2324         .class          = &dra7xx_timer_1ms_hwmod_class,
2325         .clkdm_name     = "l4per_clkdm",
2326         .main_clk       = "timer10_gfclk_mux",
2327         .prcm = {
2328                 .omap4 = {
2329                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
2330                         .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
2331                         .modulemode   = MODULEMODE_SWCTRL,
2332                 },
2333         },
2334 };
2335
2336 /* timer11 */
2337 static struct omap_hwmod dra7xx_timer11_hwmod = {
2338         .name           = "timer11",
2339         .class          = &dra7xx_timer_hwmod_class,
2340         .clkdm_name     = "l4per_clkdm",
2341         .main_clk       = "timer11_gfclk_mux",
2342         .prcm = {
2343                 .omap4 = {
2344                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
2345                         .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
2346                         .modulemode   = MODULEMODE_SWCTRL,
2347                 },
2348         },
2349 };
2350
2351 /* timer12 */
2352 static struct omap_hwmod dra7xx_timer12_hwmod = {
2353         .name           = "timer12",
2354         .class          = &dra7xx_timer_hwmod_class,
2355         .clkdm_name     = "wkupaon_clkdm",
2356         .main_clk       = "secure_32k_clk_src_ck",
2357         .prcm = {
2358                 .omap4 = {
2359                         .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET,
2360                         .context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET,
2361                 },
2362         },
2363 };
2364
2365 /* timer13 */
2366 static struct omap_hwmod dra7xx_timer13_hwmod = {
2367         .name           = "timer13",
2368         .class          = &dra7xx_timer_hwmod_class,
2369         .clkdm_name     = "l4per3_clkdm",
2370         .main_clk       = "timer13_gfclk_mux",
2371         .prcm = {
2372                 .omap4 = {
2373                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
2374                         .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
2375                         .modulemode   = MODULEMODE_SWCTRL,
2376                 },
2377         },
2378 };
2379
2380 /* timer14 */
2381 static struct omap_hwmod dra7xx_timer14_hwmod = {
2382         .name           = "timer14",
2383         .class          = &dra7xx_timer_hwmod_class,
2384         .clkdm_name     = "l4per3_clkdm",
2385         .main_clk       = "timer14_gfclk_mux",
2386         .prcm = {
2387                 .omap4 = {
2388                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
2389                         .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
2390                         .modulemode   = MODULEMODE_SWCTRL,
2391                 },
2392         },
2393 };
2394
2395 /* timer15 */
2396 static struct omap_hwmod dra7xx_timer15_hwmod = {
2397         .name           = "timer15",
2398         .class          = &dra7xx_timer_hwmod_class,
2399         .clkdm_name     = "l4per3_clkdm",
2400         .main_clk       = "timer15_gfclk_mux",
2401         .prcm = {
2402                 .omap4 = {
2403                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
2404                         .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
2405                         .modulemode   = MODULEMODE_SWCTRL,
2406                 },
2407         },
2408 };
2409
2410 /* timer16 */
2411 static struct omap_hwmod dra7xx_timer16_hwmod = {
2412         .name           = "timer16",
2413         .class          = &dra7xx_timer_hwmod_class,
2414         .clkdm_name     = "l4per3_clkdm",
2415         .main_clk       = "timer16_gfclk_mux",
2416         .prcm = {
2417                 .omap4 = {
2418                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
2419                         .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
2420                         .modulemode   = MODULEMODE_SWCTRL,
2421                 },
2422         },
2423 };
2424
2425 /*
2426  * 'uart' class
2427  *
2428  */
2429
2430 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
2431         .rev_offs       = 0x0050,
2432         .sysc_offs      = 0x0054,
2433         .syss_offs      = 0x0058,
2434         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2435                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2436                            SYSS_HAS_RESET_STATUS),
2437         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2438                            SIDLE_SMART_WKUP),
2439         .sysc_fields    = &omap_hwmod_sysc_type1,
2440 };
2441
2442 static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
2443         .name   = "uart",
2444         .sysc   = &dra7xx_uart_sysc,
2445 };
2446
2447 /* uart1 */
2448 static struct omap_hwmod dra7xx_uart1_hwmod = {
2449         .name           = "uart1",
2450         .class          = &dra7xx_uart_hwmod_class,
2451         .clkdm_name     = "l4per_clkdm",
2452         .main_clk       = "uart1_gfclk_mux",
2453         .flags          = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
2454         .prcm = {
2455                 .omap4 = {
2456                         .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
2457                         .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
2458                         .modulemode   = MODULEMODE_SWCTRL,
2459                 },
2460         },
2461 };
2462
2463 /* uart2 */
2464 static struct omap_hwmod dra7xx_uart2_hwmod = {
2465         .name           = "uart2",
2466         .class          = &dra7xx_uart_hwmod_class,
2467         .clkdm_name     = "l4per_clkdm",
2468         .main_clk       = "uart2_gfclk_mux",
2469         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2470         .prcm = {
2471                 .omap4 = {
2472                         .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2473                         .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2474                         .modulemode   = MODULEMODE_SWCTRL,
2475                 },
2476         },
2477 };
2478
2479 /* uart3 */
2480 static struct omap_hwmod dra7xx_uart3_hwmod = {
2481         .name           = "uart3",
2482         .class          = &dra7xx_uart_hwmod_class,
2483         .clkdm_name     = "l4per_clkdm",
2484         .main_clk       = "uart3_gfclk_mux",
2485         .flags          = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS,
2486         .prcm = {
2487                 .omap4 = {
2488                         .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2489                         .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2490                         .modulemode   = MODULEMODE_SWCTRL,
2491                 },
2492         },
2493 };
2494
2495 /* uart4 */
2496 static struct omap_hwmod dra7xx_uart4_hwmod = {
2497         .name           = "uart4",
2498         .class          = &dra7xx_uart_hwmod_class,
2499         .clkdm_name     = "l4per_clkdm",
2500         .main_clk       = "uart4_gfclk_mux",
2501         .flags          = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART4_FLAGS,
2502         .prcm = {
2503                 .omap4 = {
2504                         .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2505                         .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2506                         .modulemode   = MODULEMODE_SWCTRL,
2507                 },
2508         },
2509 };
2510
2511 /* uart5 */
2512 static struct omap_hwmod dra7xx_uart5_hwmod = {
2513         .name           = "uart5",
2514         .class          = &dra7xx_uart_hwmod_class,
2515         .clkdm_name     = "l4per_clkdm",
2516         .main_clk       = "uart5_gfclk_mux",
2517         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2518         .prcm = {
2519                 .omap4 = {
2520                         .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2521                         .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2522                         .modulemode   = MODULEMODE_SWCTRL,
2523                 },
2524         },
2525 };
2526
2527 /* uart6 */
2528 static struct omap_hwmod dra7xx_uart6_hwmod = {
2529         .name           = "uart6",
2530         .class          = &dra7xx_uart_hwmod_class,
2531         .clkdm_name     = "ipu_clkdm",
2532         .main_clk       = "uart6_gfclk_mux",
2533         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2534         .prcm = {
2535                 .omap4 = {
2536                         .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2537                         .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2538                         .modulemode   = MODULEMODE_SWCTRL,
2539                 },
2540         },
2541 };
2542
2543 /* uart7 */
2544 static struct omap_hwmod dra7xx_uart7_hwmod = {
2545         .name           = "uart7",
2546         .class          = &dra7xx_uart_hwmod_class,
2547         .clkdm_name     = "l4per2_clkdm",
2548         .main_clk       = "uart7_gfclk_mux",
2549         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2550         .prcm = {
2551                 .omap4 = {
2552                         .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
2553                         .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
2554                         .modulemode   = MODULEMODE_SWCTRL,
2555                 },
2556         },
2557 };
2558
2559 /* uart8 */
2560 static struct omap_hwmod dra7xx_uart8_hwmod = {
2561         .name           = "uart8",
2562         .class          = &dra7xx_uart_hwmod_class,
2563         .clkdm_name     = "l4per2_clkdm",
2564         .main_clk       = "uart8_gfclk_mux",
2565         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2566         .prcm = {
2567                 .omap4 = {
2568                         .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
2569                         .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
2570                         .modulemode   = MODULEMODE_SWCTRL,
2571                 },
2572         },
2573 };
2574
2575 /* uart9 */
2576 static struct omap_hwmod dra7xx_uart9_hwmod = {
2577         .name           = "uart9",
2578         .class          = &dra7xx_uart_hwmod_class,
2579         .clkdm_name     = "l4per2_clkdm",
2580         .main_clk       = "uart9_gfclk_mux",
2581         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2582         .prcm = {
2583                 .omap4 = {
2584                         .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
2585                         .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
2586                         .modulemode   = MODULEMODE_SWCTRL,
2587                 },
2588         },
2589 };
2590
2591 /* uart10 */
2592 static struct omap_hwmod dra7xx_uart10_hwmod = {
2593         .name           = "uart10",
2594         .class          = &dra7xx_uart_hwmod_class,
2595         .clkdm_name     = "wkupaon_clkdm",
2596         .main_clk       = "uart10_gfclk_mux",
2597         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2598         .prcm = {
2599                 .omap4 = {
2600                         .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
2601                         .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
2602                         .modulemode   = MODULEMODE_SWCTRL,
2603                 },
2604         },
2605 };
2606
2607 /* DES (the 'P' (public) device) */
2608 static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = {
2609         .rev_offs       = 0x0030,
2610         .sysc_offs      = 0x0034,
2611         .syss_offs      = 0x0038,
2612         .sysc_flags     = SYSS_HAS_RESET_STATUS,
2613 };
2614
2615 static struct omap_hwmod_class dra7xx_des_hwmod_class = {
2616         .name   = "des",
2617         .sysc   = &dra7xx_des_sysc,
2618 };
2619
2620 /* DES */
2621 static struct omap_hwmod dra7xx_des_hwmod = {
2622         .name           = "des",
2623         .class          = &dra7xx_des_hwmod_class,
2624         .clkdm_name     = "l4sec_clkdm",
2625         .main_clk       = "l3_iclk_div",
2626         .prcm = {
2627                 .omap4 = {
2628                         .clkctrl_offs = DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
2629                         .context_offs = DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
2630                         .modulemode   = MODULEMODE_HWCTRL,
2631                 },
2632         },
2633 };
2634
2635 /* rng */
2636 static struct omap_hwmod_class_sysconfig dra7xx_rng_sysc = {
2637         .rev_offs       = 0x1fe0,
2638         .sysc_offs      = 0x1fe4,
2639         .sysc_flags     = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
2640         .idlemodes      = SIDLE_FORCE | SIDLE_NO,
2641         .sysc_fields    = &omap_hwmod_sysc_type1,
2642 };
2643
2644 static struct omap_hwmod_class dra7xx_rng_hwmod_class = {
2645         .name           = "rng",
2646         .sysc           = &dra7xx_rng_sysc,
2647 };
2648
2649 static struct omap_hwmod dra7xx_rng_hwmod = {
2650         .name           = "rng",
2651         .class          = &dra7xx_rng_hwmod_class,
2652         .flags          = HWMOD_SWSUP_SIDLE,
2653         .clkdm_name     = "l4sec_clkdm",
2654         .prcm = {
2655                 .omap4 = {
2656                         .clkctrl_offs = DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET,
2657                         .context_offs = DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET,
2658                         .modulemode   = MODULEMODE_HWCTRL,
2659                 },
2660         },
2661 };
2662
2663 /*
2664  * 'usb_otg_ss' class
2665  *
2666  */
2667
2668 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
2669         .rev_offs       = 0x0000,
2670         .sysc_offs      = 0x0010,
2671         .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
2672                            SYSC_HAS_SIDLEMODE),
2673         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2674                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2675                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2676         .sysc_fields    = &omap_hwmod_sysc_type2,
2677 };
2678
2679 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2680         .name   = "usb_otg_ss",
2681         .sysc   = &dra7xx_usb_otg_ss_sysc,
2682 };
2683
2684 /* usb_otg_ss1 */
2685 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2686         { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2687 };
2688
2689 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2690         .name           = "usb_otg_ss1",
2691         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2692         .clkdm_name     = "l3init_clkdm",
2693         .main_clk       = "dpll_core_h13x2_ck",
2694         .flags          = HWMOD_CLKDM_NOAUTO,
2695         .prcm = {
2696                 .omap4 = {
2697                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2698                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2699                         .modulemode   = MODULEMODE_HWCTRL,
2700                 },
2701         },
2702         .opt_clks       = usb_otg_ss1_opt_clks,
2703         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2704 };
2705
2706 /* usb_otg_ss2 */
2707 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2708         { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2709 };
2710
2711 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2712         .name           = "usb_otg_ss2",
2713         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2714         .clkdm_name     = "l3init_clkdm",
2715         .main_clk       = "dpll_core_h13x2_ck",
2716         .flags          = HWMOD_CLKDM_NOAUTO,
2717         .prcm = {
2718                 .omap4 = {
2719                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2720                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2721                         .modulemode   = MODULEMODE_HWCTRL,
2722                 },
2723         },
2724         .opt_clks       = usb_otg_ss2_opt_clks,
2725         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2726 };
2727
2728 /* usb_otg_ss3 */
2729 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2730         .name           = "usb_otg_ss3",
2731         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2732         .clkdm_name     = "l3init_clkdm",
2733         .main_clk       = "dpll_core_h13x2_ck",
2734         .prcm = {
2735                 .omap4 = {
2736                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
2737                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2738                         .modulemode   = MODULEMODE_HWCTRL,
2739                 },
2740         },
2741 };
2742
2743 /* usb_otg_ss4 */
2744 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
2745         .name           = "usb_otg_ss4",
2746         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2747         .clkdm_name     = "l3init_clkdm",
2748         .main_clk       = "dpll_core_h13x2_ck",
2749         .prcm = {
2750                 .omap4 = {
2751                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
2752                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2753                         .modulemode   = MODULEMODE_HWCTRL,
2754                 },
2755         },
2756 };
2757
2758 /*
2759  * 'vcp' class
2760  *
2761  */
2762
2763 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
2764         .name   = "vcp",
2765 };
2766
2767 /* vcp1 */
2768 static struct omap_hwmod dra7xx_vcp1_hwmod = {
2769         .name           = "vcp1",
2770         .class          = &dra7xx_vcp_hwmod_class,
2771         .clkdm_name     = "l3main1_clkdm",
2772         .main_clk       = "l3_iclk_div",
2773         .prcm = {
2774                 .omap4 = {
2775                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
2776                         .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2777                 },
2778         },
2779 };
2780
2781 /* vcp2 */
2782 static struct omap_hwmod dra7xx_vcp2_hwmod = {
2783         .name           = "vcp2",
2784         .class          = &dra7xx_vcp_hwmod_class,
2785         .clkdm_name     = "l3main1_clkdm",
2786         .main_clk       = "l3_iclk_div",
2787         .prcm = {
2788                 .omap4 = {
2789                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
2790                         .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2791                 },
2792         },
2793 };
2794
2795 /*
2796  * 'wd_timer' class
2797  *
2798  */
2799
2800 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
2801         .rev_offs       = 0x0000,
2802         .sysc_offs      = 0x0010,
2803         .syss_offs      = 0x0014,
2804         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2805                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2806         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2807                            SIDLE_SMART_WKUP),
2808         .sysc_fields    = &omap_hwmod_sysc_type1,
2809 };
2810
2811 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
2812         .name           = "wd_timer",
2813         .sysc           = &dra7xx_wd_timer_sysc,
2814         .pre_shutdown   = &omap2_wd_timer_disable,
2815         .reset          = &omap2_wd_timer_reset,
2816 };
2817
2818 /* wd_timer2 */
2819 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
2820         .name           = "wd_timer2",
2821         .class          = &dra7xx_wd_timer_hwmod_class,
2822         .clkdm_name     = "wkupaon_clkdm",
2823         .main_clk       = "sys_32k_ck",
2824         .prcm = {
2825                 .omap4 = {
2826                         .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2827                         .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2828                         .modulemode   = MODULEMODE_SWCTRL,
2829                 },
2830         },
2831 };
2832
2833
2834 /*
2835  * Interfaces
2836  */
2837
2838 /* l3_main_1 -> dmm */
2839 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
2840         .master         = &dra7xx_l3_main_1_hwmod,
2841         .slave          = &dra7xx_dmm_hwmod,
2842         .clk            = "l3_iclk_div",
2843         .user           = OCP_USER_SDMA,
2844 };
2845
2846 /* l3_main_2 -> l3_instr */
2847 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
2848         .master         = &dra7xx_l3_main_2_hwmod,
2849         .slave          = &dra7xx_l3_instr_hwmod,
2850         .clk            = "l3_iclk_div",
2851         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2852 };
2853
2854 /* l4_cfg -> l3_main_1 */
2855 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
2856         .master         = &dra7xx_l4_cfg_hwmod,
2857         .slave          = &dra7xx_l3_main_1_hwmod,
2858         .clk            = "l3_iclk_div",
2859         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2860 };
2861
2862 /* mpu -> l3_main_1 */
2863 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
2864         .master         = &dra7xx_mpu_hwmod,
2865         .slave          = &dra7xx_l3_main_1_hwmod,
2866         .clk            = "l3_iclk_div",
2867         .user           = OCP_USER_MPU,
2868 };
2869
2870 /* l3_main_1 -> l3_main_2 */
2871 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2872         .master         = &dra7xx_l3_main_1_hwmod,
2873         .slave          = &dra7xx_l3_main_2_hwmod,
2874         .clk            = "l3_iclk_div",
2875         .user           = OCP_USER_MPU,
2876 };
2877
2878 /* l4_cfg -> l3_main_2 */
2879 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2880         .master         = &dra7xx_l4_cfg_hwmod,
2881         .slave          = &dra7xx_l3_main_2_hwmod,
2882         .clk            = "l3_iclk_div",
2883         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2884 };
2885
2886 /* l3_main_1 -> l4_cfg */
2887 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2888         .master         = &dra7xx_l3_main_1_hwmod,
2889         .slave          = &dra7xx_l4_cfg_hwmod,
2890         .clk            = "l3_iclk_div",
2891         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2892 };
2893
2894 /* l3_main_1 -> l4_per1 */
2895 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2896         .master         = &dra7xx_l3_main_1_hwmod,
2897         .slave          = &dra7xx_l4_per1_hwmod,
2898         .clk            = "l3_iclk_div",
2899         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2900 };
2901
2902 /* l3_main_1 -> l4_per2 */
2903 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2904         .master         = &dra7xx_l3_main_1_hwmod,
2905         .slave          = &dra7xx_l4_per2_hwmod,
2906         .clk            = "l3_iclk_div",
2907         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2908 };
2909
2910 /* l3_main_1 -> l4_per3 */
2911 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2912         .master         = &dra7xx_l3_main_1_hwmod,
2913         .slave          = &dra7xx_l4_per3_hwmod,
2914         .clk            = "l3_iclk_div",
2915         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2916 };
2917
2918 /* l3_main_1 -> l4_wkup */
2919 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2920         .master         = &dra7xx_l3_main_1_hwmod,
2921         .slave          = &dra7xx_l4_wkup_hwmod,
2922         .clk            = "wkupaon_iclk_mux",
2923         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2924 };
2925
2926 /* l4_per2 -> atl */
2927 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2928         .master         = &dra7xx_l4_per2_hwmod,
2929         .slave          = &dra7xx_atl_hwmod,
2930         .clk            = "l3_iclk_div",
2931         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2932 };
2933
2934 /* l3_main_1 -> bb2d */
2935 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2936         .master         = &dra7xx_l3_main_1_hwmod,
2937         .slave          = &dra7xx_bb2d_hwmod,
2938         .clk            = "l3_iclk_div",
2939         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2940 };
2941
2942 /* l4_wkup -> counter_32k */
2943 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2944         .master         = &dra7xx_l4_wkup_hwmod,
2945         .slave          = &dra7xx_counter_32k_hwmod,
2946         .clk            = "wkupaon_iclk_mux",
2947         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2948 };
2949
2950 /* l4_wkup -> ctrl_module_wkup */
2951 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2952         .master         = &dra7xx_l4_wkup_hwmod,
2953         .slave          = &dra7xx_ctrl_module_wkup_hwmod,
2954         .clk            = "wkupaon_iclk_mux",
2955         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2956 };
2957
2958 static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
2959         .master         = &dra7xx_l4_per2_hwmod,
2960         .slave          = &dra7xx_gmac_hwmod,
2961         .clk            = "dpll_gmac_ck",
2962         .user           = OCP_USER_MPU,
2963 };
2964
2965 static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
2966         .master         = &dra7xx_gmac_hwmod,
2967         .slave          = &dra7xx_mdio_hwmod,
2968         .user           = OCP_USER_MPU,
2969 };
2970
2971 /* l4_wkup -> dcan1 */
2972 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2973         .master         = &dra7xx_l4_wkup_hwmod,
2974         .slave          = &dra7xx_dcan1_hwmod,
2975         .clk            = "wkupaon_iclk_mux",
2976         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2977 };
2978
2979 /* l4_per2 -> dcan2 */
2980 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2981         .master         = &dra7xx_l4_per2_hwmod,
2982         .slave          = &dra7xx_dcan2_hwmod,
2983         .clk            = "l3_iclk_div",
2984         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2985 };
2986
2987 /* l4_cfg -> dma_system */
2988 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2989         .master         = &dra7xx_l4_cfg_hwmod,
2990         .slave          = &dra7xx_dma_system_hwmod,
2991         .clk            = "l3_iclk_div",
2992         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2993 };
2994
2995 /* l3_main_1 -> tpcc */
2996 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = {
2997         .master         = &dra7xx_l3_main_1_hwmod,
2998         .slave          = &dra7xx_tpcc_hwmod,
2999         .clk            = "l3_iclk_div",
3000         .user           = OCP_USER_MPU,
3001 };
3002
3003 /* l3_main_1 -> tptc0 */
3004 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = {
3005         .master         = &dra7xx_l3_main_1_hwmod,
3006         .slave          = &dra7xx_tptc0_hwmod,
3007         .clk            = "l3_iclk_div",
3008         .user           = OCP_USER_MPU,
3009 };
3010
3011 /* l3_main_1 -> tptc1 */
3012 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = {
3013         .master         = &dra7xx_l3_main_1_hwmod,
3014         .slave          = &dra7xx_tptc1_hwmod,
3015         .clk            = "l3_iclk_div",
3016         .user           = OCP_USER_MPU,
3017 };
3018
3019 /* l3_main_1 -> dss */
3020 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
3021         .master         = &dra7xx_l3_main_1_hwmod,
3022         .slave          = &dra7xx_dss_hwmod,
3023         .clk            = "l3_iclk_div",
3024         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3025 };
3026
3027 /* l3_main_1 -> dispc */
3028 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
3029         .master         = &dra7xx_l3_main_1_hwmod,
3030         .slave          = &dra7xx_dss_dispc_hwmod,
3031         .clk            = "l3_iclk_div",
3032         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3033 };
3034
3035 /* l3_main_1 -> dispc */
3036 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
3037         .master         = &dra7xx_l3_main_1_hwmod,
3038         .slave          = &dra7xx_dss_hdmi_hwmod,
3039         .clk            = "l3_iclk_div",
3040         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3041 };
3042
3043 /* l3_main_1 -> aes1 */
3044 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes1 = {
3045         .master         = &dra7xx_l3_main_1_hwmod,
3046         .slave          = &dra7xx_aes1_hwmod,
3047         .clk            = "l3_iclk_div",
3048         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3049 };
3050
3051 /* l3_main_1 -> aes2 */
3052 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes2 = {
3053         .master         = &dra7xx_l3_main_1_hwmod,
3054         .slave          = &dra7xx_aes2_hwmod,
3055         .clk            = "l3_iclk_div",
3056         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3057 };
3058
3059 /* l3_main_1 -> sha0 */
3060 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__sha0 = {
3061         .master         = &dra7xx_l3_main_1_hwmod,
3062         .slave          = &dra7xx_sha0_hwmod,
3063         .clk            = "l3_iclk_div",
3064         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3065 };
3066
3067 /* l4_per2 -> mcasp1 */
3068 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
3069         .master         = &dra7xx_l4_per2_hwmod,
3070         .slave          = &dra7xx_mcasp1_hwmod,
3071         .clk            = "l4_root_clk_div",
3072         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3073 };
3074
3075 /* l3_main_1 -> mcasp1 */
3076 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = {
3077         .master         = &dra7xx_l3_main_1_hwmod,
3078         .slave          = &dra7xx_mcasp1_hwmod,
3079         .clk            = "l3_iclk_div",
3080         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3081 };
3082
3083 /* l4_per2 -> mcasp2 */
3084 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = {
3085         .master         = &dra7xx_l4_per2_hwmod,
3086         .slave          = &dra7xx_mcasp2_hwmod,
3087         .clk            = "l4_root_clk_div",
3088         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3089 };
3090
3091 /* l3_main_1 -> mcasp2 */
3092 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = {
3093         .master         = &dra7xx_l3_main_1_hwmod,
3094         .slave          = &dra7xx_mcasp2_hwmod,
3095         .clk            = "l3_iclk_div",
3096         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3097 };
3098
3099 /* l4_per2 -> mcasp3 */
3100 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
3101         .master         = &dra7xx_l4_per2_hwmod,
3102         .slave          = &dra7xx_mcasp3_hwmod,
3103         .clk            = "l4_root_clk_div",
3104         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3105 };
3106
3107 /* l3_main_1 -> mcasp3 */
3108 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
3109         .master         = &dra7xx_l3_main_1_hwmod,
3110         .slave          = &dra7xx_mcasp3_hwmod,
3111         .clk            = "l3_iclk_div",
3112         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3113 };
3114
3115 /* l4_per2 -> mcasp4 */
3116 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = {
3117         .master         = &dra7xx_l4_per2_hwmod,
3118         .slave          = &dra7xx_mcasp4_hwmod,
3119         .clk            = "l4_root_clk_div",
3120         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3121 };
3122
3123 /* l4_per2 -> mcasp5 */
3124 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = {
3125         .master         = &dra7xx_l4_per2_hwmod,
3126         .slave          = &dra7xx_mcasp5_hwmod,
3127         .clk            = "l4_root_clk_div",
3128         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3129 };
3130
3131 /* l4_per2 -> mcasp6 */
3132 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
3133         .master         = &dra7xx_l4_per2_hwmod,
3134         .slave          = &dra7xx_mcasp6_hwmod,
3135         .clk            = "l4_root_clk_div",
3136         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3137 };
3138
3139 /* l4_per2 -> mcasp7 */
3140 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
3141         .master         = &dra7xx_l4_per2_hwmod,
3142         .slave          = &dra7xx_mcasp7_hwmod,
3143         .clk            = "l4_root_clk_div",
3144         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3145 };
3146
3147 /* l4_per2 -> mcasp8 */
3148 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
3149         .master         = &dra7xx_l4_per2_hwmod,
3150         .slave          = &dra7xx_mcasp8_hwmod,
3151         .clk            = "l4_root_clk_div",
3152         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3153 };
3154
3155 /* l4_per1 -> elm */
3156 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
3157         .master         = &dra7xx_l4_per1_hwmod,
3158         .slave          = &dra7xx_elm_hwmod,
3159         .clk            = "l3_iclk_div",
3160         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3161 };
3162
3163 /* l4_wkup -> gpio1 */
3164 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
3165         .master         = &dra7xx_l4_wkup_hwmod,
3166         .slave          = &dra7xx_gpio1_hwmod,
3167         .clk            = "wkupaon_iclk_mux",
3168         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3169 };
3170
3171 /* l4_per1 -> gpio2 */
3172 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
3173         .master         = &dra7xx_l4_per1_hwmod,
3174         .slave          = &dra7xx_gpio2_hwmod,
3175         .clk            = "l3_iclk_div",
3176         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3177 };
3178
3179 /* l4_per1 -> gpio3 */
3180 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
3181         .master         = &dra7xx_l4_per1_hwmod,
3182         .slave          = &dra7xx_gpio3_hwmod,
3183         .clk            = "l3_iclk_div",
3184         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3185 };
3186
3187 /* l4_per1 -> gpio4 */
3188 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
3189         .master         = &dra7xx_l4_per1_hwmod,
3190         .slave          = &dra7xx_gpio4_hwmod,
3191         .clk            = "l3_iclk_div",
3192         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3193 };
3194
3195 /* l4_per1 -> gpio5 */
3196 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
3197         .master         = &dra7xx_l4_per1_hwmod,
3198         .slave          = &dra7xx_gpio5_hwmod,
3199         .clk            = "l3_iclk_div",
3200         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3201 };
3202
3203 /* l4_per1 -> gpio6 */
3204 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
3205         .master         = &dra7xx_l4_per1_hwmod,
3206         .slave          = &dra7xx_gpio6_hwmod,
3207         .clk            = "l3_iclk_div",
3208         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3209 };
3210
3211 /* l4_per1 -> gpio7 */
3212 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
3213         .master         = &dra7xx_l4_per1_hwmod,
3214         .slave          = &dra7xx_gpio7_hwmod,
3215         .clk            = "l3_iclk_div",
3216         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3217 };
3218
3219 /* l4_per1 -> gpio8 */
3220 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
3221         .master         = &dra7xx_l4_per1_hwmod,
3222         .slave          = &dra7xx_gpio8_hwmod,
3223         .clk            = "l3_iclk_div",
3224         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3225 };
3226
3227 /* l3_main_1 -> gpmc */
3228 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
3229         .master         = &dra7xx_l3_main_1_hwmod,
3230         .slave          = &dra7xx_gpmc_hwmod,
3231         .clk            = "l3_iclk_div",
3232         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3233 };
3234
3235 /* l4_per1 -> hdq1w */
3236 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
3237         .master         = &dra7xx_l4_per1_hwmod,
3238         .slave          = &dra7xx_hdq1w_hwmod,
3239         .clk            = "l3_iclk_div",
3240         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3241 };
3242
3243 /* l4_per1 -> i2c1 */
3244 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
3245         .master         = &dra7xx_l4_per1_hwmod,
3246         .slave          = &dra7xx_i2c1_hwmod,
3247         .clk            = "l3_iclk_div",
3248         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3249 };
3250
3251 /* l4_per1 -> i2c2 */
3252 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
3253         .master         = &dra7xx_l4_per1_hwmod,
3254         .slave          = &dra7xx_i2c2_hwmod,
3255         .clk            = "l3_iclk_div",
3256         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3257 };
3258
3259 /* l4_per1 -> i2c3 */
3260 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
3261         .master         = &dra7xx_l4_per1_hwmod,
3262         .slave          = &dra7xx_i2c3_hwmod,
3263         .clk            = "l3_iclk_div",
3264         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3265 };
3266
3267 /* l4_per1 -> i2c4 */
3268 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
3269         .master         = &dra7xx_l4_per1_hwmod,
3270         .slave          = &dra7xx_i2c4_hwmod,
3271         .clk            = "l3_iclk_div",
3272         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3273 };
3274
3275 /* l4_per1 -> i2c5 */
3276 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
3277         .master         = &dra7xx_l4_per1_hwmod,
3278         .slave          = &dra7xx_i2c5_hwmod,
3279         .clk            = "l3_iclk_div",
3280         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3281 };
3282
3283 /* l4_cfg -> mailbox1 */
3284 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
3285         .master         = &dra7xx_l4_cfg_hwmod,
3286         .slave          = &dra7xx_mailbox1_hwmod,
3287         .clk            = "l3_iclk_div",
3288         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3289 };
3290
3291 /* l4_per3 -> mailbox2 */
3292 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
3293         .master         = &dra7xx_l4_per3_hwmod,
3294         .slave          = &dra7xx_mailbox2_hwmod,
3295         .clk            = "l3_iclk_div",
3296         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3297 };
3298
3299 /* l4_per3 -> mailbox3 */
3300 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
3301         .master         = &dra7xx_l4_per3_hwmod,
3302         .slave          = &dra7xx_mailbox3_hwmod,
3303         .clk            = "l3_iclk_div",
3304         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3305 };
3306
3307 /* l4_per3 -> mailbox4 */
3308 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
3309         .master         = &dra7xx_l4_per3_hwmod,
3310         .slave          = &dra7xx_mailbox4_hwmod,
3311         .clk            = "l3_iclk_div",
3312         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3313 };
3314
3315 /* l4_per3 -> mailbox5 */
3316 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
3317         .master         = &dra7xx_l4_per3_hwmod,
3318         .slave          = &dra7xx_mailbox5_hwmod,
3319         .clk            = "l3_iclk_div",
3320         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3321 };
3322
3323 /* l4_per3 -> mailbox6 */
3324 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
3325         .master         = &dra7xx_l4_per3_hwmod,
3326         .slave          = &dra7xx_mailbox6_hwmod,
3327         .clk            = "l3_iclk_div",
3328         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3329 };
3330
3331 /* l4_per3 -> mailbox7 */
3332 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
3333         .master         = &dra7xx_l4_per3_hwmod,
3334         .slave          = &dra7xx_mailbox7_hwmod,
3335         .clk            = "l3_iclk_div",
3336         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3337 };
3338
3339 /* l4_per3 -> mailbox8 */
3340 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
3341         .master         = &dra7xx_l4_per3_hwmod,
3342         .slave          = &dra7xx_mailbox8_hwmod,
3343         .clk            = "l3_iclk_div",
3344         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3345 };
3346
3347 /* l4_per3 -> mailbox9 */
3348 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
3349         .master         = &dra7xx_l4_per3_hwmod,
3350         .slave          = &dra7xx_mailbox9_hwmod,
3351         .clk            = "l3_iclk_div",
3352         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3353 };
3354
3355 /* l4_per3 -> mailbox10 */
3356 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
3357         .master         = &dra7xx_l4_per3_hwmod,
3358         .slave          = &dra7xx_mailbox10_hwmod,
3359         .clk            = "l3_iclk_div",
3360         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3361 };
3362
3363 /* l4_per3 -> mailbox11 */
3364 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
3365         .master         = &dra7xx_l4_per3_hwmod,
3366         .slave          = &dra7xx_mailbox11_hwmod,
3367         .clk            = "l3_iclk_div",
3368         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3369 };
3370
3371 /* l4_per3 -> mailbox12 */
3372 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
3373         .master         = &dra7xx_l4_per3_hwmod,
3374         .slave          = &dra7xx_mailbox12_hwmod,
3375         .clk            = "l3_iclk_div",
3376         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3377 };
3378
3379 /* l4_per3 -> mailbox13 */
3380 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
3381         .master         = &dra7xx_l4_per3_hwmod,
3382         .slave          = &dra7xx_mailbox13_hwmod,
3383         .clk            = "l3_iclk_div",
3384         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3385 };
3386
3387 /* l4_per1 -> mcspi1 */
3388 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
3389         .master         = &dra7xx_l4_per1_hwmod,
3390         .slave          = &dra7xx_mcspi1_hwmod,
3391         .clk            = "l3_iclk_div",
3392         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3393 };
3394
3395 /* l4_per1 -> mcspi2 */
3396 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
3397         .master         = &dra7xx_l4_per1_hwmod,
3398         .slave          = &dra7xx_mcspi2_hwmod,
3399         .clk            = "l3_iclk_div",
3400         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3401 };
3402
3403 /* l4_per1 -> mcspi3 */
3404 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
3405         .master         = &dra7xx_l4_per1_hwmod,
3406         .slave          = &dra7xx_mcspi3_hwmod,
3407         .clk            = "l3_iclk_div",
3408         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3409 };
3410
3411 /* l4_per1 -> mcspi4 */
3412 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
3413         .master         = &dra7xx_l4_per1_hwmod,
3414         .slave          = &dra7xx_mcspi4_hwmod,
3415         .clk            = "l3_iclk_div",
3416         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3417 };
3418
3419 /* l4_per1 -> mmc1 */
3420 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
3421         .master         = &dra7xx_l4_per1_hwmod,
3422         .slave          = &dra7xx_mmc1_hwmod,
3423         .clk            = "l3_iclk_div",
3424         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3425 };
3426
3427 /* l4_per1 -> mmc2 */
3428 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
3429         .master         = &dra7xx_l4_per1_hwmod,
3430         .slave          = &dra7xx_mmc2_hwmod,
3431         .clk            = "l3_iclk_div",
3432         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3433 };
3434
3435 /* l4_per1 -> mmc3 */
3436 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
3437         .master         = &dra7xx_l4_per1_hwmod,
3438         .slave          = &dra7xx_mmc3_hwmod,
3439         .clk            = "l3_iclk_div",
3440         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3441 };
3442
3443 /* l4_per1 -> mmc4 */
3444 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
3445         .master         = &dra7xx_l4_per1_hwmod,
3446         .slave          = &dra7xx_mmc4_hwmod,
3447         .clk            = "l3_iclk_div",
3448         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3449 };
3450
3451 /* l4_cfg -> mpu */
3452 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
3453         .master         = &dra7xx_l4_cfg_hwmod,
3454         .slave          = &dra7xx_mpu_hwmod,
3455         .clk            = "l3_iclk_div",
3456         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3457 };
3458
3459 /* l4_cfg -> ocp2scp1 */
3460 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
3461         .master         = &dra7xx_l4_cfg_hwmod,
3462         .slave          = &dra7xx_ocp2scp1_hwmod,
3463         .clk            = "l4_root_clk_div",
3464         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3465 };
3466
3467 /* l4_cfg -> ocp2scp3 */
3468 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
3469         .master         = &dra7xx_l4_cfg_hwmod,
3470         .slave          = &dra7xx_ocp2scp3_hwmod,
3471         .clk            = "l4_root_clk_div",
3472         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3473 };
3474
3475 /* l3_main_1 -> pciess1 */
3476 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
3477         .master         = &dra7xx_l3_main_1_hwmod,
3478         .slave          = &dra7xx_pciess1_hwmod,
3479         .clk            = "l3_iclk_div",
3480         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3481 };
3482
3483 /* l4_cfg -> pciess1 */
3484 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
3485         .master         = &dra7xx_l4_cfg_hwmod,
3486         .slave          = &dra7xx_pciess1_hwmod,
3487         .clk            = "l4_root_clk_div",
3488         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3489 };
3490
3491 /* l3_main_1 -> pciess2 */
3492 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
3493         .master         = &dra7xx_l3_main_1_hwmod,
3494         .slave          = &dra7xx_pciess2_hwmod,
3495         .clk            = "l3_iclk_div",
3496         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3497 };
3498
3499 /* l4_cfg -> pciess2 */
3500 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
3501         .master         = &dra7xx_l4_cfg_hwmod,
3502         .slave          = &dra7xx_pciess2_hwmod,
3503         .clk            = "l4_root_clk_div",
3504         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3505 };
3506
3507 /* l3_main_1 -> qspi */
3508 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
3509         .master         = &dra7xx_l3_main_1_hwmod,
3510         .slave          = &dra7xx_qspi_hwmod,
3511         .clk            = "l3_iclk_div",
3512         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3513 };
3514
3515 /* l4_per3 -> rtcss */
3516 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
3517         .master         = &dra7xx_l4_per3_hwmod,
3518         .slave          = &dra7xx_rtcss_hwmod,
3519         .clk            = "l4_root_clk_div",
3520         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3521 };
3522
3523 /* l4_cfg -> sata */
3524 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
3525         .master         = &dra7xx_l4_cfg_hwmod,
3526         .slave          = &dra7xx_sata_hwmod,
3527         .clk            = "l3_iclk_div",
3528         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3529 };
3530
3531 /* l4_cfg -> smartreflex_core */
3532 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
3533         .master         = &dra7xx_l4_cfg_hwmod,
3534         .slave          = &dra7xx_smartreflex_core_hwmod,
3535         .clk            = "l4_root_clk_div",
3536         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3537 };
3538
3539 /* l4_cfg -> smartreflex_mpu */
3540 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
3541         .master         = &dra7xx_l4_cfg_hwmod,
3542         .slave          = &dra7xx_smartreflex_mpu_hwmod,
3543         .clk            = "l4_root_clk_div",
3544         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3545 };
3546
3547 /* l4_cfg -> spinlock */
3548 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
3549         .master         = &dra7xx_l4_cfg_hwmod,
3550         .slave          = &dra7xx_spinlock_hwmod,
3551         .clk            = "l3_iclk_div",
3552         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3553 };
3554
3555 /* l4_wkup -> timer1 */
3556 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
3557         .master         = &dra7xx_l4_wkup_hwmod,
3558         .slave          = &dra7xx_timer1_hwmod,
3559         .clk            = "wkupaon_iclk_mux",
3560         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3561 };
3562
3563 /* l4_per1 -> timer2 */
3564 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
3565         .master         = &dra7xx_l4_per1_hwmod,
3566         .slave          = &dra7xx_timer2_hwmod,
3567         .clk            = "l3_iclk_div",
3568         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3569 };
3570
3571 /* l4_per1 -> timer3 */
3572 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
3573         .master         = &dra7xx_l4_per1_hwmod,
3574         .slave          = &dra7xx_timer3_hwmod,
3575         .clk            = "l3_iclk_div",
3576         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3577 };
3578
3579 /* l4_per1 -> timer4 */
3580 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
3581         .master         = &dra7xx_l4_per1_hwmod,
3582         .slave          = &dra7xx_timer4_hwmod,
3583         .clk            = "l3_iclk_div",
3584         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3585 };
3586
3587 /* l4_per3 -> timer5 */
3588 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
3589         .master         = &dra7xx_l4_per3_hwmod,
3590         .slave          = &dra7xx_timer5_hwmod,
3591         .clk            = "l3_iclk_div",
3592         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3593 };
3594
3595 /* l4_per3 -> timer6 */
3596 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
3597         .master         = &dra7xx_l4_per3_hwmod,
3598         .slave          = &dra7xx_timer6_hwmod,
3599         .clk            = "l3_iclk_div",
3600         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3601 };
3602
3603 /* l4_per3 -> timer7 */
3604 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
3605         .master         = &dra7xx_l4_per3_hwmod,
3606         .slave          = &dra7xx_timer7_hwmod,
3607         .clk            = "l3_iclk_div",
3608         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3609 };
3610
3611 /* l4_per3 -> timer8 */
3612 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
3613         .master         = &dra7xx_l4_per3_hwmod,
3614         .slave          = &dra7xx_timer8_hwmod,
3615         .clk            = "l3_iclk_div",
3616         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3617 };
3618
3619 /* l4_per1 -> timer9 */
3620 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
3621         .master         = &dra7xx_l4_per1_hwmod,
3622         .slave          = &dra7xx_timer9_hwmod,
3623         .clk            = "l3_iclk_div",
3624         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3625 };
3626
3627 /* l4_per1 -> timer10 */
3628 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
3629         .master         = &dra7xx_l4_per1_hwmod,
3630         .slave          = &dra7xx_timer10_hwmod,
3631         .clk            = "l3_iclk_div",
3632         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3633 };
3634
3635 /* l4_per1 -> timer11 */
3636 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
3637         .master         = &dra7xx_l4_per1_hwmod,
3638         .slave          = &dra7xx_timer11_hwmod,
3639         .clk            = "l3_iclk_div",
3640         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3641 };
3642
3643 /* l4_wkup -> timer12 */
3644 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = {
3645         .master         = &dra7xx_l4_wkup_hwmod,
3646         .slave          = &dra7xx_timer12_hwmod,
3647         .clk            = "wkupaon_iclk_mux",
3648         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3649 };
3650
3651 /* l4_per3 -> timer13 */
3652 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
3653         .master         = &dra7xx_l4_per3_hwmod,
3654         .slave          = &dra7xx_timer13_hwmod,
3655         .clk            = "l3_iclk_div",
3656         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3657 };
3658
3659 /* l4_per3 -> timer14 */
3660 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
3661         .master         = &dra7xx_l4_per3_hwmod,
3662         .slave          = &dra7xx_timer14_hwmod,
3663         .clk            = "l3_iclk_div",
3664         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3665 };
3666
3667 /* l4_per3 -> timer15 */
3668 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
3669         .master         = &dra7xx_l4_per3_hwmod,
3670         .slave          = &dra7xx_timer15_hwmod,
3671         .clk            = "l3_iclk_div",
3672         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3673 };
3674
3675 /* l4_per3 -> timer16 */
3676 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
3677         .master         = &dra7xx_l4_per3_hwmod,
3678         .slave          = &dra7xx_timer16_hwmod,
3679         .clk            = "l3_iclk_div",
3680         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3681 };
3682
3683 /* l4_per1 -> uart1 */
3684 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
3685         .master         = &dra7xx_l4_per1_hwmod,
3686         .slave          = &dra7xx_uart1_hwmod,
3687         .clk            = "l3_iclk_div",
3688         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3689 };
3690
3691 /* l4_per1 -> uart2 */
3692 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
3693         .master         = &dra7xx_l4_per1_hwmod,
3694         .slave          = &dra7xx_uart2_hwmod,
3695         .clk            = "l3_iclk_div",
3696         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3697 };
3698
3699 /* l4_per1 -> uart3 */
3700 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
3701         .master         = &dra7xx_l4_per1_hwmod,
3702         .slave          = &dra7xx_uart3_hwmod,
3703         .clk            = "l3_iclk_div",
3704         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3705 };
3706
3707 /* l4_per1 -> uart4 */
3708 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
3709         .master         = &dra7xx_l4_per1_hwmod,
3710         .slave          = &dra7xx_uart4_hwmod,
3711         .clk            = "l3_iclk_div",
3712         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3713 };
3714
3715 /* l4_per1 -> uart5 */
3716 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
3717         .master         = &dra7xx_l4_per1_hwmod,
3718         .slave          = &dra7xx_uart5_hwmod,
3719         .clk            = "l3_iclk_div",
3720         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3721 };
3722
3723 /* l4_per1 -> uart6 */
3724 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
3725         .master         = &dra7xx_l4_per1_hwmod,
3726         .slave          = &dra7xx_uart6_hwmod,
3727         .clk            = "l3_iclk_div",
3728         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3729 };
3730
3731 /* l4_per2 -> uart7 */
3732 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
3733         .master         = &dra7xx_l4_per2_hwmod,
3734         .slave          = &dra7xx_uart7_hwmod,
3735         .clk            = "l3_iclk_div",
3736         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3737 };
3738
3739 /* l4_per1 -> des */
3740 static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = {
3741         .master         = &dra7xx_l4_per1_hwmod,
3742         .slave          = &dra7xx_des_hwmod,
3743         .clk            = "l3_iclk_div",
3744         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3745 };
3746
3747 /* l4_per2 -> uart8 */
3748 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
3749         .master         = &dra7xx_l4_per2_hwmod,
3750         .slave          = &dra7xx_uart8_hwmod,
3751         .clk            = "l3_iclk_div",
3752         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3753 };
3754
3755 /* l4_per2 -> uart9 */
3756 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
3757         .master         = &dra7xx_l4_per2_hwmod,
3758         .slave          = &dra7xx_uart9_hwmod,
3759         .clk            = "l3_iclk_div",
3760         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3761 };
3762
3763 /* l4_wkup -> uart10 */
3764 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
3765         .master         = &dra7xx_l4_wkup_hwmod,
3766         .slave          = &dra7xx_uart10_hwmod,
3767         .clk            = "wkupaon_iclk_mux",
3768         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3769 };
3770
3771 /* l4_per1 -> rng */
3772 static struct omap_hwmod_ocp_if dra7xx_l4_per1__rng = {
3773         .master         = &dra7xx_l4_per1_hwmod,
3774         .slave          = &dra7xx_rng_hwmod,
3775         .user           = OCP_USER_MPU,
3776 };
3777
3778 /* l4_per3 -> usb_otg_ss1 */
3779 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
3780         .master         = &dra7xx_l4_per3_hwmod,
3781         .slave          = &dra7xx_usb_otg_ss1_hwmod,
3782         .clk            = "dpll_core_h13x2_ck",
3783         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3784 };
3785
3786 /* l4_per3 -> usb_otg_ss2 */
3787 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
3788         .master         = &dra7xx_l4_per3_hwmod,
3789         .slave          = &dra7xx_usb_otg_ss2_hwmod,
3790         .clk            = "dpll_core_h13x2_ck",
3791         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3792 };
3793
3794 /* l4_per3 -> usb_otg_ss3 */
3795 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
3796         .master         = &dra7xx_l4_per3_hwmod,
3797         .slave          = &dra7xx_usb_otg_ss3_hwmod,
3798         .clk            = "dpll_core_h13x2_ck",
3799         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3800 };
3801
3802 /* l4_per3 -> usb_otg_ss4 */
3803 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
3804         .master         = &dra7xx_l4_per3_hwmod,
3805         .slave          = &dra7xx_usb_otg_ss4_hwmod,
3806         .clk            = "dpll_core_h13x2_ck",
3807         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3808 };
3809
3810 /* l3_main_1 -> vcp1 */
3811 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
3812         .master         = &dra7xx_l3_main_1_hwmod,
3813         .slave          = &dra7xx_vcp1_hwmod,
3814         .clk            = "l3_iclk_div",
3815         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3816 };
3817
3818 /* l4_per2 -> vcp1 */
3819 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
3820         .master         = &dra7xx_l4_per2_hwmod,
3821         .slave          = &dra7xx_vcp1_hwmod,
3822         .clk            = "l3_iclk_div",
3823         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3824 };
3825
3826 /* l3_main_1 -> vcp2 */
3827 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
3828         .master         = &dra7xx_l3_main_1_hwmod,
3829         .slave          = &dra7xx_vcp2_hwmod,
3830         .clk            = "l3_iclk_div",
3831         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3832 };
3833
3834 /* l4_per2 -> vcp2 */
3835 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
3836         .master         = &dra7xx_l4_per2_hwmod,
3837         .slave          = &dra7xx_vcp2_hwmod,
3838         .clk            = "l3_iclk_div",
3839         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3840 };
3841
3842 /* l4_wkup -> wd_timer2 */
3843 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
3844         .master         = &dra7xx_l4_wkup_hwmod,
3845         .slave          = &dra7xx_wd_timer2_hwmod,
3846         .clk            = "wkupaon_iclk_mux",
3847         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3848 };
3849
3850 /* l4_per2 -> epwmss0 */
3851 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss0 = {
3852         .master         = &dra7xx_l4_per2_hwmod,
3853         .slave          = &dra7xx_epwmss0_hwmod,
3854         .clk            = "l4_root_clk_div",
3855         .user           = OCP_USER_MPU,
3856 };
3857
3858 /* l4_per2 -> epwmss1 */
3859 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss1 = {
3860         .master         = &dra7xx_l4_per2_hwmod,
3861         .slave          = &dra7xx_epwmss1_hwmod,
3862         .clk            = "l4_root_clk_div",
3863         .user           = OCP_USER_MPU,
3864 };
3865
3866 /* l4_per2 -> epwmss2 */
3867 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss2 = {
3868         .master         = &dra7xx_l4_per2_hwmod,
3869         .slave          = &dra7xx_epwmss2_hwmod,
3870         .clk            = "l4_root_clk_div",
3871         .user           = OCP_USER_MPU,
3872 };
3873
3874 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3875         &dra7xx_l3_main_1__dmm,
3876         &dra7xx_l3_main_2__l3_instr,
3877         &dra7xx_l4_cfg__l3_main_1,
3878         &dra7xx_mpu__l3_main_1,
3879         &dra7xx_l3_main_1__l3_main_2,
3880         &dra7xx_l4_cfg__l3_main_2,
3881         &dra7xx_l3_main_1__l4_cfg,
3882         &dra7xx_l3_main_1__l4_per1,
3883         &dra7xx_l3_main_1__l4_per2,
3884         &dra7xx_l3_main_1__l4_per3,
3885         &dra7xx_l3_main_1__l4_wkup,
3886         &dra7xx_l4_per2__atl,
3887         &dra7xx_l3_main_1__bb2d,
3888         &dra7xx_l4_wkup__counter_32k,
3889         &dra7xx_l4_wkup__ctrl_module_wkup,
3890         &dra7xx_l4_wkup__dcan1,
3891         &dra7xx_l4_per2__dcan2,
3892         &dra7xx_l4_per2__cpgmac0,
3893         &dra7xx_l4_per2__mcasp1,
3894         &dra7xx_l3_main_1__mcasp1,
3895         &dra7xx_l4_per2__mcasp2,
3896         &dra7xx_l3_main_1__mcasp2,
3897         &dra7xx_l4_per2__mcasp3,
3898         &dra7xx_l3_main_1__mcasp3,
3899         &dra7xx_l4_per2__mcasp4,
3900         &dra7xx_l4_per2__mcasp5,
3901         &dra7xx_l4_per2__mcasp6,
3902         &dra7xx_l4_per2__mcasp7,
3903         &dra7xx_l4_per2__mcasp8,
3904         &dra7xx_gmac__mdio,
3905         &dra7xx_l4_cfg__dma_system,
3906         &dra7xx_l3_main_1__tpcc,
3907         &dra7xx_l3_main_1__tptc0,
3908         &dra7xx_l3_main_1__tptc1,
3909         &dra7xx_l3_main_1__dss,
3910         &dra7xx_l3_main_1__dispc,
3911         &dra7xx_l3_main_1__hdmi,
3912         &dra7xx_l3_main_1__aes1,
3913         &dra7xx_l3_main_1__aes2,
3914         &dra7xx_l3_main_1__sha0,
3915         &dra7xx_l4_per1__elm,
3916         &dra7xx_l4_wkup__gpio1,
3917         &dra7xx_l4_per1__gpio2,
3918         &dra7xx_l4_per1__gpio3,
3919         &dra7xx_l4_per1__gpio4,
3920         &dra7xx_l4_per1__gpio5,
3921         &dra7xx_l4_per1__gpio6,
3922         &dra7xx_l4_per1__gpio7,
3923         &dra7xx_l4_per1__gpio8,
3924         &dra7xx_l3_main_1__gpmc,
3925         &dra7xx_l4_per1__hdq1w,
3926         &dra7xx_l4_per1__i2c1,
3927         &dra7xx_l4_per1__i2c2,
3928         &dra7xx_l4_per1__i2c3,
3929         &dra7xx_l4_per1__i2c4,
3930         &dra7xx_l4_per1__i2c5,
3931         &dra7xx_l4_cfg__mailbox1,
3932         &dra7xx_l4_per3__mailbox2,
3933         &dra7xx_l4_per3__mailbox3,
3934         &dra7xx_l4_per3__mailbox4,
3935         &dra7xx_l4_per3__mailbox5,
3936         &dra7xx_l4_per3__mailbox6,
3937         &dra7xx_l4_per3__mailbox7,
3938         &dra7xx_l4_per3__mailbox8,
3939         &dra7xx_l4_per3__mailbox9,
3940         &dra7xx_l4_per3__mailbox10,
3941         &dra7xx_l4_per3__mailbox11,
3942         &dra7xx_l4_per3__mailbox12,
3943         &dra7xx_l4_per3__mailbox13,
3944         &dra7xx_l4_per1__mcspi1,
3945         &dra7xx_l4_per1__mcspi2,
3946         &dra7xx_l4_per1__mcspi3,
3947         &dra7xx_l4_per1__mcspi4,
3948         &dra7xx_l4_per1__mmc1,
3949         &dra7xx_l4_per1__mmc2,
3950         &dra7xx_l4_per1__mmc3,
3951         &dra7xx_l4_per1__mmc4,
3952         &dra7xx_l4_cfg__mpu,
3953         &dra7xx_l4_cfg__ocp2scp1,
3954         &dra7xx_l4_cfg__ocp2scp3,
3955         &dra7xx_l3_main_1__pciess1,
3956         &dra7xx_l4_cfg__pciess1,
3957         &dra7xx_l3_main_1__pciess2,
3958         &dra7xx_l4_cfg__pciess2,
3959         &dra7xx_l3_main_1__qspi,
3960         &dra7xx_l4_cfg__sata,
3961         &dra7xx_l4_cfg__smartreflex_core,
3962         &dra7xx_l4_cfg__smartreflex_mpu,
3963         &dra7xx_l4_cfg__spinlock,
3964         &dra7xx_l4_wkup__timer1,
3965         &dra7xx_l4_per1__timer2,
3966         &dra7xx_l4_per1__timer3,
3967         &dra7xx_l4_per1__timer4,
3968         &dra7xx_l4_per3__timer5,
3969         &dra7xx_l4_per3__timer6,
3970         &dra7xx_l4_per3__timer7,
3971         &dra7xx_l4_per3__timer8,
3972         &dra7xx_l4_per1__timer9,
3973         &dra7xx_l4_per1__timer10,
3974         &dra7xx_l4_per1__timer11,
3975         &dra7xx_l4_per3__timer13,
3976         &dra7xx_l4_per3__timer14,
3977         &dra7xx_l4_per3__timer15,
3978         &dra7xx_l4_per3__timer16,
3979         &dra7xx_l4_per1__uart1,
3980         &dra7xx_l4_per1__uart2,
3981         &dra7xx_l4_per1__uart3,
3982         &dra7xx_l4_per1__uart4,
3983         &dra7xx_l4_per1__uart5,
3984         &dra7xx_l4_per1__uart6,
3985         &dra7xx_l4_per2__uart7,
3986         &dra7xx_l4_per2__uart8,
3987         &dra7xx_l4_per2__uart9,
3988         &dra7xx_l4_wkup__uart10,
3989         &dra7xx_l4_per1__des,
3990         &dra7xx_l4_per3__usb_otg_ss1,
3991         &dra7xx_l4_per3__usb_otg_ss2,
3992         &dra7xx_l4_per3__usb_otg_ss3,
3993         &dra7xx_l3_main_1__vcp1,
3994         &dra7xx_l4_per2__vcp1,
3995         &dra7xx_l3_main_1__vcp2,
3996         &dra7xx_l4_per2__vcp2,
3997         &dra7xx_l4_wkup__wd_timer2,
3998         &dra7xx_l4_per2__epwmss0,
3999         &dra7xx_l4_per2__epwmss1,
4000         &dra7xx_l4_per2__epwmss2,
4001         NULL,
4002 };
4003
4004 /* GP-only hwmod links */
4005 static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = {
4006         &dra7xx_l4_wkup__timer12,
4007         &dra7xx_l4_per1__rng,
4008         NULL,
4009 };
4010
4011 /* SoC variant specific hwmod links */
4012 static struct omap_hwmod_ocp_if *dra76x_hwmod_ocp_ifs[] __initdata = {
4013         &dra7xx_l4_per3__usb_otg_ss4,
4014         NULL,
4015 };
4016
4017 static struct omap_hwmod_ocp_if *acd_76x_hwmod_ocp_ifs[] __initdata = {
4018         NULL,
4019 };
4020
4021 static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
4022         &dra7xx_l4_per3__usb_otg_ss4,
4023         NULL,
4024 };
4025
4026 static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
4027         NULL,
4028 };
4029
4030 static struct omap_hwmod_ocp_if *rtc_hwmod_ocp_ifs[] __initdata = {
4031         &dra7xx_l4_per3__rtcss,
4032         NULL,
4033 };
4034
4035 int __init dra7xx_hwmod_init(void)
4036 {
4037         int ret;
4038
4039         omap_hwmod_init();
4040         ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
4041
4042         if (!ret && soc_is_dra74x()) {
4043                 ret = omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
4044                 if (!ret)
4045                         ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
4046         } else if (!ret && soc_is_dra72x()) {
4047                 ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
4048                 if (!ret && !of_machine_is_compatible("ti,dra718"))
4049                         ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
4050         } else if (!ret && soc_is_dra76x()) {
4051                 ret = omap_hwmod_register_links(dra76x_hwmod_ocp_ifs);
4052
4053                 if (!ret && soc_is_dra76x_acd()) {
4054                         ret = omap_hwmod_register_links(acd_76x_hwmod_ocp_ifs);
4055                 } else if (!ret && soc_is_dra76x_abz()) {
4056                         ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
4057                 }
4058         }
4059
4060         if (!ret && omap_type() == OMAP2_DEVICE_TYPE_GP)
4061                 ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs);
4062
4063         return ret;
4064 }