Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
[sfrench/cifs-2.6.git] / arch / arm / mach-omap2 / omap_hwmod_7xx_data.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Hardware modules present on the DRA7xx chips
4  *
5  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
6  *
7  * Paul Walmsley
8  * Benoit Cousson
9  *
10  * This file is automatically generated from the OMAP hardware databases.
11  * We respectfully ask that any modifications to this file be coordinated
12  * with the public linux-omap@vger.kernel.org mailing list and the
13  * authors above to ensure that the autogeneration scripts are kept
14  * up-to-date with the file contents.
15  */
16
17 #include <linux/io.h>
18 #include <linux/power/smartreflex.h>
19
20 #include <linux/omap-dma.h>
21
22 #include "omap_hwmod.h"
23 #include "omap_hwmod_common_data.h"
24 #include "cm1_7xx.h"
25 #include "cm2_7xx.h"
26 #include "prm7xx.h"
27 #include "wd_timer.h"
28 #include "soc.h"
29
30 /* Base offset for all DRA7XX interrupts external to MPUSS */
31 #define DRA7XX_IRQ_GIC_START    32
32
33 /* Base offset for all DRA7XX dma requests */
34 #define DRA7XX_DMA_REQ_START    1
35
36
37 /*
38  * IP blocks
39  */
40
41 /*
42  * 'dmm' class
43  * instance(s): dmm
44  */
45 static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
46         .name   = "dmm",
47 };
48
49 /* dmm */
50 static struct omap_hwmod dra7xx_dmm_hwmod = {
51         .name           = "dmm",
52         .class          = &dra7xx_dmm_hwmod_class,
53         .clkdm_name     = "emif_clkdm",
54         .prcm = {
55                 .omap4 = {
56                         .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
57                         .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
58                 },
59         },
60 };
61
62 /*
63  * 'l3' class
64  * instance(s): l3_instr, l3_main_1, l3_main_2
65  */
66 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
67         .name   = "l3",
68 };
69
70 /* l3_instr */
71 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
72         .name           = "l3_instr",
73         .class          = &dra7xx_l3_hwmod_class,
74         .clkdm_name     = "l3instr_clkdm",
75         .prcm = {
76                 .omap4 = {
77                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
78                         .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
79                         .modulemode   = MODULEMODE_HWCTRL,
80                 },
81         },
82 };
83
84 /* l3_main_1 */
85 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
86         .name           = "l3_main_1",
87         .class          = &dra7xx_l3_hwmod_class,
88         .clkdm_name     = "l3main1_clkdm",
89         .prcm = {
90                 .omap4 = {
91                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
92                         .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
93                 },
94         },
95 };
96
97 /* l3_main_2 */
98 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
99         .name           = "l3_main_2",
100         .class          = &dra7xx_l3_hwmod_class,
101         .clkdm_name     = "l3instr_clkdm",
102         .prcm = {
103                 .omap4 = {
104                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
105                         .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
106                         .modulemode   = MODULEMODE_HWCTRL,
107                 },
108         },
109 };
110
111 /*
112  * 'l4' class
113  * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
114  */
115 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
116         .name   = "l4",
117 };
118
119 /* l4_cfg */
120 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
121         .name           = "l4_cfg",
122         .class          = &dra7xx_l4_hwmod_class,
123         .clkdm_name     = "l4cfg_clkdm",
124         .prcm = {
125                 .omap4 = {
126                         .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
127                         .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
128                 },
129         },
130 };
131
132 /* l4_per1 */
133 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
134         .name           = "l4_per1",
135         .class          = &dra7xx_l4_hwmod_class,
136         .clkdm_name     = "l4per_clkdm",
137         .prcm = {
138                 .omap4 = {
139                         .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
140                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
141                 },
142         },
143 };
144
145 /* l4_per2 */
146 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
147         .name           = "l4_per2",
148         .class          = &dra7xx_l4_hwmod_class,
149         .clkdm_name     = "l4per2_clkdm",
150         .prcm = {
151                 .omap4 = {
152                         .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
153                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
154                 },
155         },
156 };
157
158 /* l4_per3 */
159 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
160         .name           = "l4_per3",
161         .class          = &dra7xx_l4_hwmod_class,
162         .clkdm_name     = "l4per3_clkdm",
163         .prcm = {
164                 .omap4 = {
165                         .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
166                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
167                 },
168         },
169 };
170
171 /* l4_wkup */
172 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
173         .name           = "l4_wkup",
174         .class          = &dra7xx_l4_hwmod_class,
175         .clkdm_name     = "wkupaon_clkdm",
176         .prcm = {
177                 .omap4 = {
178                         .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
179                         .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
180                 },
181         },
182 };
183
184 /*
185  * 'atl' class
186  *
187  */
188
189 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
190         .name   = "atl",
191 };
192
193 /* atl */
194 static struct omap_hwmod dra7xx_atl_hwmod = {
195         .name           = "atl",
196         .class          = &dra7xx_atl_hwmod_class,
197         .clkdm_name     = "atl_clkdm",
198         .main_clk       = "atl_gfclk_mux",
199         .prcm = {
200                 .omap4 = {
201                         .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
202                         .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
203                         .modulemode   = MODULEMODE_SWCTRL,
204                 },
205         },
206 };
207
208 /*
209  * 'bb2d' class
210  *
211  */
212
213 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
214         .name   = "bb2d",
215 };
216
217 /* bb2d */
218 static struct omap_hwmod dra7xx_bb2d_hwmod = {
219         .name           = "bb2d",
220         .class          = &dra7xx_bb2d_hwmod_class,
221         .clkdm_name     = "dss_clkdm",
222         .main_clk       = "dpll_core_h24x2_ck",
223         .prcm = {
224                 .omap4 = {
225                         .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
226                         .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
227                         .modulemode   = MODULEMODE_SWCTRL,
228                 },
229         },
230 };
231
232 /*
233  * 'counter' class
234  *
235  */
236
237 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
238         .rev_offs       = 0x0000,
239         .sysc_offs      = 0x0010,
240         .sysc_flags     = SYSC_HAS_SIDLEMODE,
241         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
242                            SIDLE_SMART_WKUP),
243         .sysc_fields    = &omap_hwmod_sysc_type1,
244 };
245
246 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
247         .name   = "counter",
248         .sysc   = &dra7xx_counter_sysc,
249 };
250
251 /* counter_32k */
252 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
253         .name           = "counter_32k",
254         .class          = &dra7xx_counter_hwmod_class,
255         .clkdm_name     = "wkupaon_clkdm",
256         .flags          = HWMOD_SWSUP_SIDLE,
257         .main_clk       = "wkupaon_iclk_mux",
258         .prcm = {
259                 .omap4 = {
260                         .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
261                         .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
262                 },
263         },
264 };
265
266 /*
267  * 'ctrl_module' class
268  *
269  */
270
271 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
272         .name   = "ctrl_module",
273 };
274
275 /* ctrl_module_wkup */
276 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
277         .name           = "ctrl_module_wkup",
278         .class          = &dra7xx_ctrl_module_hwmod_class,
279         .clkdm_name     = "wkupaon_clkdm",
280         .prcm = {
281                 .omap4 = {
282                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
283                 },
284         },
285 };
286
287 /*
288  * 'gmac' class
289  * cpsw/gmac sub system
290  */
291 static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
292         .rev_offs       = 0x0,
293         .sysc_offs      = 0x8,
294         .syss_offs      = 0x4,
295         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
296                            SYSS_HAS_RESET_STATUS),
297         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
298                            MSTANDBY_NO),
299         .sysc_fields    = &omap_hwmod_sysc_type3,
300 };
301
302 static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
303         .name           = "gmac",
304         .sysc           = &dra7xx_gmac_sysc,
305 };
306
307 static struct omap_hwmod dra7xx_gmac_hwmod = {
308         .name           = "gmac",
309         .class          = &dra7xx_gmac_hwmod_class,
310         .clkdm_name     = "gmac_clkdm",
311         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
312         .main_clk       = "dpll_gmac_ck",
313         .mpu_rt_idx     = 1,
314         .prcm           = {
315                 .omap4  = {
316                         .clkctrl_offs   = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
317                         .context_offs   = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
318                         .modulemode     = MODULEMODE_SWCTRL,
319                 },
320         },
321 };
322
323 /*
324  * 'mdio' class
325  */
326 static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
327         .name           = "davinci_mdio",
328 };
329
330 static struct omap_hwmod dra7xx_mdio_hwmod = {
331         .name           = "davinci_mdio",
332         .class          = &dra7xx_mdio_hwmod_class,
333         .clkdm_name     = "gmac_clkdm",
334         .main_clk       = "dpll_gmac_ck",
335 };
336
337 /*
338  * 'dcan' class
339  *
340  */
341
342 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
343         .name   = "dcan",
344 };
345
346 /* dcan1 */
347 static struct omap_hwmod dra7xx_dcan1_hwmod = {
348         .name           = "dcan1",
349         .class          = &dra7xx_dcan_hwmod_class,
350         .clkdm_name     = "wkupaon_clkdm",
351         .main_clk       = "dcan1_sys_clk_mux",
352         .flags          = HWMOD_CLKDM_NOAUTO,
353         .prcm = {
354                 .omap4 = {
355                         .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
356                         .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
357                         .modulemode   = MODULEMODE_SWCTRL,
358                 },
359         },
360 };
361
362 /* dcan2 */
363 static struct omap_hwmod dra7xx_dcan2_hwmod = {
364         .name           = "dcan2",
365         .class          = &dra7xx_dcan_hwmod_class,
366         .clkdm_name     = "l4per2_clkdm",
367         .main_clk       = "sys_clkin1",
368         .flags          = HWMOD_CLKDM_NOAUTO,
369         .prcm = {
370                 .omap4 = {
371                         .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
372                         .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
373                         .modulemode   = MODULEMODE_SWCTRL,
374                 },
375         },
376 };
377
378 /* pwmss  */
379 static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = {
380         .rev_offs       = 0x0,
381         .sysc_offs      = 0x4,
382         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
383                           SYSC_HAS_RESET_STATUS,
384         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
385         .sysc_fields    = &omap_hwmod_sysc_type2,
386 };
387
388 /*
389  * epwmss class
390  */
391 static struct omap_hwmod_class dra7xx_epwmss_hwmod_class = {
392         .name           = "epwmss",
393         .sysc           = &dra7xx_epwmss_sysc,
394 };
395
396 /* epwmss0 */
397 static struct omap_hwmod dra7xx_epwmss0_hwmod = {
398         .name           = "epwmss0",
399         .class          = &dra7xx_epwmss_hwmod_class,
400         .clkdm_name     = "l4per2_clkdm",
401         .main_clk       = "l4_root_clk_div",
402         .prcm           = {
403                 .omap4  = {
404                         .modulemode     = MODULEMODE_SWCTRL,
405                         .clkctrl_offs   = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,
406                         .context_offs   = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
407                 },
408         },
409 };
410
411 /* epwmss1 */
412 static struct omap_hwmod dra7xx_epwmss1_hwmod = {
413         .name           = "epwmss1",
414         .class          = &dra7xx_epwmss_hwmod_class,
415         .clkdm_name     = "l4per2_clkdm",
416         .main_clk       = "l4_root_clk_div",
417         .prcm           = {
418                 .omap4  = {
419                         .modulemode     = MODULEMODE_SWCTRL,
420                         .clkctrl_offs   = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,
421                         .context_offs   = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
422                 },
423         },
424 };
425
426 /* epwmss2 */
427 static struct omap_hwmod dra7xx_epwmss2_hwmod = {
428         .name           = "epwmss2",
429         .class          = &dra7xx_epwmss_hwmod_class,
430         .clkdm_name     = "l4per2_clkdm",
431         .main_clk       = "l4_root_clk_div",
432         .prcm           = {
433                 .omap4  = {
434                         .modulemode     = MODULEMODE_SWCTRL,
435                         .clkctrl_offs   = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,
436                         .context_offs   = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
437                 },
438         },
439 };
440
441 /*
442  * 'dma' class
443  *
444  */
445
446 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
447         .rev_offs       = 0x0000,
448         .sysc_offs      = 0x002c,
449         .syss_offs      = 0x0028,
450         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
451                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
452                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
453                            SYSS_HAS_RESET_STATUS),
454         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
455                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
456                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
457         .sysc_fields    = &omap_hwmod_sysc_type1,
458 };
459
460 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
461         .name   = "dma",
462         .sysc   = &dra7xx_dma_sysc,
463 };
464
465 /* dma dev_attr */
466 static struct omap_dma_dev_attr dma_dev_attr = {
467         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
468                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
469         .lch_count      = 32,
470 };
471
472 /* dma_system */
473 static struct omap_hwmod dra7xx_dma_system_hwmod = {
474         .name           = "dma_system",
475         .class          = &dra7xx_dma_hwmod_class,
476         .clkdm_name     = "dma_clkdm",
477         .main_clk       = "l3_iclk_div",
478         .prcm = {
479                 .omap4 = {
480                         .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
481                         .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
482                 },
483         },
484         .dev_attr       = &dma_dev_attr,
485 };
486
487 /*
488  * 'tpcc' class
489  *
490  */
491 static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
492         .name           = "tpcc",
493 };
494
495 static struct omap_hwmod dra7xx_tpcc_hwmod = {
496         .name           = "tpcc",
497         .class          = &dra7xx_tpcc_hwmod_class,
498         .clkdm_name     = "l3main1_clkdm",
499         .main_clk       = "l3_iclk_div",
500         .prcm           = {
501                 .omap4  = {
502                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET,
503                         .context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
504                 },
505         },
506 };
507
508 /*
509  * 'tptc' class
510  *
511  */
512 static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
513         .name           = "tptc",
514 };
515
516 /* tptc0 */
517 static struct omap_hwmod dra7xx_tptc0_hwmod = {
518         .name           = "tptc0",
519         .class          = &dra7xx_tptc_hwmod_class,
520         .clkdm_name     = "l3main1_clkdm",
521         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
522         .main_clk       = "l3_iclk_div",
523         .prcm           = {
524                 .omap4  = {
525                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET,
526                         .context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
527                         .modulemode   = MODULEMODE_HWCTRL,
528                 },
529         },
530 };
531
532 /* tptc1 */
533 static struct omap_hwmod dra7xx_tptc1_hwmod = {
534         .name           = "tptc1",
535         .class          = &dra7xx_tptc_hwmod_class,
536         .clkdm_name     = "l3main1_clkdm",
537         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
538         .main_clk       = "l3_iclk_div",
539         .prcm           = {
540                 .omap4  = {
541                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET,
542                         .context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
543                         .modulemode   = MODULEMODE_HWCTRL,
544                 },
545         },
546 };
547
548 /*
549  * 'dss' class
550  *
551  */
552
553 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
554         .rev_offs       = 0x0000,
555         .syss_offs      = 0x0014,
556         .sysc_flags     = SYSS_HAS_RESET_STATUS,
557 };
558
559 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
560         .name   = "dss",
561         .sysc   = &dra7xx_dss_sysc,
562         .reset  = omap_dss_reset,
563 };
564
565 /* dss */
566 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
567         { .role = "dss_clk", .clk = "dss_dss_clk" },
568         { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
569         { .role = "32khz_clk", .clk = "dss_32khz_clk" },
570         { .role = "video2_clk", .clk = "dss_video2_clk" },
571         { .role = "video1_clk", .clk = "dss_video1_clk" },
572         { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
573         { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
574 };
575
576 static struct omap_hwmod dra7xx_dss_hwmod = {
577         .name           = "dss_core",
578         .class          = &dra7xx_dss_hwmod_class,
579         .clkdm_name     = "dss_clkdm",
580         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
581         .main_clk       = "dss_dss_clk",
582         .prcm = {
583                 .omap4 = {
584                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
585                         .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
586                         .modulemode   = MODULEMODE_SWCTRL,
587                 },
588         },
589         .opt_clks       = dss_opt_clks,
590         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
591 };
592
593 /*
594  * 'dispc' class
595  * display controller
596  */
597
598 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
599         .rev_offs       = 0x0000,
600         .sysc_offs      = 0x0010,
601         .syss_offs      = 0x0014,
602         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
603                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
604                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
605                            SYSS_HAS_RESET_STATUS),
606         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
607                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
608         .sysc_fields    = &omap_hwmod_sysc_type1,
609 };
610
611 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
612         .name   = "dispc",
613         .sysc   = &dra7xx_dispc_sysc,
614 };
615
616 /* dss_dispc */
617 /* dss_dispc dev_attr */
618 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
619         .has_framedonetv_irq    = 1,
620         .manager_count          = 4,
621 };
622
623 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
624         .name           = "dss_dispc",
625         .class          = &dra7xx_dispc_hwmod_class,
626         .clkdm_name     = "dss_clkdm",
627         .main_clk       = "dss_dss_clk",
628         .prcm = {
629                 .omap4 = {
630                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
631                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
632                 },
633         },
634         .dev_attr       = &dss_dispc_dev_attr,
635         .parent_hwmod   = &dra7xx_dss_hwmod,
636 };
637
638 /*
639  * 'hdmi' class
640  * hdmi controller
641  */
642
643 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
644         .rev_offs       = 0x0000,
645         .sysc_offs      = 0x0010,
646         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
647                            SYSC_HAS_SOFTRESET),
648         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
649                            SIDLE_SMART_WKUP),
650         .sysc_fields    = &omap_hwmod_sysc_type2,
651 };
652
653 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
654         .name   = "hdmi",
655         .sysc   = &dra7xx_hdmi_sysc,
656 };
657
658 /* dss_hdmi */
659
660 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
661         { .role = "sys_clk", .clk = "dss_hdmi_clk" },
662 };
663
664 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
665         .name           = "dss_hdmi",
666         .class          = &dra7xx_hdmi_hwmod_class,
667         .clkdm_name     = "dss_clkdm",
668         .main_clk       = "dss_48mhz_clk",
669         .prcm = {
670                 .omap4 = {
671                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
672                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
673                 },
674         },
675         .opt_clks       = dss_hdmi_opt_clks,
676         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
677         .parent_hwmod   = &dra7xx_dss_hwmod,
678 };
679
680 /* AES (the 'P' (public) device) */
681 static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = {
682         .rev_offs       = 0x0080,
683         .sysc_offs      = 0x0084,
684         .syss_offs      = 0x0088,
685         .sysc_flags     = SYSS_HAS_RESET_STATUS,
686 };
687
688 static struct omap_hwmod_class dra7xx_aes_hwmod_class = {
689         .name   = "aes",
690         .sysc   = &dra7xx_aes_sysc,
691 };
692
693 /* AES1 */
694 static struct omap_hwmod dra7xx_aes1_hwmod = {
695         .name           = "aes1",
696         .class          = &dra7xx_aes_hwmod_class,
697         .clkdm_name     = "l4sec_clkdm",
698         .main_clk       = "l3_iclk_div",
699         .prcm = {
700                 .omap4 = {
701                         .clkctrl_offs = DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET,
702                         .context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET,
703                         .modulemode   = MODULEMODE_HWCTRL,
704                 },
705         },
706 };
707
708 /* AES2 */
709 static struct omap_hwmod dra7xx_aes2_hwmod = {
710         .name           = "aes2",
711         .class          = &dra7xx_aes_hwmod_class,
712         .clkdm_name     = "l4sec_clkdm",
713         .main_clk       = "l3_iclk_div",
714         .prcm = {
715                 .omap4 = {
716                         .clkctrl_offs = DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET,
717                         .context_offs = DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET,
718                         .modulemode   = MODULEMODE_HWCTRL,
719                 },
720         },
721 };
722
723 /* sha0 HIB2 (the 'P' (public) device) */
724 static struct omap_hwmod_class_sysconfig dra7xx_sha0_sysc = {
725         .rev_offs       = 0x100,
726         .sysc_offs      = 0x110,
727         .syss_offs      = 0x114,
728         .sysc_flags     = SYSS_HAS_RESET_STATUS,
729 };
730
731 static struct omap_hwmod_class dra7xx_sha0_hwmod_class = {
732         .name           = "sham",
733         .sysc           = &dra7xx_sha0_sysc,
734 };
735
736 struct omap_hwmod dra7xx_sha0_hwmod = {
737         .name           = "sham",
738         .class          = &dra7xx_sha0_hwmod_class,
739         .clkdm_name     = "l4sec_clkdm",
740         .main_clk       = "l3_iclk_div",
741         .prcm           = {
742                 .omap4 = {
743                         .clkctrl_offs = DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
744                         .context_offs = DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
745                         .modulemode   = MODULEMODE_HWCTRL,
746                 },
747         },
748 };
749
750 /*
751  * 'elm' class
752  *
753  */
754
755 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
756         .rev_offs       = 0x0000,
757         .sysc_offs      = 0x0010,
758         .syss_offs      = 0x0014,
759         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
760                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
761                            SYSS_HAS_RESET_STATUS),
762         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
763                            SIDLE_SMART_WKUP),
764         .sysc_fields    = &omap_hwmod_sysc_type1,
765 };
766
767 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
768         .name   = "elm",
769         .sysc   = &dra7xx_elm_sysc,
770 };
771
772 /* elm */
773
774 static struct omap_hwmod dra7xx_elm_hwmod = {
775         .name           = "elm",
776         .class          = &dra7xx_elm_hwmod_class,
777         .clkdm_name     = "l4per_clkdm",
778         .main_clk       = "l3_iclk_div",
779         .prcm = {
780                 .omap4 = {
781                         .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
782                         .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
783                 },
784         },
785 };
786
787 /*
788  * 'gpmc' class
789  *
790  */
791
792 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
793         .rev_offs       = 0x0000,
794         .sysc_offs      = 0x0010,
795         .syss_offs      = 0x0014,
796         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
797                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
798         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
799         .sysc_fields    = &omap_hwmod_sysc_type1,
800 };
801
802 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
803         .name   = "gpmc",
804         .sysc   = &dra7xx_gpmc_sysc,
805 };
806
807 /* gpmc */
808
809 static struct omap_hwmod dra7xx_gpmc_hwmod = {
810         .name           = "gpmc",
811         .class          = &dra7xx_gpmc_hwmod_class,
812         .clkdm_name     = "l3main1_clkdm",
813         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
814         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
815         .main_clk       = "l3_iclk_div",
816         .prcm = {
817                 .omap4 = {
818                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
819                         .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
820                         .modulemode   = MODULEMODE_HWCTRL,
821                 },
822         },
823 };
824
825 /*
826  * 'hdq1w' class
827  *
828  */
829
830 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
831         .rev_offs       = 0x0000,
832         .sysc_offs      = 0x0014,
833         .syss_offs      = 0x0018,
834         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
835                            SYSS_HAS_RESET_STATUS),
836         .sysc_fields    = &omap_hwmod_sysc_type1,
837 };
838
839 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
840         .name   = "hdq1w",
841         .sysc   = &dra7xx_hdq1w_sysc,
842 };
843
844 /* hdq1w */
845
846 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
847         .name           = "hdq1w",
848         .class          = &dra7xx_hdq1w_hwmod_class,
849         .clkdm_name     = "l4per_clkdm",
850         .flags          = HWMOD_INIT_NO_RESET,
851         .main_clk       = "func_12m_fclk",
852         .prcm = {
853                 .omap4 = {
854                         .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
855                         .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
856                         .modulemode   = MODULEMODE_SWCTRL,
857                 },
858         },
859 };
860
861 /*
862  * 'mailbox' class
863  *
864  */
865
866 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
867         .rev_offs       = 0x0000,
868         .sysc_offs      = 0x0010,
869         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
870                            SYSC_HAS_SOFTRESET),
871         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
872         .sysc_fields    = &omap_hwmod_sysc_type2,
873 };
874
875 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
876         .name   = "mailbox",
877         .sysc   = &dra7xx_mailbox_sysc,
878 };
879
880 /* mailbox1 */
881 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
882         .name           = "mailbox1",
883         .class          = &dra7xx_mailbox_hwmod_class,
884         .clkdm_name     = "l4cfg_clkdm",
885         .prcm = {
886                 .omap4 = {
887                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
888                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
889                 },
890         },
891 };
892
893 /* mailbox2 */
894 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
895         .name           = "mailbox2",
896         .class          = &dra7xx_mailbox_hwmod_class,
897         .clkdm_name     = "l4cfg_clkdm",
898         .prcm = {
899                 .omap4 = {
900                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
901                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
902                 },
903         },
904 };
905
906 /* mailbox3 */
907 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
908         .name           = "mailbox3",
909         .class          = &dra7xx_mailbox_hwmod_class,
910         .clkdm_name     = "l4cfg_clkdm",
911         .prcm = {
912                 .omap4 = {
913                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
914                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
915                 },
916         },
917 };
918
919 /* mailbox4 */
920 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
921         .name           = "mailbox4",
922         .class          = &dra7xx_mailbox_hwmod_class,
923         .clkdm_name     = "l4cfg_clkdm",
924         .prcm = {
925                 .omap4 = {
926                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
927                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
928                 },
929         },
930 };
931
932 /* mailbox5 */
933 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
934         .name           = "mailbox5",
935         .class          = &dra7xx_mailbox_hwmod_class,
936         .clkdm_name     = "l4cfg_clkdm",
937         .prcm = {
938                 .omap4 = {
939                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
940                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
941                 },
942         },
943 };
944
945 /* mailbox6 */
946 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
947         .name           = "mailbox6",
948         .class          = &dra7xx_mailbox_hwmod_class,
949         .clkdm_name     = "l4cfg_clkdm",
950         .prcm = {
951                 .omap4 = {
952                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
953                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
954                 },
955         },
956 };
957
958 /* mailbox7 */
959 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
960         .name           = "mailbox7",
961         .class          = &dra7xx_mailbox_hwmod_class,
962         .clkdm_name     = "l4cfg_clkdm",
963         .prcm = {
964                 .omap4 = {
965                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
966                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
967                 },
968         },
969 };
970
971 /* mailbox8 */
972 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
973         .name           = "mailbox8",
974         .class          = &dra7xx_mailbox_hwmod_class,
975         .clkdm_name     = "l4cfg_clkdm",
976         .prcm = {
977                 .omap4 = {
978                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
979                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
980                 },
981         },
982 };
983
984 /* mailbox9 */
985 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
986         .name           = "mailbox9",
987         .class          = &dra7xx_mailbox_hwmod_class,
988         .clkdm_name     = "l4cfg_clkdm",
989         .prcm = {
990                 .omap4 = {
991                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
992                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
993                 },
994         },
995 };
996
997 /* mailbox10 */
998 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
999         .name           = "mailbox10",
1000         .class          = &dra7xx_mailbox_hwmod_class,
1001         .clkdm_name     = "l4cfg_clkdm",
1002         .prcm = {
1003                 .omap4 = {
1004                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1005                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1006                 },
1007         },
1008 };
1009
1010 /* mailbox11 */
1011 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1012         .name           = "mailbox11",
1013         .class          = &dra7xx_mailbox_hwmod_class,
1014         .clkdm_name     = "l4cfg_clkdm",
1015         .prcm = {
1016                 .omap4 = {
1017                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1018                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1019                 },
1020         },
1021 };
1022
1023 /* mailbox12 */
1024 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1025         .name           = "mailbox12",
1026         .class          = &dra7xx_mailbox_hwmod_class,
1027         .clkdm_name     = "l4cfg_clkdm",
1028         .prcm = {
1029                 .omap4 = {
1030                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1031                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1032                 },
1033         },
1034 };
1035
1036 /* mailbox13 */
1037 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1038         .name           = "mailbox13",
1039         .class          = &dra7xx_mailbox_hwmod_class,
1040         .clkdm_name     = "l4cfg_clkdm",
1041         .prcm = {
1042                 .omap4 = {
1043                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1044                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1045                 },
1046         },
1047 };
1048
1049 /*
1050  * 'mcspi' class
1051  *
1052  */
1053
1054 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1055         .rev_offs       = 0x0000,
1056         .sysc_offs      = 0x0010,
1057         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1058                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1059         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1060                            SIDLE_SMART_WKUP),
1061         .sysc_fields    = &omap_hwmod_sysc_type2,
1062 };
1063
1064 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1065         .name   = "mcspi",
1066         .sysc   = &dra7xx_mcspi_sysc,
1067 };
1068
1069 /* mcspi1 */
1070 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1071         .name           = "mcspi1",
1072         .class          = &dra7xx_mcspi_hwmod_class,
1073         .clkdm_name     = "l4per_clkdm",
1074         .main_clk       = "func_48m_fclk",
1075         .prcm = {
1076                 .omap4 = {
1077                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1078                         .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1079                         .modulemode   = MODULEMODE_SWCTRL,
1080                 },
1081         },
1082 };
1083
1084 /* mcspi2 */
1085 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1086         .name           = "mcspi2",
1087         .class          = &dra7xx_mcspi_hwmod_class,
1088         .clkdm_name     = "l4per_clkdm",
1089         .main_clk       = "func_48m_fclk",
1090         .prcm = {
1091                 .omap4 = {
1092                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1093                         .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1094                         .modulemode   = MODULEMODE_SWCTRL,
1095                 },
1096         },
1097 };
1098
1099 /* mcspi3 */
1100 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1101         .name           = "mcspi3",
1102         .class          = &dra7xx_mcspi_hwmod_class,
1103         .clkdm_name     = "l4per_clkdm",
1104         .main_clk       = "func_48m_fclk",
1105         .prcm = {
1106                 .omap4 = {
1107                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1108                         .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1109                         .modulemode   = MODULEMODE_SWCTRL,
1110                 },
1111         },
1112 };
1113
1114 /* mcspi4 */
1115 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1116         .name           = "mcspi4",
1117         .class          = &dra7xx_mcspi_hwmod_class,
1118         .clkdm_name     = "l4per_clkdm",
1119         .main_clk       = "func_48m_fclk",
1120         .prcm = {
1121                 .omap4 = {
1122                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1123                         .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1124                         .modulemode   = MODULEMODE_SWCTRL,
1125                 },
1126         },
1127 };
1128
1129 /*
1130  * 'mcasp' class
1131  *
1132  */
1133 static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
1134         .rev_offs       = 0,
1135         .sysc_offs      = 0x0004,
1136         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1137         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1138         .sysc_fields    = &omap_hwmod_sysc_type3,
1139 };
1140
1141 static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
1142         .name   = "mcasp",
1143         .sysc   = &dra7xx_mcasp_sysc,
1144 };
1145
1146 /* mcasp1 */
1147 static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = {
1148         { .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" },
1149         { .role = "ahclkr", .clk = "mcasp1_ahclkr_mux" },
1150 };
1151
1152 static struct omap_hwmod dra7xx_mcasp1_hwmod = {
1153         .name           = "mcasp1",
1154         .class          = &dra7xx_mcasp_hwmod_class,
1155         .clkdm_name     = "ipu_clkdm",
1156         .main_clk       = "mcasp1_aux_gfclk_mux",
1157         .flags          = HWMOD_OPT_CLKS_NEEDED,
1158         .prcm = {
1159                 .omap4 = {
1160                         .clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
1161                         .context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
1162                         .modulemode   = MODULEMODE_SWCTRL,
1163                 },
1164         },
1165         .opt_clks       = mcasp1_opt_clks,
1166         .opt_clks_cnt   = ARRAY_SIZE(mcasp1_opt_clks),
1167 };
1168
1169 /* mcasp2 */
1170 static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = {
1171         { .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" },
1172         { .role = "ahclkr", .clk = "mcasp2_ahclkr_mux" },
1173 };
1174
1175 static struct omap_hwmod dra7xx_mcasp2_hwmod = {
1176         .name           = "mcasp2",
1177         .class          = &dra7xx_mcasp_hwmod_class,
1178         .clkdm_name     = "l4per2_clkdm",
1179         .main_clk       = "mcasp2_aux_gfclk_mux",
1180         .flags          = HWMOD_OPT_CLKS_NEEDED,
1181         .prcm = {
1182                 .omap4 = {
1183                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
1184                         .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
1185                         .modulemode   = MODULEMODE_SWCTRL,
1186                 },
1187         },
1188         .opt_clks       = mcasp2_opt_clks,
1189         .opt_clks_cnt   = ARRAY_SIZE(mcasp2_opt_clks),
1190 };
1191
1192 /* mcasp3 */
1193 static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = {
1194         { .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" },
1195 };
1196
1197 static struct omap_hwmod dra7xx_mcasp3_hwmod = {
1198         .name           = "mcasp3",
1199         .class          = &dra7xx_mcasp_hwmod_class,
1200         .clkdm_name     = "l4per2_clkdm",
1201         .main_clk       = "mcasp3_aux_gfclk_mux",
1202         .flags          = HWMOD_OPT_CLKS_NEEDED,
1203         .prcm = {
1204                 .omap4 = {
1205                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
1206                         .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
1207                         .modulemode   = MODULEMODE_SWCTRL,
1208                 },
1209         },
1210         .opt_clks       = mcasp3_opt_clks,
1211         .opt_clks_cnt   = ARRAY_SIZE(mcasp3_opt_clks),
1212 };
1213
1214 /* mcasp4 */
1215 static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = {
1216         { .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" },
1217 };
1218
1219 static struct omap_hwmod dra7xx_mcasp4_hwmod = {
1220         .name           = "mcasp4",
1221         .class          = &dra7xx_mcasp_hwmod_class,
1222         .clkdm_name     = "l4per2_clkdm",
1223         .main_clk       = "mcasp4_aux_gfclk_mux",
1224         .flags          = HWMOD_OPT_CLKS_NEEDED,
1225         .prcm = {
1226                 .omap4 = {
1227                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
1228                         .context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
1229                         .modulemode   = MODULEMODE_SWCTRL,
1230                 },
1231         },
1232         .opt_clks       = mcasp4_opt_clks,
1233         .opt_clks_cnt   = ARRAY_SIZE(mcasp4_opt_clks),
1234 };
1235
1236 /* mcasp5 */
1237 static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = {
1238         { .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" },
1239 };
1240
1241 static struct omap_hwmod dra7xx_mcasp5_hwmod = {
1242         .name           = "mcasp5",
1243         .class          = &dra7xx_mcasp_hwmod_class,
1244         .clkdm_name     = "l4per2_clkdm",
1245         .main_clk       = "mcasp5_aux_gfclk_mux",
1246         .flags          = HWMOD_OPT_CLKS_NEEDED,
1247         .prcm = {
1248                 .omap4 = {
1249                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
1250                         .context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
1251                         .modulemode   = MODULEMODE_SWCTRL,
1252                 },
1253         },
1254         .opt_clks       = mcasp5_opt_clks,
1255         .opt_clks_cnt   = ARRAY_SIZE(mcasp5_opt_clks),
1256 };
1257
1258 /* mcasp6 */
1259 static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = {
1260         { .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" },
1261 };
1262
1263 static struct omap_hwmod dra7xx_mcasp6_hwmod = {
1264         .name           = "mcasp6",
1265         .class          = &dra7xx_mcasp_hwmod_class,
1266         .clkdm_name     = "l4per2_clkdm",
1267         .main_clk       = "mcasp6_aux_gfclk_mux",
1268         .flags          = HWMOD_OPT_CLKS_NEEDED,
1269         .prcm = {
1270                 .omap4 = {
1271                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
1272                         .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
1273                         .modulemode   = MODULEMODE_SWCTRL,
1274                 },
1275         },
1276         .opt_clks       = mcasp6_opt_clks,
1277         .opt_clks_cnt   = ARRAY_SIZE(mcasp6_opt_clks),
1278 };
1279
1280 /* mcasp7 */
1281 static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = {
1282         { .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" },
1283 };
1284
1285 static struct omap_hwmod dra7xx_mcasp7_hwmod = {
1286         .name           = "mcasp7",
1287         .class          = &dra7xx_mcasp_hwmod_class,
1288         .clkdm_name     = "l4per2_clkdm",
1289         .main_clk       = "mcasp7_aux_gfclk_mux",
1290         .flags          = HWMOD_OPT_CLKS_NEEDED,
1291         .prcm = {
1292                 .omap4 = {
1293                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
1294                         .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
1295                         .modulemode   = MODULEMODE_SWCTRL,
1296                 },
1297         },
1298         .opt_clks       = mcasp7_opt_clks,
1299         .opt_clks_cnt   = ARRAY_SIZE(mcasp7_opt_clks),
1300 };
1301
1302 /* mcasp8 */
1303 static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = {
1304         { .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" },
1305 };
1306
1307 static struct omap_hwmod dra7xx_mcasp8_hwmod = {
1308         .name           = "mcasp8",
1309         .class          = &dra7xx_mcasp_hwmod_class,
1310         .clkdm_name     = "l4per2_clkdm",
1311         .main_clk       = "mcasp8_aux_gfclk_mux",
1312         .flags          = HWMOD_OPT_CLKS_NEEDED,
1313         .prcm = {
1314                 .omap4 = {
1315                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
1316                         .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
1317                         .modulemode   = MODULEMODE_SWCTRL,
1318                 },
1319         },
1320         .opt_clks       = mcasp8_opt_clks,
1321         .opt_clks_cnt   = ARRAY_SIZE(mcasp8_opt_clks),
1322 };
1323
1324 /*
1325  * 'mpu' class
1326  *
1327  */
1328
1329 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1330         .name   = "mpu",
1331 };
1332
1333 /* mpu */
1334 static struct omap_hwmod dra7xx_mpu_hwmod = {
1335         .name           = "mpu",
1336         .class          = &dra7xx_mpu_hwmod_class,
1337         .clkdm_name     = "mpu_clkdm",
1338         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1339         .main_clk       = "dpll_mpu_m2_ck",
1340         .prcm = {
1341                 .omap4 = {
1342                         .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1343                         .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1344                 },
1345         },
1346 };
1347
1348 /*
1349  * 'ocp2scp' class
1350  *
1351  */
1352
1353 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1354         .rev_offs       = 0x0000,
1355         .sysc_offs      = 0x0010,
1356         .syss_offs      = 0x0014,
1357         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1358                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1359         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1360         .sysc_fields    = &omap_hwmod_sysc_type1,
1361 };
1362
1363 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1364         .name   = "ocp2scp",
1365         .sysc   = &dra7xx_ocp2scp_sysc,
1366 };
1367
1368 /* ocp2scp1 */
1369 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1370         .name           = "ocp2scp1",
1371         .class          = &dra7xx_ocp2scp_hwmod_class,
1372         .clkdm_name     = "l3init_clkdm",
1373         .main_clk       = "l4_root_clk_div",
1374         .prcm = {
1375                 .omap4 = {
1376                         .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1377                         .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1378                         .modulemode   = MODULEMODE_HWCTRL,
1379                 },
1380         },
1381 };
1382
1383 /* ocp2scp3 */
1384 static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1385         .name           = "ocp2scp3",
1386         .class          = &dra7xx_ocp2scp_hwmod_class,
1387         .clkdm_name     = "l3init_clkdm",
1388         .main_clk       = "l4_root_clk_div",
1389         .prcm = {
1390                 .omap4 = {
1391                         .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1392                         .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1393                         .modulemode   = MODULEMODE_HWCTRL,
1394                 },
1395         },
1396 };
1397
1398 /*
1399  * 'PCIE' class
1400  *
1401  */
1402
1403 /*
1404  * As noted in documentation for _reset() in omap_hwmod.c, the stock reset
1405  * functionality of OMAP HWMOD layer does not deassert the hardreset lines
1406  * associated with an IP automatically leaving the driver to handle that
1407  * by itself. This does not work for PCIeSS which needs the reset lines
1408  * deasserted for the driver to start accessing registers.
1409  *
1410  * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
1411  * lines after asserting them.
1412  */
1413 int dra7xx_pciess_reset(struct omap_hwmod *oh)
1414 {
1415         int i;
1416
1417         for (i = 0; i < oh->rst_lines_cnt; i++) {
1418                 omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name);
1419                 omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name);
1420         }
1421
1422         return 0;
1423 }
1424
1425 static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
1426         .name   = "pcie",
1427         .reset  = dra7xx_pciess_reset,
1428 };
1429
1430 /* pcie1 */
1431 static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
1432         { .name = "pcie", .rst_shift = 0 },
1433 };
1434
1435 static struct omap_hwmod dra7xx_pciess1_hwmod = {
1436         .name           = "pcie1",
1437         .class          = &dra7xx_pciess_hwmod_class,
1438         .clkdm_name     = "pcie_clkdm",
1439         .rst_lines      = dra7xx_pciess1_resets,
1440         .rst_lines_cnt  = ARRAY_SIZE(dra7xx_pciess1_resets),
1441         .main_clk       = "l4_root_clk_div",
1442         .prcm = {
1443                 .omap4 = {
1444                         .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1445                         .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1446                         .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1447                         .modulemode   = MODULEMODE_SWCTRL,
1448                 },
1449         },
1450 };
1451
1452 /* pcie2 */
1453 static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
1454         { .name = "pcie", .rst_shift = 1 },
1455 };
1456
1457 /* pcie2 */
1458 static struct omap_hwmod dra7xx_pciess2_hwmod = {
1459         .name           = "pcie2",
1460         .class          = &dra7xx_pciess_hwmod_class,
1461         .clkdm_name     = "pcie_clkdm",
1462         .rst_lines      = dra7xx_pciess2_resets,
1463         .rst_lines_cnt  = ARRAY_SIZE(dra7xx_pciess2_resets),
1464         .main_clk       = "l4_root_clk_div",
1465         .prcm = {
1466                 .omap4 = {
1467                         .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1468                         .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1469                         .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1470                         .modulemode   = MODULEMODE_SWCTRL,
1471                 },
1472         },
1473 };
1474
1475 /*
1476  * 'qspi' class
1477  *
1478  */
1479
1480 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1481         .rev_offs       = 0,
1482         .sysc_offs      = 0x0010,
1483         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1484         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1485                            SIDLE_SMART_WKUP),
1486         .sysc_fields    = &omap_hwmod_sysc_type2,
1487 };
1488
1489 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1490         .name   = "qspi",
1491         .sysc   = &dra7xx_qspi_sysc,
1492 };
1493
1494 /* qspi */
1495 static struct omap_hwmod dra7xx_qspi_hwmod = {
1496         .name           = "qspi",
1497         .class          = &dra7xx_qspi_hwmod_class,
1498         .clkdm_name     = "l4per2_clkdm",
1499         .main_clk       = "qspi_gfclk_div",
1500         .prcm = {
1501                 .omap4 = {
1502                         .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1503                         .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1504                         .modulemode   = MODULEMODE_SWCTRL,
1505                 },
1506         },
1507 };
1508
1509 /*
1510  * 'rtcss' class
1511  *
1512  */
1513 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1514         .rev_offs       = 0x0074,
1515         .sysc_offs      = 0x0078,
1516         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1517         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1518                            SIDLE_SMART_WKUP),
1519         .sysc_fields    = &omap_hwmod_sysc_type3,
1520 };
1521
1522 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1523         .name   = "rtcss",
1524         .sysc   = &dra7xx_rtcss_sysc,
1525         .unlock = &omap_hwmod_rtc_unlock,
1526         .lock   = &omap_hwmod_rtc_lock,
1527 };
1528
1529 /* rtcss */
1530 static struct omap_hwmod dra7xx_rtcss_hwmod = {
1531         .name           = "rtcss",
1532         .class          = &dra7xx_rtcss_hwmod_class,
1533         .clkdm_name     = "rtc_clkdm",
1534         .main_clk       = "sys_32k_ck",
1535         .prcm = {
1536                 .omap4 = {
1537                         .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
1538                         .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
1539                         .modulemode   = MODULEMODE_SWCTRL,
1540                 },
1541         },
1542 };
1543
1544 /*
1545  * 'sata' class
1546  *
1547  */
1548
1549 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1550         .rev_offs       = 0x00fc,
1551         .sysc_offs      = 0x0000,
1552         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1553         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1554                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1555                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1556         .sysc_fields    = &omap_hwmod_sysc_type2,
1557 };
1558
1559 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1560         .name   = "sata",
1561         .sysc   = &dra7xx_sata_sysc,
1562 };
1563
1564 /* sata */
1565
1566 static struct omap_hwmod dra7xx_sata_hwmod = {
1567         .name           = "sata",
1568         .class          = &dra7xx_sata_hwmod_class,
1569         .clkdm_name     = "l3init_clkdm",
1570         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1571         .main_clk       = "func_48m_fclk",
1572         .mpu_rt_idx     = 1,
1573         .prcm = {
1574                 .omap4 = {
1575                         .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1576                         .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1577                         .modulemode   = MODULEMODE_SWCTRL,
1578                 },
1579         },
1580 };
1581
1582 /*
1583  * 'smartreflex' class
1584  *
1585  */
1586
1587 /* The IP is not compliant to type1 / type2 scheme */
1588 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
1589         .rev_offs       = -ENODEV,
1590         .sysc_offs      = 0x0038,
1591         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1592         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1593                            SIDLE_SMART_WKUP),
1594         .sysc_fields    = &omap36xx_sr_sysc_fields,
1595 };
1596
1597 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
1598         .name   = "smartreflex",
1599         .sysc   = &dra7xx_smartreflex_sysc,
1600 };
1601
1602 /* smartreflex_core */
1603 /* smartreflex_core dev_attr */
1604 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1605         .sensor_voltdm_name     = "core",
1606 };
1607
1608 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
1609         .name           = "smartreflex_core",
1610         .class          = &dra7xx_smartreflex_hwmod_class,
1611         .clkdm_name     = "coreaon_clkdm",
1612         .main_clk       = "wkupaon_iclk_mux",
1613         .prcm = {
1614                 .omap4 = {
1615                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
1616                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
1617                         .modulemode   = MODULEMODE_SWCTRL,
1618                 },
1619         },
1620         .dev_attr       = &smartreflex_core_dev_attr,
1621 };
1622
1623 /* smartreflex_mpu */
1624 /* smartreflex_mpu dev_attr */
1625 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1626         .sensor_voltdm_name     = "mpu",
1627 };
1628
1629 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
1630         .name           = "smartreflex_mpu",
1631         .class          = &dra7xx_smartreflex_hwmod_class,
1632         .clkdm_name     = "coreaon_clkdm",
1633         .main_clk       = "wkupaon_iclk_mux",
1634         .prcm = {
1635                 .omap4 = {
1636                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
1637                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
1638                         .modulemode   = MODULEMODE_SWCTRL,
1639                 },
1640         },
1641         .dev_attr       = &smartreflex_mpu_dev_attr,
1642 };
1643
1644 /*
1645  * 'spinlock' class
1646  *
1647  */
1648
1649 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
1650         .rev_offs       = 0x0000,
1651         .sysc_offs      = 0x0010,
1652         .syss_offs      = 0x0014,
1653         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1654                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1655                            SYSS_HAS_RESET_STATUS),
1656         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1657         .sysc_fields    = &omap_hwmod_sysc_type1,
1658 };
1659
1660 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
1661         .name   = "spinlock",
1662         .sysc   = &dra7xx_spinlock_sysc,
1663 };
1664
1665 /* spinlock */
1666 static struct omap_hwmod dra7xx_spinlock_hwmod = {
1667         .name           = "spinlock",
1668         .class          = &dra7xx_spinlock_hwmod_class,
1669         .clkdm_name     = "l4cfg_clkdm",
1670         .main_clk       = "l3_iclk_div",
1671         .prcm = {
1672                 .omap4 = {
1673                         .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1674                         .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1675                 },
1676         },
1677 };
1678
1679 /*
1680  * 'timer' class
1681  *
1682  * This class contains several variants: ['timer_1ms', 'timer_secure',
1683  * 'timer']
1684  */
1685
1686 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
1687         .rev_offs       = 0x0000,
1688         .sysc_offs      = 0x0010,
1689         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1690                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1691         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1692                            SIDLE_SMART_WKUP),
1693         .sysc_fields    = &omap_hwmod_sysc_type2,
1694 };
1695
1696 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
1697         .name   = "timer",
1698         .sysc   = &dra7xx_timer_1ms_sysc,
1699 };
1700
1701 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
1702         .rev_offs       = 0x0000,
1703         .sysc_offs      = 0x0010,
1704         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1705                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1706         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1707                            SIDLE_SMART_WKUP),
1708         .sysc_fields    = &omap_hwmod_sysc_type2,
1709 };
1710
1711 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
1712         .name   = "timer",
1713         .sysc   = &dra7xx_timer_sysc,
1714 };
1715
1716 /* timer1 */
1717 static struct omap_hwmod dra7xx_timer1_hwmod = {
1718         .name           = "timer1",
1719         .class          = &dra7xx_timer_1ms_hwmod_class,
1720         .clkdm_name     = "wkupaon_clkdm",
1721         .main_clk       = "timer1_gfclk_mux",
1722         .prcm = {
1723                 .omap4 = {
1724                         .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1725                         .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1726                         .modulemode   = MODULEMODE_SWCTRL,
1727                 },
1728         },
1729 };
1730
1731 /* timer2 */
1732 static struct omap_hwmod dra7xx_timer2_hwmod = {
1733         .name           = "timer2",
1734         .class          = &dra7xx_timer_1ms_hwmod_class,
1735         .clkdm_name     = "l4per_clkdm",
1736         .main_clk       = "timer2_gfclk_mux",
1737         .prcm = {
1738                 .omap4 = {
1739                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1740                         .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1741                         .modulemode   = MODULEMODE_SWCTRL,
1742                 },
1743         },
1744 };
1745
1746 /* timer3 */
1747 static struct omap_hwmod dra7xx_timer3_hwmod = {
1748         .name           = "timer3",
1749         .class          = &dra7xx_timer_hwmod_class,
1750         .clkdm_name     = "l4per_clkdm",
1751         .main_clk       = "timer3_gfclk_mux",
1752         .prcm = {
1753                 .omap4 = {
1754                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1755                         .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1756                         .modulemode   = MODULEMODE_SWCTRL,
1757                 },
1758         },
1759 };
1760
1761 /* timer4 */
1762 static struct omap_hwmod dra7xx_timer4_hwmod = {
1763         .name           = "timer4",
1764         .class          = &dra7xx_timer_hwmod_class,
1765         .clkdm_name     = "l4per_clkdm",
1766         .main_clk       = "timer4_gfclk_mux",
1767         .prcm = {
1768                 .omap4 = {
1769                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1770                         .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1771                         .modulemode   = MODULEMODE_SWCTRL,
1772                 },
1773         },
1774 };
1775
1776 /* timer5 */
1777 static struct omap_hwmod dra7xx_timer5_hwmod = {
1778         .name           = "timer5",
1779         .class          = &dra7xx_timer_hwmod_class,
1780         .clkdm_name     = "ipu_clkdm",
1781         .main_clk       = "timer5_gfclk_mux",
1782         .prcm = {
1783                 .omap4 = {
1784                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
1785                         .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
1786                         .modulemode   = MODULEMODE_SWCTRL,
1787                 },
1788         },
1789 };
1790
1791 /* timer6 */
1792 static struct omap_hwmod dra7xx_timer6_hwmod = {
1793         .name           = "timer6",
1794         .class          = &dra7xx_timer_hwmod_class,
1795         .clkdm_name     = "ipu_clkdm",
1796         .main_clk       = "timer6_gfclk_mux",
1797         .prcm = {
1798                 .omap4 = {
1799                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
1800                         .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
1801                         .modulemode   = MODULEMODE_SWCTRL,
1802                 },
1803         },
1804 };
1805
1806 /* timer7 */
1807 static struct omap_hwmod dra7xx_timer7_hwmod = {
1808         .name           = "timer7",
1809         .class          = &dra7xx_timer_hwmod_class,
1810         .clkdm_name     = "ipu_clkdm",
1811         .main_clk       = "timer7_gfclk_mux",
1812         .prcm = {
1813                 .omap4 = {
1814                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
1815                         .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
1816                         .modulemode   = MODULEMODE_SWCTRL,
1817                 },
1818         },
1819 };
1820
1821 /* timer8 */
1822 static struct omap_hwmod dra7xx_timer8_hwmod = {
1823         .name           = "timer8",
1824         .class          = &dra7xx_timer_hwmod_class,
1825         .clkdm_name     = "ipu_clkdm",
1826         .main_clk       = "timer8_gfclk_mux",
1827         .prcm = {
1828                 .omap4 = {
1829                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
1830                         .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
1831                         .modulemode   = MODULEMODE_SWCTRL,
1832                 },
1833         },
1834 };
1835
1836 /* timer9 */
1837 static struct omap_hwmod dra7xx_timer9_hwmod = {
1838         .name           = "timer9",
1839         .class          = &dra7xx_timer_hwmod_class,
1840         .clkdm_name     = "l4per_clkdm",
1841         .main_clk       = "timer9_gfclk_mux",
1842         .prcm = {
1843                 .omap4 = {
1844                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1845                         .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1846                         .modulemode   = MODULEMODE_SWCTRL,
1847                 },
1848         },
1849 };
1850
1851 /* timer10 */
1852 static struct omap_hwmod dra7xx_timer10_hwmod = {
1853         .name           = "timer10",
1854         .class          = &dra7xx_timer_1ms_hwmod_class,
1855         .clkdm_name     = "l4per_clkdm",
1856         .main_clk       = "timer10_gfclk_mux",
1857         .prcm = {
1858                 .omap4 = {
1859                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1860                         .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1861                         .modulemode   = MODULEMODE_SWCTRL,
1862                 },
1863         },
1864 };
1865
1866 /* timer11 */
1867 static struct omap_hwmod dra7xx_timer11_hwmod = {
1868         .name           = "timer11",
1869         .class          = &dra7xx_timer_hwmod_class,
1870         .clkdm_name     = "l4per_clkdm",
1871         .main_clk       = "timer11_gfclk_mux",
1872         .prcm = {
1873                 .omap4 = {
1874                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1875                         .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1876                         .modulemode   = MODULEMODE_SWCTRL,
1877                 },
1878         },
1879 };
1880
1881 /* timer12 */
1882 static struct omap_hwmod dra7xx_timer12_hwmod = {
1883         .name           = "timer12",
1884         .class          = &dra7xx_timer_hwmod_class,
1885         .clkdm_name     = "wkupaon_clkdm",
1886         .main_clk       = "secure_32k_clk_src_ck",
1887         .prcm = {
1888                 .omap4 = {
1889                         .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET,
1890                         .context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET,
1891                 },
1892         },
1893 };
1894
1895 /* timer13 */
1896 static struct omap_hwmod dra7xx_timer13_hwmod = {
1897         .name           = "timer13",
1898         .class          = &dra7xx_timer_hwmod_class,
1899         .clkdm_name     = "l4per3_clkdm",
1900         .main_clk       = "timer13_gfclk_mux",
1901         .prcm = {
1902                 .omap4 = {
1903                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
1904                         .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
1905                         .modulemode   = MODULEMODE_SWCTRL,
1906                 },
1907         },
1908 };
1909
1910 /* timer14 */
1911 static struct omap_hwmod dra7xx_timer14_hwmod = {
1912         .name           = "timer14",
1913         .class          = &dra7xx_timer_hwmod_class,
1914         .clkdm_name     = "l4per3_clkdm",
1915         .main_clk       = "timer14_gfclk_mux",
1916         .prcm = {
1917                 .omap4 = {
1918                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
1919                         .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
1920                         .modulemode   = MODULEMODE_SWCTRL,
1921                 },
1922         },
1923 };
1924
1925 /* timer15 */
1926 static struct omap_hwmod dra7xx_timer15_hwmod = {
1927         .name           = "timer15",
1928         .class          = &dra7xx_timer_hwmod_class,
1929         .clkdm_name     = "l4per3_clkdm",
1930         .main_clk       = "timer15_gfclk_mux",
1931         .prcm = {
1932                 .omap4 = {
1933                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
1934                         .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
1935                         .modulemode   = MODULEMODE_SWCTRL,
1936                 },
1937         },
1938 };
1939
1940 /* timer16 */
1941 static struct omap_hwmod dra7xx_timer16_hwmod = {
1942         .name           = "timer16",
1943         .class          = &dra7xx_timer_hwmod_class,
1944         .clkdm_name     = "l4per3_clkdm",
1945         .main_clk       = "timer16_gfclk_mux",
1946         .prcm = {
1947                 .omap4 = {
1948                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
1949                         .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
1950                         .modulemode   = MODULEMODE_SWCTRL,
1951                 },
1952         },
1953 };
1954
1955 /* DES (the 'P' (public) device) */
1956 static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = {
1957         .rev_offs       = 0x0030,
1958         .sysc_offs      = 0x0034,
1959         .syss_offs      = 0x0038,
1960         .sysc_flags     = SYSS_HAS_RESET_STATUS,
1961 };
1962
1963 static struct omap_hwmod_class dra7xx_des_hwmod_class = {
1964         .name   = "des",
1965         .sysc   = &dra7xx_des_sysc,
1966 };
1967
1968 /* DES */
1969 static struct omap_hwmod dra7xx_des_hwmod = {
1970         .name           = "des",
1971         .class          = &dra7xx_des_hwmod_class,
1972         .clkdm_name     = "l4sec_clkdm",
1973         .main_clk       = "l3_iclk_div",
1974         .prcm = {
1975                 .omap4 = {
1976                         .clkctrl_offs = DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
1977                         .context_offs = DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
1978                         .modulemode   = MODULEMODE_HWCTRL,
1979                 },
1980         },
1981 };
1982
1983 /* rng */
1984 static struct omap_hwmod_class_sysconfig dra7xx_rng_sysc = {
1985         .rev_offs       = 0x1fe0,
1986         .sysc_offs      = 0x1fe4,
1987         .sysc_flags     = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
1988         .idlemodes      = SIDLE_FORCE | SIDLE_NO,
1989         .sysc_fields    = &omap_hwmod_sysc_type1,
1990 };
1991
1992 static struct omap_hwmod_class dra7xx_rng_hwmod_class = {
1993         .name           = "rng",
1994         .sysc           = &dra7xx_rng_sysc,
1995 };
1996
1997 static struct omap_hwmod dra7xx_rng_hwmod = {
1998         .name           = "rng",
1999         .class          = &dra7xx_rng_hwmod_class,
2000         .flags          = HWMOD_SWSUP_SIDLE,
2001         .clkdm_name     = "l4sec_clkdm",
2002         .prcm = {
2003                 .omap4 = {
2004                         .clkctrl_offs = DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET,
2005                         .context_offs = DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET,
2006                         .modulemode   = MODULEMODE_HWCTRL,
2007                 },
2008         },
2009 };
2010
2011 /*
2012  * 'usb_otg_ss' class
2013  *
2014  */
2015
2016 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
2017         .rev_offs       = 0x0000,
2018         .sysc_offs      = 0x0010,
2019         .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
2020                            SYSC_HAS_SIDLEMODE),
2021         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2022                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2023                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2024         .sysc_fields    = &omap_hwmod_sysc_type2,
2025 };
2026
2027 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2028         .name   = "usb_otg_ss",
2029         .sysc   = &dra7xx_usb_otg_ss_sysc,
2030 };
2031
2032 /* usb_otg_ss1 */
2033 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2034         { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2035 };
2036
2037 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2038         .name           = "usb_otg_ss1",
2039         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2040         .clkdm_name     = "l3init_clkdm",
2041         .main_clk       = "dpll_core_h13x2_ck",
2042         .flags          = HWMOD_CLKDM_NOAUTO,
2043         .prcm = {
2044                 .omap4 = {
2045                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2046                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2047                         .modulemode   = MODULEMODE_HWCTRL,
2048                 },
2049         },
2050         .opt_clks       = usb_otg_ss1_opt_clks,
2051         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2052 };
2053
2054 /* usb_otg_ss2 */
2055 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2056         { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2057 };
2058
2059 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2060         .name           = "usb_otg_ss2",
2061         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2062         .clkdm_name     = "l3init_clkdm",
2063         .main_clk       = "dpll_core_h13x2_ck",
2064         .flags          = HWMOD_CLKDM_NOAUTO,
2065         .prcm = {
2066                 .omap4 = {
2067                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2068                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2069                         .modulemode   = MODULEMODE_HWCTRL,
2070                 },
2071         },
2072         .opt_clks       = usb_otg_ss2_opt_clks,
2073         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2074 };
2075
2076 /* usb_otg_ss3 */
2077 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2078         .name           = "usb_otg_ss3",
2079         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2080         .clkdm_name     = "l3init_clkdm",
2081         .main_clk       = "dpll_core_h13x2_ck",
2082         .prcm = {
2083                 .omap4 = {
2084                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
2085                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2086                         .modulemode   = MODULEMODE_HWCTRL,
2087                 },
2088         },
2089 };
2090
2091 /* usb_otg_ss4 */
2092 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
2093         .name           = "usb_otg_ss4",
2094         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2095         .clkdm_name     = "l3init_clkdm",
2096         .main_clk       = "dpll_core_h13x2_ck",
2097         .prcm = {
2098                 .omap4 = {
2099                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
2100                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2101                         .modulemode   = MODULEMODE_HWCTRL,
2102                 },
2103         },
2104 };
2105
2106 /*
2107  * 'vcp' class
2108  *
2109  */
2110
2111 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
2112         .name   = "vcp",
2113 };
2114
2115 /* vcp1 */
2116 static struct omap_hwmod dra7xx_vcp1_hwmod = {
2117         .name           = "vcp1",
2118         .class          = &dra7xx_vcp_hwmod_class,
2119         .clkdm_name     = "l3main1_clkdm",
2120         .main_clk       = "l3_iclk_div",
2121         .prcm = {
2122                 .omap4 = {
2123                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
2124                         .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2125                 },
2126         },
2127 };
2128
2129 /* vcp2 */
2130 static struct omap_hwmod dra7xx_vcp2_hwmod = {
2131         .name           = "vcp2",
2132         .class          = &dra7xx_vcp_hwmod_class,
2133         .clkdm_name     = "l3main1_clkdm",
2134         .main_clk       = "l3_iclk_div",
2135         .prcm = {
2136                 .omap4 = {
2137                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
2138                         .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2139                 },
2140         },
2141 };
2142
2143 /*
2144  * 'wd_timer' class
2145  *
2146  */
2147
2148 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
2149         .rev_offs       = 0x0000,
2150         .sysc_offs      = 0x0010,
2151         .syss_offs      = 0x0014,
2152         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2153                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2154         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2155                            SIDLE_SMART_WKUP),
2156         .sysc_fields    = &omap_hwmod_sysc_type1,
2157 };
2158
2159 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
2160         .name           = "wd_timer",
2161         .sysc           = &dra7xx_wd_timer_sysc,
2162         .pre_shutdown   = &omap2_wd_timer_disable,
2163         .reset          = &omap2_wd_timer_reset,
2164 };
2165
2166 /* wd_timer2 */
2167 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
2168         .name           = "wd_timer2",
2169         .class          = &dra7xx_wd_timer_hwmod_class,
2170         .clkdm_name     = "wkupaon_clkdm",
2171         .main_clk       = "sys_32k_ck",
2172         .prcm = {
2173                 .omap4 = {
2174                         .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2175                         .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2176                         .modulemode   = MODULEMODE_SWCTRL,
2177                 },
2178         },
2179 };
2180
2181
2182 /*
2183  * Interfaces
2184  */
2185
2186 /* l3_main_1 -> dmm */
2187 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
2188         .master         = &dra7xx_l3_main_1_hwmod,
2189         .slave          = &dra7xx_dmm_hwmod,
2190         .clk            = "l3_iclk_div",
2191         .user           = OCP_USER_SDMA,
2192 };
2193
2194 /* l3_main_2 -> l3_instr */
2195 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
2196         .master         = &dra7xx_l3_main_2_hwmod,
2197         .slave          = &dra7xx_l3_instr_hwmod,
2198         .clk            = "l3_iclk_div",
2199         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2200 };
2201
2202 /* l4_cfg -> l3_main_1 */
2203 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
2204         .master         = &dra7xx_l4_cfg_hwmod,
2205         .slave          = &dra7xx_l3_main_1_hwmod,
2206         .clk            = "l3_iclk_div",
2207         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2208 };
2209
2210 /* mpu -> l3_main_1 */
2211 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
2212         .master         = &dra7xx_mpu_hwmod,
2213         .slave          = &dra7xx_l3_main_1_hwmod,
2214         .clk            = "l3_iclk_div",
2215         .user           = OCP_USER_MPU,
2216 };
2217
2218 /* l3_main_1 -> l3_main_2 */
2219 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2220         .master         = &dra7xx_l3_main_1_hwmod,
2221         .slave          = &dra7xx_l3_main_2_hwmod,
2222         .clk            = "l3_iclk_div",
2223         .user           = OCP_USER_MPU,
2224 };
2225
2226 /* l4_cfg -> l3_main_2 */
2227 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2228         .master         = &dra7xx_l4_cfg_hwmod,
2229         .slave          = &dra7xx_l3_main_2_hwmod,
2230         .clk            = "l3_iclk_div",
2231         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2232 };
2233
2234 /* l3_main_1 -> l4_cfg */
2235 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2236         .master         = &dra7xx_l3_main_1_hwmod,
2237         .slave          = &dra7xx_l4_cfg_hwmod,
2238         .clk            = "l3_iclk_div",
2239         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2240 };
2241
2242 /* l3_main_1 -> l4_per1 */
2243 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2244         .master         = &dra7xx_l3_main_1_hwmod,
2245         .slave          = &dra7xx_l4_per1_hwmod,
2246         .clk            = "l3_iclk_div",
2247         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2248 };
2249
2250 /* l3_main_1 -> l4_per2 */
2251 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2252         .master         = &dra7xx_l3_main_1_hwmod,
2253         .slave          = &dra7xx_l4_per2_hwmod,
2254         .clk            = "l3_iclk_div",
2255         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2256 };
2257
2258 /* l3_main_1 -> l4_per3 */
2259 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2260         .master         = &dra7xx_l3_main_1_hwmod,
2261         .slave          = &dra7xx_l4_per3_hwmod,
2262         .clk            = "l3_iclk_div",
2263         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2264 };
2265
2266 /* l3_main_1 -> l4_wkup */
2267 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2268         .master         = &dra7xx_l3_main_1_hwmod,
2269         .slave          = &dra7xx_l4_wkup_hwmod,
2270         .clk            = "wkupaon_iclk_mux",
2271         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2272 };
2273
2274 /* l4_per2 -> atl */
2275 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2276         .master         = &dra7xx_l4_per2_hwmod,
2277         .slave          = &dra7xx_atl_hwmod,
2278         .clk            = "l3_iclk_div",
2279         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2280 };
2281
2282 /* l3_main_1 -> bb2d */
2283 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2284         .master         = &dra7xx_l3_main_1_hwmod,
2285         .slave          = &dra7xx_bb2d_hwmod,
2286         .clk            = "l3_iclk_div",
2287         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2288 };
2289
2290 /* l4_wkup -> counter_32k */
2291 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2292         .master         = &dra7xx_l4_wkup_hwmod,
2293         .slave          = &dra7xx_counter_32k_hwmod,
2294         .clk            = "wkupaon_iclk_mux",
2295         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2296 };
2297
2298 /* l4_wkup -> ctrl_module_wkup */
2299 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2300         .master         = &dra7xx_l4_wkup_hwmod,
2301         .slave          = &dra7xx_ctrl_module_wkup_hwmod,
2302         .clk            = "wkupaon_iclk_mux",
2303         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2304 };
2305
2306 static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
2307         .master         = &dra7xx_l4_per2_hwmod,
2308         .slave          = &dra7xx_gmac_hwmod,
2309         .clk            = "dpll_gmac_ck",
2310         .user           = OCP_USER_MPU,
2311 };
2312
2313 static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
2314         .master         = &dra7xx_gmac_hwmod,
2315         .slave          = &dra7xx_mdio_hwmod,
2316         .user           = OCP_USER_MPU,
2317 };
2318
2319 /* l4_wkup -> dcan1 */
2320 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2321         .master         = &dra7xx_l4_wkup_hwmod,
2322         .slave          = &dra7xx_dcan1_hwmod,
2323         .clk            = "wkupaon_iclk_mux",
2324         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2325 };
2326
2327 /* l4_per2 -> dcan2 */
2328 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2329         .master         = &dra7xx_l4_per2_hwmod,
2330         .slave          = &dra7xx_dcan2_hwmod,
2331         .clk            = "l3_iclk_div",
2332         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2333 };
2334
2335 /* l4_cfg -> dma_system */
2336 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2337         .master         = &dra7xx_l4_cfg_hwmod,
2338         .slave          = &dra7xx_dma_system_hwmod,
2339         .clk            = "l3_iclk_div",
2340         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2341 };
2342
2343 /* l3_main_1 -> tpcc */
2344 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = {
2345         .master         = &dra7xx_l3_main_1_hwmod,
2346         .slave          = &dra7xx_tpcc_hwmod,
2347         .clk            = "l3_iclk_div",
2348         .user           = OCP_USER_MPU,
2349 };
2350
2351 /* l3_main_1 -> tptc0 */
2352 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = {
2353         .master         = &dra7xx_l3_main_1_hwmod,
2354         .slave          = &dra7xx_tptc0_hwmod,
2355         .clk            = "l3_iclk_div",
2356         .user           = OCP_USER_MPU,
2357 };
2358
2359 /* l3_main_1 -> tptc1 */
2360 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = {
2361         .master         = &dra7xx_l3_main_1_hwmod,
2362         .slave          = &dra7xx_tptc1_hwmod,
2363         .clk            = "l3_iclk_div",
2364         .user           = OCP_USER_MPU,
2365 };
2366
2367 /* l3_main_1 -> dss */
2368 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2369         .master         = &dra7xx_l3_main_1_hwmod,
2370         .slave          = &dra7xx_dss_hwmod,
2371         .clk            = "l3_iclk_div",
2372         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2373 };
2374
2375 /* l3_main_1 -> dispc */
2376 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2377         .master         = &dra7xx_l3_main_1_hwmod,
2378         .slave          = &dra7xx_dss_dispc_hwmod,
2379         .clk            = "l3_iclk_div",
2380         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2381 };
2382
2383 /* l3_main_1 -> dispc */
2384 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2385         .master         = &dra7xx_l3_main_1_hwmod,
2386         .slave          = &dra7xx_dss_hdmi_hwmod,
2387         .clk            = "l3_iclk_div",
2388         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2389 };
2390
2391 /* l3_main_1 -> aes1 */
2392 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes1 = {
2393         .master         = &dra7xx_l3_main_1_hwmod,
2394         .slave          = &dra7xx_aes1_hwmod,
2395         .clk            = "l3_iclk_div",
2396         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2397 };
2398
2399 /* l3_main_1 -> aes2 */
2400 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes2 = {
2401         .master         = &dra7xx_l3_main_1_hwmod,
2402         .slave          = &dra7xx_aes2_hwmod,
2403         .clk            = "l3_iclk_div",
2404         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2405 };
2406
2407 /* l3_main_1 -> sha0 */
2408 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__sha0 = {
2409         .master         = &dra7xx_l3_main_1_hwmod,
2410         .slave          = &dra7xx_sha0_hwmod,
2411         .clk            = "l3_iclk_div",
2412         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2413 };
2414
2415 /* l4_per2 -> mcasp1 */
2416 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
2417         .master         = &dra7xx_l4_per2_hwmod,
2418         .slave          = &dra7xx_mcasp1_hwmod,
2419         .clk            = "l4_root_clk_div",
2420         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2421 };
2422
2423 /* l3_main_1 -> mcasp1 */
2424 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = {
2425         .master         = &dra7xx_l3_main_1_hwmod,
2426         .slave          = &dra7xx_mcasp1_hwmod,
2427         .clk            = "l3_iclk_div",
2428         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2429 };
2430
2431 /* l4_per2 -> mcasp2 */
2432 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = {
2433         .master         = &dra7xx_l4_per2_hwmod,
2434         .slave          = &dra7xx_mcasp2_hwmod,
2435         .clk            = "l4_root_clk_div",
2436         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2437 };
2438
2439 /* l3_main_1 -> mcasp2 */
2440 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = {
2441         .master         = &dra7xx_l3_main_1_hwmod,
2442         .slave          = &dra7xx_mcasp2_hwmod,
2443         .clk            = "l3_iclk_div",
2444         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2445 };
2446
2447 /* l4_per2 -> mcasp3 */
2448 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
2449         .master         = &dra7xx_l4_per2_hwmod,
2450         .slave          = &dra7xx_mcasp3_hwmod,
2451         .clk            = "l4_root_clk_div",
2452         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2453 };
2454
2455 /* l3_main_1 -> mcasp3 */
2456 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
2457         .master         = &dra7xx_l3_main_1_hwmod,
2458         .slave          = &dra7xx_mcasp3_hwmod,
2459         .clk            = "l3_iclk_div",
2460         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2461 };
2462
2463 /* l4_per2 -> mcasp4 */
2464 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = {
2465         .master         = &dra7xx_l4_per2_hwmod,
2466         .slave          = &dra7xx_mcasp4_hwmod,
2467         .clk            = "l4_root_clk_div",
2468         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2469 };
2470
2471 /* l4_per2 -> mcasp5 */
2472 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = {
2473         .master         = &dra7xx_l4_per2_hwmod,
2474         .slave          = &dra7xx_mcasp5_hwmod,
2475         .clk            = "l4_root_clk_div",
2476         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2477 };
2478
2479 /* l4_per2 -> mcasp6 */
2480 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
2481         .master         = &dra7xx_l4_per2_hwmod,
2482         .slave          = &dra7xx_mcasp6_hwmod,
2483         .clk            = "l4_root_clk_div",
2484         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2485 };
2486
2487 /* l4_per2 -> mcasp7 */
2488 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
2489         .master         = &dra7xx_l4_per2_hwmod,
2490         .slave          = &dra7xx_mcasp7_hwmod,
2491         .clk            = "l4_root_clk_div",
2492         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2493 };
2494
2495 /* l4_per2 -> mcasp8 */
2496 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
2497         .master         = &dra7xx_l4_per2_hwmod,
2498         .slave          = &dra7xx_mcasp8_hwmod,
2499         .clk            = "l4_root_clk_div",
2500         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2501 };
2502
2503 /* l4_per1 -> elm */
2504 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
2505         .master         = &dra7xx_l4_per1_hwmod,
2506         .slave          = &dra7xx_elm_hwmod,
2507         .clk            = "l3_iclk_div",
2508         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2509 };
2510
2511 /* l3_main_1 -> gpmc */
2512 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
2513         .master         = &dra7xx_l3_main_1_hwmod,
2514         .slave          = &dra7xx_gpmc_hwmod,
2515         .clk            = "l3_iclk_div",
2516         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2517 };
2518
2519 /* l4_per1 -> hdq1w */
2520 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
2521         .master         = &dra7xx_l4_per1_hwmod,
2522         .slave          = &dra7xx_hdq1w_hwmod,
2523         .clk            = "l3_iclk_div",
2524         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2525 };
2526
2527 /* l4_cfg -> mailbox1 */
2528 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
2529         .master         = &dra7xx_l4_cfg_hwmod,
2530         .slave          = &dra7xx_mailbox1_hwmod,
2531         .clk            = "l3_iclk_div",
2532         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2533 };
2534
2535 /* l4_per3 -> mailbox2 */
2536 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
2537         .master         = &dra7xx_l4_per3_hwmod,
2538         .slave          = &dra7xx_mailbox2_hwmod,
2539         .clk            = "l3_iclk_div",
2540         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2541 };
2542
2543 /* l4_per3 -> mailbox3 */
2544 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
2545         .master         = &dra7xx_l4_per3_hwmod,
2546         .slave          = &dra7xx_mailbox3_hwmod,
2547         .clk            = "l3_iclk_div",
2548         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2549 };
2550
2551 /* l4_per3 -> mailbox4 */
2552 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
2553         .master         = &dra7xx_l4_per3_hwmod,
2554         .slave          = &dra7xx_mailbox4_hwmod,
2555         .clk            = "l3_iclk_div",
2556         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2557 };
2558
2559 /* l4_per3 -> mailbox5 */
2560 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
2561         .master         = &dra7xx_l4_per3_hwmod,
2562         .slave          = &dra7xx_mailbox5_hwmod,
2563         .clk            = "l3_iclk_div",
2564         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2565 };
2566
2567 /* l4_per3 -> mailbox6 */
2568 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
2569         .master         = &dra7xx_l4_per3_hwmod,
2570         .slave          = &dra7xx_mailbox6_hwmod,
2571         .clk            = "l3_iclk_div",
2572         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2573 };
2574
2575 /* l4_per3 -> mailbox7 */
2576 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
2577         .master         = &dra7xx_l4_per3_hwmod,
2578         .slave          = &dra7xx_mailbox7_hwmod,
2579         .clk            = "l3_iclk_div",
2580         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2581 };
2582
2583 /* l4_per3 -> mailbox8 */
2584 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
2585         .master         = &dra7xx_l4_per3_hwmod,
2586         .slave          = &dra7xx_mailbox8_hwmod,
2587         .clk            = "l3_iclk_div",
2588         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2589 };
2590
2591 /* l4_per3 -> mailbox9 */
2592 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
2593         .master         = &dra7xx_l4_per3_hwmod,
2594         .slave          = &dra7xx_mailbox9_hwmod,
2595         .clk            = "l3_iclk_div",
2596         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2597 };
2598
2599 /* l4_per3 -> mailbox10 */
2600 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
2601         .master         = &dra7xx_l4_per3_hwmod,
2602         .slave          = &dra7xx_mailbox10_hwmod,
2603         .clk            = "l3_iclk_div",
2604         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2605 };
2606
2607 /* l4_per3 -> mailbox11 */
2608 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
2609         .master         = &dra7xx_l4_per3_hwmod,
2610         .slave          = &dra7xx_mailbox11_hwmod,
2611         .clk            = "l3_iclk_div",
2612         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2613 };
2614
2615 /* l4_per3 -> mailbox12 */
2616 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
2617         .master         = &dra7xx_l4_per3_hwmod,
2618         .slave          = &dra7xx_mailbox12_hwmod,
2619         .clk            = "l3_iclk_div",
2620         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2621 };
2622
2623 /* l4_per3 -> mailbox13 */
2624 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
2625         .master         = &dra7xx_l4_per3_hwmod,
2626         .slave          = &dra7xx_mailbox13_hwmod,
2627         .clk            = "l3_iclk_div",
2628         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2629 };
2630
2631 /* l4_per1 -> mcspi1 */
2632 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
2633         .master         = &dra7xx_l4_per1_hwmod,
2634         .slave          = &dra7xx_mcspi1_hwmod,
2635         .clk            = "l3_iclk_div",
2636         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2637 };
2638
2639 /* l4_per1 -> mcspi2 */
2640 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
2641         .master         = &dra7xx_l4_per1_hwmod,
2642         .slave          = &dra7xx_mcspi2_hwmod,
2643         .clk            = "l3_iclk_div",
2644         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2645 };
2646
2647 /* l4_per1 -> mcspi3 */
2648 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
2649         .master         = &dra7xx_l4_per1_hwmod,
2650         .slave          = &dra7xx_mcspi3_hwmod,
2651         .clk            = "l3_iclk_div",
2652         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2653 };
2654
2655 /* l4_per1 -> mcspi4 */
2656 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
2657         .master         = &dra7xx_l4_per1_hwmod,
2658         .slave          = &dra7xx_mcspi4_hwmod,
2659         .clk            = "l3_iclk_div",
2660         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2661 };
2662
2663 /* l4_cfg -> mpu */
2664 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
2665         .master         = &dra7xx_l4_cfg_hwmod,
2666         .slave          = &dra7xx_mpu_hwmod,
2667         .clk            = "l3_iclk_div",
2668         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2669 };
2670
2671 /* l4_cfg -> ocp2scp1 */
2672 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
2673         .master         = &dra7xx_l4_cfg_hwmod,
2674         .slave          = &dra7xx_ocp2scp1_hwmod,
2675         .clk            = "l4_root_clk_div",
2676         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2677 };
2678
2679 /* l4_cfg -> ocp2scp3 */
2680 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
2681         .master         = &dra7xx_l4_cfg_hwmod,
2682         .slave          = &dra7xx_ocp2scp3_hwmod,
2683         .clk            = "l4_root_clk_div",
2684         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2685 };
2686
2687 /* l3_main_1 -> pciess1 */
2688 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
2689         .master         = &dra7xx_l3_main_1_hwmod,
2690         .slave          = &dra7xx_pciess1_hwmod,
2691         .clk            = "l3_iclk_div",
2692         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2693 };
2694
2695 /* l4_cfg -> pciess1 */
2696 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
2697         .master         = &dra7xx_l4_cfg_hwmod,
2698         .slave          = &dra7xx_pciess1_hwmod,
2699         .clk            = "l4_root_clk_div",
2700         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2701 };
2702
2703 /* l3_main_1 -> pciess2 */
2704 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
2705         .master         = &dra7xx_l3_main_1_hwmod,
2706         .slave          = &dra7xx_pciess2_hwmod,
2707         .clk            = "l3_iclk_div",
2708         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2709 };
2710
2711 /* l4_cfg -> pciess2 */
2712 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
2713         .master         = &dra7xx_l4_cfg_hwmod,
2714         .slave          = &dra7xx_pciess2_hwmod,
2715         .clk            = "l4_root_clk_div",
2716         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2717 };
2718
2719 /* l3_main_1 -> qspi */
2720 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
2721         .master         = &dra7xx_l3_main_1_hwmod,
2722         .slave          = &dra7xx_qspi_hwmod,
2723         .clk            = "l3_iclk_div",
2724         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2725 };
2726
2727 /* l4_per3 -> rtcss */
2728 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
2729         .master         = &dra7xx_l4_per3_hwmod,
2730         .slave          = &dra7xx_rtcss_hwmod,
2731         .clk            = "l4_root_clk_div",
2732         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2733 };
2734
2735 /* l4_cfg -> sata */
2736 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
2737         .master         = &dra7xx_l4_cfg_hwmod,
2738         .slave          = &dra7xx_sata_hwmod,
2739         .clk            = "l3_iclk_div",
2740         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2741 };
2742
2743 /* l4_cfg -> smartreflex_core */
2744 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
2745         .master         = &dra7xx_l4_cfg_hwmod,
2746         .slave          = &dra7xx_smartreflex_core_hwmod,
2747         .clk            = "l4_root_clk_div",
2748         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2749 };
2750
2751 /* l4_cfg -> smartreflex_mpu */
2752 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
2753         .master         = &dra7xx_l4_cfg_hwmod,
2754         .slave          = &dra7xx_smartreflex_mpu_hwmod,
2755         .clk            = "l4_root_clk_div",
2756         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2757 };
2758
2759 /* l4_cfg -> spinlock */
2760 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
2761         .master         = &dra7xx_l4_cfg_hwmod,
2762         .slave          = &dra7xx_spinlock_hwmod,
2763         .clk            = "l3_iclk_div",
2764         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2765 };
2766
2767 /* l4_wkup -> timer1 */
2768 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
2769         .master         = &dra7xx_l4_wkup_hwmod,
2770         .slave          = &dra7xx_timer1_hwmod,
2771         .clk            = "wkupaon_iclk_mux",
2772         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2773 };
2774
2775 /* l4_per1 -> timer2 */
2776 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
2777         .master         = &dra7xx_l4_per1_hwmod,
2778         .slave          = &dra7xx_timer2_hwmod,
2779         .clk            = "l3_iclk_div",
2780         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2781 };
2782
2783 /* l4_per1 -> timer3 */
2784 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
2785         .master         = &dra7xx_l4_per1_hwmod,
2786         .slave          = &dra7xx_timer3_hwmod,
2787         .clk            = "l3_iclk_div",
2788         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2789 };
2790
2791 /* l4_per1 -> timer4 */
2792 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
2793         .master         = &dra7xx_l4_per1_hwmod,
2794         .slave          = &dra7xx_timer4_hwmod,
2795         .clk            = "l3_iclk_div",
2796         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2797 };
2798
2799 /* l4_per3 -> timer5 */
2800 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
2801         .master         = &dra7xx_l4_per3_hwmod,
2802         .slave          = &dra7xx_timer5_hwmod,
2803         .clk            = "l3_iclk_div",
2804         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2805 };
2806
2807 /* l4_per3 -> timer6 */
2808 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
2809         .master         = &dra7xx_l4_per3_hwmod,
2810         .slave          = &dra7xx_timer6_hwmod,
2811         .clk            = "l3_iclk_div",
2812         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2813 };
2814
2815 /* l4_per3 -> timer7 */
2816 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
2817         .master         = &dra7xx_l4_per3_hwmod,
2818         .slave          = &dra7xx_timer7_hwmod,
2819         .clk            = "l3_iclk_div",
2820         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2821 };
2822
2823 /* l4_per3 -> timer8 */
2824 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
2825         .master         = &dra7xx_l4_per3_hwmod,
2826         .slave          = &dra7xx_timer8_hwmod,
2827         .clk            = "l3_iclk_div",
2828         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2829 };
2830
2831 /* l4_per1 -> timer9 */
2832 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
2833         .master         = &dra7xx_l4_per1_hwmod,
2834         .slave          = &dra7xx_timer9_hwmod,
2835         .clk            = "l3_iclk_div",
2836         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2837 };
2838
2839 /* l4_per1 -> timer10 */
2840 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
2841         .master         = &dra7xx_l4_per1_hwmod,
2842         .slave          = &dra7xx_timer10_hwmod,
2843         .clk            = "l3_iclk_div",
2844         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2845 };
2846
2847 /* l4_per1 -> timer11 */
2848 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
2849         .master         = &dra7xx_l4_per1_hwmod,
2850         .slave          = &dra7xx_timer11_hwmod,
2851         .clk            = "l3_iclk_div",
2852         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2853 };
2854
2855 /* l4_wkup -> timer12 */
2856 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = {
2857         .master         = &dra7xx_l4_wkup_hwmod,
2858         .slave          = &dra7xx_timer12_hwmod,
2859         .clk            = "wkupaon_iclk_mux",
2860         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2861 };
2862
2863 /* l4_per3 -> timer13 */
2864 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
2865         .master         = &dra7xx_l4_per3_hwmod,
2866         .slave          = &dra7xx_timer13_hwmod,
2867         .clk            = "l3_iclk_div",
2868         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2869 };
2870
2871 /* l4_per3 -> timer14 */
2872 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
2873         .master         = &dra7xx_l4_per3_hwmod,
2874         .slave          = &dra7xx_timer14_hwmod,
2875         .clk            = "l3_iclk_div",
2876         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2877 };
2878
2879 /* l4_per3 -> timer15 */
2880 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
2881         .master         = &dra7xx_l4_per3_hwmod,
2882         .slave          = &dra7xx_timer15_hwmod,
2883         .clk            = "l3_iclk_div",
2884         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2885 };
2886
2887 /* l4_per3 -> timer16 */
2888 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
2889         .master         = &dra7xx_l4_per3_hwmod,
2890         .slave          = &dra7xx_timer16_hwmod,
2891         .clk            = "l3_iclk_div",
2892         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2893 };
2894
2895 /* l4_per1 -> des */
2896 static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = {
2897         .master         = &dra7xx_l4_per1_hwmod,
2898         .slave          = &dra7xx_des_hwmod,
2899         .clk            = "l3_iclk_div",
2900         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2901 };
2902
2903 /* l4_per1 -> rng */
2904 static struct omap_hwmod_ocp_if dra7xx_l4_per1__rng = {
2905         .master         = &dra7xx_l4_per1_hwmod,
2906         .slave          = &dra7xx_rng_hwmod,
2907         .user           = OCP_USER_MPU,
2908 };
2909
2910 /* l4_per3 -> usb_otg_ss1 */
2911 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
2912         .master         = &dra7xx_l4_per3_hwmod,
2913         .slave          = &dra7xx_usb_otg_ss1_hwmod,
2914         .clk            = "dpll_core_h13x2_ck",
2915         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2916 };
2917
2918 /* l4_per3 -> usb_otg_ss2 */
2919 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
2920         .master         = &dra7xx_l4_per3_hwmod,
2921         .slave          = &dra7xx_usb_otg_ss2_hwmod,
2922         .clk            = "dpll_core_h13x2_ck",
2923         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2924 };
2925
2926 /* l4_per3 -> usb_otg_ss3 */
2927 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
2928         .master         = &dra7xx_l4_per3_hwmod,
2929         .slave          = &dra7xx_usb_otg_ss3_hwmod,
2930         .clk            = "dpll_core_h13x2_ck",
2931         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2932 };
2933
2934 /* l4_per3 -> usb_otg_ss4 */
2935 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
2936         .master         = &dra7xx_l4_per3_hwmod,
2937         .slave          = &dra7xx_usb_otg_ss4_hwmod,
2938         .clk            = "dpll_core_h13x2_ck",
2939         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2940 };
2941
2942 /* l3_main_1 -> vcp1 */
2943 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
2944         .master         = &dra7xx_l3_main_1_hwmod,
2945         .slave          = &dra7xx_vcp1_hwmod,
2946         .clk            = "l3_iclk_div",
2947         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2948 };
2949
2950 /* l4_per2 -> vcp1 */
2951 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
2952         .master         = &dra7xx_l4_per2_hwmod,
2953         .slave          = &dra7xx_vcp1_hwmod,
2954         .clk            = "l3_iclk_div",
2955         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2956 };
2957
2958 /* l3_main_1 -> vcp2 */
2959 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
2960         .master         = &dra7xx_l3_main_1_hwmod,
2961         .slave          = &dra7xx_vcp2_hwmod,
2962         .clk            = "l3_iclk_div",
2963         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2964 };
2965
2966 /* l4_per2 -> vcp2 */
2967 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
2968         .master         = &dra7xx_l4_per2_hwmod,
2969         .slave          = &dra7xx_vcp2_hwmod,
2970         .clk            = "l3_iclk_div",
2971         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2972 };
2973
2974 /* l4_wkup -> wd_timer2 */
2975 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
2976         .master         = &dra7xx_l4_wkup_hwmod,
2977         .slave          = &dra7xx_wd_timer2_hwmod,
2978         .clk            = "wkupaon_iclk_mux",
2979         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2980 };
2981
2982 /* l4_per2 -> epwmss0 */
2983 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss0 = {
2984         .master         = &dra7xx_l4_per2_hwmod,
2985         .slave          = &dra7xx_epwmss0_hwmod,
2986         .clk            = "l4_root_clk_div",
2987         .user           = OCP_USER_MPU,
2988 };
2989
2990 /* l4_per2 -> epwmss1 */
2991 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss1 = {
2992         .master         = &dra7xx_l4_per2_hwmod,
2993         .slave          = &dra7xx_epwmss1_hwmod,
2994         .clk            = "l4_root_clk_div",
2995         .user           = OCP_USER_MPU,
2996 };
2997
2998 /* l4_per2 -> epwmss2 */
2999 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss2 = {
3000         .master         = &dra7xx_l4_per2_hwmod,
3001         .slave          = &dra7xx_epwmss2_hwmod,
3002         .clk            = "l4_root_clk_div",
3003         .user           = OCP_USER_MPU,
3004 };
3005
3006 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3007         &dra7xx_l3_main_1__dmm,
3008         &dra7xx_l3_main_2__l3_instr,
3009         &dra7xx_l4_cfg__l3_main_1,
3010         &dra7xx_mpu__l3_main_1,
3011         &dra7xx_l3_main_1__l3_main_2,
3012         &dra7xx_l4_cfg__l3_main_2,
3013         &dra7xx_l3_main_1__l4_cfg,
3014         &dra7xx_l3_main_1__l4_per1,
3015         &dra7xx_l3_main_1__l4_per2,
3016         &dra7xx_l3_main_1__l4_per3,
3017         &dra7xx_l3_main_1__l4_wkup,
3018         &dra7xx_l4_per2__atl,
3019         &dra7xx_l3_main_1__bb2d,
3020         &dra7xx_l4_wkup__counter_32k,
3021         &dra7xx_l4_wkup__ctrl_module_wkup,
3022         &dra7xx_l4_wkup__dcan1,
3023         &dra7xx_l4_per2__dcan2,
3024         &dra7xx_l4_per2__cpgmac0,
3025         &dra7xx_l4_per2__mcasp1,
3026         &dra7xx_l3_main_1__mcasp1,
3027         &dra7xx_l4_per2__mcasp2,
3028         &dra7xx_l3_main_1__mcasp2,
3029         &dra7xx_l4_per2__mcasp3,
3030         &dra7xx_l3_main_1__mcasp3,
3031         &dra7xx_l4_per2__mcasp4,
3032         &dra7xx_l4_per2__mcasp5,
3033         &dra7xx_l4_per2__mcasp6,
3034         &dra7xx_l4_per2__mcasp7,
3035         &dra7xx_l4_per2__mcasp8,
3036         &dra7xx_gmac__mdio,
3037         &dra7xx_l4_cfg__dma_system,
3038         &dra7xx_l3_main_1__tpcc,
3039         &dra7xx_l3_main_1__tptc0,
3040         &dra7xx_l3_main_1__tptc1,
3041         &dra7xx_l3_main_1__dss,
3042         &dra7xx_l3_main_1__dispc,
3043         &dra7xx_l3_main_1__hdmi,
3044         &dra7xx_l3_main_1__aes1,
3045         &dra7xx_l3_main_1__aes2,
3046         &dra7xx_l3_main_1__sha0,
3047         &dra7xx_l4_per1__elm,
3048         &dra7xx_l3_main_1__gpmc,
3049         &dra7xx_l4_per1__hdq1w,
3050         &dra7xx_l4_cfg__mailbox1,
3051         &dra7xx_l4_per3__mailbox2,
3052         &dra7xx_l4_per3__mailbox3,
3053         &dra7xx_l4_per3__mailbox4,
3054         &dra7xx_l4_per3__mailbox5,
3055         &dra7xx_l4_per3__mailbox6,
3056         &dra7xx_l4_per3__mailbox7,
3057         &dra7xx_l4_per3__mailbox8,
3058         &dra7xx_l4_per3__mailbox9,
3059         &dra7xx_l4_per3__mailbox10,
3060         &dra7xx_l4_per3__mailbox11,
3061         &dra7xx_l4_per3__mailbox12,
3062         &dra7xx_l4_per3__mailbox13,
3063         &dra7xx_l4_per1__mcspi1,
3064         &dra7xx_l4_per1__mcspi2,
3065         &dra7xx_l4_per1__mcspi3,
3066         &dra7xx_l4_per1__mcspi4,
3067         &dra7xx_l4_cfg__mpu,
3068         &dra7xx_l4_cfg__ocp2scp1,
3069         &dra7xx_l4_cfg__ocp2scp3,
3070         &dra7xx_l3_main_1__pciess1,
3071         &dra7xx_l4_cfg__pciess1,
3072         &dra7xx_l3_main_1__pciess2,
3073         &dra7xx_l4_cfg__pciess2,
3074         &dra7xx_l3_main_1__qspi,
3075         &dra7xx_l4_cfg__sata,
3076         &dra7xx_l4_cfg__smartreflex_core,
3077         &dra7xx_l4_cfg__smartreflex_mpu,
3078         &dra7xx_l4_cfg__spinlock,
3079         &dra7xx_l4_wkup__timer1,
3080         &dra7xx_l4_per1__timer2,
3081         &dra7xx_l4_per1__timer3,
3082         &dra7xx_l4_per1__timer4,
3083         &dra7xx_l4_per3__timer5,