arch/arm/mach-omap2/omap_hwmod_54xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP54xx chips
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Paul Walmsley
   7  * Benoit Cousson
   8  *
   9  * This file is automatically generated from the OMAP hardware databases.
  10  * We respectfully ask that any modifications to this file be coordinated
  11  * with the public linux-omap@vger.kernel.org mailing list and the
  12  * authors above to ensure that the autogeneration scripts are kept
  13  * up-to-date with the file contents.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include <linux/io.h>
  21 #include <linux/platform_data/gpio-omap.h>
  22 #include <linux/platform_data/hsmmc-omap.h>
  23 #include <linux/power/smartreflex.h>
  24 #include <linux/i2c-omap.h>
  25
  26 #include <linux/omap-dma.h>
  27 #include <linux/platform_data/spi-omap2-mcspi.h>
  28 #include <linux/platform_data/asoc-ti-mcbsp.h>
  29 #include <plat/dmtimer.h>
  30
  31 #include "omap_hwmod.h"
  32 #include "omap_hwmod_common_data.h"
  33 #include "cm1_54xx.h"
  34 #include "cm2_54xx.h"
  35 #include "prm54xx.h"
  36 #include "i2c.h"
  37 #include "wd_timer.h"
  38
  39 /* Base offset for all OMAP5 interrupts external to MPUSS */
  40 #define OMAP54XX_IRQ_GIC_START  32
  41
  42 /* Base offset for all OMAP5 dma requests */
  43 #define OMAP54XX_DMA_REQ_START  1
  44
  45
  46 /*
  47  * IP blocks
  48  */
  49
  50 /*
  51  * 'dmm' class
  52  * instance(s): dmm
  53  */
  54 static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
  55         .name   = "dmm",
  56 };
  57
  58 /* dmm */
  59 static struct omap_hwmod omap54xx_dmm_hwmod = {
  60         .name           = "dmm",
  61         .class          = &omap54xx_dmm_hwmod_class,
  62         .clkdm_name     = "emif_clkdm",
  63         .prcm = {
  64                 .omap4 = {
  65                         .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
  66                         .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
  67                 },
  68         },
  69 };
  70
  71 /*
  72  * 'l3' class
  73  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  74  */
  75 static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
  76         .name   = "l3",
  77 };
  78
  79 /* l3_instr */
  80 static struct omap_hwmod omap54xx_l3_instr_hwmod = {
  81         .name           = "l3_instr",
  82         .class          = &omap54xx_l3_hwmod_class,
  83         .clkdm_name     = "l3instr_clkdm",
  84         .prcm = {
  85                 .omap4 = {
  86                         .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  87                         .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  88                         .modulemode   = MODULEMODE_HWCTRL,
  89                 },
  90         },
  91 };
  92
  93 /* l3_main_1 */
  94 static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
  95         .name           = "l3_main_1",
  96         .class          = &omap54xx_l3_hwmod_class,
  97         .clkdm_name     = "l3main1_clkdm",
  98         .prcm = {
  99                 .omap4 = {
 100                         .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
 101                         .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
 102                 },
 103         },
 104 };
 105
 106 /* l3_main_2 */
 107 static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
 108         .name           = "l3_main_2",
 109         .class          = &omap54xx_l3_hwmod_class,
 110         .clkdm_name     = "l3main2_clkdm",
 111         .prcm = {
 112                 .omap4 = {
 113                         .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
 114                         .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
 115                 },
 116         },
 117 };
 118
 119 /* l3_main_3 */
 120 static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
 121         .name           = "l3_main_3",
 122         .class          = &omap54xx_l3_hwmod_class,
 123         .clkdm_name     = "l3instr_clkdm",
 124         .prcm = {
 125                 .omap4 = {
 126                         .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
 127                         .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
 128                         .modulemode   = MODULEMODE_HWCTRL,
 129                 },
 130         },
 131 };
 132
 133 /*
 134  * 'l4' class
 135  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 136  */
 137 static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
 138         .name   = "l4",
 139 };
 140
 141 /* l4_abe */
 142 static struct omap_hwmod omap54xx_l4_abe_hwmod = {
 143         .name           = "l4_abe",
 144         .class          = &omap54xx_l4_hwmod_class,
 145         .clkdm_name     = "abe_clkdm",
 146         .prcm = {
 147                 .omap4 = {
 148                         .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
 149                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 150                 },
 151         },
 152 };
 153
 154 /* l4_cfg */
 155 static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
 156         .name           = "l4_cfg",
 157         .class          = &omap54xx_l4_hwmod_class,
 158         .clkdm_name     = "l4cfg_clkdm",
 159         .prcm = {
 160                 .omap4 = {
 161                         .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 162                         .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 163                 },
 164         },
 165 };
 166
 167 /* l4_per */
 168 static struct omap_hwmod omap54xx_l4_per_hwmod = {
 169         .name           = "l4_per",
 170         .class          = &omap54xx_l4_hwmod_class,
 171         .clkdm_name     = "l4per_clkdm",
 172         .prcm = {
 173                 .omap4 = {
 174                         .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
 175                         .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 176                 },
 177         },
 178 };
 179
 180 /* l4_wkup */
 181 static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
 182         .name           = "l4_wkup",
 183         .class          = &omap54xx_l4_hwmod_class,
 184         .clkdm_name     = "wkupaon_clkdm",
 185         .prcm = {
 186                 .omap4 = {
 187                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
 188                         .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
 189                 },
 190         },
 191 };
 192
 193 /*
 194  * 'mpu_bus' class
 195  * instance(s): mpu_private
 196  */
 197 static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
 198         .name   = "mpu_bus",
 199 };
 200
 201 /* mpu_private */
 202 static struct omap_hwmod omap54xx_mpu_private_hwmod = {
 203         .name           = "mpu_private",
 204         .class          = &omap54xx_mpu_bus_hwmod_class,
 205         .clkdm_name     = "mpu_clkdm",
 206         .prcm = {
 207                 .omap4 = {
 208                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 209                 },
 210         },
 211 };
 212
 213 /*
 214  * 'counter' class
 215  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 216  */
 217
 218 static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
 219         .rev_offs       = 0x0000,
 220         .sysc_offs      = 0x0010,
 221         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 222         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 223         .sysc_fields    = &omap_hwmod_sysc_type1,
 224 };
 225
 226 static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
 227         .name   = "counter",
 228         .sysc   = &omap54xx_counter_sysc,
 229 };
 230
 231 /* counter_32k */
 232 static struct omap_hwmod omap54xx_counter_32k_hwmod = {
 233         .name           = "counter_32k",
 234         .class          = &omap54xx_counter_hwmod_class,
 235         .clkdm_name     = "wkupaon_clkdm",
 236         .flags          = HWMOD_SWSUP_SIDLE,
 237         .main_clk       = "wkupaon_iclk_mux",
 238         .prcm = {
 239                 .omap4 = {
 240                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
 241                         .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
 242                 },
 243         },
 244 };
 245
 246 /*
 247  * 'dma' class
 248  * dma controller for data exchange between memory to memory (i.e. internal or
 249  * external memory) and gp peripherals to memory or memory to gp peripherals
 250  */
 251
 252 static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = {
 253         .rev_offs       = 0x0000,
 254         .sysc_offs      = 0x002c,
 255         .syss_offs      = 0x0028,
 256         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 257                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 258                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 259                            SYSS_HAS_RESET_STATUS),
 260         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 261                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 262         .sysc_fields    = &omap_hwmod_sysc_type1,
 263 };
 264
 265 static struct omap_hwmod_class omap54xx_dma_hwmod_class = {
 266         .name   = "dma",
 267         .sysc   = &omap54xx_dma_sysc,
 268 };
 269
 270 /* dma dev_attr */
 271 static struct omap_dma_dev_attr dma_dev_attr = {
 272         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 273                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 274         .lch_count      = 32,
 275 };
 276
 277 /* dma_system */
 278 static struct omap_hwmod_irq_info omap54xx_dma_system_irqs[] = {
 279         { .name = "0", .irq = 12 + OMAP54XX_IRQ_GIC_START },
 280         { .name = "1", .irq = 13 + OMAP54XX_IRQ_GIC_START },
 281         { .name = "2", .irq = 14 + OMAP54XX_IRQ_GIC_START },
 282         { .name = "3", .irq = 15 + OMAP54XX_IRQ_GIC_START },
 283         { .irq = -1 }
 284 };
 285
 286 static struct omap_hwmod omap54xx_dma_system_hwmod = {
 287         .name           = "dma_system",
 288         .class          = &omap54xx_dma_hwmod_class,
 289         .clkdm_name     = "dma_clkdm",
 290         .mpu_irqs       = omap54xx_dma_system_irqs,
 291         .xlate_irq      = omap4_xlate_irq,
 292         .main_clk       = "l3_iclk_div",
 293         .prcm = {
 294                 .omap4 = {
 295                         .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
 296                         .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
 297                 },
 298         },
 299         .dev_attr       = &dma_dev_attr,
 300 };
 301
 302 /*
 303  * 'dmic' class
 304  * digital microphone controller
 305  */
 306
 307 static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = {
 308         .rev_offs       = 0x0000,
 309         .sysc_offs      = 0x0010,
 310         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 311                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 312         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 313                            SIDLE_SMART_WKUP),
 314         .sysc_fields    = &omap_hwmod_sysc_type2,
 315 };
 316
 317 static struct omap_hwmod_class omap54xx_dmic_hwmod_class = {
 318         .name   = "dmic",
 319         .sysc   = &omap54xx_dmic_sysc,
 320 };
 321
 322 /* dmic */
 323 static struct omap_hwmod omap54xx_dmic_hwmod = {
 324         .name           = "dmic",
 325         .class          = &omap54xx_dmic_hwmod_class,
 326         .clkdm_name     = "abe_clkdm",
 327         .main_clk       = "dmic_gfclk",
 328         .prcm = {
 329                 .omap4 = {
 330                         .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET,
 331                         .context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET,
 332                         .modulemode   = MODULEMODE_SWCTRL,
 333                 },
 334         },
 335 };
 336
 337 /*
 338  * 'dss' class
 339  * display sub-system
 340  */
 341 static struct omap_hwmod_class_sysconfig omap54xx_dss_sysc = {
 342         .rev_offs       = 0x0000,
 343         .syss_offs      = 0x0014,
 344         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 345 };
 346
 347 static struct omap_hwmod_class omap54xx_dss_hwmod_class = {
 348         .name   = "dss",
 349         .sysc   = &omap54xx_dss_sysc,
 350         .reset  = omap_dss_reset,
 351 };
 352
 353 /* dss */
 354 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 355         { .role = "32khz_clk", .clk = "dss_32khz_clk" },
 356         { .role = "sys_clk", .clk = "dss_sys_clk" },
 357         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 358 };
 359
 360 static struct omap_hwmod omap54xx_dss_hwmod = {
 361         .name           = "dss_core",
 362         .class          = &omap54xx_dss_hwmod_class,
 363         .clkdm_name     = "dss_clkdm",
 364         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 365         .main_clk       = "dss_dss_clk",
 366         .prcm = {
 367                 .omap4 = {
 368                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 369                         .context_offs = OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET,
 370                         .modulemode   = MODULEMODE_SWCTRL,
 371                 },
 372         },
 373         .opt_clks       = dss_opt_clks,
 374         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 375 };
 376
 377 /*
 378  * 'dispc' class
 379  * display controller
 380  */
 381
 382 static struct omap_hwmod_class_sysconfig omap54xx_dispc_sysc = {
 383         .rev_offs       = 0x0000,
 384         .sysc_offs      = 0x0010,
 385         .syss_offs      = 0x0014,
 386         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 387                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 388                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 389                            SYSS_HAS_RESET_STATUS),
 390         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 391                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 392         .sysc_fields    = &omap_hwmod_sysc_type1,
 393 };
 394
 395 static struct omap_hwmod_class omap54xx_dispc_hwmod_class = {
 396         .name   = "dispc",
 397         .sysc   = &omap54xx_dispc_sysc,
 398 };
 399
 400 /* dss_dispc */
 401 static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
 402         { .role = "sys_clk", .clk = "dss_sys_clk" },
 403 };
 404
 405 /* dss_dispc dev_attr */
 406 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
 407         .has_framedonetv_irq    = 1,
 408         .manager_count          = 4,
 409 };
 410
 411 static struct omap_hwmod omap54xx_dss_dispc_hwmod = {
 412         .name           = "dss_dispc",
 413         .class          = &omap54xx_dispc_hwmod_class,
 414         .clkdm_name     = "dss_clkdm",
 415         .main_clk       = "dss_dss_clk",
 416         .prcm = {
 417                 .omap4 = {
 418                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 419                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 420                 },
 421         },
 422         .opt_clks       = dss_dispc_opt_clks,
 423         .opt_clks_cnt   = ARRAY_SIZE(dss_dispc_opt_clks),
 424         .dev_attr       = &dss_dispc_dev_attr,
 425         .parent_hwmod   = &omap54xx_dss_hwmod,
 426 };
 427
 428 /*
 429  * 'dsi1' class
 430  * display serial interface controller
 431  */
 432
 433 static struct omap_hwmod_class_sysconfig omap54xx_dsi1_sysc = {
 434         .rev_offs       = 0x0000,
 435         .sysc_offs      = 0x0010,
 436         .syss_offs      = 0x0014,
 437         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 438                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 439                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 440         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 441         .sysc_fields    = &omap_hwmod_sysc_type1,
 442 };
 443
 444 static struct omap_hwmod_class omap54xx_dsi1_hwmod_class = {
 445         .name   = "dsi1",
 446         .sysc   = &omap54xx_dsi1_sysc,
 447 };
 448
 449 /* dss_dsi1_a */
 450 static struct omap_hwmod_opt_clk dss_dsi1_a_opt_clks[] = {
 451         { .role = "sys_clk", .clk = "dss_sys_clk" },
 452 };
 453
 454 static struct omap_hwmod omap54xx_dss_dsi1_a_hwmod = {
 455         .name           = "dss_dsi1",
 456         .class          = &omap54xx_dsi1_hwmod_class,
 457         .clkdm_name     = "dss_clkdm",
 458         .main_clk       = "dss_dss_clk",
 459         .prcm = {
 460                 .omap4 = {
 461                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 462                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 463                 },
 464         },
 465         .opt_clks       = dss_dsi1_a_opt_clks,
 466         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_a_opt_clks),
 467         .parent_hwmod   = &omap54xx_dss_hwmod,
 468 };
 469
 470 /* dss_dsi1_c */
 471 static struct omap_hwmod_opt_clk dss_dsi1_c_opt_clks[] = {
 472         { .role = "sys_clk", .clk = "dss_sys_clk" },
 473 };
 474
 475 static struct omap_hwmod omap54xx_dss_dsi1_c_hwmod = {
 476         .name           = "dss_dsi2",
 477         .class          = &omap54xx_dsi1_hwmod_class,
 478         .clkdm_name     = "dss_clkdm",
 479         .main_clk       = "dss_dss_clk",
 480         .prcm = {
 481                 .omap4 = {
 482                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 483                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 484                 },
 485         },
 486         .opt_clks       = dss_dsi1_c_opt_clks,
 487         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_c_opt_clks),
 488         .parent_hwmod   = &omap54xx_dss_hwmod,
 489 };
 490
 491 /*
 492  * 'hdmi' class
 493  * hdmi controller
 494  */
 495
 496 static struct omap_hwmod_class_sysconfig omap54xx_hdmi_sysc = {
 497         .rev_offs       = 0x0000,
 498         .sysc_offs      = 0x0010,
 499         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 500                            SYSC_HAS_SOFTRESET),
 501         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 502                            SIDLE_SMART_WKUP),
 503         .sysc_fields    = &omap_hwmod_sysc_type2,
 504 };
 505
 506 static struct omap_hwmod_class omap54xx_hdmi_hwmod_class = {
 507         .name   = "hdmi",
 508         .sysc   = &omap54xx_hdmi_sysc,
 509 };
 510
 511 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 512         { .role = "sys_clk", .clk = "dss_sys_clk" },
 513 };
 514
 515 static struct omap_hwmod omap54xx_dss_hdmi_hwmod = {
 516         .name           = "dss_hdmi",
 517         .class          = &omap54xx_hdmi_hwmod_class,
 518         .clkdm_name     = "dss_clkdm",
 519         .main_clk       = "dss_48mhz_clk",
 520         .prcm = {
 521                 .omap4 = {
 522                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 523                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 524                 },
 525         },
 526         .opt_clks       = dss_hdmi_opt_clks,
 527         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 528         .parent_hwmod   = &omap54xx_dss_hwmod,
 529 };
 530
 531 /*
 532  * 'rfbi' class
 533  * remote frame buffer interface
 534  */
 535
 536 static struct omap_hwmod_class_sysconfig omap54xx_rfbi_sysc = {
 537         .rev_offs       = 0x0000,
 538         .sysc_offs      = 0x0010,
 539         .syss_offs      = 0x0014,
 540         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 541                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 542         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 543         .sysc_fields    = &omap_hwmod_sysc_type1,
 544 };
 545
 546 static struct omap_hwmod_class omap54xx_rfbi_hwmod_class = {
 547         .name   = "rfbi",
 548         .sysc   = &omap54xx_rfbi_sysc,
 549 };
 550
 551 /* dss_rfbi */
 552 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 553         { .role = "ick", .clk = "l3_iclk_div" },
 554 };
 555
 556 static struct omap_hwmod omap54xx_dss_rfbi_hwmod = {
 557         .name           = "dss_rfbi",
 558         .class          = &omap54xx_rfbi_hwmod_class,
 559         .clkdm_name     = "dss_clkdm",
 560         .prcm = {
 561                 .omap4 = {
 562                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 563                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 564                 },
 565         },
 566         .opt_clks       = dss_rfbi_opt_clks,
 567         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 568         .parent_hwmod   = &omap54xx_dss_hwmod,
 569 };
 570
 571 /*
 572  * 'emif' class
 573  * external memory interface no1 (wrapper)
 574  */
 575
 576 static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
 577         .rev_offs       = 0x0000,
 578 };
 579
 580 static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
 581         .name   = "emif",
 582         .sysc   = &omap54xx_emif_sysc,
 583 };
 584
 585 /* emif1 */
 586 static struct omap_hwmod omap54xx_emif1_hwmod = {
 587         .name           = "emif1",
 588         .class          = &omap54xx_emif_hwmod_class,
 589         .clkdm_name     = "emif_clkdm",
 590         .flags          = HWMOD_INIT_NO_IDLE,
 591         .main_clk       = "dpll_core_h11x2_ck",
 592         .prcm = {
 593                 .omap4 = {
 594                         .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
 595                         .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
 596                         .modulemode   = MODULEMODE_HWCTRL,
 597                 },
 598         },
 599 };
 600
 601 /* emif2 */
 602 static struct omap_hwmod omap54xx_emif2_hwmod = {
 603         .name           = "emif2",
 604         .class          = &omap54xx_emif_hwmod_class,
 605         .clkdm_name     = "emif_clkdm",
 606         .flags          = HWMOD_INIT_NO_IDLE,
 607         .main_clk       = "dpll_core_h11x2_ck",
 608         .prcm = {
 609                 .omap4 = {
 610                         .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
 611                         .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
 612                         .modulemode   = MODULEMODE_HWCTRL,
 613                 },
 614         },
 615 };
 616
 617 /*
 618  * 'gpio' class
 619  * general purpose io module
 620  */
 621
 622 static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc = {
 623         .rev_offs       = 0x0000,
 624         .sysc_offs      = 0x0010,
 625         .syss_offs      = 0x0114,
 626         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 627                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 628                            SYSS_HAS_RESET_STATUS),
 629         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 630                            SIDLE_SMART_WKUP),
 631         .sysc_fields    = &omap_hwmod_sysc_type1,
 632 };
 633
 634 static struct omap_hwmod_class omap54xx_gpio_hwmod_class = {
 635         .name   = "gpio",
 636         .sysc   = &omap54xx_gpio_sysc,
 637         .rev    = 2,
 638 };
 639
 640 /* gpio dev_attr */
 641 static struct omap_gpio_dev_attr gpio_dev_attr = {
 642         .bank_width     = 32,
 643         .dbck_flag      = true,
 644 };
 645
 646 /* gpio1 */
 647 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 648         { .role = "dbclk", .clk = "gpio1_dbclk" },
 649 };
 650
 651 static struct omap_hwmod omap54xx_gpio1_hwmod = {
 652         .name           = "gpio1",
 653         .class          = &omap54xx_gpio_hwmod_class,
 654         .clkdm_name     = "wkupaon_clkdm",
 655         .main_clk       = "wkupaon_iclk_mux",
 656         .prcm = {
 657                 .omap4 = {
 658                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
 659                         .context_offs = OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
 660                         .modulemode   = MODULEMODE_HWCTRL,
 661                 },
 662         },
 663         .opt_clks       = gpio1_opt_clks,
 664         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 665         .dev_attr       = &gpio_dev_attr,
 666 };
 667
 668 /* gpio2 */
 669 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 670         { .role = "dbclk", .clk = "gpio2_dbclk" },
 671 };
 672
 673 static struct omap_hwmod omap54xx_gpio2_hwmod = {
 674         .name           = "gpio2",
 675         .class          = &omap54xx_gpio_hwmod_class,
 676         .clkdm_name     = "l4per_clkdm",
 677         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 678         .main_clk       = "l4_root_clk_div",
 679         .prcm = {
 680                 .omap4 = {
 681                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
 682                         .context_offs = OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
 683                         .modulemode   = MODULEMODE_HWCTRL,
 684                 },
 685         },
 686         .opt_clks       = gpio2_opt_clks,
 687         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 688         .dev_attr       = &gpio_dev_attr,
 689 };
 690
 691 /* gpio3 */
 692 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 693         { .role = "dbclk", .clk = "gpio3_dbclk" },
 694 };
 695
 696 static struct omap_hwmod omap54xx_gpio3_hwmod = {
 697         .name           = "gpio3",
 698         .class          = &omap54xx_gpio_hwmod_class,
 699         .clkdm_name     = "l4per_clkdm",
 700         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 701         .main_clk       = "l4_root_clk_div",
 702         .prcm = {
 703                 .omap4 = {
 704                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
 705                         .context_offs = OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
 706                         .modulemode   = MODULEMODE_HWCTRL,
 707                 },
 708         },
 709         .opt_clks       = gpio3_opt_clks,
 710         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 711         .dev_attr       = &gpio_dev_attr,
 712 };
 713
 714 /* gpio4 */
 715 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 716         { .role = "dbclk", .clk = "gpio4_dbclk" },
 717 };
 718
 719 static struct omap_hwmod omap54xx_gpio4_hwmod = {
 720         .name           = "gpio4",
 721         .class          = &omap54xx_gpio_hwmod_class,
 722         .clkdm_name     = "l4per_clkdm",
 723         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 724         .main_clk       = "l4_root_clk_div",
 725         .prcm = {
 726                 .omap4 = {
 727                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
 728                         .context_offs = OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
 729                         .modulemode   = MODULEMODE_HWCTRL,
 730                 },
 731         },
 732         .opt_clks       = gpio4_opt_clks,
 733         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 734         .dev_attr       = &gpio_dev_attr,
 735 };
 736
 737 /* gpio5 */
 738 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 739         { .role = "dbclk", .clk = "gpio5_dbclk" },
 740 };
 741
 742 static struct omap_hwmod omap54xx_gpio5_hwmod = {
 743         .name           = "gpio5",
 744         .class          = &omap54xx_gpio_hwmod_class,
 745         .clkdm_name     = "l4per_clkdm",
 746         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 747         .main_clk       = "l4_root_clk_div",
 748         .prcm = {
 749                 .omap4 = {
 750                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
 751                         .context_offs = OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
 752                         .modulemode   = MODULEMODE_HWCTRL,
 753                 },
 754         },
 755         .opt_clks       = gpio5_opt_clks,
 756         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
 757         .dev_attr       = &gpio_dev_attr,
 758 };
 759
 760 /* gpio6 */
 761 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
 762         { .role = "dbclk", .clk = "gpio6_dbclk" },
 763 };
 764
 765 static struct omap_hwmod omap54xx_gpio6_hwmod = {
 766         .name           = "gpio6",
 767         .class          = &omap54xx_gpio_hwmod_class,
 768         .clkdm_name     = "l4per_clkdm",
 769         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 770         .main_clk       = "l4_root_clk_div",
 771         .prcm = {
 772                 .omap4 = {
 773                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
 774                         .context_offs = OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
 775                         .modulemode   = MODULEMODE_HWCTRL,
 776                 },
 777         },
 778         .opt_clks       = gpio6_opt_clks,
 779         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
 780         .dev_attr       = &gpio_dev_attr,
 781 };
 782
 783 /* gpio7 */
 784 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
 785         { .role = "dbclk", .clk = "gpio7_dbclk" },
 786 };
 787
 788 static struct omap_hwmod omap54xx_gpio7_hwmod = {
 789         .name           = "gpio7",
 790         .class          = &omap54xx_gpio_hwmod_class,
 791         .clkdm_name     = "l4per_clkdm",
 792         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 793         .main_clk       = "l4_root_clk_div",
 794         .prcm = {
 795                 .omap4 = {
 796                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
 797                         .context_offs = OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
 798                         .modulemode   = MODULEMODE_HWCTRL,
 799                 },
 800         },
 801         .opt_clks       = gpio7_opt_clks,
 802         .opt_clks_cnt   = ARRAY_SIZE(gpio7_opt_clks),
 803         .dev_attr       = &gpio_dev_attr,
 804 };
 805
 806 /* gpio8 */
 807 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
 808         { .role = "dbclk", .clk = "gpio8_dbclk" },
 809 };
 810
 811 static struct omap_hwmod omap54xx_gpio8_hwmod = {
 812         .name           = "gpio8",
 813         .class          = &omap54xx_gpio_hwmod_class,
 814         .clkdm_name     = "l4per_clkdm",
 815         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 816         .main_clk       = "l4_root_clk_div",
 817         .prcm = {
 818                 .omap4 = {
 819                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
 820                         .context_offs = OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
 821                         .modulemode   = MODULEMODE_HWCTRL,
 822                 },
 823         },
 824         .opt_clks       = gpio8_opt_clks,
 825         .opt_clks_cnt   = ARRAY_SIZE(gpio8_opt_clks),
 826         .dev_attr       = &gpio_dev_attr,
 827 };
 828
 829 /*
 830  * 'i2c' class
 831  * multimaster high-speed i2c controller
 832  */
 833
 834 static struct omap_hwmod_class_sysconfig omap54xx_i2c_sysc = {
 835         .sysc_offs      = 0x0010,
 836         .syss_offs      = 0x0090,
 837         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 838                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 839                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 840         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 841                            SIDLE_SMART_WKUP),
 842         .clockact       = CLOCKACT_TEST_ICLK,
 843         .sysc_fields    = &omap_hwmod_sysc_type1,
 844 };
 845
 846 static struct omap_hwmod_class omap54xx_i2c_hwmod_class = {
 847         .name   = "i2c",
 848         .sysc   = &omap54xx_i2c_sysc,
 849         .reset  = &omap_i2c_reset,
 850         .rev    = OMAP_I2C_IP_VERSION_2,
 851 };
 852
 853 /* i2c dev_attr */
 854 static struct omap_i2c_dev_attr i2c_dev_attr = {
 855         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
 856 };
 857
 858 /* i2c1 */
 859 static struct omap_hwmod omap54xx_i2c1_hwmod = {
 860         .name           = "i2c1",
 861         .class          = &omap54xx_i2c_hwmod_class,
 862         .clkdm_name     = "l4per_clkdm",
 863         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 864         .main_clk       = "func_96m_fclk",
 865         .prcm = {
 866                 .omap4 = {
 867                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
 868                         .context_offs = OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
 869                         .modulemode   = MODULEMODE_SWCTRL,
 870                 },
 871         },
 872         .dev_attr       = &i2c_dev_attr,
 873 };
 874
 875 /* i2c2 */
 876 static struct omap_hwmod omap54xx_i2c2_hwmod = {
 877         .name           = "i2c2",
 878         .class          = &omap54xx_i2c_hwmod_class,
 879         .clkdm_name     = "l4per_clkdm",
 880         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 881         .main_clk       = "func_96m_fclk",
 882         .prcm = {
 883                 .omap4 = {
 884                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
 885                         .context_offs = OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
 886                         .modulemode   = MODULEMODE_SWCTRL,
 887                 },
 888         },
 889         .dev_attr       = &i2c_dev_attr,
 890 };
 891
 892 /* i2c3 */
 893 static struct omap_hwmod omap54xx_i2c3_hwmod = {
 894         .name           = "i2c3",
 895         .class          = &omap54xx_i2c_hwmod_class,
 896         .clkdm_name     = "l4per_clkdm",
 897         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 898         .main_clk       = "func_96m_fclk",
 899         .prcm = {
 900                 .omap4 = {
 901                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
 902                         .context_offs = OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
 903                         .modulemode   = MODULEMODE_SWCTRL,
 904                 },
 905         },
 906         .dev_attr       = &i2c_dev_attr,
 907 };
 908
 909 /* i2c4 */
 910 static struct omap_hwmod omap54xx_i2c4_hwmod = {
 911         .name           = "i2c4",
 912         .class          = &omap54xx_i2c_hwmod_class,
 913         .clkdm_name     = "l4per_clkdm",
 914         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 915         .main_clk       = "func_96m_fclk",
 916         .prcm = {
 917                 .omap4 = {
 918                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
 919                         .context_offs = OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
 920                         .modulemode   = MODULEMODE_SWCTRL,
 921                 },
 922         },
 923         .dev_attr       = &i2c_dev_attr,
 924 };
 925
 926 /* i2c5 */
 927 static struct omap_hwmod omap54xx_i2c5_hwmod = {
 928         .name           = "i2c5",
 929         .class          = &omap54xx_i2c_hwmod_class,
 930         .clkdm_name     = "l4per_clkdm",
 931         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 932         .main_clk       = "func_96m_fclk",
 933         .prcm = {
 934                 .omap4 = {
 935                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET,
 936                         .context_offs = OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET,
 937                         .modulemode   = MODULEMODE_SWCTRL,
 938                 },
 939         },
 940         .dev_attr       = &i2c_dev_attr,
 941 };
 942
 943 /*
 944  * 'kbd' class
 945  * keyboard controller
 946  */
 947
 948 static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = {
 949         .rev_offs       = 0x0000,
 950         .sysc_offs      = 0x0010,
 951         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
 952                            SYSC_HAS_SOFTRESET),
 953         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 954         .sysc_fields    = &omap_hwmod_sysc_type1,
 955 };
 956
 957 static struct omap_hwmod_class omap54xx_kbd_hwmod_class = {
 958         .name   = "kbd",
 959         .sysc   = &omap54xx_kbd_sysc,
 960 };
 961
 962 /* kbd */
 963 static struct omap_hwmod omap54xx_kbd_hwmod = {
 964         .name           = "kbd",
 965         .class          = &omap54xx_kbd_hwmod_class,
 966         .clkdm_name     = "wkupaon_clkdm",
 967         .main_clk       = "sys_32k_ck",
 968         .prcm = {
 969                 .omap4 = {
 970                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET,
 971                         .context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET,
 972                         .modulemode   = MODULEMODE_SWCTRL,
 973                 },
 974         },
 975 };
 976
 977 /*
 978  * 'mailbox' class
 979  * mailbox module allowing communication between the on-chip processors using a
 980  * queued mailbox-interrupt mechanism.
 981  */
 982
 983 static struct omap_hwmod_class_sysconfig omap54xx_mailbox_sysc = {
 984         .rev_offs       = 0x0000,
 985         .sysc_offs      = 0x0010,
 986         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 987                            SYSC_HAS_SOFTRESET),
 988         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 989         .sysc_fields    = &omap_hwmod_sysc_type2,
 990 };
 991
 992 static struct omap_hwmod_class omap54xx_mailbox_hwmod_class = {
 993         .name   = "mailbox",
 994         .sysc   = &omap54xx_mailbox_sysc,
 995 };
 996
 997 /* mailbox */
 998 static struct omap_hwmod omap54xx_mailbox_hwmod = {
 999         .name           = "mailbox",
1000         .class          = &omap54xx_mailbox_hwmod_class,
1001         .clkdm_name     = "l4cfg_clkdm",
1002         .prcm = {
1003                 .omap4 = {
1004                         .clkctrl_offs = OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1005                         .context_offs = OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1006                 },
1007         },
1008 };
1009
1010 /*
1011  * 'mcbsp' class
1012  * multi channel buffered serial port controller
1013  */
1014
1015 static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = {
1016         .sysc_offs      = 0x008c,
1017         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1018                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1019         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1020         .sysc_fields    = &omap_hwmod_sysc_type1,
1021 };
1022
1023 static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = {
1024         .name   = "mcbsp",
1025         .sysc   = &omap54xx_mcbsp_sysc,
1026         .rev    = MCBSP_CONFIG_TYPE4,
1027 };
1028
1029 /* mcbsp1 */
1030 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1031         { .role = "pad_fck", .clk = "pad_clks_ck" },
1032         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1033 };
1034
1035 static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
1036         .name           = "mcbsp1",
1037         .class          = &omap54xx_mcbsp_hwmod_class,
1038         .clkdm_name     = "abe_clkdm",
1039         .main_clk       = "mcbsp1_gfclk",
1040         .prcm = {
1041                 .omap4 = {
1042                         .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET,
1043                         .context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1044                         .modulemode   = MODULEMODE_SWCTRL,
1045                 },
1046         },
1047         .opt_clks       = mcbsp1_opt_clks,
1048         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1049 };
1050
1051 /* mcbsp2 */
1052 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1053         { .role = "pad_fck", .clk = "pad_clks_ck" },
1054         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1055 };
1056
1057 static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
1058         .name           = "mcbsp2",
1059         .class          = &omap54xx_mcbsp_hwmod_class,
1060         .clkdm_name     = "abe_clkdm",
1061         .main_clk       = "mcbsp2_gfclk",
1062         .prcm = {
1063                 .omap4 = {
1064                         .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET,
1065                         .context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1066                         .modulemode   = MODULEMODE_SWCTRL,
1067                 },
1068         },
1069         .opt_clks       = mcbsp2_opt_clks,
1070         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
1071 };
1072
1073 /* mcbsp3 */
1074 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
1075         { .role = "pad_fck", .clk = "pad_clks_ck" },
1076         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
1077 };
1078
1079 static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
1080         .name           = "mcbsp3",
1081         .class          = &omap54xx_mcbsp_hwmod_class,
1082         .clkdm_name     = "abe_clkdm",
1083         .main_clk       = "mcbsp3_gfclk",
1084         .prcm = {
1085                 .omap4 = {
1086                         .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET,
1087                         .context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET,
1088                         .modulemode   = MODULEMODE_SWCTRL,
1089                 },
1090         },
1091         .opt_clks       = mcbsp3_opt_clks,
1092         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
1093 };
1094
1095 /*
1096  * 'mcpdm' class
1097  * multi channel pdm controller (proprietary interface with phoenix power
1098  * ic)
1099  */
1100
1101 static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = {
1102         .rev_offs       = 0x0000,
1103         .sysc_offs      = 0x0010,
1104         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1105                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1106         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1107                            SIDLE_SMART_WKUP),
1108         .sysc_fields    = &omap_hwmod_sysc_type2,
1109 };
1110
1111 static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = {
1112         .name   = "mcpdm",
1113         .sysc   = &omap54xx_mcpdm_sysc,
1114 };
1115
1116 /* mcpdm */
1117 static struct omap_hwmod omap54xx_mcpdm_hwmod = {
1118         .name           = "mcpdm",
1119         .class          = &omap54xx_mcpdm_hwmod_class,
1120         .clkdm_name     = "abe_clkdm",
1121         /*
1122          * It's suspected that the McPDM requires an off-chip main
1123          * functional clock, controlled via I2C.  This IP block is
1124          * currently reset very early during boot, before I2C is
1125          * available, so it doesn't seem that we have any choice in
1126          * the kernel other than to avoid resetting it.  XXX This is
1127          * really a hardware issue workaround: every IP block should
1128          * be able to source its main functional clock from either
1129          * on-chip or off-chip sources.  McPDM seems to be the only
1130          * current exception.
1131          */
1132
1133         .flags          = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
1134         .main_clk       = "pad_clks_ck",
1135         .prcm = {
1136                 .omap4 = {
1137                         .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET,
1138                         .context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET,
1139                         .modulemode   = MODULEMODE_SWCTRL,
1140                 },
1141         },
1142 };
1143
1144 /*
1145  * 'mcspi' class
1146  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1147  * bus
1148  */
1149
1150 static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = {
1151         .rev_offs       = 0x0000,
1152         .sysc_offs      = 0x0010,
1153         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1154                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1155         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1156                            SIDLE_SMART_WKUP),
1157         .sysc_fields    = &omap_hwmod_sysc_type2,
1158 };
1159
1160 static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = {
1161         .name   = "mcspi",
1162         .sysc   = &omap54xx_mcspi_sysc,
1163         .rev    = OMAP4_MCSPI_REV,
1164 };
1165
1166 /* mcspi1 */
1167 /* mcspi1 dev_attr */
1168 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1169         .num_chipselect = 4,
1170 };
1171
1172 static struct omap_hwmod omap54xx_mcspi1_hwmod = {
1173         .name           = "mcspi1",
1174         .class          = &omap54xx_mcspi_hwmod_class,
1175         .clkdm_name     = "l4per_clkdm",
1176         .main_clk       = "func_48m_fclk",
1177         .prcm = {
1178                 .omap4 = {
1179                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1180                         .context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1181                         .modulemode   = MODULEMODE_SWCTRL,
1182                 },
1183         },
1184         .dev_attr       = &mcspi1_dev_attr,
1185 };
1186
1187 /* mcspi2 */
1188 /* mcspi2 dev_attr */
1189 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1190         .num_chipselect = 2,
1191 };
1192
1193 static struct omap_hwmod omap54xx_mcspi2_hwmod = {
1194         .name           = "mcspi2",
1195         .class          = &omap54xx_mcspi_hwmod_class,
1196         .clkdm_name     = "l4per_clkdm",
1197         .main_clk       = "func_48m_fclk",
1198         .prcm = {
1199                 .omap4 = {
1200                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1201                         .context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1202                         .modulemode   = MODULEMODE_SWCTRL,
1203                 },
1204         },
1205         .dev_attr       = &mcspi2_dev_attr,
1206 };
1207
1208 /* mcspi3 */
1209 /* mcspi3 dev_attr */
1210 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1211         .num_chipselect = 2,
1212 };
1213
1214 static struct omap_hwmod omap54xx_mcspi3_hwmod = {
1215         .name           = "mcspi3",
1216         .class          = &omap54xx_mcspi_hwmod_class,
1217         .clkdm_name     = "l4per_clkdm",
1218         .main_clk       = "func_48m_fclk",
1219         .prcm = {
1220                 .omap4 = {
1221                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1222                         .context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1223                         .modulemode   = MODULEMODE_SWCTRL,
1224                 },
1225         },
1226         .dev_attr       = &mcspi3_dev_attr,
1227 };
1228
1229 /* mcspi4 */
1230 /* mcspi4 dev_attr */
1231 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1232         .num_chipselect = 1,
1233 };
1234
1235 static struct omap_hwmod omap54xx_mcspi4_hwmod = {
1236         .name           = "mcspi4",
1237         .class          = &omap54xx_mcspi_hwmod_class,
1238         .clkdm_name     = "l4per_clkdm",
1239         .main_clk       = "func_48m_fclk",
1240         .prcm = {
1241                 .omap4 = {
1242                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1243                         .context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1244                         .modulemode   = MODULEMODE_SWCTRL,
1245                 },
1246         },
1247         .dev_attr       = &mcspi4_dev_attr,
1248 };
1249
1250 /*
1251  * 'mmc' class
1252  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
1253  */
1254
1255 static struct omap_hwmod_class_sysconfig omap54xx_mmc_sysc = {
1256         .rev_offs       = 0x0000,
1257         .sysc_offs      = 0x0010,
1258         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1259                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1260                            SYSC_HAS_SOFTRESET),
1261         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1262                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1263                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1264         .sysc_fields    = &omap_hwmod_sysc_type2,
1265 };
1266
1267 static struct omap_hwmod_class omap54xx_mmc_hwmod_class = {
1268         .name   = "mmc",
1269         .sysc   = &omap54xx_mmc_sysc,
1270 };
1271
1272 /* mmc1 */
1273 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1274         { .role = "32khz_clk", .clk = "mmc1_32khz_clk" },
1275 };
1276
1277 /* mmc1 dev_attr */
1278 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1279         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1280 };
1281
1282 static struct omap_hwmod omap54xx_mmc1_hwmod = {
1283         .name           = "mmc1",
1284         .class          = &omap54xx_mmc_hwmod_class,
1285         .clkdm_name     = "l3init_clkdm",
1286         .main_clk       = "mmc1_fclk",
1287         .prcm = {
1288                 .omap4 = {
1289                         .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1290                         .context_offs = OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1291                         .modulemode   = MODULEMODE_SWCTRL,
1292                 },
1293         },
1294         .opt_clks       = mmc1_opt_clks,
1295         .opt_clks_cnt   = ARRAY_SIZE(mmc1_opt_clks),
1296         .dev_attr       = &mmc1_dev_attr,
1297 };
1298
1299 /* mmc2 */
1300 static struct omap_hwmod omap54xx_mmc2_hwmod = {
1301         .name           = "mmc2",
1302         .class          = &omap54xx_mmc_hwmod_class,
1303         .clkdm_name     = "l3init_clkdm",
1304         .main_clk       = "mmc2_fclk",
1305         .prcm = {
1306                 .omap4 = {
1307                         .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1308                         .context_offs = OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1309                         .modulemode   = MODULEMODE_SWCTRL,
1310                 },
1311         },
1312 };
1313
1314 /* mmc3 */
1315 static struct omap_hwmod omap54xx_mmc3_hwmod = {
1316         .name           = "mmc3",
1317         .class          = &omap54xx_mmc_hwmod_class,
1318         .clkdm_name     = "l4per_clkdm",
1319         .main_clk       = "func_48m_fclk",
1320         .prcm = {
1321                 .omap4 = {
1322                         .clkctrl_offs = OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1323                         .context_offs = OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1324                         .modulemode   = MODULEMODE_SWCTRL,
1325                 },
1326         },
1327 };
1328
1329 /* mmc4 */
1330 static struct omap_hwmod omap54xx_mmc4_hwmod = {
1331         .name           = "mmc4",
1332         .class          = &omap54xx_mmc_hwmod_class,
1333         .clkdm_name     = "l4per_clkdm",
1334         .main_clk       = "func_48m_fclk",
1335         .prcm = {
1336                 .omap4 = {
1337                         .clkctrl_offs = OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1338                         .context_offs = OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1339                         .modulemode   = MODULEMODE_SWCTRL,
1340                 },
1341         },
1342 };
1343
1344 /* mmc5 */
1345 static struct omap_hwmod omap54xx_mmc5_hwmod = {
1346         .name           = "mmc5",
1347         .class          = &omap54xx_mmc_hwmod_class,
1348         .clkdm_name     = "l4per_clkdm",
1349         .main_clk       = "func_96m_fclk",
1350         .prcm = {
1351                 .omap4 = {
1352                         .clkctrl_offs = OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET,
1353                         .context_offs = OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET,
1354                         .modulemode   = MODULEMODE_SWCTRL,
1355                 },
1356         },
1357 };
1358
1359 /*
1360  * 'mmu' class
1361  * The memory management unit performs virtual to physical address translation
1362  * for its requestors.
1363  */
1364
1365 static struct omap_hwmod_class_sysconfig omap54xx_mmu_sysc = {
1366         .rev_offs       = 0x0000,
1367         .sysc_offs      = 0x0010,
1368         .syss_offs      = 0x0014,
1369         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1370                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1371                            SYSS_HAS_RESET_STATUS),
1372         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1373         .sysc_fields    = &omap_hwmod_sysc_type1,
1374 };
1375
1376 static struct omap_hwmod_class omap54xx_mmu_hwmod_class = {
1377         .name = "mmu",
1378         .sysc = &omap54xx_mmu_sysc,
1379 };
1380
1381 static struct omap_hwmod_rst_info omap54xx_mmu_dsp_resets[] = {
1382         { .name = "mmu_cache", .rst_shift = 1 },
1383 };
1384
1385 static struct omap_hwmod omap54xx_mmu_dsp_hwmod = {
1386         .name           = "mmu_dsp",
1387         .class          = &omap54xx_mmu_hwmod_class,
1388         .clkdm_name     = "dsp_clkdm",
1389         .rst_lines      = omap54xx_mmu_dsp_resets,
1390         .rst_lines_cnt  = ARRAY_SIZE(omap54xx_mmu_dsp_resets),
1391         .main_clk       = "dpll_iva_h11x2_ck",
1392         .prcm = {
1393                 .omap4 = {
1394                         .clkctrl_offs = OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET,
1395                         .rstctrl_offs = OMAP54XX_RM_DSP_RSTCTRL_OFFSET,
1396                         .context_offs = OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET,
1397                         .modulemode   = MODULEMODE_HWCTRL,
1398                 },
1399         },
1400 };
1401
1402 /* mmu ipu */
1403 static struct omap_hwmod_rst_info omap54xx_mmu_ipu_resets[] = {
1404         { .name = "mmu_cache", .rst_shift = 2 },
1405 };
1406
1407 static struct omap_hwmod omap54xx_mmu_ipu_hwmod = {
1408         .name           = "mmu_ipu",
1409         .class          = &omap54xx_mmu_hwmod_class,
1410         .clkdm_name     = "ipu_clkdm",
1411         .rst_lines      = omap54xx_mmu_ipu_resets,
1412         .rst_lines_cnt  = ARRAY_SIZE(omap54xx_mmu_ipu_resets),
1413         .main_clk       = "dpll_core_h22x2_ck",
1414         .prcm = {
1415                 .omap4 = {
1416                         .clkctrl_offs = OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET,
1417                         .rstctrl_offs = OMAP54XX_RM_IPU_RSTCTRL_OFFSET,
1418                         .context_offs = OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET,
1419                         .modulemode   = MODULEMODE_HWCTRL,
1420                 },
1421         },
1422 };
1423
1424 /*
1425  * 'mpu' class
1426  * mpu sub-system
1427  */
1428
1429 static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
1430         .name   = "mpu",
1431 };
1432
1433 /* mpu */
1434 static struct omap_hwmod omap54xx_mpu_hwmod = {
1435         .name           = "mpu",
1436         .class          = &omap54xx_mpu_hwmod_class,
1437         .clkdm_name     = "mpu_clkdm",
1438         .flags          = HWMOD_INIT_NO_IDLE,
1439         .main_clk       = "dpll_mpu_m2_ck",
1440         .prcm = {
1441                 .omap4 = {
1442                         .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1443                         .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
1444                 },
1445         },
1446 };
1447
1448 /*
1449  * 'spinlock' class
1450  * spinlock provides hardware assistance for synchronizing the processes
1451  * running on multiple processors
1452  */
1453
1454 static struct omap_hwmod_class_sysconfig omap54xx_spinlock_sysc = {
1455         .rev_offs       = 0x0000,
1456         .sysc_offs      = 0x0010,
1457         .syss_offs      = 0x0014,
1458         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1459                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1460                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1461         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1462         .sysc_fields    = &omap_hwmod_sysc_type1,
1463 };
1464
1465 static struct omap_hwmod_class omap54xx_spinlock_hwmod_class = {
1466         .name   = "spinlock",
1467         .sysc   = &omap54xx_spinlock_sysc,
1468 };
1469
1470 /* spinlock */
1471 static struct omap_hwmod omap54xx_spinlock_hwmod = {
1472         .name           = "spinlock",
1473         .class          = &omap54xx_spinlock_hwmod_class,
1474         .clkdm_name     = "l4cfg_clkdm",
1475         .prcm = {
1476                 .omap4 = {
1477                         .clkctrl_offs = OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1478                         .context_offs = OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1479                 },
1480         },
1481 };
1482
1483 /*
1484  * 'ocp2scp' class
1485  * bridge to transform ocp interface protocol to scp (serial control port)
1486  * protocol
1487  */
1488
1489 static struct omap_hwmod_class_sysconfig omap54xx_ocp2scp_sysc = {
1490         .rev_offs       = 0x0000,
1491         .sysc_offs      = 0x0010,
1492         .syss_offs      = 0x0014,
1493         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1494                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1495         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1496         .sysc_fields    = &omap_hwmod_sysc_type1,
1497 };
1498
1499 static struct omap_hwmod_class omap54xx_ocp2scp_hwmod_class = {
1500         .name   = "ocp2scp",
1501         .sysc   = &omap54xx_ocp2scp_sysc,
1502 };
1503
1504 /* ocp2scp1 */
1505 static struct omap_hwmod omap54xx_ocp2scp1_hwmod = {
1506         .name           = "ocp2scp1",
1507         .class          = &omap54xx_ocp2scp_hwmod_class,
1508         .clkdm_name     = "l3init_clkdm",
1509         .main_clk       = "l4_root_clk_div",
1510         .prcm = {
1511                 .omap4 = {
1512                         .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1513                         .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1514                         .modulemode   = MODULEMODE_HWCTRL,
1515                 },
1516         },
1517 };
1518
1519 /*
1520  * 'timer' class
1521  * general purpose timer module with accurate 1ms tick
1522  * This class contains several variants: ['timer_1ms', 'timer']
1523  */
1524
1525 static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
1526         .rev_offs       = 0x0000,
1527         .sysc_offs      = 0x0010,
1528         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1529                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1530         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1531                            SIDLE_SMART_WKUP),
1532         .sysc_fields    = &omap_hwmod_sysc_type2,
1533         .clockact       = CLOCKACT_TEST_ICLK,
1534 };
1535
1536 static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
1537         .name   = "timer",
1538         .sysc   = &omap54xx_timer_1ms_sysc,
1539 };
1540
1541 static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = {
1542         .rev_offs       = 0x0000,
1543         .sysc_offs      = 0x0010,
1544         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1545                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1546         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1547                            SIDLE_SMART_WKUP),
1548         .sysc_fields    = &omap_hwmod_sysc_type2,
1549 };
1550
1551 static struct omap_hwmod_class omap54xx_timer_hwmod_class = {
1552         .name   = "timer",
1553         .sysc   = &omap54xx_timer_sysc,
1554 };
1555
1556 /* timer1 */
1557 static struct omap_hwmod omap54xx_timer1_hwmod = {
1558         .name           = "timer1",
1559         .class          = &omap54xx_timer_1ms_hwmod_class,
1560         .clkdm_name     = "wkupaon_clkdm",
1561         .main_clk       = "timer1_gfclk_mux",
1562         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1563         .prcm = {
1564                 .omap4 = {
1565                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1566                         .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1567                         .modulemode   = MODULEMODE_SWCTRL,
1568                 },
1569         },
1570 };
1571
1572 /* timer2 */
1573 static struct omap_hwmod omap54xx_timer2_hwmod = {
1574         .name           = "timer2",
1575         .class          = &omap54xx_timer_1ms_hwmod_class,
1576         .clkdm_name     = "l4per_clkdm",
1577         .main_clk       = "timer2_gfclk_mux",
1578         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1579         .prcm = {
1580                 .omap4 = {
1581                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1582                         .context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1583                         .modulemode   = MODULEMODE_SWCTRL,
1584                 },
1585         },
1586 };
1587
1588 /* timer3 */
1589 static struct omap_hwmod omap54xx_timer3_hwmod = {
1590         .name           = "timer3",
1591         .class          = &omap54xx_timer_hwmod_class,
1592         .clkdm_name     = "l4per_clkdm",
1593         .main_clk       = "timer3_gfclk_mux",
1594         .prcm = {
1595                 .omap4 = {
1596                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1597                         .context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1598                         .modulemode   = MODULEMODE_SWCTRL,
1599                 },
1600         },
1601 };
1602
1603 /* timer4 */
1604 static struct omap_hwmod omap54xx_timer4_hwmod = {
1605         .name           = "timer4",
1606         .class          = &omap54xx_timer_hwmod_class,
1607         .clkdm_name     = "l4per_clkdm",
1608         .main_clk       = "timer4_gfclk_mux",
1609         .prcm = {
1610                 .omap4 = {
1611                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1612                         .context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1613                         .modulemode   = MODULEMODE_SWCTRL,
1614                 },
1615         },
1616 };
1617
1618 /* timer5 */
1619 static struct omap_hwmod omap54xx_timer5_hwmod = {
1620         .name           = "timer5",
1621         .class          = &omap54xx_timer_hwmod_class,
1622         .clkdm_name     = "abe_clkdm",
1623         .main_clk       = "timer5_gfclk_mux",
1624         .prcm = {
1625                 .omap4 = {
1626                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET,
1627                         .context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET,
1628                         .modulemode   = MODULEMODE_SWCTRL,
1629                 },
1630         },
1631 };
1632
1633 /* timer6 */
1634 static struct omap_hwmod omap54xx_timer6_hwmod = {
1635         .name           = "timer6",
1636         .class          = &omap54xx_timer_hwmod_class,
1637         .clkdm_name     = "abe_clkdm",
1638         .main_clk       = "timer6_gfclk_mux",
1639         .prcm = {
1640                 .omap4 = {
1641                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET,
1642                         .context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET,
1643                         .modulemode   = MODULEMODE_SWCTRL,
1644                 },
1645         },
1646 };
1647
1648 /* timer7 */
1649 static struct omap_hwmod omap54xx_timer7_hwmod = {
1650         .name           = "timer7",
1651         .class          = &omap54xx_timer_hwmod_class,
1652         .clkdm_name     = "abe_clkdm",
1653         .main_clk       = "timer7_gfclk_mux",
1654         .prcm = {
1655                 .omap4 = {
1656                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET,
1657                         .context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET,
1658                         .modulemode   = MODULEMODE_SWCTRL,
1659                 },
1660         },
1661 };
1662
1663 /* timer8 */
1664 static struct omap_hwmod omap54xx_timer8_hwmod = {
1665         .name           = "timer8",
1666         .class          = &omap54xx_timer_hwmod_class,
1667         .clkdm_name     = "abe_clkdm",
1668         .main_clk       = "timer8_gfclk_mux",
1669         .prcm = {
1670                 .omap4 = {
1671                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET,
1672                         .context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET,
1673                         .modulemode   = MODULEMODE_SWCTRL,
1674                 },
1675         },
1676 };
1677
1678 /* timer9 */
1679 static struct omap_hwmod omap54xx_timer9_hwmod = {
1680         .name           = "timer9",
1681         .class          = &omap54xx_timer_hwmod_class,
1682         .clkdm_name     = "l4per_clkdm",
1683         .main_clk       = "timer9_gfclk_mux",
1684         .prcm = {
1685                 .omap4 = {
1686                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1687                         .context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1688                         .modulemode   = MODULEMODE_SWCTRL,
1689                 },
1690         },
1691 };
1692
1693 /* timer10 */
1694 static struct omap_hwmod omap54xx_timer10_hwmod = {
1695         .name           = "timer10",
1696         .class          = &omap54xx_timer_1ms_hwmod_class,
1697         .clkdm_name     = "l4per_clkdm",
1698         .main_clk       = "timer10_gfclk_mux",
1699         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1700         .prcm = {
1701                 .omap4 = {
1702                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1703                         .context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1704                         .modulemode   = MODULEMODE_SWCTRL,
1705                 },
1706         },
1707 };
1708
1709 /* timer11 */
1710 static struct omap_hwmod omap54xx_timer11_hwmod = {
1711         .name           = "timer11",
1712         .class          = &omap54xx_timer_hwmod_class,
1713         .clkdm_name     = "l4per_clkdm",
1714         .main_clk       = "timer11_gfclk_mux",
1715         .prcm = {
1716                 .omap4 = {
1717                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1718                         .context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1719                         .modulemode   = MODULEMODE_SWCTRL,
1720                 },
1721         },
1722 };
1723
1724 /*
1725  * 'uart' class
1726  * universal asynchronous receiver/transmitter (uart)
1727  */
1728
1729 static struct omap_hwmod_class_sysconfig omap54xx_uart_sysc = {
1730         .rev_offs       = 0x0050,
1731         .sysc_offs      = 0x0054,
1732         .syss_offs      = 0x0058,
1733         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1734                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1735                            SYSS_HAS_RESET_STATUS),
1736         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1737                            SIDLE_SMART_WKUP),
1738         .sysc_fields    = &omap_hwmod_sysc_type1,
1739 };
1740
1741 static struct omap_hwmod_class omap54xx_uart_hwmod_class = {
1742         .name   = "uart",
1743         .sysc   = &omap54xx_uart_sysc,
1744 };
1745
1746 /* uart1 */
1747 static struct omap_hwmod omap54xx_uart1_hwmod = {
1748         .name           = "uart1",
1749         .class          = &omap54xx_uart_hwmod_class,
1750         .clkdm_name     = "l4per_clkdm",
1751         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1752         .main_clk       = "func_48m_fclk",
1753         .prcm = {
1754                 .omap4 = {
1755                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
1756                         .context_offs = OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET,
1757                         .modulemode   = MODULEMODE_SWCTRL,
1758                 },
1759         },
1760 };
1761
1762 /* uart2 */
1763 static struct omap_hwmod omap54xx_uart2_hwmod = {
1764         .name           = "uart2",
1765         .class          = &omap54xx_uart_hwmod_class,
1766         .clkdm_name     = "l4per_clkdm",
1767         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1768         .main_clk       = "func_48m_fclk",
1769         .prcm = {
1770                 .omap4 = {
1771                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
1772                         .context_offs = OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET,
1773                         .modulemode   = MODULEMODE_SWCTRL,
1774                 },
1775         },
1776 };
1777
1778 /* uart3 */
1779 static struct omap_hwmod omap54xx_uart3_hwmod = {
1780         .name           = "uart3",
1781         .class          = &omap54xx_uart_hwmod_class,
1782         .clkdm_name     = "l4per_clkdm",
1783         .flags          = DEBUG_OMAP4UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
1784         .main_clk       = "func_48m_fclk",
1785         .prcm = {
1786                 .omap4 = {
1787                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
1788                         .context_offs = OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET,
1789                         .modulemode   = MODULEMODE_SWCTRL,
1790                 },
1791         },
1792 };
1793
1794 /* uart4 */
1795 static struct omap_hwmod omap54xx_uart4_hwmod = {
1796         .name           = "uart4",
1797         .class          = &omap54xx_uart_hwmod_class,
1798         .clkdm_name     = "l4per_clkdm",
1799         .flags          = DEBUG_OMAP4UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
1800         .main_clk       = "func_48m_fclk",
1801         .prcm = {
1802                 .omap4 = {
1803                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
1804                         .context_offs = OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET,
1805                         .modulemode   = MODULEMODE_SWCTRL,
1806                 },
1807         },
1808 };
1809
1810 /* uart5 */
1811 static struct omap_hwmod omap54xx_uart5_hwmod = {
1812         .name           = "uart5",
1813         .class          = &omap54xx_uart_hwmod_class,
1814         .clkdm_name     = "l4per_clkdm",
1815         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1816         .main_clk       = "func_48m_fclk",
1817         .prcm = {
1818                 .omap4 = {
1819                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
1820                         .context_offs = OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET,
1821                         .modulemode   = MODULEMODE_SWCTRL,
1822                 },
1823         },
1824 };
1825
1826 /* uart6 */
1827 static struct omap_hwmod omap54xx_uart6_hwmod = {
1828         .name           = "uart6",
1829         .class          = &omap54xx_uart_hwmod_class,
1830         .clkdm_name     = "l4per_clkdm",
1831         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1832         .main_clk       = "func_48m_fclk",
1833         .prcm = {
1834                 .omap4 = {
1835                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET,
1836                         .context_offs = OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET,
1837                         .modulemode   = MODULEMODE_SWCTRL,
1838                 },
1839         },
1840 };
1841
1842 /*
1843  * 'usb_host_hs' class
1844  * high-speed multi-port usb host controller
1845  */
1846
1847 static struct omap_hwmod_class_sysconfig omap54xx_usb_host_hs_sysc = {
1848         .rev_offs       = 0x0000,
1849         .sysc_offs      = 0x0010,
1850         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1851                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1852         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1853                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1854                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1855         .sysc_fields    = &omap_hwmod_sysc_type2,
1856 };
1857
1858 static struct omap_hwmod_class omap54xx_usb_host_hs_hwmod_class = {
1859         .name   = "usb_host_hs",
1860         .sysc   = &omap54xx_usb_host_hs_sysc,
1861 };
1862
1863 static struct omap_hwmod omap54xx_usb_host_hs_hwmod = {
1864         .name           = "usb_host_hs",
1865         .class          = &omap54xx_usb_host_hs_hwmod_class,
1866         .clkdm_name     = "l3init_clkdm",
1867         /*
1868          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1869          * id: i660
1870          *
1871          * Description:
1872          * In the following configuration :
1873          * - USBHOST module is set to smart-idle mode
1874          * - PRCM asserts idle_req to the USBHOST module ( This typically
1875          *   happens when the system is going to a low power mode : all ports
1876          *   have been suspended, the master part of the USBHOST module has
1877          *   entered the standby state, and SW has cut the functional clocks)
1878          * - an USBHOST interrupt occurs before the module is able to answer
1879          *   idle_ack, typically a remote wakeup IRQ.
1880          * Then the USB HOST module will enter a deadlock situation where it
1881          * is no more accessible nor functional.
1882          *
1883          * Workaround:
1884          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1885          */
1886
1887         /*
1888          * Errata: USB host EHCI may stall when entering smart-standby mode
1889          * Id: i571
1890          *
1891          * Description:
1892          * When the USBHOST module is set to smart-standby mode, and when it is
1893          * ready to enter the standby state (i.e. all ports are suspended and
1894          * all attached devices are in suspend mode), then it can wrongly assert
1895          * the Mstandby signal too early while there are still some residual OCP
1896          * transactions ongoing. If this condition occurs, the internal state
1897          * machine may go to an undefined state and the USB link may be stuck
1898          * upon the next resume.
1899          *
1900          * Workaround:
1901          * Don't use smart standby; use only force standby,
1902          * hence HWMOD_SWSUP_MSTANDBY
1903          */
1904
1905         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1906         .main_clk       = "l3init_60m_fclk",
1907         .prcm = {
1908                 .omap4 = {
1909                         .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET,
1910                         .context_offs = OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET,
1911                         .modulemode   = MODULEMODE_SWCTRL,
1912                 },
1913         },
1914 };
1915
1916 /*
1917  * 'usb_tll_hs' class
1918  * usb_tll_hs module is the adapter on the usb_host_hs ports
1919  */
1920
1921 static struct omap_hwmod_class_sysconfig omap54xx_usb_tll_hs_sysc = {
1922         .rev_offs       = 0x0000,
1923         .sysc_offs      = 0x0010,
1924         .syss_offs      = 0x0014,
1925         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1926                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1927                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1928         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1929         .sysc_fields    = &omap_hwmod_sysc_type1,
1930 };
1931
1932 static struct omap_hwmod_class omap54xx_usb_tll_hs_hwmod_class = {
1933         .name   = "usb_tll_hs",
1934         .sysc   = &omap54xx_usb_tll_hs_sysc,
1935 };
1936
1937 static struct omap_hwmod omap54xx_usb_tll_hs_hwmod = {
1938         .name           = "usb_tll_hs",
1939         .class          = &omap54xx_usb_tll_hs_hwmod_class,
1940         .clkdm_name     = "l3init_clkdm",
1941         .main_clk       = "l4_root_clk_div",
1942         .prcm = {
1943                 .omap4 = {
1944                         .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET,
1945                         .context_offs = OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET,
1946                         .modulemode   = MODULEMODE_HWCTRL,
1947                 },
1948         },
1949 };
1950
1951 /*
1952  * 'usb_otg_ss' class
1953  * 2.0 super speed (usb_otg_ss) controller
1954  */
1955
1956 static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
1957         .rev_offs       = 0x0000,
1958         .sysc_offs      = 0x0010,
1959         .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
1960                            SYSC_HAS_SIDLEMODE),
1961         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1962                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1963                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1964         .sysc_fields    = &omap_hwmod_sysc_type2,
1965 };
1966
1967 static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
1968         .name   = "usb_otg_ss",
1969         .sysc   = &omap54xx_usb_otg_ss_sysc,
1970 };
1971
1972 /* usb_otg_ss */
1973 static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
1974         { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
1975 };
1976
1977 static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
1978         .name           = "usb_otg_ss",
1979         .class          = &omap54xx_usb_otg_ss_hwmod_class,
1980         .clkdm_name     = "l3init_clkdm",
1981         .flags          = HWMOD_SWSUP_SIDLE,
1982         .main_clk       = "dpll_core_h13x2_ck",
1983         .prcm = {
1984                 .omap4 = {
1985                         .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
1986                         .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET,
1987                         .modulemode   = MODULEMODE_HWCTRL,
1988                 },
1989         },
1990         .opt_clks       = usb_otg_ss_opt_clks,
1991         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss_opt_clks),
1992 };
1993
1994 /*
1995  * 'wd_timer' class
1996  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1997  * overflow condition
1998  */
1999
2000 static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc = {
2001         .rev_offs       = 0x0000,
2002         .sysc_offs      = 0x0010,
2003         .syss_offs      = 0x0014,
2004         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2005                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2006         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2007                            SIDLE_SMART_WKUP),
2008         .sysc_fields    = &omap_hwmod_sysc_type1,
2009 };
2010
2011 static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class = {
2012         .name           = "wd_timer",
2013         .sysc           = &omap54xx_wd_timer_sysc,
2014         .pre_shutdown   = &omap2_wd_timer_disable,
2015 };
2016
2017 /* wd_timer2 */
2018 static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
2019         .name           = "wd_timer2",
2020         .class          = &omap54xx_wd_timer_hwmod_class,
2021         .clkdm_name     = "wkupaon_clkdm",
2022         .main_clk       = "sys_32k_ck",
2023         .prcm = {
2024                 .omap4 = {
2025                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2026                         .context_offs = OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2027                         .modulemode   = MODULEMODE_SWCTRL,
2028                 },
2029         },
2030 };
2031
2032 /*
2033  * 'ocp2scp' class
2034  * bridge to transform ocp interface protocol to scp (serial control port)
2035  * protocol
2036  */
2037 /* ocp2scp3 */
2038 static struct omap_hwmod omap54xx_ocp2scp3_hwmod;
2039 /* l4_cfg -> ocp2scp3 */
2040 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp3 = {
2041         .master         = &omap54xx_l4_cfg_hwmod,
2042         .slave          = &omap54xx_ocp2scp3_hwmod,
2043         .clk            = "l4_root_clk_div",
2044         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2045 };
2046
2047 static struct omap_hwmod omap54xx_ocp2scp3_hwmod = {
2048         .name           = "ocp2scp3",
2049         .class          = &omap54xx_ocp2scp_hwmod_class,
2050         .clkdm_name     = "l3init_clkdm",
2051         .prcm = {
2052                 .omap4 = {
2053                         .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
2054                         .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
2055                         .modulemode   = MODULEMODE_HWCTRL,
2056                 },
2057         },
2058 };
2059
2060 /*
2061  * 'sata' class
2062  * sata:  serial ata interface  gen2 compliant   ( 1 rx/ 1 tx)
2063  */
2064
2065 static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
2066         .sysc_offs      = 0x0000,
2067         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
2068         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2069                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2070                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2071         .sysc_fields    = &omap_hwmod_sysc_type2,
2072 };
2073
2074 static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
2075         .name   = "sata",
2076         .sysc   = &omap54xx_sata_sysc,
2077 };
2078
2079 /* sata */
2080 static struct omap_hwmod omap54xx_sata_hwmod = {
2081         .name           = "sata",
2082         .class          = &omap54xx_sata_hwmod_class,
2083         .clkdm_name     = "l3init_clkdm",
2084         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2085         .main_clk       = "func_48m_fclk",
2086         .mpu_rt_idx     = 1,
2087         .prcm = {
2088                 .omap4 = {
2089                         .clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
2090                         .context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
2091                         .modulemode   = MODULEMODE_SWCTRL,
2092                 },
2093         },
2094 };
2095
2096 /* l4_cfg -> sata */
2097 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = {
2098         .master         = &omap54xx_l4_cfg_hwmod,
2099         .slave          = &omap54xx_sata_hwmod,
2100         .clk            = "l3_iclk_div",
2101         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2102 };
2103
2104 /*
2105  * Interfaces
2106  */
2107
2108 /* l3_main_1 -> dmm */
2109 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
2110         .master         = &omap54xx_l3_main_1_hwmod,
2111         .slave          = &omap54xx_dmm_hwmod,
2112         .clk            = "l3_iclk_div",
2113         .user           = OCP_USER_SDMA,
2114 };
2115
2116 /* l3_main_3 -> l3_instr */
2117 static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
2118         .master         = &omap54xx_l3_main_3_hwmod,
2119         .slave          = &omap54xx_l3_instr_hwmod,
2120         .clk            = "l3_iclk_div",
2121         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2122 };
2123
2124 /* l3_main_2 -> l3_main_1 */
2125 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
2126         .master         = &omap54xx_l3_main_2_hwmod,
2127         .slave          = &omap54xx_l3_main_1_hwmod,
2128         .clk            = "l3_iclk_div",
2129         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2130 };
2131
2132 /* l4_cfg -> l3_main_1 */
2133 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
2134         .master         = &omap54xx_l4_cfg_hwmod,
2135         .slave          = &omap54xx_l3_main_1_hwmod,
2136         .clk            = "l3_iclk_div",
2137         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2138 };
2139
2140 /* l4_cfg -> mmu_dsp */
2141 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mmu_dsp = {
2142         .master         = &omap54xx_l4_cfg_hwmod,
2143         .slave          = &omap54xx_mmu_dsp_hwmod,
2144         .clk            = "l4_root_clk_div",
2145         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2146 };
2147
2148 /* mpu -> l3_main_1 */
2149 static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
2150         .master         = &omap54xx_mpu_hwmod,
2151         .slave          = &omap54xx_l3_main_1_hwmod,
2152         .clk            = "l3_iclk_div",
2153         .user           = OCP_USER_MPU,
2154 };
2155
2156 /* l3_main_1 -> l3_main_2 */
2157 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
2158         .master         = &omap54xx_l3_main_1_hwmod,
2159         .slave          = &omap54xx_l3_main_2_hwmod,
2160         .clk            = "l3_iclk_div",
2161         .user           = OCP_USER_MPU,
2162 };
2163
2164 /* l4_cfg -> l3_main_2 */
2165 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
2166         .master         = &omap54xx_l4_cfg_hwmod,
2167         .slave          = &omap54xx_l3_main_2_hwmod,
2168         .clk            = "l3_iclk_div",
2169         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2170 };
2171
2172 /* l3_main_2 -> mmu_ipu */
2173 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__mmu_ipu = {
2174         .master         = &omap54xx_l3_main_2_hwmod,
2175         .slave          = &omap54xx_mmu_ipu_hwmod,
2176         .clk            = "l3_iclk_div",
2177         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2178 };
2179
2180 /* l3_main_1 -> l3_main_3 */
2181 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
2182         .master         = &omap54xx_l3_main_1_hwmod,
2183         .slave          = &omap54xx_l3_main_3_hwmod,
2184         .clk            = "l3_iclk_div",
2185         .user           = OCP_USER_MPU,
2186 };
2187
2188 /* l3_main_2 -> l3_main_3 */
2189 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
2190         .master         = &omap54xx_l3_main_2_hwmod,
2191         .slave          = &omap54xx_l3_main_3_hwmod,
2192         .clk            = "l3_iclk_div",
2193         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2194 };
2195
2196 /* l4_cfg -> l3_main_3 */
2197 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
2198         .master         = &omap54xx_l4_cfg_hwmod,
2199         .slave          = &omap54xx_l3_main_3_hwmod,
2200         .clk            = "l3_iclk_div",
2201         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2202 };
2203
2204 /* l3_main_1 -> l4_abe */
2205 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
2206         .master         = &omap54xx_l3_main_1_hwmod,
2207         .slave          = &omap54xx_l4_abe_hwmod,
2208         .clk            = "abe_iclk",
2209         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2210 };
2211
2212 /* mpu -> l4_abe */
2213 static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
2214         .master         = &omap54xx_mpu_hwmod,
2215         .slave          = &omap54xx_l4_abe_hwmod,
2216         .clk            = "abe_iclk",
2217         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2218 };
2219
2220 /* l3_main_1 -> l4_cfg */
2221 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
2222         .master         = &omap54xx_l3_main_1_hwmod,
2223         .slave          = &omap54xx_l4_cfg_hwmod,
2224         .clk            = "l4_root_clk_div",
2225         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2226 };
2227
2228 /* l3_main_2 -> l4_per */
2229 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
2230         .master         = &omap54xx_l3_main_2_hwmod,
2231         .slave          = &omap54xx_l4_per_hwmod,
2232         .clk            = "l4_root_clk_div",
2233         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2234 };
2235
2236 /* l3_main_1 -> l4_wkup */
2237 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
2238         .master         = &omap54xx_l3_main_1_hwmod,
2239         .slave          = &omap54xx_l4_wkup_hwmod,
2240         .clk            = "wkupaon_iclk_mux",
2241         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2242 };
2243
2244 /* mpu -> mpu_private */
2245 static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
2246         .master         = &omap54xx_mpu_hwmod,
2247         .slave          = &omap54xx_mpu_private_hwmod,
2248         .clk            = "l3_iclk_div",
2249         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2250 };
2251
2252 /* l4_wkup -> counter_32k */
2253 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
2254         .master         = &omap54xx_l4_wkup_hwmod,
2255         .slave          = &omap54xx_counter_32k_hwmod,
2256         .clk            = "wkupaon_iclk_mux",
2257         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2258 };
2259
2260 static struct omap_hwmod_addr_space omap54xx_dma_system_addrs[] = {
2261         {
2262                 .pa_start       = 0x4a056000,
2263                 .pa_end         = 0x4a056fff,
2264                 .flags          = ADDR_TYPE_RT
2265         },
2266         { }
2267 };
2268
2269 /* l4_cfg -> dma_system */
2270 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = {
2271         .master         = &omap54xx_l4_cfg_hwmod,
2272         .slave          = &omap54xx_dma_system_hwmod,
2273         .clk            = "l4_root_clk_div",
2274         .addr           = omap54xx_dma_system_addrs,
2275         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2276 };
2277
2278 /* l4_abe -> dmic */
2279 static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = {
2280         .master         = &omap54xx_l4_abe_hwmod,
2281         .slave          = &omap54xx_dmic_hwmod,
2282         .clk            = "abe_iclk",
2283         .user           = OCP_USER_MPU,
2284 };
2285
2286 /* l3_main_2 -> dss */
2287 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss = {
2288         .master         = &omap54xx_l3_main_2_hwmod,
2289         .slave          = &omap54xx_dss_hwmod,
2290         .clk            = "l3_iclk_div",
2291         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2292 };
2293
2294 /* l3_main_2 -> dss_dispc */
2295 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dispc = {
2296         .master         = &omap54xx_l3_main_2_hwmod,
2297         .slave          = &omap54xx_dss_dispc_hwmod,
2298         .clk            = "l3_iclk_div",
2299         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2300 };
2301
2302 /* l3_main_2 -> dss_dsi1_a */
2303 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_a = {
2304         .master         = &omap54xx_l3_main_2_hwmod,
2305         .slave          = &omap54xx_dss_dsi1_a_hwmod,
2306         .clk            = "l3_iclk_div",
2307         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2308 };
2309
2310 /* l3_main_2 -> dss_dsi1_c */
2311 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_c = {
2312         .master         = &omap54xx_l3_main_2_hwmod,
2313         .slave          = &omap54xx_dss_dsi1_c_hwmod,
2314         .clk            = "l3_iclk_div",
2315         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2316 };
2317
2318 /* l3_main_2 -> dss_hdmi */
2319 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_hdmi = {
2320         .master         = &omap54xx_l3_main_2_hwmod,
2321         .slave          = &omap54xx_dss_hdmi_hwmod,
2322         .clk            = "l3_iclk_div",
2323         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2324 };
2325
2326 /* l3_main_2 -> dss_rfbi */
2327 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_rfbi = {
2328         .master         = &omap54xx_l3_main_2_hwmod,
2329         .slave          = &omap54xx_dss_rfbi_hwmod,
2330         .clk            = "l3_iclk_div",
2331         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2332 };
2333
2334 /* mpu -> emif1 */
2335 static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
2336         .master         = &omap54xx_mpu_hwmod,
2337         .slave          = &omap54xx_emif1_hwmod,
2338         .clk            = "dpll_core_h11x2_ck",
2339         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2340 };
2341
2342 /* mpu -> emif2 */
2343 static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
2344         .master         = &omap54xx_mpu_hwmod,
2345         .slave          = &omap54xx_emif2_hwmod,
2346         .clk            = "dpll_core_h11x2_ck",
2347         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2348 };
2349
2350 /* l4_wkup -> gpio1 */
2351 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__gpio1 = {
2352         .master         = &omap54xx_l4_wkup_hwmod,
2353         .slave          = &omap54xx_gpio1_hwmod,
2354         .clk            = "wkupaon_iclk_mux",
2355         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2356 };
2357
2358 /* l4_per -> gpio2 */
2359 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio2 = {
2360         .master         = &omap54xx_l4_per_hwmod,
2361         .slave          = &omap54xx_gpio2_hwmod,
2362         .clk            = "l4_root_clk_div",
2363         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2364 };
2365
2366 /* l4_per -> gpio3 */
2367 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio3 = {
2368         .master         = &omap54xx_l4_per_hwmod,
2369         .slave          = &omap54xx_gpio3_hwmod,
2370         .clk            = "l4_root_clk_div",
2371         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2372 };
2373
2374 /* l4_per -> gpio4 */
2375 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio4 = {
2376         .master         = &omap54xx_l4_per_hwmod,
2377         .slave          = &omap54xx_gpio4_hwmod,
2378         .clk            = "l4_root_clk_div",
2379         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2380 };
2381
2382 /* l4_per -> gpio5 */
2383 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio5 = {
2384         .master         = &omap54xx_l4_per_hwmod,
2385         .slave          = &omap54xx_gpio5_hwmod,
2386         .clk            = "l4_root_clk_div",
2387         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2388 };
2389
2390 /* l4_per -> gpio6 */
2391 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio6 = {
2392         .master         = &omap54xx_l4_per_hwmod,
2393         .slave          = &omap54xx_gpio6_hwmod,
2394         .clk            = "l4_root_clk_div",
2395         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2396 };
2397
2398 /* l4_per -> gpio7 */
2399 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio7 = {
2400         .master         = &omap54xx_l4_per_hwmod,
2401         .slave          = &omap54xx_gpio7_hwmod,
2402         .clk            = "l4_root_clk_div",
2403         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2404 };
2405
2406 /* l4_per -> gpio8 */
2407 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio8 = {
2408         .master         = &omap54xx_l4_per_hwmod,
2409         .slave          = &omap54xx_gpio8_hwmod,
2410         .clk            = "l4_root_clk_div",
2411         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2412 };
2413
2414 /* l4_per -> i2c1 */
2415 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c1 = {
2416         .master         = &omap54xx_l4_per_hwmod,
2417         .slave          = &omap54xx_i2c1_hwmod,
2418         .clk            = "l4_root_clk_div",
2419         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2420 };
2421
2422 /* l4_per -> i2c2 */
2423 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c2 = {
2424         .master         = &omap54xx_l4_per_hwmod,
2425         .slave          = &omap54xx_i2c2_hwmod,
2426         .clk            = "l4_root_clk_div",
2427         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2428 };
2429
2430 /* l4_per -> i2c3 */
2431 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c3 = {
2432         .master         = &omap54xx_l4_per_hwmod,
2433         .slave          = &omap54xx_i2c3_hwmod,
2434         .clk            = "l4_root_clk_div",
2435         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2436 };
2437
2438 /* l4_per -> i2c4 */
2439 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c4 = {
2440         .master         = &omap54xx_l4_per_hwmod,
2441         .slave          = &omap54xx_i2c4_hwmod,
2442         .clk            = "l4_root_clk_div",
2443         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2444 };
2445
2446 /* l4_per -> i2c5 */
2447 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c5 = {
2448         .master         = &omap54xx_l4_per_hwmod,
2449         .slave          = &omap54xx_i2c5_hwmod,
2450         .clk            = "l4_root_clk_div",
2451         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2452 };
2453
2454 /* l4_wkup -> kbd */
2455 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
2456         .master         = &omap54xx_l4_wkup_hwmod,
2457         .slave          = &omap54xx_kbd_hwmod,
2458         .clk            = "wkupaon_iclk_mux",
2459         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2460 };
2461
2462 /* l4_cfg -> mailbox */
2463 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mailbox = {
2464         .master         = &omap54xx_l4_cfg_hwmod,
2465         .slave          = &omap54xx_mailbox_hwmod,
2466         .clk            = "l4_root_clk_div",
2467         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2468 };
2469
2470 /* l4_abe -> mcbsp1 */
2471 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
2472         .master         = &omap54xx_l4_abe_hwmod,
2473         .slave          = &omap54xx_mcbsp1_hwmod,
2474         .clk            = "abe_iclk",
2475         .user           = OCP_USER_MPU,
2476 };
2477
2478 /* l4_abe -> mcbsp2 */
2479 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2 = {
2480         .master         = &omap54xx_l4_abe_hwmod,
2481         .slave          = &omap54xx_mcbsp2_hwmod,
2482         .clk            = "abe_iclk",
2483         .user           = OCP_USER_MPU,
2484 };
2485
2486 /* l4_abe -> mcbsp3 */
2487 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3 = {
2488         .master         = &omap54xx_l4_abe_hwmod,
2489         .slave          = &omap54xx_mcbsp3_hwmod,
2490         .clk            = "abe_iclk",
2491         .user           = OCP_USER_MPU,
2492 };
2493
2494 /* l4_abe -> mcpdm */
2495 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = {
2496         .master         = &omap54xx_l4_abe_hwmod,
2497         .slave          = &omap54xx_mcpdm_hwmod,
2498         .clk            = "abe_iclk",
2499         .user           = OCP_USER_MPU,
2500 };
2501
2502 /* l4_per -> mcspi1 */
2503 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1 = {
2504         .master         = &omap54xx_l4_per_hwmod,
2505         .slave          = &omap54xx_mcspi1_hwmod,
2506         .clk            = "l4_root_clk_div",
2507         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2508 };
2509
2510 /* l4_per -> mcspi2 */
2511 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2 = {
2512         .master         = &omap54xx_l4_per_hwmod,
2513         .slave          = &omap54xx_mcspi2_hwmod,
2514         .clk            = "l4_root_clk_div",
2515         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2516 };
2517
2518 /* l4_per -> mcspi3 */
2519 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3 = {
2520         .master         = &omap54xx_l4_per_hwmod,
2521         .slave          = &omap54xx_mcspi3_hwmod,
2522         .clk            = "l4_root_clk_div",
2523         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2524 };
2525
2526 /* l4_per -> mcspi4 */
2527 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = {
2528         .master         = &omap54xx_l4_per_hwmod,
2529         .slave          = &omap54xx_mcspi4_hwmod,
2530         .clk            = "l4_root_clk_div",
2531         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2532 };
2533
2534 /* l4_per -> mmc1 */
2535 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc1 = {
2536         .master         = &omap54xx_l4_per_hwmod,
2537         .slave          = &omap54xx_mmc1_hwmod,
2538         .clk            = "l3_iclk_div",
2539         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2540 };
2541
2542 /* l4_per -> mmc2 */
2543 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc2 = {
2544         .master         = &omap54xx_l4_per_hwmod,
2545         .slave          = &omap54xx_mmc2_hwmod,
2546         .clk            = "l3_iclk_div",
2547         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2548 };
2549
2550 /* l4_per -> mmc3 */
2551 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc3 = {
2552         .master         = &omap54xx_l4_per_hwmod,
2553         .slave          = &omap54xx_mmc3_hwmod,
2554         .clk            = "l4_root_clk_div",
2555         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2556 };
2557
2558 /* l4_per -> mmc4 */
2559 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc4 = {
2560         .master         = &omap54xx_l4_per_hwmod,
2561         .slave          = &omap54xx_mmc4_hwmod,
2562         .clk            = "l4_root_clk_div",
2563         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2564 };
2565
2566 /* l4_per -> mmc5 */
2567 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc5 = {
2568         .master         = &omap54xx_l4_per_hwmod,
2569         .slave          = &omap54xx_mmc5_hwmod,
2570         .clk            = "l4_root_clk_div",
2571         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2572 };
2573
2574 /* l4_cfg -> mpu */
2575 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
2576         .master         = &omap54xx_l4_cfg_hwmod,
2577         .slave          = &omap54xx_mpu_hwmod,
2578         .clk            = "l4_root_clk_div",
2579         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2580 };
2581
2582 /* l4_cfg -> spinlock */
2583 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__spinlock = {
2584         .master         = &omap54xx_l4_cfg_hwmod,
2585         .slave          = &omap54xx_spinlock_hwmod,
2586         .clk            = "l4_root_clk_div",
2587         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2588 };
2589
2590 /* l4_cfg -> ocp2scp1 */
2591 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp1 = {
2592         .master         = &omap54xx_l4_cfg_hwmod,
2593         .slave          = &omap54xx_ocp2scp1_hwmod,
2594         .clk            = "l4_root_clk_div",
2595         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2596 };
2597
2598 /* l4_wkup -> timer1 */
2599 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
2600         .master         = &omap54xx_l4_wkup_hwmod,
2601         .slave          = &omap54xx_timer1_hwmod,
2602         .clk            = "wkupaon_iclk_mux",
2603         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2604 };
2605
2606 /* l4_per -> timer2 */
2607 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = {
2608         .master         = &omap54xx_l4_per_hwmod,
2609         .slave          = &omap54xx_timer2_hwmod,
2610         .clk            = "l4_root_clk_div",
2611         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2612 };
2613
2614 /* l4_per -> timer3 */
2615 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = {
2616         .master         = &omap54xx_l4_per_hwmod,
2617         .slave          = &omap54xx_timer3_hwmod,
2618         .clk            = "l4_root_clk_div",
2619         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2620 };
2621
2622 /* l4_per -> timer4 */
2623 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = {
2624         .master         = &omap54xx_l4_per_hwmod,
2625         .slave          = &omap54xx_timer4_hwmod,
2626         .clk            = "l4_root_clk_div",
2627         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2628 };
2629
2630 /* l4_abe -> timer5 */
2631 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = {
2632         .master         = &omap54xx_l4_abe_hwmod,
2633         .slave          = &omap54xx_timer5_hwmod,
2634         .clk            = "abe_iclk",
2635         .user           = OCP_USER_MPU,
2636 };
2637
2638 /* l4_abe -> timer6 */
2639 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = {
2640         .master         = &omap54xx_l4_abe_hwmod,
2641         .slave          = &omap54xx_timer6_hwmod,
2642         .clk            = "abe_iclk",
2643         .user           = OCP_USER_MPU,
2644 };
2645
2646 /* l4_abe -> timer7 */
2647 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = {
2648         .master         = &omap54xx_l4_abe_hwmod,
2649         .slave          = &omap54xx_timer7_hwmod,
2650         .clk            = "abe_iclk",
2651         .user           = OCP_USER_MPU,
2652 };
2653
2654 /* l4_abe -> timer8 */
2655 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = {
2656         .master         = &omap54xx_l4_abe_hwmod,
2657         .slave          = &omap54xx_timer8_hwmod,
2658         .clk            = "abe_iclk",
2659         .user           = OCP_USER_MPU,
2660 };
2661
2662 /* l4_per -> timer9 */
2663 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = {
2664         .master         = &omap54xx_l4_per_hwmod,
2665         .slave          = &omap54xx_timer9_hwmod,
2666         .clk            = "l4_root_clk_div",
2667         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2668 };
2669
2670 /* l4_per -> timer10 */
2671 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = {
2672         .master         = &omap54xx_l4_per_hwmod,
2673         .slave          = &omap54xx_timer10_hwmod,
2674         .clk            = "l4_root_clk_div",
2675         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2676 };
2677
2678 /* l4_per -> timer11 */
2679 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = {
2680         .master         = &omap54xx_l4_per_hwmod,
2681         .slave          = &omap54xx_timer11_hwmod,
2682         .clk            = "l4_root_clk_div",
2683         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2684 };
2685
2686 /* l4_per -> uart1 */
2687 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart1 = {
2688         .master         = &omap54xx_l4_per_hwmod,
2689         .slave          = &omap54xx_uart1_hwmod,
2690         .clk            = "l4_root_clk_div",
2691         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2692 };
2693
2694 /* l4_per -> uart2 */
2695 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart2 = {
2696         .master         = &omap54xx_l4_per_hwmod,
2697         .slave          = &omap54xx_uart2_hwmod,
2698         .clk            = "l4_root_clk_div",
2699         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2700 };
2701
2702 /* l4_per -> uart3 */
2703 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart3 = {
2704         .master         = &omap54xx_l4_per_hwmod,
2705         .slave          = &omap54xx_uart3_hwmod,
2706         .clk            = "l4_root_clk_div",
2707         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2708 };
2709
2710 /* l4_per -> uart4 */
2711 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart4 = {
2712         .master         = &omap54xx_l4_per_hwmod,
2713         .slave          = &omap54xx_uart4_hwmod,
2714         .clk            = "l4_root_clk_div",
2715         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2716 };
2717
2718 /* l4_per -> uart5 */
2719 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart5 = {
2720         .master         = &omap54xx_l4_per_hwmod,
2721         .slave          = &omap54xx_uart5_hwmod,
2722         .clk            = "l4_root_clk_div",
2723         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2724 };
2725
2726 /* l4_per -> uart6 */
2727 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = {
2728         .master         = &omap54xx_l4_per_hwmod,
2729         .slave          = &omap54xx_uart6_hwmod,
2730         .clk            = "l4_root_clk_div",
2731         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2732 };
2733
2734 /* l4_cfg -> usb_host_hs */
2735 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs = {
2736         .master         = &omap54xx_l4_cfg_hwmod,
2737         .slave          = &omap54xx_usb_host_hs_hwmod,
2738         .clk            = "l3_iclk_div",
2739         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2740 };
2741
2742 /* l4_cfg -> usb_tll_hs */
2743 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_tll_hs = {
2744         .master         = &omap54xx_l4_cfg_hwmod,
2745         .slave          = &omap54xx_usb_tll_hs_hwmod,
2746         .clk            = "l4_root_clk_div",
2747         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2748 };
2749
2750 /* l4_cfg -> usb_otg_ss */
2751 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
2752         .master         = &omap54xx_l4_cfg_hwmod,
2753         .slave          = &omap54xx_usb_otg_ss_hwmod,
2754         .clk            = "dpll_core_h13x2_ck",
2755         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2756 };
2757
2758 /* l4_wkup -> wd_timer2 */
2759 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2 = {
2760         .master         = &omap54xx_l4_wkup_hwmod,
2761         .slave          = &omap54xx_wd_timer2_hwmod,
2762         .clk            = "wkupaon_iclk_mux",
2763         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2764 };
2765
2766 static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
2767         &omap54xx_l3_main_1__dmm,
2768         &omap54xx_l3_main_3__l3_instr,
2769         &omap54xx_l3_main_2__l3_main_1,
2770         &omap54xx_l4_cfg__l3_main_1,
2771         &omap54xx_mpu__l3_main_1,
2772         &omap54xx_l3_main_1__l3_main_2,
2773         &omap54xx_l4_cfg__l3_main_2,
2774         &omap54xx_l3_main_1__l3_main_3,
2775         &omap54xx_l3_main_2__l3_main_3,
2776         &omap54xx_l4_cfg__l3_main_3,
2777         &omap54xx_l3_main_1__l4_abe,
2778         &omap54xx_mpu__l4_abe,
2779         &omap54xx_l3_main_1__l4_cfg,
2780         &omap54xx_l3_main_2__l4_per,
2781         &omap54xx_l3_main_1__l4_wkup,
2782         &omap54xx_mpu__mpu_private,
2783         &omap54xx_l4_wkup__counter_32k,
2784         &omap54xx_l4_cfg__dma_system,
2785         &omap54xx_l4_abe__dmic,
2786         &omap54xx_l4_cfg__mmu_dsp,
2787         &omap54xx_l3_main_2__dss,
2788         &omap54xx_l3_main_2__dss_dispc,
2789         &omap54xx_l3_main_2__dss_dsi1_a,
2790         &omap54xx_l3_main_2__dss_dsi1_c,
2791         &omap54xx_l3_main_2__dss_hdmi,
2792         &omap54xx_l3_main_2__dss_rfbi,
2793         &omap54xx_mpu__emif1,
2794         &omap54xx_mpu__emif2,
2795         &omap54xx_l4_wkup__gpio1,
2796         &omap54xx_l4_per__gpio2,
2797         &omap54xx_l4_per__gpio3,
2798         &omap54xx_l4_per__gpio4,
2799         &omap54xx_l4_per__gpio5,
2800         &omap54xx_l4_per__gpio6,
2801         &omap54xx_l4_per__gpio7,
2802         &omap54xx_l4_per__gpio8,
2803         &omap54xx_l4_per__i2c1,
2804         &omap54xx_l4_per__i2c2,
2805         &omap54xx_l4_per__i2c3,
2806         &omap54xx_l4_per__i2c4,
2807         &omap54xx_l4_per__i2c5,
2808         &omap54xx_l3_main_2__mmu_ipu,
2809         &omap54xx_l4_wkup__kbd,
2810         &omap54xx_l4_cfg__mailbox,
2811         &omap54xx_l4_abe__mcbsp1,
2812         &omap54xx_l4_abe__mcbsp2,
2813         &omap54xx_l4_abe__mcbsp3,
2814         &omap54xx_l4_abe__mcpdm,
2815         &omap54xx_l4_per__mcspi1,
2816         &omap54xx_l4_per__mcspi2,
2817         &omap54xx_l4_per__mcspi3,
2818         &omap54xx_l4_per__mcspi4,
2819         &omap54xx_l4_per__mmc1,
2820         &omap54xx_l4_per__mmc2,
2821         &omap54xx_l4_per__mmc3,
2822         &omap54xx_l4_per__mmc4,
2823         &omap54xx_l4_per__mmc5,
2824         &omap54xx_l4_cfg__mpu,
2825         &omap54xx_l4_cfg__spinlock,
2826         &omap54xx_l4_cfg__ocp2scp1,
2827         &omap54xx_l4_wkup__timer1,
2828         &omap54xx_l4_per__timer2,
2829         &omap54xx_l4_per__timer3,
2830         &omap54xx_l4_per__timer4,
2831         &omap54xx_l4_abe__timer5,
2832         &omap54xx_l4_abe__timer6,
2833         &omap54xx_l4_abe__timer7,
2834         &omap54xx_l4_abe__timer8,
2835         &omap54xx_l4_per__timer9,
2836         &omap54xx_l4_per__timer10,
2837         &omap54xx_l4_per__timer11,
2838         &omap54xx_l4_per__uart1,
2839         &omap54xx_l4_per__uart2,
2840         &omap54xx_l4_per__uart3,
2841         &omap54xx_l4_per__uart4,
2842         &omap54xx_l4_per__uart5,
2843         &omap54xx_l4_per__uart6,
2844         &omap54xx_l4_cfg__usb_host_hs,
2845         &omap54xx_l4_cfg__usb_tll_hs,
2846         &omap54xx_l4_cfg__usb_otg_ss,
2847         &omap54xx_l4_wkup__wd_timer2,
2848         &omap54xx_l4_cfg__ocp2scp3,
2849         &omap54xx_l4_cfg__sata,
2850         NULL,
2851 };
2852
2853 int __init omap54xx_hwmod_init(void)
2854 {
2855         omap_hwmod_init();
2856         return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
2857 }