arch/arm/mach-omap2/omap_hwmod_54xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP54xx chips
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Paul Walmsley
   7  * Benoit Cousson
   8  *
   9  * This file is automatically generated from the OMAP hardware databases.
  10  * We respectfully ask that any modifications to this file be coordinated
  11  * with the public linux-omap@vger.kernel.org mailing list and the
  12  * authors above to ensure that the autogeneration scripts are kept
  13  * up-to-date with the file contents.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include <linux/io.h>
  21 #include <linux/platform_data/gpio-omap.h>
  22 #include <linux/platform_data/hsmmc-omap.h>
  23 #include <linux/power/smartreflex.h>
  24 #include <linux/i2c-omap.h>
  25
  26 #include <linux/omap-dma.h>
  27 #include <linux/platform_data/spi-omap2-mcspi.h>
  28 #include <linux/platform_data/asoc-ti-mcbsp.h>
  29 #include <plat/dmtimer.h>
  30
  31 #include "omap_hwmod.h"
  32 #include "omap_hwmod_common_data.h"
  33 #include "cm1_54xx.h"
  34 #include "cm2_54xx.h"
  35 #include "prm54xx.h"
  36 #include "i2c.h"
  37 #include "wd_timer.h"
  38
  39 /* Base offset for all OMAP5 interrupts external to MPUSS */
  40 #define OMAP54XX_IRQ_GIC_START  32
  41
  42 /* Base offset for all OMAP5 dma requests */
  43 #define OMAP54XX_DMA_REQ_START  1
  44
  45
  46 /*
  47  * IP blocks
  48  */
  49
  50 /*
  51  * 'dmm' class
  52  * instance(s): dmm
  53  */
  54 static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
  55         .name   = "dmm",
  56 };
  57
  58 /* dmm */
  59 static struct omap_hwmod omap54xx_dmm_hwmod = {
  60         .name           = "dmm",
  61         .class          = &omap54xx_dmm_hwmod_class,
  62         .clkdm_name     = "emif_clkdm",
  63         .prcm = {
  64                 .omap4 = {
  65                         .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
  66                         .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
  67                 },
  68         },
  69 };
  70
  71 /*
  72  * 'l3' class
  73  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  74  */
  75 static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
  76         .name   = "l3",
  77 };
  78
  79 /* l3_instr */
  80 static struct omap_hwmod omap54xx_l3_instr_hwmod = {
  81         .name           = "l3_instr",
  82         .class          = &omap54xx_l3_hwmod_class,
  83         .clkdm_name     = "l3instr_clkdm",
  84         .prcm = {
  85                 .omap4 = {
  86                         .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  87                         .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  88                         .modulemode   = MODULEMODE_HWCTRL,
  89                 },
  90         },
  91 };
  92
  93 /* l3_main_1 */
  94 static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
  95         .name           = "l3_main_1",
  96         .class          = &omap54xx_l3_hwmod_class,
  97         .clkdm_name     = "l3main1_clkdm",
  98         .prcm = {
  99                 .omap4 = {
 100                         .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
 101                         .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
 102                 },
 103         },
 104 };
 105
 106 /* l3_main_2 */
 107 static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
 108         .name           = "l3_main_2",
 109         .class          = &omap54xx_l3_hwmod_class,
 110         .clkdm_name     = "l3main2_clkdm",
 111         .prcm = {
 112                 .omap4 = {
 113                         .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
 114                         .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
 115                 },
 116         },
 117 };
 118
 119 /* l3_main_3 */
 120 static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
 121         .name           = "l3_main_3",
 122         .class          = &omap54xx_l3_hwmod_class,
 123         .clkdm_name     = "l3instr_clkdm",
 124         .prcm = {
 125                 .omap4 = {
 126                         .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
 127                         .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
 128                         .modulemode   = MODULEMODE_HWCTRL,
 129                 },
 130         },
 131 };
 132
 133 /*
 134  * 'l4' class
 135  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 136  */
 137 static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
 138         .name   = "l4",
 139 };
 140
 141 /* l4_abe */
 142 static struct omap_hwmod omap54xx_l4_abe_hwmod = {
 143         .name           = "l4_abe",
 144         .class          = &omap54xx_l4_hwmod_class,
 145         .clkdm_name     = "abe_clkdm",
 146         .prcm = {
 147                 .omap4 = {
 148                         .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
 149                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 150                 },
 151         },
 152 };
 153
 154 /* l4_cfg */
 155 static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
 156         .name           = "l4_cfg",
 157         .class          = &omap54xx_l4_hwmod_class,
 158         .clkdm_name     = "l4cfg_clkdm",
 159         .prcm = {
 160                 .omap4 = {
 161                         .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 162                         .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 163                 },
 164         },
 165 };
 166
 167 /* l4_per */
 168 static struct omap_hwmod omap54xx_l4_per_hwmod = {
 169         .name           = "l4_per",
 170         .class          = &omap54xx_l4_hwmod_class,
 171         .clkdm_name     = "l4per_clkdm",
 172         .prcm = {
 173                 .omap4 = {
 174                         .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
 175                         .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 176                 },
 177         },
 178 };
 179
 180 /* l4_wkup */
 181 static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
 182         .name           = "l4_wkup",
 183         .class          = &omap54xx_l4_hwmod_class,
 184         .clkdm_name     = "wkupaon_clkdm",
 185         .prcm = {
 186                 .omap4 = {
 187                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
 188                         .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
 189                 },
 190         },
 191 };
 192
 193 /*
 194  * 'mpu_bus' class
 195  * instance(s): mpu_private
 196  */
 197 static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
 198         .name   = "mpu_bus",
 199 };
 200
 201 /* mpu_private */
 202 static struct omap_hwmod omap54xx_mpu_private_hwmod = {
 203         .name           = "mpu_private",
 204         .class          = &omap54xx_mpu_bus_hwmod_class,
 205         .clkdm_name     = "mpu_clkdm",
 206         .prcm = {
 207                 .omap4 = {
 208                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 209                 },
 210         },
 211 };
 212
 213 /*
 214  * 'counter' class
 215  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 216  */
 217
 218 static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
 219         .rev_offs       = 0x0000,
 220         .sysc_offs      = 0x0010,
 221         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 222         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 223         .sysc_fields    = &omap_hwmod_sysc_type1,
 224 };
 225
 226 static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
 227         .name   = "counter",
 228         .sysc   = &omap54xx_counter_sysc,
 229 };
 230
 231 /* counter_32k */
 232 static struct omap_hwmod omap54xx_counter_32k_hwmod = {
 233         .name           = "counter_32k",
 234         .class          = &omap54xx_counter_hwmod_class,
 235         .clkdm_name     = "wkupaon_clkdm",
 236         .flags          = HWMOD_SWSUP_SIDLE,
 237         .main_clk       = "wkupaon_iclk_mux",
 238         .prcm = {
 239                 .omap4 = {
 240                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
 241                         .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
 242                 },
 243         },
 244 };
 245
 246 /*
 247  * 'dma' class
 248  * dma controller for data exchange between memory to memory (i.e. internal or
 249  * external memory) and gp peripherals to memory or memory to gp peripherals
 250  */
 251
 252 static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = {
 253         .rev_offs       = 0x0000,
 254         .sysc_offs      = 0x002c,
 255         .syss_offs      = 0x0028,
 256         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 257                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 258                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 259                            SYSS_HAS_RESET_STATUS),
 260         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 261                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 262         .sysc_fields    = &omap_hwmod_sysc_type1,
 263 };
 264
 265 static struct omap_hwmod_class omap54xx_dma_hwmod_class = {
 266         .name   = "dma",
 267         .sysc   = &omap54xx_dma_sysc,
 268 };
 269
 270 /* dma dev_attr */
 271 static struct omap_dma_dev_attr dma_dev_attr = {
 272         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 273                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 274         .lch_count      = 32,
 275 };
 276
 277 /* dma_system */
 278 static struct omap_hwmod_irq_info omap54xx_dma_system_irqs[] = {
 279         { .name = "0", .irq = 12 + OMAP54XX_IRQ_GIC_START },
 280         { .name = "1", .irq = 13 + OMAP54XX_IRQ_GIC_START },
 281         { .name = "2", .irq = 14 + OMAP54XX_IRQ_GIC_START },
 282         { .name = "3", .irq = 15 + OMAP54XX_IRQ_GIC_START },
 283         { .irq = -1 }
 284 };
 285
 286 static struct omap_hwmod omap54xx_dma_system_hwmod = {
 287         .name           = "dma_system",
 288         .class          = &omap54xx_dma_hwmod_class,
 289         .clkdm_name     = "dma_clkdm",
 290         .mpu_irqs       = omap54xx_dma_system_irqs,
 291         .xlate_irq      = omap4_xlate_irq,
 292         .main_clk       = "l3_iclk_div",
 293         .prcm = {
 294                 .omap4 = {
 295                         .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
 296                         .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
 297                 },
 298         },
 299         .dev_attr       = &dma_dev_attr,
 300 };
 301
 302 /*
 303  * 'dmic' class
 304  * digital microphone controller
 305  */
 306
 307 static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = {
 308         .rev_offs       = 0x0000,
 309         .sysc_offs      = 0x0010,
 310         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 311                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 312         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 313                            SIDLE_SMART_WKUP),
 314         .sysc_fields    = &omap_hwmod_sysc_type2,
 315 };
 316
 317 static struct omap_hwmod_class omap54xx_dmic_hwmod_class = {
 318         .name   = "dmic",
 319         .sysc   = &omap54xx_dmic_sysc,
 320 };
 321
 322 /* dmic */
 323 static struct omap_hwmod omap54xx_dmic_hwmod = {
 324         .name           = "dmic",
 325         .class          = &omap54xx_dmic_hwmod_class,
 326         .clkdm_name     = "abe_clkdm",
 327         .main_clk       = "dmic_gfclk",
 328         .prcm = {
 329                 .omap4 = {
 330                         .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET,
 331                         .context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET,
 332                         .modulemode   = MODULEMODE_SWCTRL,
 333                 },
 334         },
 335 };
 336
 337 /*
 338  * 'dss' class
 339  * display sub-system
 340  */
 341 static struct omap_hwmod_class_sysconfig omap54xx_dss_sysc = {
 342         .rev_offs       = 0x0000,
 343         .syss_offs      = 0x0014,
 344         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 345 };
 346
 347 static struct omap_hwmod_class omap54xx_dss_hwmod_class = {
 348         .name   = "dss",
 349         .sysc   = &omap54xx_dss_sysc,
 350         .reset  = omap_dss_reset,
 351 };
 352
 353 /* dss */
 354 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 355         { .role = "32khz_clk", .clk = "dss_32khz_clk" },
 356         { .role = "sys_clk", .clk = "dss_sys_clk" },
 357         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 358 };
 359
 360 static struct omap_hwmod omap54xx_dss_hwmod = {
 361         .name           = "dss_core",
 362         .class          = &omap54xx_dss_hwmod_class,
 363         .clkdm_name     = "dss_clkdm",
 364         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 365         .main_clk       = "dss_dss_clk",
 366         .prcm = {
 367                 .omap4 = {
 368                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 369                         .context_offs = OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET,
 370                         .modulemode   = MODULEMODE_SWCTRL,
 371                 },
 372         },
 373         .opt_clks       = dss_opt_clks,
 374         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 375 };
 376
 377 /*
 378  * 'dispc' class
 379  * display controller
 380  */
 381
 382 static struct omap_hwmod_class_sysconfig omap54xx_dispc_sysc = {
 383         .rev_offs       = 0x0000,
 384         .sysc_offs      = 0x0010,
 385         .syss_offs      = 0x0014,
 386         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 387                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 388                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 389                            SYSS_HAS_RESET_STATUS),
 390         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 391                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 392         .sysc_fields    = &omap_hwmod_sysc_type1,
 393 };
 394
 395 static struct omap_hwmod_class omap54xx_dispc_hwmod_class = {
 396         .name   = "dispc",
 397         .sysc   = &omap54xx_dispc_sysc,
 398 };
 399
 400 /* dss_dispc */
 401 static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
 402         { .role = "sys_clk", .clk = "dss_sys_clk" },
 403 };
 404
 405 /* dss_dispc dev_attr */
 406 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
 407         .has_framedonetv_irq    = 1,
 408         .manager_count          = 4,
 409 };
 410
 411 static struct omap_hwmod omap54xx_dss_dispc_hwmod = {
 412         .name           = "dss_dispc",
 413         .class          = &omap54xx_dispc_hwmod_class,
 414         .clkdm_name     = "dss_clkdm",
 415         .main_clk       = "dss_dss_clk",
 416         .prcm = {
 417                 .omap4 = {
 418                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 419                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 420                 },
 421         },
 422         .opt_clks       = dss_dispc_opt_clks,
 423         .opt_clks_cnt   = ARRAY_SIZE(dss_dispc_opt_clks),
 424         .dev_attr       = &dss_dispc_dev_attr,
 425         .parent_hwmod   = &omap54xx_dss_hwmod,
 426 };
 427
 428 /*
 429  * 'dsi1' class
 430  * display serial interface controller
 431  */
 432
 433 static struct omap_hwmod_class_sysconfig omap54xx_dsi1_sysc = {
 434         .rev_offs       = 0x0000,
 435         .sysc_offs      = 0x0010,
 436         .syss_offs      = 0x0014,
 437         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 438                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 439                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 440         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 441         .sysc_fields    = &omap_hwmod_sysc_type1,
 442 };
 443
 444 static struct omap_hwmod_class omap54xx_dsi1_hwmod_class = {
 445         .name   = "dsi1",
 446         .sysc   = &omap54xx_dsi1_sysc,
 447 };
 448
 449 /* dss_dsi1_a */
 450 static struct omap_hwmod_opt_clk dss_dsi1_a_opt_clks[] = {
 451         { .role = "sys_clk", .clk = "dss_sys_clk" },
 452 };
 453
 454 static struct omap_hwmod omap54xx_dss_dsi1_a_hwmod = {
 455         .name           = "dss_dsi1",
 456         .class          = &omap54xx_dsi1_hwmod_class,
 457         .clkdm_name     = "dss_clkdm",
 458         .main_clk       = "dss_dss_clk",
 459         .prcm = {
 460                 .omap4 = {
 461                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 462                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 463                 },
 464         },
 465         .opt_clks       = dss_dsi1_a_opt_clks,
 466         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_a_opt_clks),
 467         .parent_hwmod   = &omap54xx_dss_hwmod,
 468 };
 469
 470 /* dss_dsi1_c */
 471 static struct omap_hwmod_opt_clk dss_dsi1_c_opt_clks[] = {
 472         { .role = "sys_clk", .clk = "dss_sys_clk" },
 473 };
 474
 475 static struct omap_hwmod omap54xx_dss_dsi1_c_hwmod = {
 476         .name           = "dss_dsi2",
 477         .class          = &omap54xx_dsi1_hwmod_class,
 478         .clkdm_name     = "dss_clkdm",
 479         .main_clk       = "dss_dss_clk",
 480         .prcm = {
 481                 .omap4 = {
 482                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 483                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 484                 },
 485         },
 486         .opt_clks       = dss_dsi1_c_opt_clks,
 487         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_c_opt_clks),
 488         .parent_hwmod   = &omap54xx_dss_hwmod,
 489 };
 490
 491 /*
 492  * 'hdmi' class
 493  * hdmi controller
 494  */
 495
 496 static struct omap_hwmod_class_sysconfig omap54xx_hdmi_sysc = {
 497         .rev_offs       = 0x0000,
 498         .sysc_offs      = 0x0010,
 499         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 500                            SYSC_HAS_SOFTRESET),
 501         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 502                            SIDLE_SMART_WKUP),
 503         .sysc_fields    = &omap_hwmod_sysc_type2,
 504 };
 505
 506 static struct omap_hwmod_class omap54xx_hdmi_hwmod_class = {
 507         .name   = "hdmi",
 508         .sysc   = &omap54xx_hdmi_sysc,
 509 };
 510
 511 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 512         { .role = "sys_clk", .clk = "dss_sys_clk" },
 513 };
 514
 515 static struct omap_hwmod omap54xx_dss_hdmi_hwmod = {
 516         .name           = "dss_hdmi",
 517         .class          = &omap54xx_hdmi_hwmod_class,
 518         .clkdm_name     = "dss_clkdm",
 519         .main_clk       = "dss_48mhz_clk",
 520         .prcm = {
 521                 .omap4 = {
 522                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 523                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 524                 },
 525         },
 526         .opt_clks       = dss_hdmi_opt_clks,
 527         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 528         .parent_hwmod   = &omap54xx_dss_hwmod,
 529 };
 530
 531 /*
 532  * 'rfbi' class
 533  * remote frame buffer interface
 534  */
 535
 536 static struct omap_hwmod_class_sysconfig omap54xx_rfbi_sysc = {
 537         .rev_offs       = 0x0000,
 538         .sysc_offs      = 0x0010,
 539         .syss_offs      = 0x0014,
 540         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 541                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 542         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 543         .sysc_fields    = &omap_hwmod_sysc_type1,
 544 };
 545
 546 static struct omap_hwmod_class omap54xx_rfbi_hwmod_class = {
 547         .name   = "rfbi",
 548         .sysc   = &omap54xx_rfbi_sysc,
 549 };
 550
 551 /* dss_rfbi */
 552 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 553         { .role = "ick", .clk = "l3_iclk_div" },
 554 };
 555
 556 static struct omap_hwmod omap54xx_dss_rfbi_hwmod = {
 557         .name           = "dss_rfbi",
 558         .class          = &omap54xx_rfbi_hwmod_class,
 559         .clkdm_name     = "dss_clkdm",
 560         .prcm = {
 561                 .omap4 = {
 562                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 563                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 564                 },
 565         },
 566         .opt_clks       = dss_rfbi_opt_clks,
 567         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 568         .parent_hwmod   = &omap54xx_dss_hwmod,
 569 };
 570
 571 /*
 572  * 'emif' class
 573  * external memory interface no1 (wrapper)
 574  */
 575
 576 static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
 577         .rev_offs       = 0x0000,
 578 };
 579
 580 static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
 581         .name   = "emif",
 582         .sysc   = &omap54xx_emif_sysc,
 583 };
 584
 585 /* emif1 */
 586 static struct omap_hwmod omap54xx_emif1_hwmod = {
 587         .name           = "emif1",
 588         .class          = &omap54xx_emif_hwmod_class,
 589         .clkdm_name     = "emif_clkdm",
 590         .flags          = HWMOD_INIT_NO_IDLE,
 591         .main_clk       = "dpll_core_h11x2_ck",
 592         .prcm = {
 593                 .omap4 = {
 594                         .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
 595                         .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
 596                         .modulemode   = MODULEMODE_HWCTRL,
 597                 },
 598         },
 599 };
 600
 601 /* emif2 */
 602 static struct omap_hwmod omap54xx_emif2_hwmod = {
 603         .name           = "emif2",
 604         .class          = &omap54xx_emif_hwmod_class,
 605         .clkdm_name     = "emif_clkdm",
 606         .flags          = HWMOD_INIT_NO_IDLE,
 607         .main_clk       = "dpll_core_h11x2_ck",
 608         .prcm = {
 609                 .omap4 = {
 610                         .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
 611                         .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
 612                         .modulemode   = MODULEMODE_HWCTRL,
 613                 },
 614         },
 615 };
 616
 617 /*
 618  * 'gpio' class
 619  * general purpose io module
 620  */
 621
 622 static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc = {
 623         .rev_offs       = 0x0000,
 624         .sysc_offs      = 0x0010,
 625         .syss_offs      = 0x0114,
 626         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 627                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 628                            SYSS_HAS_RESET_STATUS),
 629         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 630                            SIDLE_SMART_WKUP),
 631         .sysc_fields    = &omap_hwmod_sysc_type1,
 632 };
 633
 634 static struct omap_hwmod_class omap54xx_gpio_hwmod_class = {
 635         .name   = "gpio",
 636         .sysc   = &omap54xx_gpio_sysc,
 637         .rev    = 2,
 638 };
 639
 640 /* gpio dev_attr */
 641 static struct omap_gpio_dev_attr gpio_dev_attr = {
 642         .bank_width     = 32,
 643         .dbck_flag      = true,
 644 };
 645
 646 /* gpio1 */
 647 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 648         { .role = "dbclk", .clk = "gpio1_dbclk" },
 649 };
 650
 651 static struct omap_hwmod omap54xx_gpio1_hwmod = {
 652         .name           = "gpio1",
 653         .class          = &omap54xx_gpio_hwmod_class,
 654         .clkdm_name     = "wkupaon_clkdm",
 655         .main_clk       = "wkupaon_iclk_mux",
 656         .prcm = {
 657                 .omap4 = {
 658                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
 659                         .context_offs = OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
 660                         .modulemode   = MODULEMODE_HWCTRL,
 661                 },
 662         },
 663         .opt_clks       = gpio1_opt_clks,
 664         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 665         .dev_attr       = &gpio_dev_attr,
 666 };
 667
 668 /* gpio2 */
 669 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 670         { .role = "dbclk", .clk = "gpio2_dbclk" },
 671 };
 672
 673 static struct omap_hwmod omap54xx_gpio2_hwmod = {
 674         .name           = "gpio2",
 675         .class          = &omap54xx_gpio_hwmod_class,
 676         .clkdm_name     = "l4per_clkdm",
 677         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 678         .main_clk       = "l4_root_clk_div",
 679         .prcm = {
 680                 .omap4 = {
 681                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
 682                         .context_offs = OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
 683                         .modulemode   = MODULEMODE_HWCTRL,
 684                 },
 685         },
 686         .opt_clks       = gpio2_opt_clks,
 687         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 688         .dev_attr       = &gpio_dev_attr,
 689 };
 690
 691 /* gpio3 */
 692 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 693         { .role = "dbclk", .clk = "gpio3_dbclk" },
 694 };
 695
 696 static struct omap_hwmod omap54xx_gpio3_hwmod = {
 697         .name           = "gpio3",
 698         .class          = &omap54xx_gpio_hwmod_class,
 699         .clkdm_name     = "l4per_clkdm",
 700         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 701         .main_clk       = "l4_root_clk_div",
 702         .prcm = {
 703                 .omap4 = {
 704                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
 705                         .context_offs = OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
 706                         .modulemode   = MODULEMODE_HWCTRL,
 707                 },
 708         },
 709         .opt_clks       = gpio3_opt_clks,
 710         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 711         .dev_attr       = &gpio_dev_attr,
 712 };
 713
 714 /* gpio4 */
 715 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 716         { .role = "dbclk", .clk = "gpio4_dbclk" },
 717 };
 718
 719 static struct omap_hwmod omap54xx_gpio4_hwmod = {
 720         .name           = "gpio4",
 721         .class          = &omap54xx_gpio_hwmod_class,
 722         .clkdm_name     = "l4per_clkdm",
 723         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 724         .main_clk       = "l4_root_clk_div",
 725         .prcm = {
 726                 .omap4 = {
 727                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
 728                         .context_offs = OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
 729                         .modulemode   = MODULEMODE_HWCTRL,
 730                 },
 731         },
 732         .opt_clks       = gpio4_opt_clks,
 733         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 734         .dev_attr       = &gpio_dev_attr,
 735 };
 736
 737 /* gpio5 */
 738 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 739         { .role = "dbclk", .clk = "gpio5_dbclk" },
 740 };
 741
 742 static struct omap_hwmod omap54xx_gpio5_hwmod = {
 743         .name           = "gpio5",
 744         .class          = &omap54xx_gpio_hwmod_class,
 745         .clkdm_name     = "l4per_clkdm",
 746         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 747         .main_clk       = "l4_root_clk_div",
 748         .prcm = {
 749                 .omap4 = {
 750                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
 751                         .context_offs = OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
 752                         .modulemode   = MODULEMODE_HWCTRL,
 753                 },
 754         },
 755         .opt_clks       = gpio5_opt_clks,
 756         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
 757         .dev_attr       = &gpio_dev_attr,
 758 };
 759
 760 /* gpio6 */
 761 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
 762         { .role = "dbclk", .clk = "gpio6_dbclk" },
 763 };
 764
 765 static struct omap_hwmod omap54xx_gpio6_hwmod = {
 766         .name           = "gpio6",
 767         .class          = &omap54xx_gpio_hwmod_class,
 768         .clkdm_name     = "l4per_clkdm",
 769         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 770         .main_clk       = "l4_root_clk_div",
 771         .prcm = {
 772                 .omap4 = {
 773                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
 774                         .context_offs = OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
 775                         .modulemode   = MODULEMODE_HWCTRL,
 776                 },
 777         },
 778         .opt_clks       = gpio6_opt_clks,
 779         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
 780         .dev_attr       = &gpio_dev_attr,
 781 };
 782
 783 /* gpio7 */
 784 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
 785         { .role = "dbclk", .clk = "gpio7_dbclk" },
 786 };
 787
 788 static struct omap_hwmod omap54xx_gpio7_hwmod = {
 789         .name           = "gpio7",
 790         .class          = &omap54xx_gpio_hwmod_class,
 791         .clkdm_name     = "l4per_clkdm",
 792         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 793         .main_clk       = "l4_root_clk_div",
 794         .prcm = {
 795                 .omap4 = {
 796                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
 797                         .context_offs = OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
 798                         .modulemode   = MODULEMODE_HWCTRL,
 799                 },
 800         },
 801         .opt_clks       = gpio7_opt_clks,
 802         .opt_clks_cnt   = ARRAY_SIZE(gpio7_opt_clks),
 803         .dev_attr       = &gpio_dev_attr,
 804 };
 805
 806 /* gpio8 */
 807 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
 808         { .role = "dbclk", .clk = "gpio8_dbclk" },
 809 };
 810
 811 static struct omap_hwmod omap54xx_gpio8_hwmod = {
 812         .name           = "gpio8",
 813         .class          = &omap54xx_gpio_hwmod_class,
 814         .clkdm_name     = "l4per_clkdm",
 815         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 816         .main_clk       = "l4_root_clk_div",
 817         .prcm = {
 818                 .omap4 = {
 819                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
 820                         .context_offs = OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
 821                         .modulemode   = MODULEMODE_HWCTRL,
 822                 },
 823         },
 824         .opt_clks       = gpio8_opt_clks,
 825         .opt_clks_cnt   = ARRAY_SIZE(gpio8_opt_clks),
 826         .dev_attr       = &gpio_dev_attr,
 827 };
 828
 829 /*
 830  * 'i2c' class
 831  * multimaster high-speed i2c controller
 832  */
 833
 834 static struct omap_hwmod_class_sysconfig omap54xx_i2c_sysc = {
 835         .sysc_offs      = 0x0010,
 836         .syss_offs      = 0x0090,
 837         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 838                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 839                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 840         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 841                            SIDLE_SMART_WKUP),
 842         .sysc_fields    = &omap_hwmod_sysc_type1,
 843 };
 844
 845 static struct omap_hwmod_class omap54xx_i2c_hwmod_class = {
 846         .name   = "i2c",
 847         .sysc   = &omap54xx_i2c_sysc,
 848         .reset  = &omap_i2c_reset,
 849         .rev    = OMAP_I2C_IP_VERSION_2,
 850 };
 851
 852 /* i2c dev_attr */
 853 static struct omap_i2c_dev_attr i2c_dev_attr = {
 854         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
 855 };
 856
 857 /* i2c1 */
 858 static struct omap_hwmod omap54xx_i2c1_hwmod = {
 859         .name           = "i2c1",
 860         .class          = &omap54xx_i2c_hwmod_class,
 861         .clkdm_name     = "l4per_clkdm",
 862         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 863         .main_clk       = "func_96m_fclk",
 864         .prcm = {
 865                 .omap4 = {
 866                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
 867                         .context_offs = OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
 868                         .modulemode   = MODULEMODE_SWCTRL,
 869                 },
 870         },
 871         .dev_attr       = &i2c_dev_attr,
 872 };
 873
 874 /* i2c2 */
 875 static struct omap_hwmod omap54xx_i2c2_hwmod = {
 876         .name           = "i2c2",
 877         .class          = &omap54xx_i2c_hwmod_class,
 878         .clkdm_name     = "l4per_clkdm",
 879         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 880         .main_clk       = "func_96m_fclk",
 881         .prcm = {
 882                 .omap4 = {
 883                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
 884                         .context_offs = OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
 885                         .modulemode   = MODULEMODE_SWCTRL,
 886                 },
 887         },
 888         .dev_attr       = &i2c_dev_attr,
 889 };
 890
 891 /* i2c3 */
 892 static struct omap_hwmod omap54xx_i2c3_hwmod = {
 893         .name           = "i2c3",
 894         .class          = &omap54xx_i2c_hwmod_class,
 895         .clkdm_name     = "l4per_clkdm",
 896         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 897         .main_clk       = "func_96m_fclk",
 898         .prcm = {
 899                 .omap4 = {
 900                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
 901                         .context_offs = OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
 902                         .modulemode   = MODULEMODE_SWCTRL,
 903                 },
 904         },
 905         .dev_attr       = &i2c_dev_attr,
 906 };
 907
 908 /* i2c4 */
 909 static struct omap_hwmod omap54xx_i2c4_hwmod = {
 910         .name           = "i2c4",
 911         .class          = &omap54xx_i2c_hwmod_class,
 912         .clkdm_name     = "l4per_clkdm",
 913         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 914         .main_clk       = "func_96m_fclk",
 915         .prcm = {
 916                 .omap4 = {
 917                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
 918                         .context_offs = OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
 919                         .modulemode   = MODULEMODE_SWCTRL,
 920                 },
 921         },
 922         .dev_attr       = &i2c_dev_attr,
 923 };
 924
 925 /* i2c5 */
 926 static struct omap_hwmod omap54xx_i2c5_hwmod = {
 927         .name           = "i2c5",
 928         .class          = &omap54xx_i2c_hwmod_class,
 929         .clkdm_name     = "l4per_clkdm",
 930         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 931         .main_clk       = "func_96m_fclk",
 932         .prcm = {
 933                 .omap4 = {
 934                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET,
 935                         .context_offs = OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET,
 936                         .modulemode   = MODULEMODE_SWCTRL,
 937                 },
 938         },
 939         .dev_attr       = &i2c_dev_attr,
 940 };
 941
 942 /*
 943  * 'kbd' class
 944  * keyboard controller
 945  */
 946
 947 static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = {
 948         .rev_offs       = 0x0000,
 949         .sysc_offs      = 0x0010,
 950         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
 951                            SYSC_HAS_SOFTRESET),
 952         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 953         .sysc_fields    = &omap_hwmod_sysc_type1,
 954 };
 955
 956 static struct omap_hwmod_class omap54xx_kbd_hwmod_class = {
 957         .name   = "kbd",
 958         .sysc   = &omap54xx_kbd_sysc,
 959 };
 960
 961 /* kbd */
 962 static struct omap_hwmod omap54xx_kbd_hwmod = {
 963         .name           = "kbd",
 964         .class          = &omap54xx_kbd_hwmod_class,
 965         .clkdm_name     = "wkupaon_clkdm",
 966         .main_clk       = "sys_32k_ck",
 967         .prcm = {
 968                 .omap4 = {
 969                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET,
 970                         .context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET,
 971                         .modulemode   = MODULEMODE_SWCTRL,
 972                 },
 973         },
 974 };
 975
 976 /*
 977  * 'mailbox' class
 978  * mailbox module allowing communication between the on-chip processors using a
 979  * queued mailbox-interrupt mechanism.
 980  */
 981
 982 static struct omap_hwmod_class_sysconfig omap54xx_mailbox_sysc = {
 983         .rev_offs       = 0x0000,
 984         .sysc_offs      = 0x0010,
 985         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 986                            SYSC_HAS_SOFTRESET),
 987         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 988         .sysc_fields    = &omap_hwmod_sysc_type2,
 989 };
 990
 991 static struct omap_hwmod_class omap54xx_mailbox_hwmod_class = {
 992         .name   = "mailbox",
 993         .sysc   = &omap54xx_mailbox_sysc,
 994 };
 995
 996 /* mailbox */
 997 static struct omap_hwmod omap54xx_mailbox_hwmod = {
 998         .name           = "mailbox",
 999         .class          = &omap54xx_mailbox_hwmod_class,
1000         .clkdm_name     = "l4cfg_clkdm",
1001         .prcm = {
1002                 .omap4 = {
1003                         .clkctrl_offs = OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1004                         .context_offs = OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1005                 },
1006         },
1007 };
1008
1009 /*
1010  * 'mcbsp' class
1011  * multi channel buffered serial port controller
1012  */
1013
1014 static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = {
1015         .sysc_offs      = 0x008c,
1016         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1017                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1018         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1019         .sysc_fields    = &omap_hwmod_sysc_type1,
1020 };
1021
1022 static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = {
1023         .name   = "mcbsp",
1024         .sysc   = &omap54xx_mcbsp_sysc,
1025         .rev    = MCBSP_CONFIG_TYPE4,
1026 };
1027
1028 /* mcbsp1 */
1029 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1030         { .role = "pad_fck", .clk = "pad_clks_ck" },
1031         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1032 };
1033
1034 static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
1035         .name           = "mcbsp1",
1036         .class          = &omap54xx_mcbsp_hwmod_class,
1037         .clkdm_name     = "abe_clkdm",
1038         .main_clk       = "mcbsp1_gfclk",
1039         .prcm = {
1040                 .omap4 = {
1041                         .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET,
1042                         .context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1043                         .modulemode   = MODULEMODE_SWCTRL,
1044                 },
1045         },
1046         .opt_clks       = mcbsp1_opt_clks,
1047         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1048 };
1049
1050 /* mcbsp2 */
1051 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1052         { .role = "pad_fck", .clk = "pad_clks_ck" },
1053         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1054 };
1055
1056 static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
1057         .name           = "mcbsp2",
1058         .class          = &omap54xx_mcbsp_hwmod_class,
1059         .clkdm_name     = "abe_clkdm",
1060         .main_clk       = "mcbsp2_gfclk",
1061         .prcm = {
1062                 .omap4 = {
1063                         .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET,
1064                         .context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1065                         .modulemode   = MODULEMODE_SWCTRL,
1066                 },
1067         },
1068         .opt_clks       = mcbsp2_opt_clks,
1069         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
1070 };
1071
1072 /* mcbsp3 */
1073 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
1074         { .role = "pad_fck", .clk = "pad_clks_ck" },
1075         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
1076 };
1077
1078 static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
1079         .name           = "mcbsp3",
1080         .class          = &omap54xx_mcbsp_hwmod_class,
1081         .clkdm_name     = "abe_clkdm",
1082         .main_clk       = "mcbsp3_gfclk",
1083         .prcm = {
1084                 .omap4 = {
1085                         .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET,
1086                         .context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET,
1087                         .modulemode   = MODULEMODE_SWCTRL,
1088                 },
1089         },
1090         .opt_clks       = mcbsp3_opt_clks,
1091         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
1092 };
1093
1094 /*
1095  * 'mcpdm' class
1096  * multi channel pdm controller (proprietary interface with phoenix power
1097  * ic)
1098  */
1099
1100 static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = {
1101         .rev_offs       = 0x0000,
1102         .sysc_offs      = 0x0010,
1103         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1104                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1105         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1106                            SIDLE_SMART_WKUP),
1107         .sysc_fields    = &omap_hwmod_sysc_type2,
1108 };
1109
1110 static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = {
1111         .name   = "mcpdm",
1112         .sysc   = &omap54xx_mcpdm_sysc,
1113 };
1114
1115 /* mcpdm */
1116 static struct omap_hwmod omap54xx_mcpdm_hwmod = {
1117         .name           = "mcpdm",
1118         .class          = &omap54xx_mcpdm_hwmod_class,
1119         .clkdm_name     = "abe_clkdm",
1120         /*
1121          * It's suspected that the McPDM requires an off-chip main
1122          * functional clock, controlled via I2C.  This IP block is
1123          * currently reset very early during boot, before I2C is
1124          * available, so it doesn't seem that we have any choice in
1125          * the kernel other than to avoid resetting it.  XXX This is
1126          * really a hardware issue workaround: every IP block should
1127          * be able to source its main functional clock from either
1128          * on-chip or off-chip sources.  McPDM seems to be the only
1129          * current exception.
1130          */
1131
1132         .flags          = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
1133         .main_clk       = "pad_clks_ck",
1134         .prcm = {
1135                 .omap4 = {
1136                         .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET,
1137                         .context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET,
1138                         .modulemode   = MODULEMODE_SWCTRL,
1139                 },
1140         },
1141 };
1142
1143 /*
1144  * 'mcspi' class
1145  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1146  * bus
1147  */
1148
1149 static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = {
1150         .rev_offs       = 0x0000,
1151         .sysc_offs      = 0x0010,
1152         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1153                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1154         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1155                            SIDLE_SMART_WKUP),
1156         .sysc_fields    = &omap_hwmod_sysc_type2,
1157 };
1158
1159 static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = {
1160         .name   = "mcspi",
1161         .sysc   = &omap54xx_mcspi_sysc,
1162         .rev    = OMAP4_MCSPI_REV,
1163 };
1164
1165 /* mcspi1 */
1166 /* mcspi1 dev_attr */
1167 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1168         .num_chipselect = 4,
1169 };
1170
1171 static struct omap_hwmod omap54xx_mcspi1_hwmod = {
1172         .name           = "mcspi1",
1173         .class          = &omap54xx_mcspi_hwmod_class,
1174         .clkdm_name     = "l4per_clkdm",
1175         .main_clk       = "func_48m_fclk",
1176         .prcm = {
1177                 .omap4 = {
1178                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1179                         .context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1180                         .modulemode   = MODULEMODE_SWCTRL,
1181                 },
1182         },
1183         .dev_attr       = &mcspi1_dev_attr,
1184 };
1185
1186 /* mcspi2 */
1187 /* mcspi2 dev_attr */
1188 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1189         .num_chipselect = 2,
1190 };
1191
1192 static struct omap_hwmod omap54xx_mcspi2_hwmod = {
1193         .name           = "mcspi2",
1194         .class          = &omap54xx_mcspi_hwmod_class,
1195         .clkdm_name     = "l4per_clkdm",
1196         .main_clk       = "func_48m_fclk",
1197         .prcm = {
1198                 .omap4 = {
1199                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1200                         .context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1201                         .modulemode   = MODULEMODE_SWCTRL,
1202                 },
1203         },
1204         .dev_attr       = &mcspi2_dev_attr,
1205 };
1206
1207 /* mcspi3 */
1208 /* mcspi3 dev_attr */
1209 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1210         .num_chipselect = 2,
1211 };
1212
1213 static struct omap_hwmod omap54xx_mcspi3_hwmod = {
1214         .name           = "mcspi3",
1215         .class          = &omap54xx_mcspi_hwmod_class,
1216         .clkdm_name     = "l4per_clkdm",
1217         .main_clk       = "func_48m_fclk",
1218         .prcm = {
1219                 .omap4 = {
1220                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1221                         .context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1222                         .modulemode   = MODULEMODE_SWCTRL,
1223                 },
1224         },
1225         .dev_attr       = &mcspi3_dev_attr,
1226 };
1227
1228 /* mcspi4 */
1229 /* mcspi4 dev_attr */
1230 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1231         .num_chipselect = 1,
1232 };
1233
1234 static struct omap_hwmod omap54xx_mcspi4_hwmod = {
1235         .name           = "mcspi4",
1236         .class          = &omap54xx_mcspi_hwmod_class,
1237         .clkdm_name     = "l4per_clkdm",
1238         .main_clk       = "func_48m_fclk",
1239         .prcm = {
1240                 .omap4 = {
1241                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1242                         .context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1243                         .modulemode   = MODULEMODE_SWCTRL,
1244                 },
1245         },
1246         .dev_attr       = &mcspi4_dev_attr,
1247 };
1248
1249 /*
1250  * 'mmc' class
1251  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
1252  */
1253
1254 static struct omap_hwmod_class_sysconfig omap54xx_mmc_sysc = {
1255         .rev_offs       = 0x0000,
1256         .sysc_offs      = 0x0010,
1257         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1258                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1259                            SYSC_HAS_SOFTRESET),
1260         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1261                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1262                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1263         .sysc_fields    = &omap_hwmod_sysc_type2,
1264 };
1265
1266 static struct omap_hwmod_class omap54xx_mmc_hwmod_class = {
1267         .name   = "mmc",
1268         .sysc   = &omap54xx_mmc_sysc,
1269 };
1270
1271 /* mmc1 */
1272 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1273         { .role = "32khz_clk", .clk = "mmc1_32khz_clk" },
1274 };
1275
1276 /* mmc1 dev_attr */
1277 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1278         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1279 };
1280
1281 static struct omap_hwmod omap54xx_mmc1_hwmod = {
1282         .name           = "mmc1",
1283         .class          = &omap54xx_mmc_hwmod_class,
1284         .clkdm_name     = "l3init_clkdm",
1285         .main_clk       = "mmc1_fclk",
1286         .prcm = {
1287                 .omap4 = {
1288                         .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1289                         .context_offs = OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1290                         .modulemode   = MODULEMODE_SWCTRL,
1291                 },
1292         },
1293         .opt_clks       = mmc1_opt_clks,
1294         .opt_clks_cnt   = ARRAY_SIZE(mmc1_opt_clks),
1295         .dev_attr       = &mmc1_dev_attr,
1296 };
1297
1298 /* mmc2 */
1299 static struct omap_hwmod omap54xx_mmc2_hwmod = {
1300         .name           = "mmc2",
1301         .class          = &omap54xx_mmc_hwmod_class,
1302         .clkdm_name     = "l3init_clkdm",
1303         .main_clk       = "mmc2_fclk",
1304         .prcm = {
1305                 .omap4 = {
1306                         .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1307                         .context_offs = OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1308                         .modulemode   = MODULEMODE_SWCTRL,
1309                 },
1310         },
1311 };
1312
1313 /* mmc3 */
1314 static struct omap_hwmod omap54xx_mmc3_hwmod = {
1315         .name           = "mmc3",
1316         .class          = &omap54xx_mmc_hwmod_class,
1317         .clkdm_name     = "l4per_clkdm",
1318         .main_clk       = "func_48m_fclk",
1319         .prcm = {
1320                 .omap4 = {
1321                         .clkctrl_offs = OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1322                         .context_offs = OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1323                         .modulemode   = MODULEMODE_SWCTRL,
1324                 },
1325         },
1326 };
1327
1328 /* mmc4 */
1329 static struct omap_hwmod omap54xx_mmc4_hwmod = {
1330         .name           = "mmc4",
1331         .class          = &omap54xx_mmc_hwmod_class,
1332         .clkdm_name     = "l4per_clkdm",
1333         .main_clk       = "func_48m_fclk",
1334         .prcm = {
1335                 .omap4 = {
1336                         .clkctrl_offs = OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1337                         .context_offs = OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1338                         .modulemode   = MODULEMODE_SWCTRL,
1339                 },
1340         },
1341 };
1342
1343 /* mmc5 */
1344 static struct omap_hwmod omap54xx_mmc5_hwmod = {
1345         .name           = "mmc5",
1346         .class          = &omap54xx_mmc_hwmod_class,
1347         .clkdm_name     = "l4per_clkdm",
1348         .main_clk       = "func_96m_fclk",
1349         .prcm = {
1350                 .omap4 = {
1351                         .clkctrl_offs = OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET,
1352                         .context_offs = OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET,
1353                         .modulemode   = MODULEMODE_SWCTRL,
1354                 },
1355         },
1356 };
1357
1358 /*
1359  * 'mmu' class
1360  * The memory management unit performs virtual to physical address translation
1361  * for its requestors.
1362  */
1363
1364 static struct omap_hwmod_class_sysconfig omap54xx_mmu_sysc = {
1365         .rev_offs       = 0x0000,
1366         .sysc_offs      = 0x0010,
1367         .syss_offs      = 0x0014,
1368         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1369                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1370                            SYSS_HAS_RESET_STATUS),
1371         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1372         .sysc_fields    = &omap_hwmod_sysc_type1,
1373 };
1374
1375 static struct omap_hwmod_class omap54xx_mmu_hwmod_class = {
1376         .name = "mmu",
1377         .sysc = &omap54xx_mmu_sysc,
1378 };
1379
1380 static struct omap_hwmod_rst_info omap54xx_mmu_dsp_resets[] = {
1381         { .name = "mmu_cache", .rst_shift = 1 },
1382 };
1383
1384 static struct omap_hwmod omap54xx_mmu_dsp_hwmod = {
1385         .name           = "mmu_dsp",
1386         .class          = &omap54xx_mmu_hwmod_class,
1387         .clkdm_name     = "dsp_clkdm",
1388         .rst_lines      = omap54xx_mmu_dsp_resets,
1389         .rst_lines_cnt  = ARRAY_SIZE(omap54xx_mmu_dsp_resets),
1390         .main_clk       = "dpll_iva_h11x2_ck",
1391         .prcm = {
1392                 .omap4 = {
1393                         .clkctrl_offs = OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET,
1394                         .rstctrl_offs = OMAP54XX_RM_DSP_RSTCTRL_OFFSET,
1395                         .context_offs = OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET,
1396                         .modulemode   = MODULEMODE_HWCTRL,
1397                 },
1398         },
1399 };
1400
1401 /* mmu ipu */
1402 static struct omap_hwmod_rst_info omap54xx_mmu_ipu_resets[] = {
1403         { .name = "mmu_cache", .rst_shift = 2 },
1404 };
1405
1406 static struct omap_hwmod omap54xx_mmu_ipu_hwmod = {
1407         .name           = "mmu_ipu",
1408         .class          = &omap54xx_mmu_hwmod_class,
1409         .clkdm_name     = "ipu_clkdm",
1410         .rst_lines      = omap54xx_mmu_ipu_resets,
1411         .rst_lines_cnt  = ARRAY_SIZE(omap54xx_mmu_ipu_resets),
1412         .main_clk       = "dpll_core_h22x2_ck",
1413         .prcm = {
1414                 .omap4 = {
1415                         .clkctrl_offs = OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET,
1416                         .rstctrl_offs = OMAP54XX_RM_IPU_RSTCTRL_OFFSET,
1417                         .context_offs = OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET,
1418                         .modulemode   = MODULEMODE_HWCTRL,
1419                 },
1420         },
1421 };
1422
1423 /*
1424  * 'mpu' class
1425  * mpu sub-system
1426  */
1427
1428 static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
1429         .name   = "mpu",
1430 };
1431
1432 /* mpu */
1433 static struct omap_hwmod omap54xx_mpu_hwmod = {
1434         .name           = "mpu",
1435         .class          = &omap54xx_mpu_hwmod_class,
1436         .clkdm_name     = "mpu_clkdm",
1437         .flags          = HWMOD_INIT_NO_IDLE,
1438         .main_clk       = "dpll_mpu_m2_ck",
1439         .prcm = {
1440                 .omap4 = {
1441                         .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1442                         .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
1443                 },
1444         },
1445 };
1446
1447 /*
1448  * 'spinlock' class
1449  * spinlock provides hardware assistance for synchronizing the processes
1450  * running on multiple processors
1451  */
1452
1453 static struct omap_hwmod_class_sysconfig omap54xx_spinlock_sysc = {
1454         .rev_offs       = 0x0000,
1455         .sysc_offs      = 0x0010,
1456         .syss_offs      = 0x0014,
1457         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1458                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1459                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1460         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1461         .sysc_fields    = &omap_hwmod_sysc_type1,
1462 };
1463
1464 static struct omap_hwmod_class omap54xx_spinlock_hwmod_class = {
1465         .name   = "spinlock",
1466         .sysc   = &omap54xx_spinlock_sysc,
1467 };
1468
1469 /* spinlock */
1470 static struct omap_hwmod omap54xx_spinlock_hwmod = {
1471         .name           = "spinlock",
1472         .class          = &omap54xx_spinlock_hwmod_class,
1473         .clkdm_name     = "l4cfg_clkdm",
1474         .prcm = {
1475                 .omap4 = {
1476                         .clkctrl_offs = OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1477                         .context_offs = OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1478                 },
1479         },
1480 };
1481
1482 /*
1483  * 'ocp2scp' class
1484  * bridge to transform ocp interface protocol to scp (serial control port)
1485  * protocol
1486  */
1487
1488 static struct omap_hwmod_class_sysconfig omap54xx_ocp2scp_sysc = {
1489         .rev_offs       = 0x0000,
1490         .sysc_offs      = 0x0010,
1491         .syss_offs      = 0x0014,
1492         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1493                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1494         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1495         .sysc_fields    = &omap_hwmod_sysc_type1,
1496 };
1497
1498 static struct omap_hwmod_class omap54xx_ocp2scp_hwmod_class = {
1499         .name   = "ocp2scp",
1500         .sysc   = &omap54xx_ocp2scp_sysc,
1501 };
1502
1503 /* ocp2scp1 */
1504 static struct omap_hwmod omap54xx_ocp2scp1_hwmod = {
1505         .name           = "ocp2scp1",
1506         .class          = &omap54xx_ocp2scp_hwmod_class,
1507         .clkdm_name     = "l3init_clkdm",
1508         .main_clk       = "l4_root_clk_div",
1509         .prcm = {
1510                 .omap4 = {
1511                         .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1512                         .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1513                         .modulemode   = MODULEMODE_HWCTRL,
1514                 },
1515         },
1516 };
1517
1518 /*
1519  * 'timer' class
1520  * general purpose timer module with accurate 1ms tick
1521  * This class contains several variants: ['timer_1ms', 'timer']
1522  */
1523
1524 static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
1525         .rev_offs       = 0x0000,
1526         .sysc_offs      = 0x0010,
1527         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1528                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1529         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1530                            SIDLE_SMART_WKUP),
1531         .sysc_fields    = &omap_hwmod_sysc_type2,
1532 };
1533
1534 static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
1535         .name   = "timer",
1536         .sysc   = &omap54xx_timer_1ms_sysc,
1537 };
1538
1539 static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = {
1540         .rev_offs       = 0x0000,
1541         .sysc_offs      = 0x0010,
1542         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1543                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1544         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1545                            SIDLE_SMART_WKUP),
1546         .sysc_fields    = &omap_hwmod_sysc_type2,
1547 };
1548
1549 static struct omap_hwmod_class omap54xx_timer_hwmod_class = {
1550         .name   = "timer",
1551         .sysc   = &omap54xx_timer_sysc,
1552 };
1553
1554 /* timer1 */
1555 static struct omap_hwmod omap54xx_timer1_hwmod = {
1556         .name           = "timer1",
1557         .class          = &omap54xx_timer_1ms_hwmod_class,
1558         .clkdm_name     = "wkupaon_clkdm",
1559         .main_clk       = "timer1_gfclk_mux",
1560         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1561         .prcm = {
1562                 .omap4 = {
1563                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1564                         .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1565                         .modulemode   = MODULEMODE_SWCTRL,
1566                 },
1567         },
1568 };
1569
1570 /* timer2 */
1571 static struct omap_hwmod omap54xx_timer2_hwmod = {
1572         .name           = "timer2",
1573         .class          = &omap54xx_timer_1ms_hwmod_class,
1574         .clkdm_name     = "l4per_clkdm",
1575         .main_clk       = "timer2_gfclk_mux",
1576         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1577         .prcm = {
1578                 .omap4 = {
1579                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1580                         .context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1581                         .modulemode   = MODULEMODE_SWCTRL,
1582                 },
1583         },
1584 };
1585
1586 /* timer3 */
1587 static struct omap_hwmod omap54xx_timer3_hwmod = {
1588         .name           = "timer3",
1589         .class          = &omap54xx_timer_hwmod_class,
1590         .clkdm_name     = "l4per_clkdm",
1591         .main_clk       = "timer3_gfclk_mux",
1592         .prcm = {
1593                 .omap4 = {
1594                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1595                         .context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1596                         .modulemode   = MODULEMODE_SWCTRL,
1597                 },
1598         },
1599 };
1600
1601 /* timer4 */
1602 static struct omap_hwmod omap54xx_timer4_hwmod = {
1603         .name           = "timer4",
1604         .class          = &omap54xx_timer_hwmod_class,
1605         .clkdm_name     = "l4per_clkdm",
1606         .main_clk       = "timer4_gfclk_mux",
1607         .prcm = {
1608                 .omap4 = {
1609                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1610                         .context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1611                         .modulemode   = MODULEMODE_SWCTRL,
1612                 },
1613         },
1614 };
1615
1616 /* timer5 */
1617 static struct omap_hwmod omap54xx_timer5_hwmod = {
1618         .name           = "timer5",
1619         .class          = &omap54xx_timer_hwmod_class,
1620         .clkdm_name     = "abe_clkdm",
1621         .main_clk       = "timer5_gfclk_mux",
1622         .prcm = {
1623                 .omap4 = {
1624                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET,
1625                         .context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET,
1626                         .modulemode   = MODULEMODE_SWCTRL,
1627                 },
1628         },
1629 };
1630
1631 /* timer6 */
1632 static struct omap_hwmod omap54xx_timer6_hwmod = {
1633         .name           = "timer6",
1634         .class          = &omap54xx_timer_hwmod_class,
1635         .clkdm_name     = "abe_clkdm",
1636         .main_clk       = "timer6_gfclk_mux",
1637         .prcm = {
1638                 .omap4 = {
1639                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET,
1640                         .context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET,
1641                         .modulemode   = MODULEMODE_SWCTRL,
1642                 },
1643         },
1644 };
1645
1646 /* timer7 */
1647 static struct omap_hwmod omap54xx_timer7_hwmod = {
1648         .name           = "timer7",
1649         .class          = &omap54xx_timer_hwmod_class,
1650         .clkdm_name     = "abe_clkdm",
1651         .main_clk       = "timer7_gfclk_mux",
1652         .prcm = {
1653                 .omap4 = {
1654                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET,
1655                         .context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET,
1656                         .modulemode   = MODULEMODE_SWCTRL,
1657                 },
1658         },
1659 };
1660
1661 /* timer8 */
1662 static struct omap_hwmod omap54xx_timer8_hwmod = {
1663         .name           = "timer8",
1664         .class          = &omap54xx_timer_hwmod_class,
1665         .clkdm_name     = "abe_clkdm",
1666         .main_clk       = "timer8_gfclk_mux",
1667         .prcm = {
1668                 .omap4 = {
1669                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET,
1670                         .context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET,
1671                         .modulemode   = MODULEMODE_SWCTRL,
1672                 },
1673         },
1674 };
1675
1676 /* timer9 */
1677 static struct omap_hwmod omap54xx_timer9_hwmod = {
1678         .name           = "timer9",
1679         .class          = &omap54xx_timer_hwmod_class,
1680         .clkdm_name     = "l4per_clkdm",
1681         .main_clk       = "timer9_gfclk_mux",
1682         .prcm = {
1683                 .omap4 = {
1684                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1685                         .context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1686                         .modulemode   = MODULEMODE_SWCTRL,
1687                 },
1688         },
1689 };
1690
1691 /* timer10 */
1692 static struct omap_hwmod omap54xx_timer10_hwmod = {
1693         .name           = "timer10",
1694         .class          = &omap54xx_timer_1ms_hwmod_class,
1695         .clkdm_name     = "l4per_clkdm",
1696         .main_clk       = "timer10_gfclk_mux",
1697         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1698         .prcm = {
1699                 .omap4 = {
1700                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1701                         .context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1702                         .modulemode   = MODULEMODE_SWCTRL,
1703                 },
1704         },
1705 };
1706
1707 /* timer11 */
1708 static struct omap_hwmod omap54xx_timer11_hwmod = {
1709         .name           = "timer11",
1710         .class          = &omap54xx_timer_hwmod_class,
1711         .clkdm_name     = "l4per_clkdm",
1712         .main_clk       = "timer11_gfclk_mux",
1713         .prcm = {
1714                 .omap4 = {
1715                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1716                         .context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1717                         .modulemode   = MODULEMODE_SWCTRL,
1718                 },
1719         },
1720 };
1721
1722 /*
1723  * 'uart' class
1724  * universal asynchronous receiver/transmitter (uart)
1725  */
1726
1727 static struct omap_hwmod_class_sysconfig omap54xx_uart_sysc = {
1728         .rev_offs       = 0x0050,
1729         .sysc_offs      = 0x0054,
1730         .syss_offs      = 0x0058,
1731         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1732                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1733                            SYSS_HAS_RESET_STATUS),
1734         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1735                            SIDLE_SMART_WKUP),
1736         .sysc_fields    = &omap_hwmod_sysc_type1,
1737 };
1738
1739 static struct omap_hwmod_class omap54xx_uart_hwmod_class = {
1740         .name   = "uart",
1741         .sysc   = &omap54xx_uart_sysc,
1742 };
1743
1744 /* uart1 */
1745 static struct omap_hwmod omap54xx_uart1_hwmod = {
1746         .name           = "uart1",
1747         .class          = &omap54xx_uart_hwmod_class,
1748         .clkdm_name     = "l4per_clkdm",
1749         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1750         .main_clk       = "func_48m_fclk",
1751         .prcm = {
1752                 .omap4 = {
1753                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
1754                         .context_offs = OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET,
1755                         .modulemode   = MODULEMODE_SWCTRL,
1756                 },
1757         },
1758 };
1759
1760 /* uart2 */
1761 static struct omap_hwmod omap54xx_uart2_hwmod = {
1762         .name           = "uart2",
1763         .class          = &omap54xx_uart_hwmod_class,
1764         .clkdm_name     = "l4per_clkdm",
1765         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1766         .main_clk       = "func_48m_fclk",
1767         .prcm = {
1768                 .omap4 = {
1769                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
1770                         .context_offs = OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET,
1771                         .modulemode   = MODULEMODE_SWCTRL,
1772                 },
1773         },
1774 };
1775
1776 /* uart3 */
1777 static struct omap_hwmod omap54xx_uart3_hwmod = {
1778         .name           = "uart3",
1779         .class          = &omap54xx_uart_hwmod_class,
1780         .clkdm_name     = "l4per_clkdm",
1781         .flags          = DEBUG_OMAP4UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
1782         .main_clk       = "func_48m_fclk",
1783         .prcm = {
1784                 .omap4 = {
1785                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
1786                         .context_offs = OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET,
1787                         .modulemode   = MODULEMODE_SWCTRL,
1788                 },
1789         },
1790 };
1791
1792 /* uart4 */
1793 static struct omap_hwmod omap54xx_uart4_hwmod = {
1794         .name           = "uart4",
1795         .class          = &omap54xx_uart_hwmod_class,
1796         .clkdm_name     = "l4per_clkdm",
1797         .flags          = DEBUG_OMAP4UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
1798         .main_clk       = "func_48m_fclk",
1799         .prcm = {
1800                 .omap4 = {
1801                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
1802                         .context_offs = OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET,
1803                         .modulemode   = MODULEMODE_SWCTRL,
1804                 },
1805         },
1806 };
1807
1808 /* uart5 */
1809 static struct omap_hwmod omap54xx_uart5_hwmod = {
1810         .name           = "uart5",
1811         .class          = &omap54xx_uart_hwmod_class,
1812         .clkdm_name     = "l4per_clkdm",
1813         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1814         .main_clk       = "func_48m_fclk",
1815         .prcm = {
1816                 .omap4 = {
1817                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
1818                         .context_offs = OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET,
1819                         .modulemode   = MODULEMODE_SWCTRL,
1820                 },
1821         },
1822 };
1823
1824 /* uart6 */
1825 static struct omap_hwmod omap54xx_uart6_hwmod = {
1826         .name           = "uart6",
1827         .class          = &omap54xx_uart_hwmod_class,
1828         .clkdm_name     = "l4per_clkdm",
1829         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1830         .main_clk       = "func_48m_fclk",
1831         .prcm = {
1832                 .omap4 = {
1833                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET,
1834                         .context_offs = OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET,
1835                         .modulemode   = MODULEMODE_SWCTRL,
1836                 },
1837         },
1838 };
1839
1840 /*
1841  * 'usb_host_hs' class
1842  * high-speed multi-port usb host controller
1843  */
1844
1845 static struct omap_hwmod_class_sysconfig omap54xx_usb_host_hs_sysc = {
1846         .rev_offs       = 0x0000,
1847         .sysc_offs      = 0x0010,
1848         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1849                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1850         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1851                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1852                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1853         .sysc_fields    = &omap_hwmod_sysc_type2,
1854 };
1855
1856 static struct omap_hwmod_class omap54xx_usb_host_hs_hwmod_class = {
1857         .name   = "usb_host_hs",
1858         .sysc   = &omap54xx_usb_host_hs_sysc,
1859 };
1860
1861 static struct omap_hwmod omap54xx_usb_host_hs_hwmod = {
1862         .name           = "usb_host_hs",
1863         .class          = &omap54xx_usb_host_hs_hwmod_class,
1864         .clkdm_name     = "l3init_clkdm",
1865         /*
1866          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1867          * id: i660
1868          *
1869          * Description:
1870          * In the following configuration :
1871          * - USBHOST module is set to smart-idle mode
1872          * - PRCM asserts idle_req to the USBHOST module ( This typically
1873          *   happens when the system is going to a low power mode : all ports
1874          *   have been suspended, the master part of the USBHOST module has
1875          *   entered the standby state, and SW has cut the functional clocks)
1876          * - an USBHOST interrupt occurs before the module is able to answer
1877          *   idle_ack, typically a remote wakeup IRQ.
1878          * Then the USB HOST module will enter a deadlock situation where it
1879          * is no more accessible nor functional.
1880          *
1881          * Workaround:
1882          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1883          */
1884
1885         /*
1886          * Errata: USB host EHCI may stall when entering smart-standby mode
1887          * Id: i571
1888          *
1889          * Description:
1890          * When the USBHOST module is set to smart-standby mode, and when it is
1891          * ready to enter the standby state (i.e. all ports are suspended and
1892          * all attached devices are in suspend mode), then it can wrongly assert
1893          * the Mstandby signal too early while there are still some residual OCP
1894          * transactions ongoing. If this condition occurs, the internal state
1895          * machine may go to an undefined state and the USB link may be stuck
1896          * upon the next resume.
1897          *
1898          * Workaround:
1899          * Don't use smart standby; use only force standby,
1900          * hence HWMOD_SWSUP_MSTANDBY
1901          */
1902
1903         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1904         .main_clk       = "l3init_60m_fclk",
1905         .prcm = {
1906                 .omap4 = {
1907                         .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET,
1908                         .context_offs = OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET,
1909                         .modulemode   = MODULEMODE_SWCTRL,
1910                 },
1911         },
1912 };
1913
1914 /*
1915  * 'usb_tll_hs' class
1916  * usb_tll_hs module is the adapter on the usb_host_hs ports
1917  */
1918
1919 static struct omap_hwmod_class_sysconfig omap54xx_usb_tll_hs_sysc = {
1920         .rev_offs       = 0x0000,
1921         .sysc_offs      = 0x0010,
1922         .syss_offs      = 0x0014,
1923         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1924                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1925                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1926         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1927         .sysc_fields    = &omap_hwmod_sysc_type1,
1928 };
1929
1930 static struct omap_hwmod_class omap54xx_usb_tll_hs_hwmod_class = {
1931         .name   = "usb_tll_hs",
1932         .sysc   = &omap54xx_usb_tll_hs_sysc,
1933 };
1934
1935 static struct omap_hwmod omap54xx_usb_tll_hs_hwmod = {
1936         .name           = "usb_tll_hs",
1937         .class          = &omap54xx_usb_tll_hs_hwmod_class,
1938         .clkdm_name     = "l3init_clkdm",
1939         .main_clk       = "l4_root_clk_div",
1940         .prcm = {
1941                 .omap4 = {
1942                         .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET,
1943                         .context_offs = OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET,
1944                         .modulemode   = MODULEMODE_HWCTRL,
1945                 },
1946         },
1947 };
1948
1949 /*
1950  * 'usb_otg_ss' class
1951  * 2.0 super speed (usb_otg_ss) controller
1952  */
1953
1954 static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
1955         .rev_offs       = 0x0000,
1956         .sysc_offs      = 0x0010,
1957         .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
1958                            SYSC_HAS_SIDLEMODE),
1959         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1960                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1961                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1962         .sysc_fields    = &omap_hwmod_sysc_type2,
1963 };
1964
1965 static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
1966         .name   = "usb_otg_ss",
1967         .sysc   = &omap54xx_usb_otg_ss_sysc,
1968 };
1969
1970 /* usb_otg_ss */
1971 static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
1972         { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
1973 };
1974
1975 static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
1976         .name           = "usb_otg_ss",
1977         .class          = &omap54xx_usb_otg_ss_hwmod_class,
1978         .clkdm_name     = "l3init_clkdm",
1979         .flags          = HWMOD_SWSUP_SIDLE,
1980         .main_clk       = "dpll_core_h13x2_ck",
1981         .prcm = {
1982                 .omap4 = {
1983                         .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
1984                         .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET,
1985                         .modulemode   = MODULEMODE_HWCTRL,
1986                 },
1987         },
1988         .opt_clks       = usb_otg_ss_opt_clks,
1989         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss_opt_clks),
1990 };
1991
1992 /*
1993  * 'wd_timer' class
1994  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1995  * overflow condition
1996  */
1997
1998 static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc = {
1999         .rev_offs       = 0x0000,
2000         .sysc_offs      = 0x0010,
2001         .syss_offs      = 0x0014,
2002         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2003                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2004         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2005                            SIDLE_SMART_WKUP),
2006         .sysc_fields    = &omap_hwmod_sysc_type1,
2007 };
2008
2009 static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class = {
2010         .name           = "wd_timer",
2011         .sysc           = &omap54xx_wd_timer_sysc,
2012         .pre_shutdown   = &omap2_wd_timer_disable,
2013 };
2014
2015 /* wd_timer2 */
2016 static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
2017         .name           = "wd_timer2",
2018         .class          = &omap54xx_wd_timer_hwmod_class,
2019         .clkdm_name     = "wkupaon_clkdm",
2020         .main_clk       = "sys_32k_ck",
2021         .prcm = {
2022                 .omap4 = {
2023                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2024                         .context_offs = OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2025                         .modulemode   = MODULEMODE_SWCTRL,
2026                 },
2027         },
2028 };
2029
2030 /*
2031  * 'ocp2scp' class
2032  * bridge to transform ocp interface protocol to scp (serial control port)
2033  * protocol
2034  */
2035 /* ocp2scp3 */
2036 static struct omap_hwmod omap54xx_ocp2scp3_hwmod;
2037 /* l4_cfg -> ocp2scp3 */
2038 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp3 = {
2039         .master         = &omap54xx_l4_cfg_hwmod,
2040         .slave          = &omap54xx_ocp2scp3_hwmod,
2041         .clk            = "l4_root_clk_div",
2042         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2043 };
2044
2045 static struct omap_hwmod omap54xx_ocp2scp3_hwmod = {
2046         .name           = "ocp2scp3",
2047         .class          = &omap54xx_ocp2scp_hwmod_class,
2048         .clkdm_name     = "l3init_clkdm",
2049         .prcm = {
2050                 .omap4 = {
2051                         .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
2052                         .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
2053                         .modulemode   = MODULEMODE_HWCTRL,
2054                 },
2055         },
2056 };
2057
2058 /*
2059  * 'sata' class
2060  * sata:  serial ata interface  gen2 compliant   ( 1 rx/ 1 tx)
2061  */
2062
2063 static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
2064         .sysc_offs      = 0x0000,
2065         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
2066         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2067                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2068                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2069         .sysc_fields    = &omap_hwmod_sysc_type2,
2070 };
2071
2072 static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
2073         .name   = "sata",
2074         .sysc   = &omap54xx_sata_sysc,
2075 };
2076
2077 /* sata */
2078 static struct omap_hwmod omap54xx_sata_hwmod = {
2079         .name           = "sata",
2080         .class          = &omap54xx_sata_hwmod_class,
2081         .clkdm_name     = "l3init_clkdm",
2082         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2083         .main_clk       = "func_48m_fclk",
2084         .mpu_rt_idx     = 1,
2085         .prcm = {
2086                 .omap4 = {
2087                         .clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
2088                         .context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
2089                         .modulemode   = MODULEMODE_SWCTRL,
2090                 },
2091         },
2092 };
2093
2094 /* l4_cfg -> sata */
2095 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = {
2096         .master         = &omap54xx_l4_cfg_hwmod,
2097         .slave          = &omap54xx_sata_hwmod,
2098         .clk            = "l3_iclk_div",
2099         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2100 };
2101
2102 /*
2103  * Interfaces
2104  */
2105
2106 /* l3_main_1 -> dmm */
2107 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
2108         .master         = &omap54xx_l3_main_1_hwmod,
2109         .slave          = &omap54xx_dmm_hwmod,
2110         .clk            = "l3_iclk_div",
2111         .user           = OCP_USER_SDMA,
2112 };
2113
2114 /* l3_main_3 -> l3_instr */
2115 static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
2116         .master         = &omap54xx_l3_main_3_hwmod,
2117         .slave          = &omap54xx_l3_instr_hwmod,
2118         .clk            = "l3_iclk_div",
2119         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2120 };
2121
2122 /* l3_main_2 -> l3_main_1 */
2123 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
2124         .master         = &omap54xx_l3_main_2_hwmod,
2125         .slave          = &omap54xx_l3_main_1_hwmod,
2126         .clk            = "l3_iclk_div",
2127         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2128 };
2129
2130 /* l4_cfg -> l3_main_1 */
2131 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
2132         .master         = &omap54xx_l4_cfg_hwmod,
2133         .slave          = &omap54xx_l3_main_1_hwmod,
2134         .clk            = "l3_iclk_div",
2135         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2136 };
2137
2138 /* l4_cfg -> mmu_dsp */
2139 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mmu_dsp = {
2140         .master         = &omap54xx_l4_cfg_hwmod,
2141         .slave          = &omap54xx_mmu_dsp_hwmod,
2142         .clk            = "l4_root_clk_div",
2143         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2144 };
2145
2146 /* mpu -> l3_main_1 */
2147 static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
2148         .master         = &omap54xx_mpu_hwmod,
2149         .slave          = &omap54xx_l3_main_1_hwmod,
2150         .clk            = "l3_iclk_div",
2151         .user           = OCP_USER_MPU,
2152 };
2153
2154 /* l3_main_1 -> l3_main_2 */
2155 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
2156         .master         = &omap54xx_l3_main_1_hwmod,
2157         .slave          = &omap54xx_l3_main_2_hwmod,
2158         .clk            = "l3_iclk_div",
2159         .user           = OCP_USER_MPU,
2160 };
2161
2162 /* l4_cfg -> l3_main_2 */
2163 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
2164         .master         = &omap54xx_l4_cfg_hwmod,
2165         .slave          = &omap54xx_l3_main_2_hwmod,
2166         .clk            = "l3_iclk_div",
2167         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2168 };
2169
2170 /* l3_main_2 -> mmu_ipu */
2171 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__mmu_ipu = {
2172         .master         = &omap54xx_l3_main_2_hwmod,
2173         .slave          = &omap54xx_mmu_ipu_hwmod,
2174         .clk            = "l3_iclk_div",
2175         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2176 };
2177
2178 /* l3_main_1 -> l3_main_3 */
2179 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
2180         .master         = &omap54xx_l3_main_1_hwmod,
2181         .slave          = &omap54xx_l3_main_3_hwmod,
2182         .clk            = "l3_iclk_div",
2183         .user           = OCP_USER_MPU,
2184 };
2185
2186 /* l3_main_2 -> l3_main_3 */
2187 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
2188         .master         = &omap54xx_l3_main_2_hwmod,
2189         .slave          = &omap54xx_l3_main_3_hwmod,
2190         .clk            = "l3_iclk_div",
2191         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2192 };
2193
2194 /* l4_cfg -> l3_main_3 */
2195 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
2196         .master         = &omap54xx_l4_cfg_hwmod,
2197         .slave          = &omap54xx_l3_main_3_hwmod,
2198         .clk            = "l3_iclk_div",
2199         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2200 };
2201
2202 /* l3_main_1 -> l4_abe */
2203 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
2204         .master         = &omap54xx_l3_main_1_hwmod,
2205         .slave          = &omap54xx_l4_abe_hwmod,
2206         .clk            = "abe_iclk",
2207         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2208 };
2209
2210 /* mpu -> l4_abe */
2211 static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
2212         .master         = &omap54xx_mpu_hwmod,
2213         .slave          = &omap54xx_l4_abe_hwmod,
2214         .clk            = "abe_iclk",
2215         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2216 };
2217
2218 /* l3_main_1 -> l4_cfg */
2219 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
2220         .master         = &omap54xx_l3_main_1_hwmod,
2221         .slave          = &omap54xx_l4_cfg_hwmod,
2222         .clk            = "l4_root_clk_div",
2223         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2224 };
2225
2226 /* l3_main_2 -> l4_per */
2227 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
2228         .master         = &omap54xx_l3_main_2_hwmod,
2229         .slave          = &omap54xx_l4_per_hwmod,
2230         .clk            = "l4_root_clk_div",
2231         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2232 };
2233
2234 /* l3_main_1 -> l4_wkup */
2235 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
2236         .master         = &omap54xx_l3_main_1_hwmod,
2237         .slave          = &omap54xx_l4_wkup_hwmod,
2238         .clk            = "wkupaon_iclk_mux",
2239         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2240 };
2241
2242 /* mpu -> mpu_private */
2243 static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
2244         .master         = &omap54xx_mpu_hwmod,
2245         .slave          = &omap54xx_mpu_private_hwmod,
2246         .clk            = "l3_iclk_div",
2247         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2248 };
2249
2250 /* l4_wkup -> counter_32k */
2251 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
2252         .master         = &omap54xx_l4_wkup_hwmod,
2253         .slave          = &omap54xx_counter_32k_hwmod,
2254         .clk            = "wkupaon_iclk_mux",
2255         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2256 };
2257
2258 static struct omap_hwmod_addr_space omap54xx_dma_system_addrs[] = {
2259         {
2260                 .pa_start       = 0x4a056000,
2261                 .pa_end         = 0x4a056fff,
2262                 .flags          = ADDR_TYPE_RT
2263         },
2264         { }
2265 };
2266
2267 /* l4_cfg -> dma_system */
2268 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = {
2269         .master         = &omap54xx_l4_cfg_hwmod,
2270         .slave          = &omap54xx_dma_system_hwmod,
2271         .clk            = "l4_root_clk_div",
2272         .addr           = omap54xx_dma_system_addrs,
2273         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2274 };
2275
2276 /* l4_abe -> dmic */
2277 static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = {
2278         .master         = &omap54xx_l4_abe_hwmod,
2279         .slave          = &omap54xx_dmic_hwmod,
2280         .clk            = "abe_iclk",
2281         .user           = OCP_USER_MPU,
2282 };
2283
2284 /* l3_main_2 -> dss */
2285 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss = {
2286         .master         = &omap54xx_l3_main_2_hwmod,
2287         .slave          = &omap54xx_dss_hwmod,
2288         .clk            = "l3_iclk_div",
2289         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2290 };
2291
2292 /* l3_main_2 -> dss_dispc */
2293 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dispc = {
2294         .master         = &omap54xx_l3_main_2_hwmod,
2295         .slave          = &omap54xx_dss_dispc_hwmod,
2296         .clk            = "l3_iclk_div",
2297         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2298 };
2299
2300 /* l3_main_2 -> dss_dsi1_a */
2301 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_a = {
2302         .master         = &omap54xx_l3_main_2_hwmod,
2303         .slave          = &omap54xx_dss_dsi1_a_hwmod,
2304         .clk            = "l3_iclk_div",
2305         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2306 };
2307
2308 /* l3_main_2 -> dss_dsi1_c */
2309 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_c = {
2310         .master         = &omap54xx_l3_main_2_hwmod,
2311         .slave          = &omap54xx_dss_dsi1_c_hwmod,
2312         .clk            = "l3_iclk_div",
2313         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2314 };
2315
2316 /* l3_main_2 -> dss_hdmi */
2317 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_hdmi = {
2318         .master         = &omap54xx_l3_main_2_hwmod,
2319         .slave          = &omap54xx_dss_hdmi_hwmod,
2320         .clk            = "l3_iclk_div",
2321         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2322 };
2323
2324 /* l3_main_2 -> dss_rfbi */
2325 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_rfbi = {
2326         .master         = &omap54xx_l3_main_2_hwmod,
2327         .slave          = &omap54xx_dss_rfbi_hwmod,
2328         .clk            = "l3_iclk_div",
2329         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2330 };
2331
2332 /* mpu -> emif1 */
2333 static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
2334         .master         = &omap54xx_mpu_hwmod,
2335         .slave          = &omap54xx_emif1_hwmod,
2336         .clk            = "dpll_core_h11x2_ck",
2337         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2338 };
2339
2340 /* mpu -> emif2 */
2341 static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
2342         .master         = &omap54xx_mpu_hwmod,
2343         .slave          = &omap54xx_emif2_hwmod,
2344         .clk            = "dpll_core_h11x2_ck",
2345         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2346 };
2347
2348 /* l4_wkup -> gpio1 */
2349 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__gpio1 = {
2350         .master         = &omap54xx_l4_wkup_hwmod,
2351         .slave          = &omap54xx_gpio1_hwmod,
2352         .clk            = "wkupaon_iclk_mux",
2353         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2354 };
2355
2356 /* l4_per -> gpio2 */
2357 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio2 = {
2358         .master         = &omap54xx_l4_per_hwmod,
2359         .slave          = &omap54xx_gpio2_hwmod,
2360         .clk            = "l4_root_clk_div",
2361         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2362 };
2363
2364 /* l4_per -> gpio3 */
2365 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio3 = {
2366         .master         = &omap54xx_l4_per_hwmod,
2367         .slave          = &omap54xx_gpio3_hwmod,
2368         .clk            = "l4_root_clk_div",
2369         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2370 };
2371
2372 /* l4_per -> gpio4 */
2373 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio4 = {
2374         .master         = &omap54xx_l4_per_hwmod,
2375         .slave          = &omap54xx_gpio4_hwmod,
2376         .clk            = "l4_root_clk_div",
2377         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2378 };
2379
2380 /* l4_per -> gpio5 */
2381 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio5 = {
2382         .master         = &omap54xx_l4_per_hwmod,
2383         .slave          = &omap54xx_gpio5_hwmod,
2384         .clk            = "l4_root_clk_div",
2385         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2386 };
2387
2388 /* l4_per -> gpio6 */
2389 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio6 = {
2390         .master         = &omap54xx_l4_per_hwmod,
2391         .slave          = &omap54xx_gpio6_hwmod,
2392         .clk            = "l4_root_clk_div",
2393         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2394 };
2395
2396 /* l4_per -> gpio7 */
2397 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio7 = {
2398         .master         = &omap54xx_l4_per_hwmod,
2399         .slave          = &omap54xx_gpio7_hwmod,
2400         .clk            = "l4_root_clk_div",
2401         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2402 };
2403
2404 /* l4_per -> gpio8 */
2405 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio8 = {
2406         .master         = &omap54xx_l4_per_hwmod,
2407         .slave          = &omap54xx_gpio8_hwmod,
2408         .clk            = "l4_root_clk_div",
2409         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2410 };
2411
2412 /* l4_per -> i2c1 */
2413 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c1 = {
2414         .master         = &omap54xx_l4_per_hwmod,
2415         .slave          = &omap54xx_i2c1_hwmod,
2416         .clk            = "l4_root_clk_div",
2417         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2418 };
2419
2420 /* l4_per -> i2c2 */
2421 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c2 = {
2422         .master         = &omap54xx_l4_per_hwmod,
2423         .slave          = &omap54xx_i2c2_hwmod,
2424         .clk            = "l4_root_clk_div",
2425         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2426 };
2427
2428 /* l4_per -> i2c3 */
2429 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c3 = {
2430         .master         = &omap54xx_l4_per_hwmod,
2431         .slave          = &omap54xx_i2c3_hwmod,
2432         .clk            = "l4_root_clk_div",
2433         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2434 };
2435
2436 /* l4_per -> i2c4 */
2437 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c4 = {
2438         .master         = &omap54xx_l4_per_hwmod,
2439         .slave          = &omap54xx_i2c4_hwmod,
2440         .clk            = "l4_root_clk_div",
2441         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2442 };
2443
2444 /* l4_per -> i2c5 */
2445 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c5 = {
2446         .master         = &omap54xx_l4_per_hwmod,
2447         .slave          = &omap54xx_i2c5_hwmod,
2448         .clk            = "l4_root_clk_div",
2449         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2450 };
2451
2452 /* l4_wkup -> kbd */
2453 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
2454         .master         = &omap54xx_l4_wkup_hwmod,
2455         .slave          = &omap54xx_kbd_hwmod,
2456         .clk            = "wkupaon_iclk_mux",
2457         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2458 };
2459
2460 /* l4_cfg -> mailbox */
2461 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mailbox = {
2462         .master         = &omap54xx_l4_cfg_hwmod,
2463         .slave          = &omap54xx_mailbox_hwmod,
2464         .clk            = "l4_root_clk_div",
2465         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2466 };
2467
2468 /* l4_abe -> mcbsp1 */
2469 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
2470         .master         = &omap54xx_l4_abe_hwmod,
2471         .slave          = &omap54xx_mcbsp1_hwmod,
2472         .clk            = "abe_iclk",
2473         .user           = OCP_USER_MPU,
2474 };
2475
2476 /* l4_abe -> mcbsp2 */
2477 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2 = {
2478         .master         = &omap54xx_l4_abe_hwmod,
2479         .slave          = &omap54xx_mcbsp2_hwmod,
2480         .clk            = "abe_iclk",
2481         .user           = OCP_USER_MPU,
2482 };
2483
2484 /* l4_abe -> mcbsp3 */
2485 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3 = {
2486         .master         = &omap54xx_l4_abe_hwmod,
2487         .slave          = &omap54xx_mcbsp3_hwmod,
2488         .clk            = "abe_iclk",
2489         .user           = OCP_USER_MPU,
2490 };
2491
2492 /* l4_abe -> mcpdm */
2493 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = {
2494         .master         = &omap54xx_l4_abe_hwmod,
2495         .slave          = &omap54xx_mcpdm_hwmod,
2496         .clk            = "abe_iclk",
2497         .user           = OCP_USER_MPU,
2498 };
2499
2500 /* l4_per -> mcspi1 */
2501 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1 = {
2502         .master         = &omap54xx_l4_per_hwmod,
2503         .slave          = &omap54xx_mcspi1_hwmod,
2504         .clk            = "l4_root_clk_div",
2505         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2506 };
2507
2508 /* l4_per -> mcspi2 */
2509 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2 = {
2510         .master         = &omap54xx_l4_per_hwmod,
2511         .slave          = &omap54xx_mcspi2_hwmod,
2512         .clk            = "l4_root_clk_div",
2513         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2514 };
2515
2516 /* l4_per -> mcspi3 */
2517 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3 = {
2518         .master         = &omap54xx_l4_per_hwmod,
2519         .slave          = &omap54xx_mcspi3_hwmod,
2520         .clk            = "l4_root_clk_div",
2521         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2522 };
2523
2524 /* l4_per -> mcspi4 */
2525 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = {
2526         .master         = &omap54xx_l4_per_hwmod,
2527         .slave          = &omap54xx_mcspi4_hwmod,
2528         .clk            = "l4_root_clk_div",
2529         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2530 };
2531
2532 /* l4_per -> mmc1 */
2533 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc1 = {
2534         .master         = &omap54xx_l4_per_hwmod,
2535         .slave          = &omap54xx_mmc1_hwmod,
2536         .clk            = "l3_iclk_div",
2537         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2538 };
2539
2540 /* l4_per -> mmc2 */
2541 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc2 = {
2542         .master         = &omap54xx_l4_per_hwmod,
2543         .slave          = &omap54xx_mmc2_hwmod,
2544         .clk            = "l3_iclk_div",
2545         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2546 };
2547
2548 /* l4_per -> mmc3 */
2549 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc3 = {
2550         .master         = &omap54xx_l4_per_hwmod,
2551         .slave          = &omap54xx_mmc3_hwmod,
2552         .clk            = "l4_root_clk_div",
2553         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2554 };
2555
2556 /* l4_per -> mmc4 */
2557 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc4 = {
2558         .master         = &omap54xx_l4_per_hwmod,
2559         .slave          = &omap54xx_mmc4_hwmod,
2560         .clk            = "l4_root_clk_div",
2561         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2562 };
2563
2564 /* l4_per -> mmc5 */
2565 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc5 = {
2566         .master         = &omap54xx_l4_per_hwmod,
2567         .slave          = &omap54xx_mmc5_hwmod,
2568         .clk            = "l4_root_clk_div",
2569         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2570 };
2571
2572 /* l4_cfg -> mpu */
2573 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
2574         .master         = &omap54xx_l4_cfg_hwmod,
2575         .slave          = &omap54xx_mpu_hwmod,
2576         .clk            = "l4_root_clk_div",
2577         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2578 };
2579
2580 /* l4_cfg -> spinlock */
2581 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__spinlock = {
2582         .master         = &omap54xx_l4_cfg_hwmod,
2583         .slave          = &omap54xx_spinlock_hwmod,
2584         .clk            = "l4_root_clk_div",
2585         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2586 };
2587
2588 /* l4_cfg -> ocp2scp1 */
2589 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp1 = {
2590         .master         = &omap54xx_l4_cfg_hwmod,
2591         .slave          = &omap54xx_ocp2scp1_hwmod,
2592         .clk            = "l4_root_clk_div",
2593         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2594 };
2595
2596 /* l4_wkup -> timer1 */
2597 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
2598         .master         = &omap54xx_l4_wkup_hwmod,
2599         .slave          = &omap54xx_timer1_hwmod,
2600         .clk            = "wkupaon_iclk_mux",
2601         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2602 };
2603
2604 /* l4_per -> timer2 */
2605 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = {
2606         .master         = &omap54xx_l4_per_hwmod,
2607         .slave          = &omap54xx_timer2_hwmod,
2608         .clk            = "l4_root_clk_div",
2609         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2610 };
2611
2612 /* l4_per -> timer3 */
2613 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = {
2614         .master         = &omap54xx_l4_per_hwmod,
2615         .slave          = &omap54xx_timer3_hwmod,
2616         .clk            = "l4_root_clk_div",
2617         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2618 };
2619
2620 /* l4_per -> timer4 */
2621 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = {
2622         .master         = &omap54xx_l4_per_hwmod,
2623         .slave          = &omap54xx_timer4_hwmod,
2624         .clk            = "l4_root_clk_div",
2625         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2626 };
2627
2628 /* l4_abe -> timer5 */
2629 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = {
2630         .master         = &omap54xx_l4_abe_hwmod,
2631         .slave          = &omap54xx_timer5_hwmod,
2632         .clk            = "abe_iclk",
2633         .user           = OCP_USER_MPU,
2634 };
2635
2636 /* l4_abe -> timer6 */
2637 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = {
2638         .master         = &omap54xx_l4_abe_hwmod,
2639         .slave          = &omap54xx_timer6_hwmod,
2640         .clk            = "abe_iclk",
2641         .user           = OCP_USER_MPU,
2642 };
2643
2644 /* l4_abe -> timer7 */
2645 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = {
2646         .master         = &omap54xx_l4_abe_hwmod,
2647         .slave          = &omap54xx_timer7_hwmod,
2648         .clk            = "abe_iclk",
2649         .user           = OCP_USER_MPU,
2650 };
2651
2652 /* l4_abe -> timer8 */
2653 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = {
2654         .master         = &omap54xx_l4_abe_hwmod,
2655         .slave          = &omap54xx_timer8_hwmod,
2656         .clk            = "abe_iclk",
2657         .user           = OCP_USER_MPU,
2658 };
2659
2660 /* l4_per -> timer9 */
2661 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = {
2662         .master         = &omap54xx_l4_per_hwmod,
2663         .slave          = &omap54xx_timer9_hwmod,
2664         .clk            = "l4_root_clk_div",
2665         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2666 };
2667
2668 /* l4_per -> timer10 */
2669 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = {
2670         .master         = &omap54xx_l4_per_hwmod,
2671         .slave          = &omap54xx_timer10_hwmod,
2672         .clk            = "l4_root_clk_div",
2673         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2674 };
2675
2676 /* l4_per -> timer11 */
2677 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = {
2678         .master         = &omap54xx_l4_per_hwmod,
2679         .slave          = &omap54xx_timer11_hwmod,
2680         .clk            = "l4_root_clk_div",
2681         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2682 };
2683
2684 /* l4_per -> uart1 */
2685 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart1 = {
2686         .master         = &omap54xx_l4_per_hwmod,
2687         .slave          = &omap54xx_uart1_hwmod,
2688         .clk            = "l4_root_clk_div",
2689         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2690 };
2691
2692 /* l4_per -> uart2 */
2693 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart2 = {
2694         .master         = &omap54xx_l4_per_hwmod,
2695         .slave          = &omap54xx_uart2_hwmod,
2696         .clk            = "l4_root_clk_div",
2697         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2698 };
2699
2700 /* l4_per -> uart3 */
2701 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart3 = {
2702         .master         = &omap54xx_l4_per_hwmod,
2703         .slave          = &omap54xx_uart3_hwmod,
2704         .clk            = "l4_root_clk_div",
2705         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2706 };
2707
2708 /* l4_per -> uart4 */
2709 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart4 = {
2710         .master         = &omap54xx_l4_per_hwmod,
2711         .slave          = &omap54xx_uart4_hwmod,
2712         .clk            = "l4_root_clk_div",
2713         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2714 };
2715
2716 /* l4_per -> uart5 */
2717 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart5 = {
2718         .master         = &omap54xx_l4_per_hwmod,
2719         .slave          = &omap54xx_uart5_hwmod,
2720         .clk            = "l4_root_clk_div",
2721         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2722 };
2723
2724 /* l4_per -> uart6 */
2725 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = {
2726         .master         = &omap54xx_l4_per_hwmod,
2727         .slave          = &omap54xx_uart6_hwmod,
2728         .clk            = "l4_root_clk_div",
2729         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2730 };
2731
2732 /* l4_cfg -> usb_host_hs */
2733 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs = {
2734         .master         = &omap54xx_l4_cfg_hwmod,
2735         .slave          = &omap54xx_usb_host_hs_hwmod,
2736         .clk            = "l3_iclk_div",
2737         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2738 };
2739
2740 /* l4_cfg -> usb_tll_hs */
2741 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_tll_hs = {
2742         .master         = &omap54xx_l4_cfg_hwmod,
2743         .slave          = &omap54xx_usb_tll_hs_hwmod,
2744         .clk            = "l4_root_clk_div",
2745         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2746 };
2747
2748 /* l4_cfg -> usb_otg_ss */
2749 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
2750         .master         = &omap54xx_l4_cfg_hwmod,
2751         .slave          = &omap54xx_usb_otg_ss_hwmod,
2752         .clk            = "dpll_core_h13x2_ck",
2753         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2754 };
2755
2756 /* l4_wkup -> wd_timer2 */
2757 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2 = {
2758         .master         = &omap54xx_l4_wkup_hwmod,
2759         .slave          = &omap54xx_wd_timer2_hwmod,
2760         .clk            = "wkupaon_iclk_mux",
2761         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2762 };
2763
2764 static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
2765         &omap54xx_l3_main_1__dmm,
2766         &omap54xx_l3_main_3__l3_instr,
2767         &omap54xx_l3_main_2__l3_main_1,
2768         &omap54xx_l4_cfg__l3_main_1,
2769         &omap54xx_mpu__l3_main_1,
2770         &omap54xx_l3_main_1__l3_main_2,
2771         &omap54xx_l4_cfg__l3_main_2,
2772         &omap54xx_l3_main_1__l3_main_3,
2773         &omap54xx_l3_main_2__l3_main_3,
2774         &omap54xx_l4_cfg__l3_main_3,
2775         &omap54xx_l3_main_1__l4_abe,
2776         &omap54xx_mpu__l4_abe,
2777         &omap54xx_l3_main_1__l4_cfg,
2778         &omap54xx_l3_main_2__l4_per,
2779         &omap54xx_l3_main_1__l4_wkup,
2780         &omap54xx_mpu__mpu_private,
2781         &omap54xx_l4_wkup__counter_32k,
2782         &omap54xx_l4_cfg__dma_system,
2783         &omap54xx_l4_abe__dmic,
2784         &omap54xx_l4_cfg__mmu_dsp,
2785         &omap54xx_l3_main_2__dss,
2786         &omap54xx_l3_main_2__dss_dispc,
2787         &omap54xx_l3_main_2__dss_dsi1_a,
2788         &omap54xx_l3_main_2__dss_dsi1_c,
2789         &omap54xx_l3_main_2__dss_hdmi,
2790         &omap54xx_l3_main_2__dss_rfbi,
2791         &omap54xx_mpu__emif1,
2792         &omap54xx_mpu__emif2,
2793         &omap54xx_l4_wkup__gpio1,
2794         &omap54xx_l4_per__gpio2,
2795         &omap54xx_l4_per__gpio3,
2796         &omap54xx_l4_per__gpio4,
2797         &omap54xx_l4_per__gpio5,
2798         &omap54xx_l4_per__gpio6,
2799         &omap54xx_l4_per__gpio7,
2800         &omap54xx_l4_per__gpio8,
2801         &omap54xx_l4_per__i2c1,
2802         &omap54xx_l4_per__i2c2,
2803         &omap54xx_l4_per__i2c3,
2804         &omap54xx_l4_per__i2c4,
2805         &omap54xx_l4_per__i2c5,
2806         &omap54xx_l3_main_2__mmu_ipu,
2807         &omap54xx_l4_wkup__kbd,
2808         &omap54xx_l4_cfg__mailbox,
2809         &omap54xx_l4_abe__mcbsp1,
2810         &omap54xx_l4_abe__mcbsp2,
2811         &omap54xx_l4_abe__mcbsp3,
2812         &omap54xx_l4_abe__mcpdm,
2813         &omap54xx_l4_per__mcspi1,
2814         &omap54xx_l4_per__mcspi2,
2815         &omap54xx_l4_per__mcspi3,
2816         &omap54xx_l4_per__mcspi4,
2817         &omap54xx_l4_per__mmc1,
2818         &omap54xx_l4_per__mmc2,
2819         &omap54xx_l4_per__mmc3,
2820         &omap54xx_l4_per__mmc4,
2821         &omap54xx_l4_per__mmc5,
2822         &omap54xx_l4_cfg__mpu,
2823         &omap54xx_l4_cfg__spinlock,
2824         &omap54xx_l4_cfg__ocp2scp1,
2825         &omap54xx_l4_wkup__timer1,
2826         &omap54xx_l4_per__timer2,
2827         &omap54xx_l4_per__timer3,
2828         &omap54xx_l4_per__timer4,
2829         &omap54xx_l4_abe__timer5,
2830         &omap54xx_l4_abe__timer6,
2831         &omap54xx_l4_abe__timer7,
2832         &omap54xx_l4_abe__timer8,
2833         &omap54xx_l4_per__timer9,
2834         &omap54xx_l4_per__timer10,
2835         &omap54xx_l4_per__timer11,
2836         &omap54xx_l4_per__uart1,
2837         &omap54xx_l4_per__uart2,
2838         &omap54xx_l4_per__uart3,
2839         &omap54xx_l4_per__uart4,
2840         &omap54xx_l4_per__uart5,
2841         &omap54xx_l4_per__uart6,
2842         &omap54xx_l4_cfg__usb_host_hs,
2843         &omap54xx_l4_cfg__usb_tll_hs,
2844         &omap54xx_l4_cfg__usb_otg_ss,
2845         &omap54xx_l4_wkup__wd_timer2,
2846         &omap54xx_l4_cfg__ocp2scp3,
2847         &omap54xx_l4_cfg__sata,
2848         NULL,
2849 };
2850
2851 int __init omap54xx_hwmod_init(void)
2852 {
2853         omap_hwmod_init();
2854         return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
2855 }