2 * Hardware modules present on the OMAP44xx chips
4 * Copyright (C) 2009-2011 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
23 #include <plat/omap_hwmod.h>
26 #include <plat/gpio.h>
28 #include <plat/mcspi.h>
29 #include <plat/mcbsp.h>
32 #include <plat/dmtimer.h>
33 #include <plat/common.h>
35 #include "omap_hwmod_common_data.h"
40 #include "prm-regbits-44xx.h"
43 /* Base offset for all OMAP4 interrupts external to MPUSS */
44 #define OMAP44XX_IRQ_GIC_START 32
46 /* Base offset for all OMAP4 dma requests */
47 #define OMAP44XX_DMA_REQ_START 1
49 /* Backward references (IPs with Bus Master capability) */
50 static struct omap_hwmod omap44xx_aess_hwmod;
51 static struct omap_hwmod omap44xx_dma_system_hwmod;
52 static struct omap_hwmod omap44xx_dmm_hwmod;
53 static struct omap_hwmod omap44xx_dsp_hwmod;
54 static struct omap_hwmod omap44xx_dss_hwmod;
55 static struct omap_hwmod omap44xx_emif_fw_hwmod;
56 static struct omap_hwmod omap44xx_hsi_hwmod;
57 static struct omap_hwmod omap44xx_ipu_hwmod;
58 static struct omap_hwmod omap44xx_iss_hwmod;
59 static struct omap_hwmod omap44xx_iva_hwmod;
60 static struct omap_hwmod omap44xx_l3_instr_hwmod;
61 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
62 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
63 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
64 static struct omap_hwmod omap44xx_l4_abe_hwmod;
65 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
66 static struct omap_hwmod omap44xx_l4_per_hwmod;
67 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
68 static struct omap_hwmod omap44xx_mmc1_hwmod;
69 static struct omap_hwmod omap44xx_mmc2_hwmod;
70 static struct omap_hwmod omap44xx_mpu_hwmod;
71 static struct omap_hwmod omap44xx_mpu_private_hwmod;
72 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
73 static struct omap_hwmod omap44xx_usb_host_hs_hwmod;
74 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod;
77 * Interconnects omap_hwmod structures
78 * hwmods that compose the global OMAP interconnect
85 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
90 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
91 { .irq = 113 + OMAP44XX_IRQ_GIC_START },
95 /* l3_main_1 -> dmm */
96 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
97 .master = &omap44xx_l3_main_1_hwmod,
98 .slave = &omap44xx_dmm_hwmod,
100 .user = OCP_USER_SDMA,
103 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
105 .pa_start = 0x4e000000,
106 .pa_end = 0x4e0007ff,
107 .flags = ADDR_TYPE_RT
113 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
114 .master = &omap44xx_mpu_hwmod,
115 .slave = &omap44xx_dmm_hwmod,
117 .addr = omap44xx_dmm_addrs,
118 .user = OCP_USER_MPU,
121 /* dmm slave ports */
122 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
123 &omap44xx_l3_main_1__dmm,
127 static struct omap_hwmod omap44xx_dmm_hwmod = {
129 .class = &omap44xx_dmm_hwmod_class,
130 .clkdm_name = "l3_emif_clkdm",
133 .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
134 .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
137 .slaves = omap44xx_dmm_slaves,
138 .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
139 .mpu_irqs = omap44xx_dmm_irqs,
144 * instance(s): emif_fw
146 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
152 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
153 .master = &omap44xx_dmm_hwmod,
154 .slave = &omap44xx_emif_fw_hwmod,
156 .user = OCP_USER_MPU | OCP_USER_SDMA,
159 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
161 .pa_start = 0x4a20c000,
162 .pa_end = 0x4a20c0ff,
163 .flags = ADDR_TYPE_RT
168 /* l4_cfg -> emif_fw */
169 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
170 .master = &omap44xx_l4_cfg_hwmod,
171 .slave = &omap44xx_emif_fw_hwmod,
173 .addr = omap44xx_emif_fw_addrs,
174 .user = OCP_USER_MPU,
177 /* emif_fw slave ports */
178 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
179 &omap44xx_dmm__emif_fw,
180 &omap44xx_l4_cfg__emif_fw,
183 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
185 .class = &omap44xx_emif_fw_hwmod_class,
186 .clkdm_name = "l3_emif_clkdm",
189 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
190 .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
193 .slaves = omap44xx_emif_fw_slaves,
194 .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
199 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
201 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
206 /* iva -> l3_instr */
207 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
208 .master = &omap44xx_iva_hwmod,
209 .slave = &omap44xx_l3_instr_hwmod,
211 .user = OCP_USER_MPU | OCP_USER_SDMA,
214 /* l3_main_3 -> l3_instr */
215 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
216 .master = &omap44xx_l3_main_3_hwmod,
217 .slave = &omap44xx_l3_instr_hwmod,
219 .user = OCP_USER_MPU | OCP_USER_SDMA,
222 /* l3_instr slave ports */
223 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
224 &omap44xx_iva__l3_instr,
225 &omap44xx_l3_main_3__l3_instr,
228 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
230 .class = &omap44xx_l3_hwmod_class,
231 .clkdm_name = "l3_instr_clkdm",
234 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
235 .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
236 .modulemode = MODULEMODE_HWCTRL,
239 .slaves = omap44xx_l3_instr_slaves,
240 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
244 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
245 { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
246 { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
250 /* dsp -> l3_main_1 */
251 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
252 .master = &omap44xx_dsp_hwmod,
253 .slave = &omap44xx_l3_main_1_hwmod,
255 .user = OCP_USER_MPU | OCP_USER_SDMA,
258 /* dss -> l3_main_1 */
259 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
260 .master = &omap44xx_dss_hwmod,
261 .slave = &omap44xx_l3_main_1_hwmod,
263 .user = OCP_USER_MPU | OCP_USER_SDMA,
266 /* l3_main_2 -> l3_main_1 */
267 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
268 .master = &omap44xx_l3_main_2_hwmod,
269 .slave = &omap44xx_l3_main_1_hwmod,
271 .user = OCP_USER_MPU | OCP_USER_SDMA,
274 /* l4_cfg -> l3_main_1 */
275 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
276 .master = &omap44xx_l4_cfg_hwmod,
277 .slave = &omap44xx_l3_main_1_hwmod,
279 .user = OCP_USER_MPU | OCP_USER_SDMA,
282 /* mmc1 -> l3_main_1 */
283 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
284 .master = &omap44xx_mmc1_hwmod,
285 .slave = &omap44xx_l3_main_1_hwmod,
287 .user = OCP_USER_MPU | OCP_USER_SDMA,
290 /* mmc2 -> l3_main_1 */
291 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
292 .master = &omap44xx_mmc2_hwmod,
293 .slave = &omap44xx_l3_main_1_hwmod,
295 .user = OCP_USER_MPU | OCP_USER_SDMA,
298 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
300 .pa_start = 0x44000000,
301 .pa_end = 0x44000fff,
302 .flags = ADDR_TYPE_RT
307 /* mpu -> l3_main_1 */
308 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
309 .master = &omap44xx_mpu_hwmod,
310 .slave = &omap44xx_l3_main_1_hwmod,
312 .addr = omap44xx_l3_main_1_addrs,
313 .user = OCP_USER_MPU,
316 /* l3_main_1 slave ports */
317 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
318 &omap44xx_dsp__l3_main_1,
319 &omap44xx_dss__l3_main_1,
320 &omap44xx_l3_main_2__l3_main_1,
321 &omap44xx_l4_cfg__l3_main_1,
322 &omap44xx_mmc1__l3_main_1,
323 &omap44xx_mmc2__l3_main_1,
324 &omap44xx_mpu__l3_main_1,
327 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
329 .class = &omap44xx_l3_hwmod_class,
330 .clkdm_name = "l3_1_clkdm",
331 .mpu_irqs = omap44xx_l3_main_1_irqs,
334 .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
335 .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
338 .slaves = omap44xx_l3_main_1_slaves,
339 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
343 /* dma_system -> l3_main_2 */
344 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
345 .master = &omap44xx_dma_system_hwmod,
346 .slave = &omap44xx_l3_main_2_hwmod,
348 .user = OCP_USER_MPU | OCP_USER_SDMA,
351 /* hsi -> l3_main_2 */
352 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
353 .master = &omap44xx_hsi_hwmod,
354 .slave = &omap44xx_l3_main_2_hwmod,
356 .user = OCP_USER_MPU | OCP_USER_SDMA,
359 /* ipu -> l3_main_2 */
360 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
361 .master = &omap44xx_ipu_hwmod,
362 .slave = &omap44xx_l3_main_2_hwmod,
364 .user = OCP_USER_MPU | OCP_USER_SDMA,
367 /* iss -> l3_main_2 */
368 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
369 .master = &omap44xx_iss_hwmod,
370 .slave = &omap44xx_l3_main_2_hwmod,
372 .user = OCP_USER_MPU | OCP_USER_SDMA,
375 /* iva -> l3_main_2 */
376 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
377 .master = &omap44xx_iva_hwmod,
378 .slave = &omap44xx_l3_main_2_hwmod,
380 .user = OCP_USER_MPU | OCP_USER_SDMA,
383 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
385 .pa_start = 0x44800000,
386 .pa_end = 0x44801fff,
387 .flags = ADDR_TYPE_RT
392 /* l3_main_1 -> l3_main_2 */
393 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
394 .master = &omap44xx_l3_main_1_hwmod,
395 .slave = &omap44xx_l3_main_2_hwmod,
397 .addr = omap44xx_l3_main_2_addrs,
398 .user = OCP_USER_MPU,
401 /* l4_cfg -> l3_main_2 */
402 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
403 .master = &omap44xx_l4_cfg_hwmod,
404 .slave = &omap44xx_l3_main_2_hwmod,
406 .user = OCP_USER_MPU | OCP_USER_SDMA,
409 /* usb_otg_hs -> l3_main_2 */
410 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
411 .master = &omap44xx_usb_otg_hs_hwmod,
412 .slave = &omap44xx_l3_main_2_hwmod,
414 .user = OCP_USER_MPU | OCP_USER_SDMA,
417 /* l3_main_2 slave ports */
418 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
419 &omap44xx_dma_system__l3_main_2,
420 &omap44xx_hsi__l3_main_2,
421 &omap44xx_ipu__l3_main_2,
422 &omap44xx_iss__l3_main_2,
423 &omap44xx_iva__l3_main_2,
424 &omap44xx_l3_main_1__l3_main_2,
425 &omap44xx_l4_cfg__l3_main_2,
426 &omap44xx_usb_otg_hs__l3_main_2,
429 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
431 .class = &omap44xx_l3_hwmod_class,
432 .clkdm_name = "l3_2_clkdm",
435 .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
436 .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
439 .slaves = omap44xx_l3_main_2_slaves,
440 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
444 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
446 .pa_start = 0x45000000,
447 .pa_end = 0x45000fff,
448 .flags = ADDR_TYPE_RT
453 /* l3_main_1 -> l3_main_3 */
454 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
455 .master = &omap44xx_l3_main_1_hwmod,
456 .slave = &omap44xx_l3_main_3_hwmod,
458 .addr = omap44xx_l3_main_3_addrs,
459 .user = OCP_USER_MPU,
462 /* l3_main_2 -> l3_main_3 */
463 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
464 .master = &omap44xx_l3_main_2_hwmod,
465 .slave = &omap44xx_l3_main_3_hwmod,
467 .user = OCP_USER_MPU | OCP_USER_SDMA,
470 /* l4_cfg -> l3_main_3 */
471 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
472 .master = &omap44xx_l4_cfg_hwmod,
473 .slave = &omap44xx_l3_main_3_hwmod,
475 .user = OCP_USER_MPU | OCP_USER_SDMA,
478 /* l3_main_3 slave ports */
479 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
480 &omap44xx_l3_main_1__l3_main_3,
481 &omap44xx_l3_main_2__l3_main_3,
482 &omap44xx_l4_cfg__l3_main_3,
485 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
487 .class = &omap44xx_l3_hwmod_class,
488 .clkdm_name = "l3_instr_clkdm",
491 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
492 .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
493 .modulemode = MODULEMODE_HWCTRL,
496 .slaves = omap44xx_l3_main_3_slaves,
497 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
502 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
504 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
510 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
511 .master = &omap44xx_aess_hwmod,
512 .slave = &omap44xx_l4_abe_hwmod,
513 .clk = "ocp_abe_iclk",
514 .user = OCP_USER_MPU | OCP_USER_SDMA,
518 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
519 .master = &omap44xx_dsp_hwmod,
520 .slave = &omap44xx_l4_abe_hwmod,
521 .clk = "ocp_abe_iclk",
522 .user = OCP_USER_MPU | OCP_USER_SDMA,
525 /* l3_main_1 -> l4_abe */
526 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
527 .master = &omap44xx_l3_main_1_hwmod,
528 .slave = &omap44xx_l4_abe_hwmod,
530 .user = OCP_USER_MPU | OCP_USER_SDMA,
534 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
535 .master = &omap44xx_mpu_hwmod,
536 .slave = &omap44xx_l4_abe_hwmod,
537 .clk = "ocp_abe_iclk",
538 .user = OCP_USER_MPU | OCP_USER_SDMA,
541 /* l4_abe slave ports */
542 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
543 &omap44xx_aess__l4_abe,
544 &omap44xx_dsp__l4_abe,
545 &omap44xx_l3_main_1__l4_abe,
546 &omap44xx_mpu__l4_abe,
549 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
551 .class = &omap44xx_l4_hwmod_class,
552 .clkdm_name = "abe_clkdm",
555 .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
558 .slaves = omap44xx_l4_abe_slaves,
559 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
563 /* l3_main_1 -> l4_cfg */
564 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
565 .master = &omap44xx_l3_main_1_hwmod,
566 .slave = &omap44xx_l4_cfg_hwmod,
568 .user = OCP_USER_MPU | OCP_USER_SDMA,
571 /* l4_cfg slave ports */
572 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
573 &omap44xx_l3_main_1__l4_cfg,
576 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
578 .class = &omap44xx_l4_hwmod_class,
579 .clkdm_name = "l4_cfg_clkdm",
582 .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
583 .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
586 .slaves = omap44xx_l4_cfg_slaves,
587 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
591 /* l3_main_2 -> l4_per */
592 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
593 .master = &omap44xx_l3_main_2_hwmod,
594 .slave = &omap44xx_l4_per_hwmod,
596 .user = OCP_USER_MPU | OCP_USER_SDMA,
599 /* l4_per slave ports */
600 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
601 &omap44xx_l3_main_2__l4_per,
604 static struct omap_hwmod omap44xx_l4_per_hwmod = {
606 .class = &omap44xx_l4_hwmod_class,
607 .clkdm_name = "l4_per_clkdm",
610 .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
611 .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
614 .slaves = omap44xx_l4_per_slaves,
615 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
619 /* l4_cfg -> l4_wkup */
620 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
621 .master = &omap44xx_l4_cfg_hwmod,
622 .slave = &omap44xx_l4_wkup_hwmod,
624 .user = OCP_USER_MPU | OCP_USER_SDMA,
627 /* l4_wkup slave ports */
628 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
629 &omap44xx_l4_cfg__l4_wkup,
632 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
634 .class = &omap44xx_l4_hwmod_class,
635 .clkdm_name = "l4_wkup_clkdm",
638 .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
639 .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
642 .slaves = omap44xx_l4_wkup_slaves,
643 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
648 * instance(s): mpu_private
650 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
655 /* mpu -> mpu_private */
656 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
657 .master = &omap44xx_mpu_hwmod,
658 .slave = &omap44xx_mpu_private_hwmod,
660 .user = OCP_USER_MPU | OCP_USER_SDMA,
663 /* mpu_private slave ports */
664 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
665 &omap44xx_mpu__mpu_private,
668 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
669 .name = "mpu_private",
670 .class = &omap44xx_mpu_bus_hwmod_class,
671 .clkdm_name = "mpuss_clkdm",
672 .slaves = omap44xx_mpu_private_slaves,
673 .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
677 * Modules omap_hwmod structures
679 * The following IPs are excluded for the moment because:
680 * - They do not need an explicit SW control using omap_hwmod API.
681 * - They still need to be validated with the driver
682 * properly adapted to omap_hwmod / omap_device
689 * ctrl_module_pad_core
690 * ctrl_module_pad_wkup
723 * audio engine sub system
726 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
729 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
730 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
731 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
732 MSTANDBY_SMART_WKUP),
733 .sysc_fields = &omap_hwmod_sysc_type2,
736 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
738 .sysc = &omap44xx_aess_sysc,
742 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
743 { .irq = 99 + OMAP44XX_IRQ_GIC_START },
747 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
748 { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
749 { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
750 { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
751 { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
752 { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
753 { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
754 { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
755 { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
759 /* aess master ports */
760 static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
761 &omap44xx_aess__l4_abe,
764 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
766 .pa_start = 0x401f1000,
767 .pa_end = 0x401f13ff,
768 .flags = ADDR_TYPE_RT
774 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
775 .master = &omap44xx_l4_abe_hwmod,
776 .slave = &omap44xx_aess_hwmod,
777 .clk = "ocp_abe_iclk",
778 .addr = omap44xx_aess_addrs,
779 .user = OCP_USER_MPU,
782 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
784 .pa_start = 0x490f1000,
785 .pa_end = 0x490f13ff,
786 .flags = ADDR_TYPE_RT
791 /* l4_abe -> aess (dma) */
792 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
793 .master = &omap44xx_l4_abe_hwmod,
794 .slave = &omap44xx_aess_hwmod,
795 .clk = "ocp_abe_iclk",
796 .addr = omap44xx_aess_dma_addrs,
797 .user = OCP_USER_SDMA,
800 /* aess slave ports */
801 static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
802 &omap44xx_l4_abe__aess,
803 &omap44xx_l4_abe__aess_dma,
806 static struct omap_hwmod omap44xx_aess_hwmod = {
808 .class = &omap44xx_aess_hwmod_class,
809 .clkdm_name = "abe_clkdm",
810 .mpu_irqs = omap44xx_aess_irqs,
811 .sdma_reqs = omap44xx_aess_sdma_reqs,
812 .main_clk = "aess_fck",
815 .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
816 .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
817 .modulemode = MODULEMODE_SWCTRL,
820 .slaves = omap44xx_aess_slaves,
821 .slaves_cnt = ARRAY_SIZE(omap44xx_aess_slaves),
822 .masters = omap44xx_aess_masters,
823 .masters_cnt = ARRAY_SIZE(omap44xx_aess_masters),
828 * bangap reference for ldo regulators
831 static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
836 static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
837 { .role = "fclk", .clk = "bandgap_fclk" },
840 static struct omap_hwmod omap44xx_bandgap_hwmod = {
842 .class = &omap44xx_bandgap_hwmod_class,
843 .clkdm_name = "l4_wkup_clkdm",
846 .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET,
849 .opt_clks = bandgap_opt_clks,
850 .opt_clks_cnt = ARRAY_SIZE(bandgap_opt_clks),
855 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
858 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
861 .sysc_flags = SYSC_HAS_SIDLEMODE,
862 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
864 .sysc_fields = &omap_hwmod_sysc_type1,
867 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
869 .sysc = &omap44xx_counter_sysc,
873 static struct omap_hwmod omap44xx_counter_32k_hwmod;
874 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
876 .pa_start = 0x4a304000,
877 .pa_end = 0x4a30401f,
878 .flags = ADDR_TYPE_RT
883 /* l4_wkup -> counter_32k */
884 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
885 .master = &omap44xx_l4_wkup_hwmod,
886 .slave = &omap44xx_counter_32k_hwmod,
887 .clk = "l4_wkup_clk_mux_ck",
888 .addr = omap44xx_counter_32k_addrs,
889 .user = OCP_USER_MPU | OCP_USER_SDMA,
892 /* counter_32k slave ports */
893 static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
894 &omap44xx_l4_wkup__counter_32k,
897 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
898 .name = "counter_32k",
899 .class = &omap44xx_counter_hwmod_class,
900 .clkdm_name = "l4_wkup_clkdm",
901 .flags = HWMOD_SWSUP_SIDLE,
902 .main_clk = "sys_32k_ck",
905 .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
906 .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
909 .slaves = omap44xx_counter_32k_slaves,
910 .slaves_cnt = ARRAY_SIZE(omap44xx_counter_32k_slaves),
915 * dma controller for data exchange between memory to memory (i.e. internal or
916 * external memory) and gp peripherals to memory or memory to gp peripherals
919 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
923 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
924 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
925 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
926 SYSS_HAS_RESET_STATUS),
927 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
928 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
929 .sysc_fields = &omap_hwmod_sysc_type1,
932 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
934 .sysc = &omap44xx_dma_sysc,
938 static struct omap_dma_dev_attr dma_dev_attr = {
939 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
940 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
945 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
946 { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
947 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
948 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
949 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
953 /* dma_system master ports */
954 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
955 &omap44xx_dma_system__l3_main_2,
958 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
960 .pa_start = 0x4a056000,
961 .pa_end = 0x4a056fff,
962 .flags = ADDR_TYPE_RT
967 /* l4_cfg -> dma_system */
968 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
969 .master = &omap44xx_l4_cfg_hwmod,
970 .slave = &omap44xx_dma_system_hwmod,
972 .addr = omap44xx_dma_system_addrs,
973 .user = OCP_USER_MPU | OCP_USER_SDMA,
976 /* dma_system slave ports */
977 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
978 &omap44xx_l4_cfg__dma_system,
981 static struct omap_hwmod omap44xx_dma_system_hwmod = {
982 .name = "dma_system",
983 .class = &omap44xx_dma_hwmod_class,
984 .clkdm_name = "l3_dma_clkdm",
985 .mpu_irqs = omap44xx_dma_system_irqs,
986 .main_clk = "l3_div_ck",
989 .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
990 .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
993 .dev_attr = &dma_dev_attr,
994 .slaves = omap44xx_dma_system_slaves,
995 .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves),
996 .masters = omap44xx_dma_system_masters,
997 .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters),
1002 * digital microphone controller
1005 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
1007 .sysc_offs = 0x0010,
1008 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1009 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1010 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1012 .sysc_fields = &omap_hwmod_sysc_type2,
1015 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
1017 .sysc = &omap44xx_dmic_sysc,
1021 static struct omap_hwmod omap44xx_dmic_hwmod;
1022 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
1023 { .irq = 114 + OMAP44XX_IRQ_GIC_START },
1027 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
1028 { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
1032 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
1034 .pa_start = 0x4012e000,
1035 .pa_end = 0x4012e07f,
1036 .flags = ADDR_TYPE_RT
1041 /* l4_abe -> dmic */
1042 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
1043 .master = &omap44xx_l4_abe_hwmod,
1044 .slave = &omap44xx_dmic_hwmod,
1045 .clk = "ocp_abe_iclk",
1046 .addr = omap44xx_dmic_addrs,
1047 .user = OCP_USER_MPU,
1050 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
1052 .pa_start = 0x4902e000,
1053 .pa_end = 0x4902e07f,
1054 .flags = ADDR_TYPE_RT
1059 /* l4_abe -> dmic (dma) */
1060 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
1061 .master = &omap44xx_l4_abe_hwmod,
1062 .slave = &omap44xx_dmic_hwmod,
1063 .clk = "ocp_abe_iclk",
1064 .addr = omap44xx_dmic_dma_addrs,
1065 .user = OCP_USER_SDMA,
1068 /* dmic slave ports */
1069 static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
1070 &omap44xx_l4_abe__dmic,
1071 &omap44xx_l4_abe__dmic_dma,
1074 static struct omap_hwmod omap44xx_dmic_hwmod = {
1076 .class = &omap44xx_dmic_hwmod_class,
1077 .clkdm_name = "abe_clkdm",
1078 .mpu_irqs = omap44xx_dmic_irqs,
1079 .sdma_reqs = omap44xx_dmic_sdma_reqs,
1080 .main_clk = "dmic_fck",
1083 .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
1084 .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
1085 .modulemode = MODULEMODE_SWCTRL,
1088 .slaves = omap44xx_dmic_slaves,
1089 .slaves_cnt = ARRAY_SIZE(omap44xx_dmic_slaves),
1097 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
1102 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
1103 { .irq = 28 + OMAP44XX_IRQ_GIC_START },
1107 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
1108 { .name = "mmu_cache", .rst_shift = 1 },
1111 static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
1112 { .name = "dsp", .rst_shift = 0 },
1116 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1117 .master = &omap44xx_dsp_hwmod,
1118 .slave = &omap44xx_iva_hwmod,
1119 .clk = "dpll_iva_m5x2_ck",
1122 /* dsp master ports */
1123 static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
1124 &omap44xx_dsp__l3_main_1,
1125 &omap44xx_dsp__l4_abe,
1130 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1131 .master = &omap44xx_l4_cfg_hwmod,
1132 .slave = &omap44xx_dsp_hwmod,
1134 .user = OCP_USER_MPU | OCP_USER_SDMA,
1137 /* dsp slave ports */
1138 static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1139 &omap44xx_l4_cfg__dsp,
1142 /* Pseudo hwmod for reset control purpose only */
1143 static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1145 .class = &omap44xx_dsp_hwmod_class,
1146 .clkdm_name = "tesla_clkdm",
1147 .flags = HWMOD_INIT_NO_RESET,
1148 .rst_lines = omap44xx_dsp_c0_resets,
1149 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1152 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1157 static struct omap_hwmod omap44xx_dsp_hwmod = {
1159 .class = &omap44xx_dsp_hwmod_class,
1160 .clkdm_name = "tesla_clkdm",
1161 .mpu_irqs = omap44xx_dsp_irqs,
1162 .rst_lines = omap44xx_dsp_resets,
1163 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
1164 .main_clk = "dsp_fck",
1167 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
1168 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1169 .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
1170 .modulemode = MODULEMODE_HWCTRL,
1173 .slaves = omap44xx_dsp_slaves,
1174 .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves),
1175 .masters = omap44xx_dsp_masters,
1176 .masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters),
1181 * display sub-system
1184 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1186 .syss_offs = 0x0014,
1187 .sysc_flags = SYSS_HAS_RESET_STATUS,
1190 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1192 .sysc = &omap44xx_dss_sysc,
1193 .reset = omap_dss_reset,
1197 /* dss master ports */
1198 static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1199 &omap44xx_dss__l3_main_1,
1202 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1204 .pa_start = 0x58000000,
1205 .pa_end = 0x5800007f,
1206 .flags = ADDR_TYPE_RT
1211 /* l3_main_2 -> dss */
1212 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1213 .master = &omap44xx_l3_main_2_hwmod,
1214 .slave = &omap44xx_dss_hwmod,
1216 .addr = omap44xx_dss_dma_addrs,
1217 .user = OCP_USER_SDMA,
1220 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1222 .pa_start = 0x48040000,
1223 .pa_end = 0x4804007f,
1224 .flags = ADDR_TYPE_RT
1230 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1231 .master = &omap44xx_l4_per_hwmod,
1232 .slave = &omap44xx_dss_hwmod,
1234 .addr = omap44xx_dss_addrs,
1235 .user = OCP_USER_MPU,
1238 /* dss slave ports */
1239 static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1240 &omap44xx_l3_main_2__dss,
1241 &omap44xx_l4_per__dss,
1244 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1245 { .role = "sys_clk", .clk = "dss_sys_clk" },
1246 { .role = "tv_clk", .clk = "dss_tv_clk" },
1247 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
1250 static struct omap_hwmod omap44xx_dss_hwmod = {
1252 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1253 .class = &omap44xx_dss_hwmod_class,
1254 .clkdm_name = "l3_dss_clkdm",
1255 .main_clk = "dss_dss_clk",
1258 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1259 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1262 .opt_clks = dss_opt_clks,
1263 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1264 .slaves = omap44xx_dss_slaves,
1265 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves),
1266 .masters = omap44xx_dss_masters,
1267 .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters),
1272 * display controller
1275 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1277 .sysc_offs = 0x0010,
1278 .syss_offs = 0x0014,
1279 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1280 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1281 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1282 SYSS_HAS_RESET_STATUS),
1283 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1284 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1285 .sysc_fields = &omap_hwmod_sysc_type1,
1288 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1290 .sysc = &omap44xx_dispc_sysc,
1294 static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1295 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1296 { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1300 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1301 { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
1305 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1307 .pa_start = 0x58001000,
1308 .pa_end = 0x58001fff,
1309 .flags = ADDR_TYPE_RT
1314 /* l3_main_2 -> dss_dispc */
1315 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1316 .master = &omap44xx_l3_main_2_hwmod,
1317 .slave = &omap44xx_dss_dispc_hwmod,
1319 .addr = omap44xx_dss_dispc_dma_addrs,
1320 .user = OCP_USER_SDMA,
1323 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1325 .pa_start = 0x48041000,
1326 .pa_end = 0x48041fff,
1327 .flags = ADDR_TYPE_RT
1332 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
1334 .has_framedonetv_irq = 1
1337 /* l4_per -> dss_dispc */
1338 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1339 .master = &omap44xx_l4_per_hwmod,
1340 .slave = &omap44xx_dss_dispc_hwmod,
1342 .addr = omap44xx_dss_dispc_addrs,
1343 .user = OCP_USER_MPU,
1346 /* dss_dispc slave ports */
1347 static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1348 &omap44xx_l3_main_2__dss_dispc,
1349 &omap44xx_l4_per__dss_dispc,
1352 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1353 .name = "dss_dispc",
1354 .class = &omap44xx_dispc_hwmod_class,
1355 .clkdm_name = "l3_dss_clkdm",
1356 .mpu_irqs = omap44xx_dss_dispc_irqs,
1357 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
1358 .main_clk = "dss_dss_clk",
1361 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1362 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1365 .slaves = omap44xx_dss_dispc_slaves,
1366 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1367 .dev_attr = &omap44xx_dss_dispc_dev_attr
1372 * display serial interface controller
1375 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1377 .sysc_offs = 0x0010,
1378 .syss_offs = 0x0014,
1379 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1380 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1381 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1382 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1383 .sysc_fields = &omap_hwmod_sysc_type1,
1386 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1388 .sysc = &omap44xx_dsi_sysc,
1392 static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1393 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1394 { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1398 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1399 { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
1403 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1405 .pa_start = 0x58004000,
1406 .pa_end = 0x580041ff,
1407 .flags = ADDR_TYPE_RT
1412 /* l3_main_2 -> dss_dsi1 */
1413 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1414 .master = &omap44xx_l3_main_2_hwmod,
1415 .slave = &omap44xx_dss_dsi1_hwmod,
1417 .addr = omap44xx_dss_dsi1_dma_addrs,
1418 .user = OCP_USER_SDMA,
1421 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1423 .pa_start = 0x48044000,
1424 .pa_end = 0x480441ff,
1425 .flags = ADDR_TYPE_RT
1430 /* l4_per -> dss_dsi1 */
1431 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1432 .master = &omap44xx_l4_per_hwmod,
1433 .slave = &omap44xx_dss_dsi1_hwmod,
1435 .addr = omap44xx_dss_dsi1_addrs,
1436 .user = OCP_USER_MPU,
1439 /* dss_dsi1 slave ports */
1440 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1441 &omap44xx_l3_main_2__dss_dsi1,
1442 &omap44xx_l4_per__dss_dsi1,
1445 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1446 { .role = "sys_clk", .clk = "dss_sys_clk" },
1449 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1451 .class = &omap44xx_dsi_hwmod_class,
1452 .clkdm_name = "l3_dss_clkdm",
1453 .mpu_irqs = omap44xx_dss_dsi1_irqs,
1454 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
1455 .main_clk = "dss_dss_clk",
1458 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1459 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1462 .opt_clks = dss_dsi1_opt_clks,
1463 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
1464 .slaves = omap44xx_dss_dsi1_slaves,
1465 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1469 static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1470 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1471 { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1475 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1476 { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1480 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1482 .pa_start = 0x58005000,
1483 .pa_end = 0x580051ff,
1484 .flags = ADDR_TYPE_RT
1489 /* l3_main_2 -> dss_dsi2 */
1490 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1491 .master = &omap44xx_l3_main_2_hwmod,
1492 .slave = &omap44xx_dss_dsi2_hwmod,
1494 .addr = omap44xx_dss_dsi2_dma_addrs,
1495 .user = OCP_USER_SDMA,
1498 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1500 .pa_start = 0x48045000,
1501 .pa_end = 0x480451ff,
1502 .flags = ADDR_TYPE_RT
1507 /* l4_per -> dss_dsi2 */
1508 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1509 .master = &omap44xx_l4_per_hwmod,
1510 .slave = &omap44xx_dss_dsi2_hwmod,
1512 .addr = omap44xx_dss_dsi2_addrs,
1513 .user = OCP_USER_MPU,
1516 /* dss_dsi2 slave ports */
1517 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1518 &omap44xx_l3_main_2__dss_dsi2,
1519 &omap44xx_l4_per__dss_dsi2,
1522 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
1523 { .role = "sys_clk", .clk = "dss_sys_clk" },
1526 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1528 .class = &omap44xx_dsi_hwmod_class,
1529 .clkdm_name = "l3_dss_clkdm",
1530 .mpu_irqs = omap44xx_dss_dsi2_irqs,
1531 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
1532 .main_clk = "dss_dss_clk",
1535 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1536 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1539 .opt_clks = dss_dsi2_opt_clks,
1540 .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
1541 .slaves = omap44xx_dss_dsi2_slaves,
1542 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1550 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1552 .sysc_offs = 0x0010,
1553 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1554 SYSC_HAS_SOFTRESET),
1555 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1557 .sysc_fields = &omap_hwmod_sysc_type2,
1560 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1562 .sysc = &omap44xx_hdmi_sysc,
1566 static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1567 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1568 { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1572 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1573 { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1577 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1579 .pa_start = 0x58006000,
1580 .pa_end = 0x58006fff,
1581 .flags = ADDR_TYPE_RT
1586 /* l3_main_2 -> dss_hdmi */
1587 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1588 .master = &omap44xx_l3_main_2_hwmod,
1589 .slave = &omap44xx_dss_hdmi_hwmod,
1591 .addr = omap44xx_dss_hdmi_dma_addrs,
1592 .user = OCP_USER_SDMA,
1595 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1597 .pa_start = 0x48046000,
1598 .pa_end = 0x48046fff,
1599 .flags = ADDR_TYPE_RT
1604 /* l4_per -> dss_hdmi */
1605 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1606 .master = &omap44xx_l4_per_hwmod,
1607 .slave = &omap44xx_dss_hdmi_hwmod,
1609 .addr = omap44xx_dss_hdmi_addrs,
1610 .user = OCP_USER_MPU,
1613 /* dss_hdmi slave ports */
1614 static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1615 &omap44xx_l3_main_2__dss_hdmi,
1616 &omap44xx_l4_per__dss_hdmi,
1619 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
1620 { .role = "sys_clk", .clk = "dss_sys_clk" },
1623 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1625 .class = &omap44xx_hdmi_hwmod_class,
1626 .clkdm_name = "l3_dss_clkdm",
1627 .mpu_irqs = omap44xx_dss_hdmi_irqs,
1628 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
1629 .main_clk = "dss_48mhz_clk",
1632 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1633 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1636 .opt_clks = dss_hdmi_opt_clks,
1637 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
1638 .slaves = omap44xx_dss_hdmi_slaves,
1639 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1644 * remote frame buffer interface
1647 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1649 .sysc_offs = 0x0010,
1650 .syss_offs = 0x0014,
1651 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1652 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1653 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1654 .sysc_fields = &omap_hwmod_sysc_type1,
1657 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1659 .sysc = &omap44xx_rfbi_sysc,
1663 static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1664 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1665 { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1669 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1671 .pa_start = 0x58002000,
1672 .pa_end = 0x580020ff,
1673 .flags = ADDR_TYPE_RT
1678 /* l3_main_2 -> dss_rfbi */
1679 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1680 .master = &omap44xx_l3_main_2_hwmod,
1681 .slave = &omap44xx_dss_rfbi_hwmod,
1683 .addr = omap44xx_dss_rfbi_dma_addrs,
1684 .user = OCP_USER_SDMA,
1687 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1689 .pa_start = 0x48042000,
1690 .pa_end = 0x480420ff,
1691 .flags = ADDR_TYPE_RT
1696 /* l4_per -> dss_rfbi */
1697 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1698 .master = &omap44xx_l4_per_hwmod,
1699 .slave = &omap44xx_dss_rfbi_hwmod,
1701 .addr = omap44xx_dss_rfbi_addrs,
1702 .user = OCP_USER_MPU,
1705 /* dss_rfbi slave ports */
1706 static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1707 &omap44xx_l3_main_2__dss_rfbi,
1708 &omap44xx_l4_per__dss_rfbi,
1711 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1712 { .role = "ick", .clk = "dss_fck" },
1715 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1717 .class = &omap44xx_rfbi_hwmod_class,
1718 .clkdm_name = "l3_dss_clkdm",
1719 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
1720 .main_clk = "dss_dss_clk",
1723 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1724 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1727 .opt_clks = dss_rfbi_opt_clks,
1728 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
1729 .slaves = omap44xx_dss_rfbi_slaves,
1730 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1738 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1743 static struct omap_hwmod omap44xx_dss_venc_hwmod;
1744 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1746 .pa_start = 0x58003000,
1747 .pa_end = 0x580030ff,
1748 .flags = ADDR_TYPE_RT
1753 /* l3_main_2 -> dss_venc */
1754 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1755 .master = &omap44xx_l3_main_2_hwmod,
1756 .slave = &omap44xx_dss_venc_hwmod,
1758 .addr = omap44xx_dss_venc_dma_addrs,
1759 .user = OCP_USER_SDMA,
1762 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1764 .pa_start = 0x48043000,
1765 .pa_end = 0x480430ff,
1766 .flags = ADDR_TYPE_RT
1771 /* l4_per -> dss_venc */
1772 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1773 .master = &omap44xx_l4_per_hwmod,
1774 .slave = &omap44xx_dss_venc_hwmod,
1776 .addr = omap44xx_dss_venc_addrs,
1777 .user = OCP_USER_MPU,
1780 /* dss_venc slave ports */
1781 static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1782 &omap44xx_l3_main_2__dss_venc,
1783 &omap44xx_l4_per__dss_venc,
1786 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1788 .class = &omap44xx_venc_hwmod_class,
1789 .clkdm_name = "l3_dss_clkdm",
1790 .main_clk = "dss_tv_clk",
1793 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1794 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1797 .slaves = omap44xx_dss_venc_slaves,
1798 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1803 * general purpose io module
1806 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1808 .sysc_offs = 0x0010,
1809 .syss_offs = 0x0114,
1810 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1811 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1812 SYSS_HAS_RESET_STATUS),
1813 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1815 .sysc_fields = &omap_hwmod_sysc_type1,
1818 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1820 .sysc = &omap44xx_gpio_sysc,
1825 static struct omap_gpio_dev_attr gpio_dev_attr = {
1831 static struct omap_hwmod omap44xx_gpio1_hwmod;
1832 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1833 { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1837 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1839 .pa_start = 0x4a310000,
1840 .pa_end = 0x4a3101ff,
1841 .flags = ADDR_TYPE_RT
1846 /* l4_wkup -> gpio1 */
1847 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1848 .master = &omap44xx_l4_wkup_hwmod,
1849 .slave = &omap44xx_gpio1_hwmod,
1850 .clk = "l4_wkup_clk_mux_ck",
1851 .addr = omap44xx_gpio1_addrs,
1852 .user = OCP_USER_MPU | OCP_USER_SDMA,
1855 /* gpio1 slave ports */
1856 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1857 &omap44xx_l4_wkup__gpio1,
1860 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1861 { .role = "dbclk", .clk = "gpio1_dbclk" },
1864 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1866 .class = &omap44xx_gpio_hwmod_class,
1867 .clkdm_name = "l4_wkup_clkdm",
1868 .mpu_irqs = omap44xx_gpio1_irqs,
1869 .main_clk = "gpio1_ick",
1872 .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1873 .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1874 .modulemode = MODULEMODE_HWCTRL,
1877 .opt_clks = gpio1_opt_clks,
1878 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1879 .dev_attr = &gpio_dev_attr,
1880 .slaves = omap44xx_gpio1_slaves,
1881 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves),
1885 static struct omap_hwmod omap44xx_gpio2_hwmod;
1886 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1887 { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1891 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1893 .pa_start = 0x48055000,
1894 .pa_end = 0x480551ff,
1895 .flags = ADDR_TYPE_RT
1900 /* l4_per -> gpio2 */
1901 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1902 .master = &omap44xx_l4_per_hwmod,
1903 .slave = &omap44xx_gpio2_hwmod,
1905 .addr = omap44xx_gpio2_addrs,
1906 .user = OCP_USER_MPU | OCP_USER_SDMA,
1909 /* gpio2 slave ports */
1910 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1911 &omap44xx_l4_per__gpio2,
1914 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1915 { .role = "dbclk", .clk = "gpio2_dbclk" },
1918 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1920 .class = &omap44xx_gpio_hwmod_class,
1921 .clkdm_name = "l4_per_clkdm",
1922 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1923 .mpu_irqs = omap44xx_gpio2_irqs,
1924 .main_clk = "gpio2_ick",
1927 .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1928 .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1929 .modulemode = MODULEMODE_HWCTRL,
1932 .opt_clks = gpio2_opt_clks,
1933 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1934 .dev_attr = &gpio_dev_attr,
1935 .slaves = omap44xx_gpio2_slaves,
1936 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves),
1940 static struct omap_hwmod omap44xx_gpio3_hwmod;
1941 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1942 { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1946 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1948 .pa_start = 0x48057000,
1949 .pa_end = 0x480571ff,
1950 .flags = ADDR_TYPE_RT
1955 /* l4_per -> gpio3 */
1956 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1957 .master = &omap44xx_l4_per_hwmod,
1958 .slave = &omap44xx_gpio3_hwmod,
1960 .addr = omap44xx_gpio3_addrs,
1961 .user = OCP_USER_MPU | OCP_USER_SDMA,
1964 /* gpio3 slave ports */
1965 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1966 &omap44xx_l4_per__gpio3,
1969 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1970 { .role = "dbclk", .clk = "gpio3_dbclk" },
1973 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1975 .class = &omap44xx_gpio_hwmod_class,
1976 .clkdm_name = "l4_per_clkdm",
1977 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1978 .mpu_irqs = omap44xx_gpio3_irqs,
1979 .main_clk = "gpio3_ick",
1982 .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1983 .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1984 .modulemode = MODULEMODE_HWCTRL,
1987 .opt_clks = gpio3_opt_clks,
1988 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1989 .dev_attr = &gpio_dev_attr,
1990 .slaves = omap44xx_gpio3_slaves,
1991 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves),
1995 static struct omap_hwmod omap44xx_gpio4_hwmod;
1996 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1997 { .irq = 32 + OMAP44XX_IRQ_GIC_START },
2001 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
2003 .pa_start = 0x48059000,
2004 .pa_end = 0x480591ff,
2005 .flags = ADDR_TYPE_RT
2010 /* l4_per -> gpio4 */
2011 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
2012 .master = &omap44xx_l4_per_hwmod,
2013 .slave = &omap44xx_gpio4_hwmod,
2015 .addr = omap44xx_gpio4_addrs,
2016 .user = OCP_USER_MPU | OCP_USER_SDMA,
2019 /* gpio4 slave ports */
2020 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
2021 &omap44xx_l4_per__gpio4,
2024 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2025 { .role = "dbclk", .clk = "gpio4_dbclk" },
2028 static struct omap_hwmod omap44xx_gpio4_hwmod = {
2030 .class = &omap44xx_gpio_hwmod_class,
2031 .clkdm_name = "l4_per_clkdm",
2032 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2033 .mpu_irqs = omap44xx_gpio4_irqs,
2034 .main_clk = "gpio4_ick",
2037 .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
2038 .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
2039 .modulemode = MODULEMODE_HWCTRL,
2042 .opt_clks = gpio4_opt_clks,
2043 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
2044 .dev_attr = &gpio_dev_attr,
2045 .slaves = omap44xx_gpio4_slaves,
2046 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves),
2050 static struct omap_hwmod omap44xx_gpio5_hwmod;
2051 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
2052 { .irq = 33 + OMAP44XX_IRQ_GIC_START },
2056 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
2058 .pa_start = 0x4805b000,
2059 .pa_end = 0x4805b1ff,
2060 .flags = ADDR_TYPE_RT
2065 /* l4_per -> gpio5 */
2066 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
2067 .master = &omap44xx_l4_per_hwmod,
2068 .slave = &omap44xx_gpio5_hwmod,
2070 .addr = omap44xx_gpio5_addrs,
2071 .user = OCP_USER_MPU | OCP_USER_SDMA,
2074 /* gpio5 slave ports */
2075 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
2076 &omap44xx_l4_per__gpio5,
2079 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2080 { .role = "dbclk", .clk = "gpio5_dbclk" },
2083 static struct omap_hwmod omap44xx_gpio5_hwmod = {
2085 .class = &omap44xx_gpio_hwmod_class,
2086 .clkdm_name = "l4_per_clkdm",
2087 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2088 .mpu_irqs = omap44xx_gpio5_irqs,
2089 .main_clk = "gpio5_ick",
2092 .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
2093 .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
2094 .modulemode = MODULEMODE_HWCTRL,
2097 .opt_clks = gpio5_opt_clks,
2098 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
2099 .dev_attr = &gpio_dev_attr,
2100 .slaves = omap44xx_gpio5_slaves,
2101 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves),
2105 static struct omap_hwmod omap44xx_gpio6_hwmod;
2106 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
2107 { .irq = 34 + OMAP44XX_IRQ_GIC_START },
2111 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
2113 .pa_start = 0x4805d000,
2114 .pa_end = 0x4805d1ff,
2115 .flags = ADDR_TYPE_RT
2120 /* l4_per -> gpio6 */
2121 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
2122 .master = &omap44xx_l4_per_hwmod,
2123 .slave = &omap44xx_gpio6_hwmod,
2125 .addr = omap44xx_gpio6_addrs,
2126 .user = OCP_USER_MPU | OCP_USER_SDMA,
2129 /* gpio6 slave ports */
2130 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
2131 &omap44xx_l4_per__gpio6,
2134 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2135 { .role = "dbclk", .clk = "gpio6_dbclk" },
2138 static struct omap_hwmod omap44xx_gpio6_hwmod = {
2140 .class = &omap44xx_gpio_hwmod_class,
2141 .clkdm_name = "l4_per_clkdm",
2142 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2143 .mpu_irqs = omap44xx_gpio6_irqs,
2144 .main_clk = "gpio6_ick",
2147 .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
2148 .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
2149 .modulemode = MODULEMODE_HWCTRL,
2152 .opt_clks = gpio6_opt_clks,
2153 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
2154 .dev_attr = &gpio_dev_attr,
2155 .slaves = omap44xx_gpio6_slaves,
2156 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves),
2161 * mipi high-speed synchronous serial interface (multichannel and full-duplex
2165 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
2167 .sysc_offs = 0x0010,
2168 .syss_offs = 0x0014,
2169 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
2170 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2171 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2172 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2173 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2174 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2175 .sysc_fields = &omap_hwmod_sysc_type1,
2178 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2180 .sysc = &omap44xx_hsi_sysc,
2184 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2185 { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2186 { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2187 { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2191 /* hsi master ports */
2192 static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2193 &omap44xx_hsi__l3_main_2,
2196 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2198 .pa_start = 0x4a058000,
2199 .pa_end = 0x4a05bfff,
2200 .flags = ADDR_TYPE_RT
2206 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2207 .master = &omap44xx_l4_cfg_hwmod,
2208 .slave = &omap44xx_hsi_hwmod,
2210 .addr = omap44xx_hsi_addrs,
2211 .user = OCP_USER_MPU | OCP_USER_SDMA,
2214 /* hsi slave ports */
2215 static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2216 &omap44xx_l4_cfg__hsi,
2219 static struct omap_hwmod omap44xx_hsi_hwmod = {
2221 .class = &omap44xx_hsi_hwmod_class,
2222 .clkdm_name = "l3_init_clkdm",
2223 .mpu_irqs = omap44xx_hsi_irqs,
2224 .main_clk = "hsi_fck",
2227 .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
2228 .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
2229 .modulemode = MODULEMODE_HWCTRL,
2232 .slaves = omap44xx_hsi_slaves,
2233 .slaves_cnt = ARRAY_SIZE(omap44xx_hsi_slaves),
2234 .masters = omap44xx_hsi_masters,
2235 .masters_cnt = ARRAY_SIZE(omap44xx_hsi_masters),
2240 * multimaster high-speed i2c controller
2243 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2244 .sysc_offs = 0x0010,
2245 .syss_offs = 0x0090,
2246 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2247 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2248 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2249 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2251 .clockact = CLOCKACT_TEST_ICLK,
2252 .sysc_fields = &omap_hwmod_sysc_type1,
2255 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
2257 .sysc = &omap44xx_i2c_sysc,
2258 .rev = OMAP_I2C_IP_VERSION_2,
2259 .reset = &omap_i2c_reset,
2262 static struct omap_i2c_dev_attr i2c_dev_attr = {
2263 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
2267 static struct omap_hwmod omap44xx_i2c1_hwmod;
2268 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2269 { .irq = 56 + OMAP44XX_IRQ_GIC_START },
2273 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2274 { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2275 { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
2279 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
2281 .pa_start = 0x48070000,
2282 .pa_end = 0x480700ff,
2283 .flags = ADDR_TYPE_RT
2288 /* l4_per -> i2c1 */
2289 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2290 .master = &omap44xx_l4_per_hwmod,
2291 .slave = &omap44xx_i2c1_hwmod,
2293 .addr = omap44xx_i2c1_addrs,
2294 .user = OCP_USER_MPU | OCP_USER_SDMA,
2297 /* i2c1 slave ports */
2298 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2299 &omap44xx_l4_per__i2c1,
2302 static struct omap_hwmod omap44xx_i2c1_hwmod = {
2304 .class = &omap44xx_i2c_hwmod_class,
2305 .clkdm_name = "l4_per_clkdm",
2306 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2307 .mpu_irqs = omap44xx_i2c1_irqs,
2308 .sdma_reqs = omap44xx_i2c1_sdma_reqs,
2309 .main_clk = "i2c1_fck",
2312 .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
2313 .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
2314 .modulemode = MODULEMODE_SWCTRL,
2317 .slaves = omap44xx_i2c1_slaves,
2318 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves),
2319 .dev_attr = &i2c_dev_attr,
2323 static struct omap_hwmod omap44xx_i2c2_hwmod;
2324 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2325 { .irq = 57 + OMAP44XX_IRQ_GIC_START },
2329 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2330 { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2331 { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
2335 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
2337 .pa_start = 0x48072000,
2338 .pa_end = 0x480720ff,
2339 .flags = ADDR_TYPE_RT
2344 /* l4_per -> i2c2 */
2345 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
2346 .master = &omap44xx_l4_per_hwmod,
2347 .slave = &omap44xx_i2c2_hwmod,
2349 .addr = omap44xx_i2c2_addrs,
2350 .user = OCP_USER_MPU | OCP_USER_SDMA,
2353 /* i2c2 slave ports */
2354 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2355 &omap44xx_l4_per__i2c2,
2358 static struct omap_hwmod omap44xx_i2c2_hwmod = {
2360 .class = &omap44xx_i2c_hwmod_class,
2361 .clkdm_name = "l4_per_clkdm",
2362 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2363 .mpu_irqs = omap44xx_i2c2_irqs,
2364 .sdma_reqs = omap44xx_i2c2_sdma_reqs,
2365 .main_clk = "i2c2_fck",
2368 .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
2369 .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
2370 .modulemode = MODULEMODE_SWCTRL,
2373 .slaves = omap44xx_i2c2_slaves,
2374 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves),
2375 .dev_attr = &i2c_dev_attr,
2379 static struct omap_hwmod omap44xx_i2c3_hwmod;
2380 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2381 { .irq = 61 + OMAP44XX_IRQ_GIC_START },
2385 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2386 { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2387 { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
2391 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
2393 .pa_start = 0x48060000,
2394 .pa_end = 0x480600ff,
2395 .flags = ADDR_TYPE_RT
2400 /* l4_per -> i2c3 */
2401 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
2402 .master = &omap44xx_l4_per_hwmod,
2403 .slave = &omap44xx_i2c3_hwmod,
2405 .addr = omap44xx_i2c3_addrs,
2406 .user = OCP_USER_MPU | OCP_USER_SDMA,
2409 /* i2c3 slave ports */
2410 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2411 &omap44xx_l4_per__i2c3,
2414 static struct omap_hwmod omap44xx_i2c3_hwmod = {
2416 .class = &omap44xx_i2c_hwmod_class,
2417 .clkdm_name = "l4_per_clkdm",
2418 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2419 .mpu_irqs = omap44xx_i2c3_irqs,
2420 .sdma_reqs = omap44xx_i2c3_sdma_reqs,
2421 .main_clk = "i2c3_fck",
2424 .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
2425 .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
2426 .modulemode = MODULEMODE_SWCTRL,
2429 .slaves = omap44xx_i2c3_slaves,
2430 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves),
2431 .dev_attr = &i2c_dev_attr,
2435 static struct omap_hwmod omap44xx_i2c4_hwmod;
2436 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2437 { .irq = 62 + OMAP44XX_IRQ_GIC_START },
2441 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2442 { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2443 { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
2447 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
2449 .pa_start = 0x48350000,
2450 .pa_end = 0x483500ff,
2451 .flags = ADDR_TYPE_RT
2456 /* l4_per -> i2c4 */
2457 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2458 .master = &omap44xx_l4_per_hwmod,
2459 .slave = &omap44xx_i2c4_hwmod,
2461 .addr = omap44xx_i2c4_addrs,
2462 .user = OCP_USER_MPU | OCP_USER_SDMA,
2465 /* i2c4 slave ports */
2466 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2467 &omap44xx_l4_per__i2c4,
2470 static struct omap_hwmod omap44xx_i2c4_hwmod = {
2472 .class = &omap44xx_i2c_hwmod_class,
2473 .clkdm_name = "l4_per_clkdm",
2474 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2475 .mpu_irqs = omap44xx_i2c4_irqs,
2476 .sdma_reqs = omap44xx_i2c4_sdma_reqs,
2477 .main_clk = "i2c4_fck",
2480 .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
2481 .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
2482 .modulemode = MODULEMODE_SWCTRL,
2485 .slaves = omap44xx_i2c4_slaves,
2486 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves),
2487 .dev_attr = &i2c_dev_attr,
2492 * imaging processor unit
2495 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2500 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2501 { .irq = 100 + OMAP44XX_IRQ_GIC_START },
2505 static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
2506 { .name = "cpu0", .rst_shift = 0 },
2509 static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2510 { .name = "cpu1", .rst_shift = 1 },
2513 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2514 { .name = "mmu_cache", .rst_shift = 2 },
2517 /* ipu master ports */
2518 static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2519 &omap44xx_ipu__l3_main_2,
2522 /* l3_main_2 -> ipu */
2523 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2524 .master = &omap44xx_l3_main_2_hwmod,
2525 .slave = &omap44xx_ipu_hwmod,
2527 .user = OCP_USER_MPU | OCP_USER_SDMA,
2530 /* ipu slave ports */
2531 static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2532 &omap44xx_l3_main_2__ipu,
2535 /* Pseudo hwmod for reset control purpose only */
2536 static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2538 .class = &omap44xx_ipu_hwmod_class,
2539 .clkdm_name = "ducati_clkdm",
2540 .flags = HWMOD_INIT_NO_RESET,
2541 .rst_lines = omap44xx_ipu_c0_resets,
2542 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2545 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2550 /* Pseudo hwmod for reset control purpose only */
2551 static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2553 .class = &omap44xx_ipu_hwmod_class,
2554 .clkdm_name = "ducati_clkdm",
2555 .flags = HWMOD_INIT_NO_RESET,
2556 .rst_lines = omap44xx_ipu_c1_resets,
2557 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2560 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2565 static struct omap_hwmod omap44xx_ipu_hwmod = {
2567 .class = &omap44xx_ipu_hwmod_class,
2568 .clkdm_name = "ducati_clkdm",
2569 .mpu_irqs = omap44xx_ipu_irqs,
2570 .rst_lines = omap44xx_ipu_resets,
2571 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
2572 .main_clk = "ipu_fck",
2575 .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2576 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2577 .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2578 .modulemode = MODULEMODE_HWCTRL,
2581 .slaves = omap44xx_ipu_slaves,
2582 .slaves_cnt = ARRAY_SIZE(omap44xx_ipu_slaves),
2583 .masters = omap44xx_ipu_masters,
2584 .masters_cnt = ARRAY_SIZE(omap44xx_ipu_masters),
2589 * external images sensor pixel data processor
2592 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2594 .sysc_offs = 0x0010,
2595 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2596 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2597 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2598 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2599 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2600 .sysc_fields = &omap_hwmod_sysc_type2,
2603 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2605 .sysc = &omap44xx_iss_sysc,
2609 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2610 { .irq = 24 + OMAP44XX_IRQ_GIC_START },
2614 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2615 { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2616 { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2617 { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2618 { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2622 /* iss master ports */
2623 static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2624 &omap44xx_iss__l3_main_2,
2627 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2629 .pa_start = 0x52000000,
2630 .pa_end = 0x520000ff,
2631 .flags = ADDR_TYPE_RT
2636 /* l3_main_2 -> iss */
2637 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2638 .master = &omap44xx_l3_main_2_hwmod,
2639 .slave = &omap44xx_iss_hwmod,
2641 .addr = omap44xx_iss_addrs,
2642 .user = OCP_USER_MPU | OCP_USER_SDMA,
2645 /* iss slave ports */
2646 static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2647 &omap44xx_l3_main_2__iss,
2650 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2651 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2654 static struct omap_hwmod omap44xx_iss_hwmod = {
2656 .class = &omap44xx_iss_hwmod_class,
2657 .clkdm_name = "iss_clkdm",
2658 .mpu_irqs = omap44xx_iss_irqs,
2659 .sdma_reqs = omap44xx_iss_sdma_reqs,
2660 .main_clk = "iss_fck",
2663 .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
2664 .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
2665 .modulemode = MODULEMODE_SWCTRL,
2668 .opt_clks = iss_opt_clks,
2669 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
2670 .slaves = omap44xx_iss_slaves,
2671 .slaves_cnt = ARRAY_SIZE(omap44xx_iss_slaves),
2672 .masters = omap44xx_iss_masters,
2673 .masters_cnt = ARRAY_SIZE(omap44xx_iss_masters),
2678 * multi-standard video encoder/decoder hardware accelerator
2681 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
2686 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2687 { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2688 { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2689 { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
2693 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2694 { .name = "logic", .rst_shift = 2 },
2697 static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2698 { .name = "seq0", .rst_shift = 0 },
2701 static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2702 { .name = "seq1", .rst_shift = 1 },
2705 /* iva master ports */
2706 static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2707 &omap44xx_iva__l3_main_2,
2708 &omap44xx_iva__l3_instr,
2711 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2713 .pa_start = 0x5a000000,
2714 .pa_end = 0x5a07ffff,
2715 .flags = ADDR_TYPE_RT
2720 /* l3_main_2 -> iva */
2721 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2722 .master = &omap44xx_l3_main_2_hwmod,
2723 .slave = &omap44xx_iva_hwmod,
2725 .addr = omap44xx_iva_addrs,
2726 .user = OCP_USER_MPU,
2729 /* iva slave ports */
2730 static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2732 &omap44xx_l3_main_2__iva,
2735 /* Pseudo hwmod for reset control purpose only */
2736 static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2738 .class = &omap44xx_iva_hwmod_class,
2739 .clkdm_name = "ivahd_clkdm",
2740 .flags = HWMOD_INIT_NO_RESET,
2741 .rst_lines = omap44xx_iva_seq0_resets,
2742 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2745 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2750 /* Pseudo hwmod for reset control purpose only */
2751 static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2753 .class = &omap44xx_iva_hwmod_class,
2754 .clkdm_name = "ivahd_clkdm",
2755 .flags = HWMOD_INIT_NO_RESET,
2756 .rst_lines = omap44xx_iva_seq1_resets,
2757 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2760 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2765 static struct omap_hwmod omap44xx_iva_hwmod = {
2767 .class = &omap44xx_iva_hwmod_class,
2768 .clkdm_name = "ivahd_clkdm",
2769 .mpu_irqs = omap44xx_iva_irqs,
2770 .rst_lines = omap44xx_iva_resets,
2771 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
2772 .main_clk = "iva_fck",
2775 .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
2776 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2777 .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
2778 .modulemode = MODULEMODE_HWCTRL,
2781 .slaves = omap44xx_iva_slaves,
2782 .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves),
2783 .masters = omap44xx_iva_masters,
2784 .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters),
2789 * keyboard controller
2792 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2794 .sysc_offs = 0x0010,
2795 .syss_offs = 0x0014,
2796 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2797 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2798 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2799 SYSS_HAS_RESET_STATUS),
2800 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2801 .sysc_fields = &omap_hwmod_sysc_type1,
2804 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2806 .sysc = &omap44xx_kbd_sysc,
2810 static struct omap_hwmod omap44xx_kbd_hwmod;
2811 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2812 { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2816 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2818 .pa_start = 0x4a31c000,
2819 .pa_end = 0x4a31c07f,
2820 .flags = ADDR_TYPE_RT
2825 /* l4_wkup -> kbd */
2826 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2827 .master = &omap44xx_l4_wkup_hwmod,
2828 .slave = &omap44xx_kbd_hwmod,
2829 .clk = "l4_wkup_clk_mux_ck",
2830 .addr = omap44xx_kbd_addrs,
2831 .user = OCP_USER_MPU | OCP_USER_SDMA,
2834 /* kbd slave ports */
2835 static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2836 &omap44xx_l4_wkup__kbd,
2839 static struct omap_hwmod omap44xx_kbd_hwmod = {
2841 .class = &omap44xx_kbd_hwmod_class,
2842 .clkdm_name = "l4_wkup_clkdm",
2843 .mpu_irqs = omap44xx_kbd_irqs,
2844 .main_clk = "kbd_fck",
2847 .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
2848 .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
2849 .modulemode = MODULEMODE_SWCTRL,
2852 .slaves = omap44xx_kbd_slaves,
2853 .slaves_cnt = ARRAY_SIZE(omap44xx_kbd_slaves),
2858 * mailbox module allowing communication between the on-chip processors using a
2859 * queued mailbox-interrupt mechanism.
2862 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2864 .sysc_offs = 0x0010,
2865 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2866 SYSC_HAS_SOFTRESET),
2867 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2868 .sysc_fields = &omap_hwmod_sysc_type2,
2871 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2873 .sysc = &omap44xx_mailbox_sysc,
2877 static struct omap_hwmod omap44xx_mailbox_hwmod;
2878 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2879 { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2883 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2885 .pa_start = 0x4a0f4000,
2886 .pa_end = 0x4a0f41ff,
2887 .flags = ADDR_TYPE_RT
2892 /* l4_cfg -> mailbox */
2893 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2894 .master = &omap44xx_l4_cfg_hwmod,
2895 .slave = &omap44xx_mailbox_hwmod,
2897 .addr = omap44xx_mailbox_addrs,
2898 .user = OCP_USER_MPU | OCP_USER_SDMA,
2901 /* mailbox slave ports */
2902 static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2903 &omap44xx_l4_cfg__mailbox,
2906 static struct omap_hwmod omap44xx_mailbox_hwmod = {
2908 .class = &omap44xx_mailbox_hwmod_class,
2909 .clkdm_name = "l4_cfg_clkdm",
2910 .mpu_irqs = omap44xx_mailbox_irqs,
2913 .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
2914 .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
2917 .slaves = omap44xx_mailbox_slaves,
2918 .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves),
2923 * multi channel buffered serial port controller
2926 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2927 .sysc_offs = 0x008c,
2928 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2929 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2930 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2931 .sysc_fields = &omap_hwmod_sysc_type1,
2934 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2936 .sysc = &omap44xx_mcbsp_sysc,
2937 .rev = MCBSP_CONFIG_TYPE4,
2941 static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2942 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2943 { .irq = 17 + OMAP44XX_IRQ_GIC_START },
2947 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2948 { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2949 { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
2953 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2956 .pa_start = 0x40122000,
2957 .pa_end = 0x401220ff,
2958 .flags = ADDR_TYPE_RT
2963 /* l4_abe -> mcbsp1 */
2964 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2965 .master = &omap44xx_l4_abe_hwmod,
2966 .slave = &omap44xx_mcbsp1_hwmod,
2967 .clk = "ocp_abe_iclk",
2968 .addr = omap44xx_mcbsp1_addrs,
2969 .user = OCP_USER_MPU,
2972 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2975 .pa_start = 0x49022000,
2976 .pa_end = 0x490220ff,
2977 .flags = ADDR_TYPE_RT
2982 /* l4_abe -> mcbsp1 (dma) */
2983 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2984 .master = &omap44xx_l4_abe_hwmod,
2985 .slave = &omap44xx_mcbsp1_hwmod,
2986 .clk = "ocp_abe_iclk",
2987 .addr = omap44xx_mcbsp1_dma_addrs,
2988 .user = OCP_USER_SDMA,
2991 /* mcbsp1 slave ports */
2992 static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
2993 &omap44xx_l4_abe__mcbsp1,
2994 &omap44xx_l4_abe__mcbsp1_dma,
2997 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
2999 .class = &omap44xx_mcbsp_hwmod_class,
3000 .clkdm_name = "abe_clkdm",
3001 .mpu_irqs = omap44xx_mcbsp1_irqs,
3002 .sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
3003 .main_clk = "mcbsp1_fck",
3006 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
3007 .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
3008 .modulemode = MODULEMODE_SWCTRL,
3011 .slaves = omap44xx_mcbsp1_slaves,
3012 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
3016 static struct omap_hwmod omap44xx_mcbsp2_hwmod;
3017 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
3018 { .irq = 22 + OMAP44XX_IRQ_GIC_START },
3022 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
3023 { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
3024 { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
3028 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
3031 .pa_start = 0x40124000,
3032 .pa_end = 0x401240ff,
3033 .flags = ADDR_TYPE_RT
3038 /* l4_abe -> mcbsp2 */
3039 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
3040 .master = &omap44xx_l4_abe_hwmod,
3041 .slave = &omap44xx_mcbsp2_hwmod,
3042 .clk = "ocp_abe_iclk",
3043 .addr = omap44xx_mcbsp2_addrs,
3044 .user = OCP_USER_MPU,
3047 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
3050 .pa_start = 0x49024000,
3051 .pa_end = 0x490240ff,
3052 .flags = ADDR_TYPE_RT
3057 /* l4_abe -> mcbsp2 (dma) */
3058 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
3059 .master = &omap44xx_l4_abe_hwmod,
3060 .slave = &omap44xx_mcbsp2_hwmod,
3061 .clk = "ocp_abe_iclk",
3062 .addr = omap44xx_mcbsp2_dma_addrs,
3063 .user = OCP_USER_SDMA,
3066 /* mcbsp2 slave ports */
3067 static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
3068 &omap44xx_l4_abe__mcbsp2,
3069 &omap44xx_l4_abe__mcbsp2_dma,
3072 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
3074 .class = &omap44xx_mcbsp_hwmod_class,
3075 .clkdm_name = "abe_clkdm",
3076 .mpu_irqs = omap44xx_mcbsp2_irqs,
3077 .sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
3078 .main_clk = "mcbsp2_fck",
3081 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
3082 .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
3083 .modulemode = MODULEMODE_SWCTRL,
3086 .slaves = omap44xx_mcbsp2_slaves,
3087 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
3091 static struct omap_hwmod omap44xx_mcbsp3_hwmod;
3092 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
3093 { .irq = 23 + OMAP44XX_IRQ_GIC_START },
3097 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
3098 { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
3099 { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
3103 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
3106 .pa_start = 0x40126000,
3107 .pa_end = 0x401260ff,
3108 .flags = ADDR_TYPE_RT
3113 /* l4_abe -> mcbsp3 */
3114 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
3115 .master = &omap44xx_l4_abe_hwmod,
3116 .slave = &omap44xx_mcbsp3_hwmod,
3117 .clk = "ocp_abe_iclk",
3118 .addr = omap44xx_mcbsp3_addrs,
3119 .user = OCP_USER_MPU,
3122 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
3125 .pa_start = 0x49026000,
3126 .pa_end = 0x490260ff,
3127 .flags = ADDR_TYPE_RT
3132 /* l4_abe -> mcbsp3 (dma) */
3133 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
3134 .master = &omap44xx_l4_abe_hwmod,
3135 .slave = &omap44xx_mcbsp3_hwmod,
3136 .clk = "ocp_abe_iclk",
3137 .addr = omap44xx_mcbsp3_dma_addrs,
3138 .user = OCP_USER_SDMA,
3141 /* mcbsp3 slave ports */
3142 static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
3143 &omap44xx_l4_abe__mcbsp3,
3144 &omap44xx_l4_abe__mcbsp3_dma,
3147 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
3149 .class = &omap44xx_mcbsp_hwmod_class,
3150 .clkdm_name = "abe_clkdm",
3151 .mpu_irqs = omap44xx_mcbsp3_irqs,
3152 .sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
3153 .main_clk = "mcbsp3_fck",
3156 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
3157 .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
3158 .modulemode = MODULEMODE_SWCTRL,
3161 .slaves = omap44xx_mcbsp3_slaves,
3162 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
3166 static struct omap_hwmod omap44xx_mcbsp4_hwmod;
3167 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
3168 { .irq = 16 + OMAP44XX_IRQ_GIC_START },
3172 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
3173 { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
3174 { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
3178 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
3180 .pa_start = 0x48096000,
3181 .pa_end = 0x480960ff,
3182 .flags = ADDR_TYPE_RT
3187 /* l4_per -> mcbsp4 */
3188 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3189 .master = &omap44xx_l4_per_hwmod,
3190 .slave = &omap44xx_mcbsp4_hwmod,
3192 .addr = omap44xx_mcbsp4_addrs,
3193 .user = OCP_USER_MPU | OCP_USER_SDMA,
3196 /* mcbsp4 slave ports */
3197 static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
3198 &omap44xx_l4_per__mcbsp4,
3201 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
3203 .class = &omap44xx_mcbsp_hwmod_class,
3204 .clkdm_name = "l4_per_clkdm",
3205 .mpu_irqs = omap44xx_mcbsp4_irqs,
3206 .sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
3207 .main_clk = "mcbsp4_fck",
3210 .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
3211 .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
3212 .modulemode = MODULEMODE_SWCTRL,
3215 .slaves = omap44xx_mcbsp4_slaves,
3216 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
3221 * multi channel pdm controller (proprietary interface with phoenix power
3225 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
3227 .sysc_offs = 0x0010,
3228 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3229 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3230 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3232 .sysc_fields = &omap_hwmod_sysc_type2,
3235 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3237 .sysc = &omap44xx_mcpdm_sysc,
3241 static struct omap_hwmod omap44xx_mcpdm_hwmod;
3242 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3243 { .irq = 112 + OMAP44XX_IRQ_GIC_START },
3247 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3248 { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3249 { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
3253 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3255 .pa_start = 0x40132000,
3256 .pa_end = 0x4013207f,
3257 .flags = ADDR_TYPE_RT
3262 /* l4_abe -> mcpdm */
3263 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3264 .master = &omap44xx_l4_abe_hwmod,
3265 .slave = &omap44xx_mcpdm_hwmod,
3266 .clk = "ocp_abe_iclk",
3267 .addr = omap44xx_mcpdm_addrs,
3268 .user = OCP_USER_MPU,
3271 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3273 .pa_start = 0x49032000,
3274 .pa_end = 0x4903207f,
3275 .flags = ADDR_TYPE_RT
3280 /* l4_abe -> mcpdm (dma) */
3281 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3282 .master = &omap44xx_l4_abe_hwmod,
3283 .slave = &omap44xx_mcpdm_hwmod,
3284 .clk = "ocp_abe_iclk",
3285 .addr = omap44xx_mcpdm_dma_addrs,
3286 .user = OCP_USER_SDMA,
3289 /* mcpdm slave ports */
3290 static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3291 &omap44xx_l4_abe__mcpdm,
3292 &omap44xx_l4_abe__mcpdm_dma,
3295 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3297 .class = &omap44xx_mcpdm_hwmod_class,
3298 .clkdm_name = "abe_clkdm",
3299 .mpu_irqs = omap44xx_mcpdm_irqs,
3300 .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
3301 .main_clk = "mcpdm_fck",
3304 .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
3305 .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
3306 .modulemode = MODULEMODE_SWCTRL,
3309 .slaves = omap44xx_mcpdm_slaves,
3310 .slaves_cnt = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3315 * multichannel serial port interface (mcspi) / master/slave synchronous serial
3319 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
3321 .sysc_offs = 0x0010,
3322 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3323 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3324 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3326 .sysc_fields = &omap_hwmod_sysc_type2,
3329 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3331 .sysc = &omap44xx_mcspi_sysc,
3332 .rev = OMAP4_MCSPI_REV,
3336 static struct omap_hwmod omap44xx_mcspi1_hwmod;
3337 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3338 { .irq = 65 + OMAP44XX_IRQ_GIC_START },
3342 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3343 { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
3344 { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
3345 { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
3346 { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
3347 { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
3348 { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
3349 { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
3350 { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
3354 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3356 .pa_start = 0x48098000,
3357 .pa_end = 0x480981ff,
3358 .flags = ADDR_TYPE_RT
3363 /* l4_per -> mcspi1 */
3364 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3365 .master = &omap44xx_l4_per_hwmod,
3366 .slave = &omap44xx_mcspi1_hwmod,
3368 .addr = omap44xx_mcspi1_addrs,
3369 .user = OCP_USER_MPU | OCP_USER_SDMA,
3372 /* mcspi1 slave ports */
3373 static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3374 &omap44xx_l4_per__mcspi1,
3377 /* mcspi1 dev_attr */
3378 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
3379 .num_chipselect = 4,
3382 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3384 .class = &omap44xx_mcspi_hwmod_class,
3385 .clkdm_name = "l4_per_clkdm",
3386 .mpu_irqs = omap44xx_mcspi1_irqs,
3387 .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
3388 .main_clk = "mcspi1_fck",
3391 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
3392 .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
3393 .modulemode = MODULEMODE_SWCTRL,
3396 .dev_attr = &mcspi1_dev_attr,
3397 .slaves = omap44xx_mcspi1_slaves,
3398 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3402 static struct omap_hwmod omap44xx_mcspi2_hwmod;
3403 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3404 { .irq = 66 + OMAP44XX_IRQ_GIC_START },
3408 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3409 { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
3410 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
3411 { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
3412 { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
3416 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3418 .pa_start = 0x4809a000,
3419 .pa_end = 0x4809a1ff,
3420 .flags = ADDR_TYPE_RT
3425 /* l4_per -> mcspi2 */
3426 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3427 .master = &omap44xx_l4_per_hwmod,
3428 .slave = &omap44xx_mcspi2_hwmod,
3430 .addr = omap44xx_mcspi2_addrs,
3431 .user = OCP_USER_MPU | OCP_USER_SDMA,
3434 /* mcspi2 slave ports */
3435 static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3436 &omap44xx_l4_per__mcspi2,
3439 /* mcspi2 dev_attr */
3440 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
3441 .num_chipselect = 2,
3444 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3446 .class = &omap44xx_mcspi_hwmod_class,
3447 .clkdm_name = "l4_per_clkdm",
3448 .mpu_irqs = omap44xx_mcspi2_irqs,
3449 .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
3450 .main_clk = "mcspi2_fck",
3453 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
3454 .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
3455 .modulemode = MODULEMODE_SWCTRL,
3458 .dev_attr = &mcspi2_dev_attr,
3459 .slaves = omap44xx_mcspi2_slaves,
3460 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3464 static struct omap_hwmod omap44xx_mcspi3_hwmod;
3465 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3466 { .irq = 91 + OMAP44XX_IRQ_GIC_START },
3470 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3471 { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
3472 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
3473 { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
3474 { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
3478 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3480 .pa_start = 0x480b8000,
3481 .pa_end = 0x480b81ff,
3482 .flags = ADDR_TYPE_RT
3487 /* l4_per -> mcspi3 */
3488 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3489 .master = &omap44xx_l4_per_hwmod,
3490 .slave = &omap44xx_mcspi3_hwmod,
3492 .addr = omap44xx_mcspi3_addrs,
3493 .user = OCP_USER_MPU | OCP_USER_SDMA,
3496 /* mcspi3 slave ports */
3497 static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
3498 &omap44xx_l4_per__mcspi3,
3501 /* mcspi3 dev_attr */
3502 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
3503 .num_chipselect = 2,
3506 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3508 .class = &omap44xx_mcspi_hwmod_class,
3509 .clkdm_name = "l4_per_clkdm",
3510 .mpu_irqs = omap44xx_mcspi3_irqs,
3511 .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
3512 .main_clk = "mcspi3_fck",
3515 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
3516 .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
3517 .modulemode = MODULEMODE_SWCTRL,
3520 .dev_attr = &mcspi3_dev_attr,
3521 .slaves = omap44xx_mcspi3_slaves,
3522 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves),
3526 static struct omap_hwmod omap44xx_mcspi4_hwmod;
3527 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3528 { .irq = 48 + OMAP44XX_IRQ_GIC_START },
3532 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3533 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
3534 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
3538 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3540 .pa_start = 0x480ba000,
3541 .pa_end = 0x480ba1ff,
3542 .flags = ADDR_TYPE_RT
3547 /* l4_per -> mcspi4 */
3548 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3549 .master = &omap44xx_l4_per_hwmod,
3550 .slave = &omap44xx_mcspi4_hwmod,
3552 .addr = omap44xx_mcspi4_addrs,
3553 .user = OCP_USER_MPU | OCP_USER_SDMA,
3556 /* mcspi4 slave ports */
3557 static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
3558 &omap44xx_l4_per__mcspi4,
3561 /* mcspi4 dev_attr */
3562 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
3563 .num_chipselect = 1,
3566 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3568 .class = &omap44xx_mcspi_hwmod_class,
3569 .clkdm_name = "l4_per_clkdm",
3570 .mpu_irqs = omap44xx_mcspi4_irqs,
3571 .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
3572 .main_clk = "mcspi4_fck",
3575 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
3576 .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
3577 .modulemode = MODULEMODE_SWCTRL,
3580 .dev_attr = &mcspi4_dev_attr,
3581 .slaves = omap44xx_mcspi4_slaves,
3582 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves),
3587 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
3590 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3592 .sysc_offs = 0x0010,
3593 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
3594 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
3595 SYSC_HAS_SOFTRESET),
3596 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3597 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3598 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3599 .sysc_fields = &omap_hwmod_sysc_type2,
3602 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3604 .sysc = &omap44xx_mmc_sysc,
3608 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3609 { .irq = 83 + OMAP44XX_IRQ_GIC_START },
3613 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3614 { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3615 { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
3619 /* mmc1 master ports */
3620 static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
3621 &omap44xx_mmc1__l3_main_1,
3624 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3626 .pa_start = 0x4809c000,
3627 .pa_end = 0x4809c3ff,
3628 .flags = ADDR_TYPE_RT
3633 /* l4_per -> mmc1 */
3634 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3635 .master = &omap44xx_l4_per_hwmod,
3636 .slave = &omap44xx_mmc1_hwmod,
3638 .addr = omap44xx_mmc1_addrs,
3639 .user = OCP_USER_MPU | OCP_USER_SDMA,
3642 /* mmc1 slave ports */
3643 static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3644 &omap44xx_l4_per__mmc1,
3648 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3649 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3652 static struct omap_hwmod omap44xx_mmc1_hwmod = {
3654 .class = &omap44xx_mmc_hwmod_class,
3655 .clkdm_name = "l3_init_clkdm",
3656 .mpu_irqs = omap44xx_mmc1_irqs,
3657 .sdma_reqs = omap44xx_mmc1_sdma_reqs,
3658 .main_clk = "mmc1_fck",
3661 .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
3662 .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
3663 .modulemode = MODULEMODE_SWCTRL,
3666 .dev_attr = &mmc1_dev_attr,
3667 .slaves = omap44xx_mmc1_slaves,
3668 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves),
3669 .masters = omap44xx_mmc1_masters,
3670 .masters_cnt = ARRAY_SIZE(omap44xx_mmc1_masters),
3674 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3675 { .irq = 86 + OMAP44XX_IRQ_GIC_START },
3679 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3680 { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3681 { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
3685 /* mmc2 master ports */
3686 static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
3687 &omap44xx_mmc2__l3_main_1,
3690 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3692 .pa_start = 0x480b4000,
3693 .pa_end = 0x480b43ff,
3694 .flags = ADDR_TYPE_RT
3699 /* l4_per -> mmc2 */
3700 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3701 .master = &omap44xx_l4_per_hwmod,
3702 .slave = &omap44xx_mmc2_hwmod,
3704 .addr = omap44xx_mmc2_addrs,
3705 .user = OCP_USER_MPU | OCP_USER_SDMA,
3708 /* mmc2 slave ports */
3709 static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3710 &omap44xx_l4_per__mmc2,
3713 static struct omap_hwmod omap44xx_mmc2_hwmod = {
3715 .class = &omap44xx_mmc_hwmod_class,
3716 .clkdm_name = "l3_init_clkdm",
3717 .mpu_irqs = omap44xx_mmc2_irqs,
3718 .sdma_reqs = omap44xx_mmc2_sdma_reqs,
3719 .main_clk = "mmc2_fck",
3722 .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
3723 .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
3724 .modulemode = MODULEMODE_SWCTRL,
3727 .slaves = omap44xx_mmc2_slaves,
3728 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc2_slaves),
3729 .masters = omap44xx_mmc2_masters,
3730 .masters_cnt = ARRAY_SIZE(omap44xx_mmc2_masters),
3734 static struct omap_hwmod omap44xx_mmc3_hwmod;
3735 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3736 { .irq = 94 + OMAP44XX_IRQ_GIC_START },
3740 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3741 { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3742 { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
3746 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3748 .pa_start = 0x480ad000,
3749 .pa_end = 0x480ad3ff,
3750 .flags = ADDR_TYPE_RT
3755 /* l4_per -> mmc3 */
3756 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3757 .master = &omap44xx_l4_per_hwmod,
3758 .slave = &omap44xx_mmc3_hwmod,
3760 .addr = omap44xx_mmc3_addrs,
3761 .user = OCP_USER_MPU | OCP_USER_SDMA,
3764 /* mmc3 slave ports */
3765 static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3766 &omap44xx_l4_per__mmc3,
3769 static struct omap_hwmod omap44xx_mmc3_hwmod = {
3771 .class = &omap44xx_mmc_hwmod_class,
3772 .clkdm_name = "l4_per_clkdm",
3773 .mpu_irqs = omap44xx_mmc3_irqs,
3774 .sdma_reqs = omap44xx_mmc3_sdma_reqs,
3775 .main_clk = "mmc3_fck",
3778 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
3779 .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
3780 .modulemode = MODULEMODE_SWCTRL,
3783 .slaves = omap44xx_mmc3_slaves,
3784 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc3_slaves),
3788 static struct omap_hwmod omap44xx_mmc4_hwmod;
3789 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3790 { .irq = 96 + OMAP44XX_IRQ_GIC_START },
3794 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3795 { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3796 { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
3800 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3802 .pa_start = 0x480d1000,
3803 .pa_end = 0x480d13ff,
3804 .flags = ADDR_TYPE_RT
3809 /* l4_per -> mmc4 */
3810 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3811 .master = &omap44xx_l4_per_hwmod,
3812 .slave = &omap44xx_mmc4_hwmod,
3814 .addr = omap44xx_mmc4_addrs,
3815 .user = OCP_USER_MPU | OCP_USER_SDMA,
3818 /* mmc4 slave ports */
3819 static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3820 &omap44xx_l4_per__mmc4,
3823 static struct omap_hwmod omap44xx_mmc4_hwmod = {
3825 .class = &omap44xx_mmc_hwmod_class,
3826 .clkdm_name = "l4_per_clkdm",
3827 .mpu_irqs = omap44xx_mmc4_irqs,
3829 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
3830 .main_clk = "mmc4_fck",
3833 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
3834 .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
3835 .modulemode = MODULEMODE_SWCTRL,
3838 .slaves = omap44xx_mmc4_slaves,
3839 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc4_slaves),
3843 static struct omap_hwmod omap44xx_mmc5_hwmod;
3844 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3845 { .irq = 59 + OMAP44XX_IRQ_GIC_START },
3849 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3850 { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3851 { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
3855 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3857 .pa_start = 0x480d5000,
3858 .pa_end = 0x480d53ff,
3859 .flags = ADDR_TYPE_RT
3864 /* l4_per -> mmc5 */
3865 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3866 .master = &omap44xx_l4_per_hwmod,
3867 .slave = &omap44xx_mmc5_hwmod,
3869 .addr = omap44xx_mmc5_addrs,
3870 .user = OCP_USER_MPU | OCP_USER_SDMA,
3873 /* mmc5 slave ports */
3874 static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3875 &omap44xx_l4_per__mmc5,
3878 static struct omap_hwmod omap44xx_mmc5_hwmod = {
3880 .class = &omap44xx_mmc_hwmod_class,
3881 .clkdm_name = "l4_per_clkdm",
3882 .mpu_irqs = omap44xx_mmc5_irqs,
3883 .sdma_reqs = omap44xx_mmc5_sdma_reqs,
3884 .main_clk = "mmc5_fck",
3887 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
3888 .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
3889 .modulemode = MODULEMODE_SWCTRL,
3892 .slaves = omap44xx_mmc5_slaves,
3893 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc5_slaves),
3901 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
3906 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3907 { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
3908 { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
3909 { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
3913 /* mpu master ports */
3914 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
3915 &omap44xx_mpu__l3_main_1,
3916 &omap44xx_mpu__l4_abe,
3920 static struct omap_hwmod omap44xx_mpu_hwmod = {
3922 .class = &omap44xx_mpu_hwmod_class,
3923 .clkdm_name = "mpuss_clkdm",
3924 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3925 .mpu_irqs = omap44xx_mpu_irqs,
3926 .main_clk = "dpll_mpu_m2_ck",
3929 .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
3930 .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
3933 .masters = omap44xx_mpu_masters,
3934 .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters),
3938 * 'smartreflex' class
3939 * smartreflex module (monitor silicon performance and outputs a measure of
3940 * performance error)
3943 /* The IP is not compliant to type1 / type2 scheme */
3944 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
3949 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
3950 .sysc_offs = 0x0038,
3951 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
3952 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3954 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
3957 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
3958 .name = "smartreflex",
3959 .sysc = &omap44xx_smartreflex_sysc,
3963 /* smartreflex_core */
3964 static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
3965 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
3966 { .irq = 19 + OMAP44XX_IRQ_GIC_START },
3970 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
3972 .pa_start = 0x4a0dd000,
3973 .pa_end = 0x4a0dd03f,
3974 .flags = ADDR_TYPE_RT
3979 /* l4_cfg -> smartreflex_core */
3980 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
3981 .master = &omap44xx_l4_cfg_hwmod,
3982 .slave = &omap44xx_smartreflex_core_hwmod,
3984 .addr = omap44xx_smartreflex_core_addrs,
3985 .user = OCP_USER_MPU | OCP_USER_SDMA,
3988 /* smartreflex_core slave ports */
3989 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
3990 &omap44xx_l4_cfg__smartreflex_core,
3993 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
3994 .name = "smartreflex_core",
3995 .class = &omap44xx_smartreflex_hwmod_class,
3996 .clkdm_name = "l4_ao_clkdm",
3997 .mpu_irqs = omap44xx_smartreflex_core_irqs,
3999 .main_clk = "smartreflex_core_fck",
4003 .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
4004 .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
4005 .modulemode = MODULEMODE_SWCTRL,
4008 .slaves = omap44xx_smartreflex_core_slaves,
4009 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
4012 /* smartreflex_iva */
4013 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
4014 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
4015 { .irq = 102 + OMAP44XX_IRQ_GIC_START },
4019 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
4021 .pa_start = 0x4a0db000,
4022 .pa_end = 0x4a0db03f,
4023 .flags = ADDR_TYPE_RT
4028 /* l4_cfg -> smartreflex_iva */
4029 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
4030 .master = &omap44xx_l4_cfg_hwmod,
4031 .slave = &omap44xx_smartreflex_iva_hwmod,
4033 .addr = omap44xx_smartreflex_iva_addrs,
4034 .user = OCP_USER_MPU | OCP_USER_SDMA,
4037 /* smartreflex_iva slave ports */
4038 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
4039 &omap44xx_l4_cfg__smartreflex_iva,
4042 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
4043 .name = "smartreflex_iva",
4044 .class = &omap44xx_smartreflex_hwmod_class,
4045 .clkdm_name = "l4_ao_clkdm",
4046 .mpu_irqs = omap44xx_smartreflex_iva_irqs,
4047 .main_clk = "smartreflex_iva_fck",
4051 .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
4052 .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
4053 .modulemode = MODULEMODE_SWCTRL,
4056 .slaves = omap44xx_smartreflex_iva_slaves,
4057 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
4060 /* smartreflex_mpu */
4061 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
4062 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
4063 { .irq = 18 + OMAP44XX_IRQ_GIC_START },
4067 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
4069 .pa_start = 0x4a0d9000,
4070 .pa_end = 0x4a0d903f,
4071 .flags = ADDR_TYPE_RT
4076 /* l4_cfg -> smartreflex_mpu */
4077 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
4078 .master = &omap44xx_l4_cfg_hwmod,
4079 .slave = &omap44xx_smartreflex_mpu_hwmod,
4081 .addr = omap44xx_smartreflex_mpu_addrs,
4082 .user = OCP_USER_MPU | OCP_USER_SDMA,
4085 /* smartreflex_mpu slave ports */
4086 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
4087 &omap44xx_l4_cfg__smartreflex_mpu,
4090 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
4091 .name = "smartreflex_mpu",
4092 .class = &omap44xx_smartreflex_hwmod_class,
4093 .clkdm_name = "l4_ao_clkdm",
4094 .mpu_irqs = omap44xx_smartreflex_mpu_irqs,
4095 .main_clk = "smartreflex_mpu_fck",
4099 .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
4100 .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
4101 .modulemode = MODULEMODE_SWCTRL,
4104 .slaves = omap44xx_smartreflex_mpu_slaves,
4105 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
4110 * spinlock provides hardware assistance for synchronizing the processes
4111 * running on multiple processors
4114 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
4116 .sysc_offs = 0x0010,
4117 .syss_offs = 0x0014,
4118 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4119 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
4120 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4121 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4123 .sysc_fields = &omap_hwmod_sysc_type1,
4126 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
4128 .sysc = &omap44xx_spinlock_sysc,
4132 static struct omap_hwmod omap44xx_spinlock_hwmod;
4133 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
4135 .pa_start = 0x4a0f6000,
4136 .pa_end = 0x4a0f6fff,
4137 .flags = ADDR_TYPE_RT
4142 /* l4_cfg -> spinlock */
4143 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
4144 .master = &omap44xx_l4_cfg_hwmod,
4145 .slave = &omap44xx_spinlock_hwmod,
4147 .addr = omap44xx_spinlock_addrs,
4148 .user = OCP_USER_MPU | OCP_USER_SDMA,
4151 /* spinlock slave ports */
4152 static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
4153 &omap44xx_l4_cfg__spinlock,
4156 static struct omap_hwmod omap44xx_spinlock_hwmod = {
4158 .class = &omap44xx_spinlock_hwmod_class,
4159 .clkdm_name = "l4_cfg_clkdm",
4162 .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
4163 .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
4166 .slaves = omap44xx_spinlock_slaves,
4167 .slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves),
4172 * general purpose timer module with accurate 1ms tick
4173 * This class contains several variants: ['timer_1ms', 'timer']
4176 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
4178 .sysc_offs = 0x0010,
4179 .syss_offs = 0x0014,
4180 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4181 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
4182 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4183 SYSS_HAS_RESET_STATUS),
4184 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
4185 .sysc_fields = &omap_hwmod_sysc_type1,
4188 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
4190 .sysc = &omap44xx_timer_1ms_sysc,
4193 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
4195 .sysc_offs = 0x0010,
4196 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
4197 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
4198 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4200 .sysc_fields = &omap_hwmod_sysc_type2,
4203 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
4205 .sysc = &omap44xx_timer_sysc,
4208 /* always-on timers dev attribute */
4209 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
4210 .timer_capability = OMAP_TIMER_ALWON,
4213 /* pwm timers dev attribute */
4214 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
4215 .timer_capability = OMAP_TIMER_HAS_PWM,
4219 static struct omap_hwmod omap44xx_timer1_hwmod;
4220 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
4221 { .irq = 37 + OMAP44XX_IRQ_GIC_START },
4225 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
4227 .pa_start = 0x4a318000,
4228 .pa_end = 0x4a31807f,
4229 .flags = ADDR_TYPE_RT
4234 /* l4_wkup -> timer1 */
4235 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4236 .master = &omap44xx_l4_wkup_hwmod,
4237 .slave = &omap44xx_timer1_hwmod,
4238 .clk = "l4_wkup_clk_mux_ck",
4239 .addr = omap44xx_timer1_addrs,
4240 .user = OCP_USER_MPU | OCP_USER_SDMA,
4243 /* timer1 slave ports */
4244 static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
4245 &omap44xx_l4_wkup__timer1,
4248 static struct omap_hwmod omap44xx_timer1_hwmod = {
4250 .class = &omap44xx_timer_1ms_hwmod_class,
4251 .clkdm_name = "l4_wkup_clkdm",
4252 .mpu_irqs = omap44xx_timer1_irqs,
4253 .main_clk = "timer1_fck",
4256 .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
4257 .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
4258 .modulemode = MODULEMODE_SWCTRL,
4261 .dev_attr = &capability_alwon_dev_attr,
4262 .slaves = omap44xx_timer1_slaves,
4263 .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves),
4267 static struct omap_hwmod omap44xx_timer2_hwmod;
4268 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
4269 { .irq = 38 + OMAP44XX_IRQ_GIC_START },
4273 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
4275 .pa_start = 0x48032000,
4276 .pa_end = 0x4803207f,
4277 .flags = ADDR_TYPE_RT
4282 /* l4_per -> timer2 */
4283 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4284 .master = &omap44xx_l4_per_hwmod,
4285 .slave = &omap44xx_timer2_hwmod,
4287 .addr = omap44xx_timer2_addrs,
4288 .user = OCP_USER_MPU | OCP_USER_SDMA,
4291 /* timer2 slave ports */
4292 static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
4293 &omap44xx_l4_per__timer2,
4296 static struct omap_hwmod omap44xx_timer2_hwmod = {
4298 .class = &omap44xx_timer_1ms_hwmod_class,
4299 .clkdm_name = "l4_per_clkdm",
4300 .mpu_irqs = omap44xx_timer2_irqs,
4301 .main_clk = "timer2_fck",
4304 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
4305 .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
4306 .modulemode = MODULEMODE_SWCTRL,
4309 .dev_attr = &capability_alwon_dev_attr,
4310 .slaves = omap44xx_timer2_slaves,
4311 .slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves),
4315 static struct omap_hwmod omap44xx_timer3_hwmod;
4316 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4317 { .irq = 39 + OMAP44XX_IRQ_GIC_START },
4321 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4323 .pa_start = 0x48034000,
4324 .pa_end = 0x4803407f,
4325 .flags = ADDR_TYPE_RT
4330 /* l4_per -> timer3 */
4331 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4332 .master = &omap44xx_l4_per_hwmod,
4333 .slave = &omap44xx_timer3_hwmod,
4335 .addr = omap44xx_timer3_addrs,
4336 .user = OCP_USER_MPU | OCP_USER_SDMA,
4339 /* timer3 slave ports */
4340 static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
4341 &omap44xx_l4_per__timer3,
4344 static struct omap_hwmod omap44xx_timer3_hwmod = {
4346 .class = &omap44xx_timer_hwmod_class,
4347 .clkdm_name = "l4_per_clkdm",
4348 .mpu_irqs = omap44xx_timer3_irqs,
4349 .main_clk = "timer3_fck",
4352 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
4353 .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
4354 .modulemode = MODULEMODE_SWCTRL,
4357 .dev_attr = &capability_alwon_dev_attr,
4358 .slaves = omap44xx_timer3_slaves,
4359 .slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves),
4363 static struct omap_hwmod omap44xx_timer4_hwmod;
4364 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4365 { .irq = 40 + OMAP44XX_IRQ_GIC_START },
4369 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4371 .pa_start = 0x48036000,
4372 .pa_end = 0x4803607f,
4373 .flags = ADDR_TYPE_RT
4378 /* l4_per -> timer4 */
4379 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4380 .master = &omap44xx_l4_per_hwmod,
4381 .slave = &omap44xx_timer4_hwmod,
4383 .addr = omap44xx_timer4_addrs,
4384 .user = OCP_USER_MPU | OCP_USER_SDMA,
4387 /* timer4 slave ports */
4388 static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
4389 &omap44xx_l4_per__timer4,
4392 static struct omap_hwmod omap44xx_timer4_hwmod = {
4394 .class = &omap44xx_timer_hwmod_class,
4395 .clkdm_name = "l4_per_clkdm",
4396 .mpu_irqs = omap44xx_timer4_irqs,
4397 .main_clk = "timer4_fck",
4400 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
4401 .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
4402 .modulemode = MODULEMODE_SWCTRL,
4405 .dev_attr = &capability_alwon_dev_attr,
4406 .slaves = omap44xx_timer4_slaves,
4407 .slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves),
4411 static struct omap_hwmod omap44xx_timer5_hwmod;
4412 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4413 { .irq = 41 + OMAP44XX_IRQ_GIC_START },
4417 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4419 .pa_start = 0x40138000,
4420 .pa_end = 0x4013807f,
4421 .flags = ADDR_TYPE_RT
4426 /* l4_abe -> timer5 */
4427 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4428 .master = &omap44xx_l4_abe_hwmod,
4429 .slave = &omap44xx_timer5_hwmod,
4430 .clk = "ocp_abe_iclk",
4431 .addr = omap44xx_timer5_addrs,
4432 .user = OCP_USER_MPU,
4435 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4437 .pa_start = 0x49038000,
4438 .pa_end = 0x4903807f,
4439 .flags = ADDR_TYPE_RT
4444 /* l4_abe -> timer5 (dma) */
4445 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4446 .master = &omap44xx_l4_abe_hwmod,
4447 .slave = &omap44xx_timer5_hwmod,
4448 .clk = "ocp_abe_iclk",
4449 .addr = omap44xx_timer5_dma_addrs,
4450 .user = OCP_USER_SDMA,
4453 /* timer5 slave ports */
4454 static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
4455 &omap44xx_l4_abe__timer5,
4456 &omap44xx_l4_abe__timer5_dma,
4459 static struct omap_hwmod omap44xx_timer5_hwmod = {
4461 .class = &omap44xx_timer_hwmod_class,
4462 .clkdm_name = "abe_clkdm",
4463 .mpu_irqs = omap44xx_timer5_irqs,
4464 .main_clk = "timer5_fck",
4467 .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
4468 .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
4469 .modulemode = MODULEMODE_SWCTRL,
4472 .dev_attr = &capability_alwon_dev_attr,
4473 .slaves = omap44xx_timer5_slaves,
4474 .slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves),
4478 static struct omap_hwmod omap44xx_timer6_hwmod;
4479 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4480 { .irq = 42 + OMAP44XX_IRQ_GIC_START },
4484 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4486 .pa_start = 0x4013a000,
4487 .pa_end = 0x4013a07f,
4488 .flags = ADDR_TYPE_RT
4493 /* l4_abe -> timer6 */
4494 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4495 .master = &omap44xx_l4_abe_hwmod,
4496 .slave = &omap44xx_timer6_hwmod,
4497 .clk = "ocp_abe_iclk",
4498 .addr = omap44xx_timer6_addrs,
4499 .user = OCP_USER_MPU,
4502 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4504 .pa_start = 0x4903a000,
4505 .pa_end = 0x4903a07f,
4506 .flags = ADDR_TYPE_RT
4511 /* l4_abe -> timer6 (dma) */
4512 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4513 .master = &omap44xx_l4_abe_hwmod,
4514 .slave = &omap44xx_timer6_hwmod,
4515 .clk = "ocp_abe_iclk",
4516 .addr = omap44xx_timer6_dma_addrs,
4517 .user = OCP_USER_SDMA,
4520 /* timer6 slave ports */
4521 static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
4522 &omap44xx_l4_abe__timer6,
4523 &omap44xx_l4_abe__timer6_dma,
4526 static struct omap_hwmod omap44xx_timer6_hwmod = {
4528 .class = &omap44xx_timer_hwmod_class,
4529 .clkdm_name = "abe_clkdm",
4530 .mpu_irqs = omap44xx_timer6_irqs,
4532 .main_clk = "timer6_fck",
4535 .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
4536 .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
4537 .modulemode = MODULEMODE_SWCTRL,
4540 .dev_attr = &capability_alwon_dev_attr,
4541 .slaves = omap44xx_timer6_slaves,
4542 .slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves),
4546 static struct omap_hwmod omap44xx_timer7_hwmod;
4547 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4548 { .irq = 43 + OMAP44XX_IRQ_GIC_START },
4552 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4554 .pa_start = 0x4013c000,
4555 .pa_end = 0x4013c07f,
4556 .flags = ADDR_TYPE_RT
4561 /* l4_abe -> timer7 */
4562 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4563 .master = &omap44xx_l4_abe_hwmod,
4564 .slave = &omap44xx_timer7_hwmod,
4565 .clk = "ocp_abe_iclk",
4566 .addr = omap44xx_timer7_addrs,
4567 .user = OCP_USER_MPU,
4570 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4572 .pa_start = 0x4903c000,
4573 .pa_end = 0x4903c07f,
4574 .flags = ADDR_TYPE_RT
4579 /* l4_abe -> timer7 (dma) */
4580 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4581 .master = &omap44xx_l4_abe_hwmod,
4582 .slave = &omap44xx_timer7_hwmod,
4583 .clk = "ocp_abe_iclk",
4584 .addr = omap44xx_timer7_dma_addrs,
4585 .user = OCP_USER_SDMA,
4588 /* timer7 slave ports */
4589 static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
4590 &omap44xx_l4_abe__timer7,
4591 &omap44xx_l4_abe__timer7_dma,
4594 static struct omap_hwmod omap44xx_timer7_hwmod = {
4596 .class = &omap44xx_timer_hwmod_class,
4597 .clkdm_name = "abe_clkdm",
4598 .mpu_irqs = omap44xx_timer7_irqs,
4599 .main_clk = "timer7_fck",
4602 .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
4603 .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
4604 .modulemode = MODULEMODE_SWCTRL,
4607 .dev_attr = &capability_alwon_dev_attr,
4608 .slaves = omap44xx_timer7_slaves,
4609 .slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves),
4613 static struct omap_hwmod omap44xx_timer8_hwmod;
4614 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4615 { .irq = 44 + OMAP44XX_IRQ_GIC_START },
4619 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4621 .pa_start = 0x4013e000,
4622 .pa_end = 0x4013e07f,
4623 .flags = ADDR_TYPE_RT
4628 /* l4_abe -> timer8 */
4629 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4630 .master = &omap44xx_l4_abe_hwmod,
4631 .slave = &omap44xx_timer8_hwmod,
4632 .clk = "ocp_abe_iclk",
4633 .addr = omap44xx_timer8_addrs,
4634 .user = OCP_USER_MPU,
4637 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4639 .pa_start = 0x4903e000,
4640 .pa_end = 0x4903e07f,
4641 .flags = ADDR_TYPE_RT
4646 /* l4_abe -> timer8 (dma) */
4647 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4648 .master = &omap44xx_l4_abe_hwmod,
4649 .slave = &omap44xx_timer8_hwmod,
4650 .clk = "ocp_abe_iclk",
4651 .addr = omap44xx_timer8_dma_addrs,
4652 .user = OCP_USER_SDMA,
4655 /* timer8 slave ports */
4656 static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
4657 &omap44xx_l4_abe__timer8,
4658 &omap44xx_l4_abe__timer8_dma,
4661 static struct omap_hwmod omap44xx_timer8_hwmod = {
4663 .class = &omap44xx_timer_hwmod_class,
4664 .clkdm_name = "abe_clkdm",
4665 .mpu_irqs = omap44xx_timer8_irqs,
4666 .main_clk = "timer8_fck",
4669 .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
4670 .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
4671 .modulemode = MODULEMODE_SWCTRL,
4674 .dev_attr = &capability_pwm_dev_attr,
4675 .slaves = omap44xx_timer8_slaves,
4676 .slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves),
4680 static struct omap_hwmod omap44xx_timer9_hwmod;
4681 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4682 { .irq = 45 + OMAP44XX_IRQ_GIC_START },
4686 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4688 .pa_start = 0x4803e000,
4689 .pa_end = 0x4803e07f,
4690 .flags = ADDR_TYPE_RT
4695 /* l4_per -> timer9 */
4696 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4697 .master = &omap44xx_l4_per_hwmod,
4698 .slave = &omap44xx_timer9_hwmod,
4700 .addr = omap44xx_timer9_addrs,
4701 .user = OCP_USER_MPU | OCP_USER_SDMA,
4704 /* timer9 slave ports */
4705 static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
4706 &omap44xx_l4_per__timer9,
4709 static struct omap_hwmod omap44xx_timer9_hwmod = {
4711 .class = &omap44xx_timer_hwmod_class,
4712 .clkdm_name = "l4_per_clkdm",
4713 .mpu_irqs = omap44xx_timer9_irqs,
4714 .main_clk = "timer9_fck",
4717 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
4718 .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
4719 .modulemode = MODULEMODE_SWCTRL,
4722 .dev_attr = &capability_pwm_dev_attr,
4723 .slaves = omap44xx_timer9_slaves,
4724 .slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves),
4728 static struct omap_hwmod omap44xx_timer10_hwmod;
4729 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4730 { .irq = 46 + OMAP44XX_IRQ_GIC_START },
4734 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4736 .pa_start = 0x48086000,
4737 .pa_end = 0x4808607f,
4738 .flags = ADDR_TYPE_RT
4743 /* l4_per -> timer10 */
4744 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4745 .master = &omap44xx_l4_per_hwmod,
4746 .slave = &omap44xx_timer10_hwmod,
4748 .addr = omap44xx_timer10_addrs,
4749 .user = OCP_USER_MPU | OCP_USER_SDMA,
4752 /* timer10 slave ports */
4753 static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
4754 &omap44xx_l4_per__timer10,
4757 static struct omap_hwmod omap44xx_timer10_hwmod = {
4759 .class = &omap44xx_timer_1ms_hwmod_class,
4760 .clkdm_name = "l4_per_clkdm",
4761 .mpu_irqs = omap44xx_timer10_irqs,
4762 .main_clk = "timer10_fck",
4765 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
4766 .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
4767 .modulemode = MODULEMODE_SWCTRL,
4770 .dev_attr = &capability_pwm_dev_attr,
4771 .slaves = omap44xx_timer10_slaves,
4772 .slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves),
4776 static struct omap_hwmod omap44xx_timer11_hwmod;
4777 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4778 { .irq = 47 + OMAP44XX_IRQ_GIC_START },
4782 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4784 .pa_start = 0x48088000,
4785 .pa_end = 0x4808807f,
4786 .flags = ADDR_TYPE_RT
4791 /* l4_per -> timer11 */
4792 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4793 .master = &omap44xx_l4_per_hwmod,
4794 .slave = &omap44xx_timer11_hwmod,
4796 .addr = omap44xx_timer11_addrs,
4797 .user = OCP_USER_MPU | OCP_USER_SDMA,
4800 /* timer11 slave ports */
4801 static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
4802 &omap44xx_l4_per__timer11,
4805 static struct omap_hwmod omap44xx_timer11_hwmod = {
4807 .class = &omap44xx_timer_hwmod_class,
4808 .clkdm_name = "l4_per_clkdm",
4809 .mpu_irqs = omap44xx_timer11_irqs,
4810 .main_clk = "timer11_fck",
4813 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
4814 .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
4815 .modulemode = MODULEMODE_SWCTRL,
4818 .dev_attr = &capability_pwm_dev_attr,
4819 .slaves = omap44xx_timer11_slaves,
4820 .slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves),
4825 * universal asynchronous receiver/transmitter (uart)
4828 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
4830 .sysc_offs = 0x0054,
4831 .syss_offs = 0x0058,
4832 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4833 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4834 SYSS_HAS_RESET_STATUS),
4835 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4837 .sysc_fields = &omap_hwmod_sysc_type1,
4840 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
4842 .sysc = &omap44xx_uart_sysc,
4846 static struct omap_hwmod omap44xx_uart1_hwmod;
4847 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4848 { .irq = 72 + OMAP44XX_IRQ_GIC_START },
4852 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4853 { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
4854 { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
4858 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
4860 .pa_start = 0x4806a000,
4861 .pa_end = 0x4806a0ff,
4862 .flags = ADDR_TYPE_RT
4867 /* l4_per -> uart1 */
4868 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4869 .master = &omap44xx_l4_per_hwmod,
4870 .slave = &omap44xx_uart1_hwmod,
4872 .addr = omap44xx_uart1_addrs,
4873 .user = OCP_USER_MPU | OCP_USER_SDMA,
4876 /* uart1 slave ports */
4877 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
4878 &omap44xx_l4_per__uart1,
4881 static struct omap_hwmod omap44xx_uart1_hwmod = {
4883 .class = &omap44xx_uart_hwmod_class,
4884 .clkdm_name = "l4_per_clkdm",
4885 .mpu_irqs = omap44xx_uart1_irqs,
4886 .sdma_reqs = omap44xx_uart1_sdma_reqs,
4887 .main_clk = "uart1_fck",
4890 .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
4891 .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
4892 .modulemode = MODULEMODE_SWCTRL,
4895 .slaves = omap44xx_uart1_slaves,
4896 .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves),
4900 static struct omap_hwmod omap44xx_uart2_hwmod;
4901 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4902 { .irq = 73 + OMAP44XX_IRQ_GIC_START },
4906 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4907 { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
4908 { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
4912 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
4914 .pa_start = 0x4806c000,
4915 .pa_end = 0x4806c0ff,
4916 .flags = ADDR_TYPE_RT
4921 /* l4_per -> uart2 */
4922 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4923 .master = &omap44xx_l4_per_hwmod,
4924 .slave = &omap44xx_uart2_hwmod,
4926 .addr = omap44xx_uart2_addrs,
4927 .user = OCP_USER_MPU | OCP_USER_SDMA,
4930 /* uart2 slave ports */
4931 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
4932 &omap44xx_l4_per__uart2,
4935 static struct omap_hwmod omap44xx_uart2_hwmod = {
4937 .class = &omap44xx_uart_hwmod_class,
4938 .clkdm_name = "l4_per_clkdm",
4939 .mpu_irqs = omap44xx_uart2_irqs,
4940 .sdma_reqs = omap44xx_uart2_sdma_reqs,
4941 .main_clk = "uart2_fck",
4944 .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
4945 .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
4946 .modulemode = MODULEMODE_SWCTRL,
4949 .slaves = omap44xx_uart2_slaves,
4950 .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves),
4954 static struct omap_hwmod omap44xx_uart3_hwmod;
4955 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
4956 { .irq = 74 + OMAP44XX_IRQ_GIC_START },
4960 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
4961 { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
4962 { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
4966 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
4968 .pa_start = 0x48020000,
4969 .pa_end = 0x480200ff,
4970 .flags = ADDR_TYPE_RT
4975 /* l4_per -> uart3 */
4976 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4977 .master = &omap44xx_l4_per_hwmod,
4978 .slave = &omap44xx_uart3_hwmod,
4980 .addr = omap44xx_uart3_addrs,
4981 .user = OCP_USER_MPU | OCP_USER_SDMA,
4984 /* uart3 slave ports */
4985 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
4986 &omap44xx_l4_per__uart3,
4989 static struct omap_hwmod omap44xx_uart3_hwmod = {
4991 .class = &omap44xx_uart_hwmod_class,
4992 .clkdm_name = "l4_per_clkdm",
4993 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
4994 .mpu_irqs = omap44xx_uart3_irqs,
4995 .sdma_reqs = omap44xx_uart3_sdma_reqs,
4996 .main_clk = "uart3_fck",
4999 .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
5000 .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
5001 .modulemode = MODULEMODE_SWCTRL,
5004 .slaves = omap44xx_uart3_slaves,
5005 .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves),
5009 static struct omap_hwmod omap44xx_uart4_hwmod;
5010 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
5011 { .irq = 70 + OMAP44XX_IRQ_GIC_START },
5015 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
5016 { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
5017 { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
5021 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
5023 .pa_start = 0x4806e000,
5024 .pa_end = 0x4806e0ff,
5025 .flags = ADDR_TYPE_RT
5030 /* l4_per -> uart4 */
5031 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
5032 .master = &omap44xx_l4_per_hwmod,
5033 .slave = &omap44xx_uart4_hwmod,
5035 .addr = omap44xx_uart4_addrs,
5036 .user = OCP_USER_MPU | OCP_USER_SDMA,
5039 /* uart4 slave ports */
5040 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
5041 &omap44xx_l4_per__uart4,
5044 static struct omap_hwmod omap44xx_uart4_hwmod = {
5046 .class = &omap44xx_uart_hwmod_class,
5047 .clkdm_name = "l4_per_clkdm",
5048 .mpu_irqs = omap44xx_uart4_irqs,
5049 .sdma_reqs = omap44xx_uart4_sdma_reqs,
5050 .main_clk = "uart4_fck",
5053 .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
5054 .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
5055 .modulemode = MODULEMODE_SWCTRL,
5058 .slaves = omap44xx_uart4_slaves,
5059 .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves),
5063 * 'usb_otg_hs' class
5064 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
5067 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
5069 .sysc_offs = 0x0404,
5070 .syss_offs = 0x0408,
5071 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
5072 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
5073 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
5074 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5075 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
5077 .sysc_fields = &omap_hwmod_sysc_type1,
5080 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
5081 .name = "usb_otg_hs",
5082 .sysc = &omap44xx_usb_otg_hs_sysc,
5086 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
5087 { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
5088 { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
5092 /* usb_otg_hs master ports */
5093 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
5094 &omap44xx_usb_otg_hs__l3_main_2,
5097 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
5099 .pa_start = 0x4a0ab000,
5100 .pa_end = 0x4a0ab003,
5101 .flags = ADDR_TYPE_RT
5106 /* l4_cfg -> usb_otg_hs */
5107 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
5108 .master = &omap44xx_l4_cfg_hwmod,
5109 .slave = &omap44xx_usb_otg_hs_hwmod,
5111 .addr = omap44xx_usb_otg_hs_addrs,
5112 .user = OCP_USER_MPU | OCP_USER_SDMA,
5115 /* usb_otg_hs slave ports */
5116 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
5117 &omap44xx_l4_cfg__usb_otg_hs,
5120 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
5121 { .role = "xclk", .clk = "usb_otg_hs_xclk" },
5124 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
5125 .name = "usb_otg_hs",
5126 .class = &omap44xx_usb_otg_hs_hwmod_class,
5127 .clkdm_name = "l3_init_clkdm",
5128 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
5129 .mpu_irqs = omap44xx_usb_otg_hs_irqs,
5130 .main_clk = "usb_otg_hs_ick",
5133 .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
5134 .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
5135 .modulemode = MODULEMODE_HWCTRL,
5138 .opt_clks = usb_otg_hs_opt_clks,
5139 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
5140 .slaves = omap44xx_usb_otg_hs_slaves,
5141 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
5142 .masters = omap44xx_usb_otg_hs_masters,
5143 .masters_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
5148 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
5149 * overflow condition
5152 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
5154 .sysc_offs = 0x0010,
5155 .syss_offs = 0x0014,
5156 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
5157 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
5158 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5160 .sysc_fields = &omap_hwmod_sysc_type1,
5163 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
5165 .sysc = &omap44xx_wd_timer_sysc,
5166 .pre_shutdown = &omap2_wd_timer_disable,
5170 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
5171 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
5172 { .irq = 80 + OMAP44XX_IRQ_GIC_START },
5176 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
5178 .pa_start = 0x4a314000,
5179 .pa_end = 0x4a31407f,
5180 .flags = ADDR_TYPE_RT
5185 /* l4_wkup -> wd_timer2 */
5186 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
5187 .master = &omap44xx_l4_wkup_hwmod,
5188 .slave = &omap44xx_wd_timer2_hwmod,
5189 .clk = "l4_wkup_clk_mux_ck",
5190 .addr = omap44xx_wd_timer2_addrs,
5191 .user = OCP_USER_MPU | OCP_USER_SDMA,
5194 /* wd_timer2 slave ports */
5195 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
5196 &omap44xx_l4_wkup__wd_timer2,
5199 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
5200 .name = "wd_timer2",
5201 .class = &omap44xx_wd_timer_hwmod_class,
5202 .clkdm_name = "l4_wkup_clkdm",
5203 .mpu_irqs = omap44xx_wd_timer2_irqs,
5204 .main_clk = "wd_timer2_fck",
5207 .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
5208 .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
5209 .modulemode = MODULEMODE_SWCTRL,
5212 .slaves = omap44xx_wd_timer2_slaves,
5213 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
5217 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
5218 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
5219 { .irq = 36 + OMAP44XX_IRQ_GIC_START },
5223 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
5225 .pa_start = 0x40130000,
5226 .pa_end = 0x4013007f,
5227 .flags = ADDR_TYPE_RT
5232 /* l4_abe -> wd_timer3 */
5233 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
5234 .master = &omap44xx_l4_abe_hwmod,
5235 .slave = &omap44xx_wd_timer3_hwmod,
5236 .clk = "ocp_abe_iclk",
5237 .addr = omap44xx_wd_timer3_addrs,
5238 .user = OCP_USER_MPU,
5241 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
5243 .pa_start = 0x49030000,
5244 .pa_end = 0x4903007f,
5245 .flags = ADDR_TYPE_RT
5250 /* l4_abe -> wd_timer3 (dma) */
5251 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5252 .master = &omap44xx_l4_abe_hwmod,
5253 .slave = &omap44xx_wd_timer3_hwmod,
5254 .clk = "ocp_abe_iclk",
5255 .addr = omap44xx_wd_timer3_dma_addrs,
5256 .user = OCP_USER_SDMA,
5259 /* wd_timer3 slave ports */
5260 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
5261 &omap44xx_l4_abe__wd_timer3,
5262 &omap44xx_l4_abe__wd_timer3_dma,
5265 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
5266 .name = "wd_timer3",
5267 .class = &omap44xx_wd_timer_hwmod_class,
5268 .clkdm_name = "abe_clkdm",
5269 .mpu_irqs = omap44xx_wd_timer3_irqs,
5270 .main_clk = "wd_timer3_fck",
5273 .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
5274 .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
5275 .modulemode = MODULEMODE_SWCTRL,
5278 .slaves = omap44xx_wd_timer3_slaves,
5279 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
5283 * 'usb_host_hs' class
5284 * high-speed multi-port usb host controller
5286 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
5287 .master = &omap44xx_usb_host_hs_hwmod,
5288 .slave = &omap44xx_l3_main_2_hwmod,
5290 .user = OCP_USER_MPU | OCP_USER_SDMA,
5293 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
5295 .sysc_offs = 0x0010,
5296 .syss_offs = 0x0014,
5297 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
5298 SYSC_HAS_SOFTRESET),
5299 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5300 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
5301 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
5302 .sysc_fields = &omap_hwmod_sysc_type2,
5305 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
5306 .name = "usb_host_hs",
5307 .sysc = &omap44xx_usb_host_hs_sysc,
5310 static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_masters[] = {
5311 &omap44xx_usb_host_hs__l3_main_2,
5314 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
5317 .pa_start = 0x4a064000,
5318 .pa_end = 0x4a0647ff,
5319 .flags = ADDR_TYPE_RT
5323 .pa_start = 0x4a064800,
5324 .pa_end = 0x4a064bff,
5328 .pa_start = 0x4a064c00,
5329 .pa_end = 0x4a064fff,
5334 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
5335 { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
5336 { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
5340 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
5341 .master = &omap44xx_l4_cfg_hwmod,
5342 .slave = &omap44xx_usb_host_hs_hwmod,
5344 .addr = omap44xx_usb_host_hs_addrs,
5345 .user = OCP_USER_MPU | OCP_USER_SDMA,
5348 static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_slaves[] = {
5349 &omap44xx_l4_cfg__usb_host_hs,
5352 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
5353 .name = "usb_host_hs",
5354 .class = &omap44xx_usb_host_hs_hwmod_class,
5355 .clkdm_name = "l3_init_clkdm",
5356 .main_clk = "usb_host_hs_fck",
5359 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
5360 .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
5361 .modulemode = MODULEMODE_SWCTRL,
5364 .mpu_irqs = omap44xx_usb_host_hs_irqs,
5365 .slaves = omap44xx_usb_host_hs_slaves,
5366 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_host_hs_slaves),
5367 .masters = omap44xx_usb_host_hs_masters,
5368 .masters_cnt = ARRAY_SIZE(omap44xx_usb_host_hs_masters),
5371 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
5375 * In the following configuration :
5376 * - USBHOST module is set to smart-idle mode
5377 * - PRCM asserts idle_req to the USBHOST module ( This typically
5378 * happens when the system is going to a low power mode : all ports
5379 * have been suspended, the master part of the USBHOST module has
5380 * entered the standby state, and SW has cut the functional clocks)
5381 * - an USBHOST interrupt occurs before the module is able to answer
5382 * idle_ack, typically a remote wakeup IRQ.
5383 * Then the USB HOST module will enter a deadlock situation where it
5384 * is no more accessible nor functional.
5387 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
5391 * Errata: USB host EHCI may stall when entering smart-standby mode
5395 * When the USBHOST module is set to smart-standby mode, and when it is
5396 * ready to enter the standby state (i.e. all ports are suspended and
5397 * all attached devices are in suspend mode), then it can wrongly assert
5398 * the Mstandby signal too early while there are still some residual OCP
5399 * transactions ongoing. If this condition occurs, the internal state
5400 * machine may go to an undefined state and the USB link may be stuck
5401 * upon the next resume.
5404 * Don't use smart standby; use only force standby,
5405 * hence HWMOD_SWSUP_MSTANDBY
5409 * During system boot; If the hwmod framework resets the module
5410 * the module will have smart idle settings; which can lead to deadlock
5411 * (above Errata Id:i660); so, dont reset the module during boot;
5412 * Use HWMOD_INIT_NO_RESET.
5415 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
5416 HWMOD_INIT_NO_RESET,
5420 * 'usb_tll_hs' class
5421 * usb_tll_hs module is the adapter on the usb_host_hs ports
5423 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
5425 .sysc_offs = 0x0010,
5426 .syss_offs = 0x0014,
5427 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
5428 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
5430 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
5431 .sysc_fields = &omap_hwmod_sysc_type1,
5434 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
5435 .name = "usb_tll_hs",
5436 .sysc = &omap44xx_usb_tll_hs_sysc,
5439 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
5440 { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
5444 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
5447 .pa_start = 0x4a062000,
5448 .pa_end = 0x4a063fff,
5449 .flags = ADDR_TYPE_RT
5454 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
5455 .master = &omap44xx_l4_cfg_hwmod,
5456 .slave = &omap44xx_usb_tll_hs_hwmod,
5458 .addr = omap44xx_usb_tll_hs_addrs,
5459 .user = OCP_USER_MPU | OCP_USER_SDMA,
5462 static struct omap_hwmod_ocp_if *omap44xx_usb_tll_hs_slaves[] = {
5463 &omap44xx_l4_cfg__usb_tll_hs,
5466 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
5467 .name = "usb_tll_hs",
5468 .class = &omap44xx_usb_tll_hs_hwmod_class,
5469 .clkdm_name = "l3_init_clkdm",
5470 .main_clk = "usb_tll_hs_ick",
5473 .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
5474 .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
5475 .modulemode = MODULEMODE_HWCTRL,
5478 .mpu_irqs = omap44xx_usb_tll_hs_irqs,
5479 .slaves = omap44xx_usb_tll_hs_slaves,
5480 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_tll_hs_slaves),
5483 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
5486 &omap44xx_dmm_hwmod,
5489 &omap44xx_emif_fw_hwmod,
5492 &omap44xx_l3_instr_hwmod,
5493 &omap44xx_l3_main_1_hwmod,
5494 &omap44xx_l3_main_2_hwmod,
5495 &omap44xx_l3_main_3_hwmod,
5498 &omap44xx_l4_abe_hwmod,
5499 &omap44xx_l4_cfg_hwmod,
5500 &omap44xx_l4_per_hwmod,
5501 &omap44xx_l4_wkup_hwmod,
5504 &omap44xx_mpu_private_hwmod,
5507 /* &omap44xx_aess_hwmod, */
5510 &omap44xx_bandgap_hwmod,
5513 /* &omap44xx_counter_32k_hwmod, */
5516 &omap44xx_dma_system_hwmod,
5519 &omap44xx_dmic_hwmod,
5522 &omap44xx_dsp_hwmod,
5523 &omap44xx_dsp_c0_hwmod,
5526 &omap44xx_dss_hwmod,
5527 &omap44xx_dss_dispc_hwmod,
5528 &omap44xx_dss_dsi1_hwmod,
5529 &omap44xx_dss_dsi2_hwmod,
5530 &omap44xx_dss_hdmi_hwmod,
5531 &omap44xx_dss_rfbi_hwmod,
5532 &omap44xx_dss_venc_hwmod,
5535 &omap44xx_gpio1_hwmod,
5536 &omap44xx_gpio2_hwmod,
5537 &omap44xx_gpio3_hwmod,
5538 &omap44xx_gpio4_hwmod,
5539 &omap44xx_gpio5_hwmod,
5540 &omap44xx_gpio6_hwmod,
5543 /* &omap44xx_hsi_hwmod, */
5546 &omap44xx_i2c1_hwmod,
5547 &omap44xx_i2c2_hwmod,
5548 &omap44xx_i2c3_hwmod,
5549 &omap44xx_i2c4_hwmod,
5552 &omap44xx_ipu_hwmod,
5553 &omap44xx_ipu_c0_hwmod,
5554 &omap44xx_ipu_c1_hwmod,
5557 /* &omap44xx_iss_hwmod, */
5560 &omap44xx_iva_hwmod,
5561 &omap44xx_iva_seq0_hwmod,
5562 &omap44xx_iva_seq1_hwmod,
5565 &omap44xx_kbd_hwmod,
5568 &omap44xx_mailbox_hwmod,
5571 &omap44xx_mcbsp1_hwmod,
5572 &omap44xx_mcbsp2_hwmod,
5573 &omap44xx_mcbsp3_hwmod,
5574 &omap44xx_mcbsp4_hwmod,
5577 &omap44xx_mcpdm_hwmod,
5580 &omap44xx_mcspi1_hwmod,
5581 &omap44xx_mcspi2_hwmod,
5582 &omap44xx_mcspi3_hwmod,
5583 &omap44xx_mcspi4_hwmod,
5586 &omap44xx_mmc1_hwmod,
5587 &omap44xx_mmc2_hwmod,
5588 &omap44xx_mmc3_hwmod,
5589 &omap44xx_mmc4_hwmod,
5590 &omap44xx_mmc5_hwmod,
5593 &omap44xx_mpu_hwmod,
5595 /* smartreflex class */
5596 &omap44xx_smartreflex_core_hwmod,
5597 &omap44xx_smartreflex_iva_hwmod,
5598 &omap44xx_smartreflex_mpu_hwmod,
5600 /* spinlock class */
5601 &omap44xx_spinlock_hwmod,
5604 &omap44xx_timer1_hwmod,
5605 &omap44xx_timer2_hwmod,
5606 &omap44xx_timer3_hwmod,
5607 &omap44xx_timer4_hwmod,
5608 &omap44xx_timer5_hwmod,
5609 &omap44xx_timer6_hwmod,
5610 &omap44xx_timer7_hwmod,
5611 &omap44xx_timer8_hwmod,
5612 &omap44xx_timer9_hwmod,
5613 &omap44xx_timer10_hwmod,
5614 &omap44xx_timer11_hwmod,
5617 &omap44xx_uart1_hwmod,
5618 &omap44xx_uart2_hwmod,
5619 &omap44xx_uart3_hwmod,
5620 &omap44xx_uart4_hwmod,
5622 /* usb host class */
5623 &omap44xx_usb_host_hs_hwmod,
5624 &omap44xx_usb_tll_hs_hwmod,
5626 /* usb_otg_hs class */
5627 &omap44xx_usb_otg_hs_hwmod,
5629 /* wd_timer class */
5630 &omap44xx_wd_timer2_hwmod,
5631 &omap44xx_wd_timer3_hwmod,
5635 int __init omap44xx_hwmod_init(void)
5637 return omap_hwmod_register(omap44xx_hwmods);