arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  * Note that this file is currently not in sync with autogeneration scripts.
  16  * The above note to be removed, once it is synced up.
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License version 2 as
  20  * published by the Free Software Foundation.
  21  */
  22
  23 #include <linux/io.h>
  24 #include <linux/platform_data/gpio-omap.h>
  25 #include <linux/platform_data/hsmmc-omap.h>
  26 #include <linux/power/smartreflex.h>
  27 #include <linux/i2c-omap.h>
  28
  29 #include <linux/omap-dma.h>
  30
  31 #include <linux/platform_data/spi-omap2-mcspi.h>
  32 #include <linux/platform_data/asoc-ti-mcbsp.h>
  33 #include <plat/dmtimer.h>
  34
  35 #include "omap_hwmod.h"
  36 #include "omap_hwmod_common_data.h"
  37 #include "cm1_44xx.h"
  38 #include "cm2_44xx.h"
  39 #include "prm44xx.h"
  40 #include "prm-regbits-44xx.h"
  41 #include "i2c.h"
  42 #include "wd_timer.h"
  43
  44 /* Base offset for all OMAP4 interrupts external to MPUSS */
  45 #define OMAP44XX_IRQ_GIC_START  32
  46
  47 /* Base offset for all OMAP4 dma requests */
  48 #define OMAP44XX_DMA_REQ_START  1
  49
  50 /*
  51  * IP blocks
  52  */
  53
  54 /*
  55  * 'dmm' class
  56  * instance(s): dmm
  57  */
  58 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  59         .name   = "dmm",
  60 };
  61
  62 /* dmm */
  63 static struct omap_hwmod omap44xx_dmm_hwmod = {
  64         .name           = "dmm",
  65         .class          = &omap44xx_dmm_hwmod_class,
  66         .clkdm_name     = "l3_emif_clkdm",
  67         .prcm = {
  68                 .omap4 = {
  69                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  70                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  71                 },
  72         },
  73 };
  74
  75 /*
  76  * 'l3' class
  77  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  78  */
  79 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
  80         .name   = "l3",
  81 };
  82
  83 /* l3_instr */
  84 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
  85         .name           = "l3_instr",
  86         .class          = &omap44xx_l3_hwmod_class,
  87         .clkdm_name     = "l3_instr_clkdm",
  88         .prcm = {
  89                 .omap4 = {
  90                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  91                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  92                         .modulemode   = MODULEMODE_HWCTRL,
  93                 },
  94         },
  95 };
  96
  97 /* l3_main_1 */
  98 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
  99         .name           = "l3_main_1",
 100         .class          = &omap44xx_l3_hwmod_class,
 101         .clkdm_name     = "l3_1_clkdm",
 102         .prcm = {
 103                 .omap4 = {
 104                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 105                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 106                 },
 107         },
 108 };
 109
 110 /* l3_main_2 */
 111 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 112         .name           = "l3_main_2",
 113         .class          = &omap44xx_l3_hwmod_class,
 114         .clkdm_name     = "l3_2_clkdm",
 115         .prcm = {
 116                 .omap4 = {
 117                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 118                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 119                 },
 120         },
 121 };
 122
 123 /* l3_main_3 */
 124 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 125         .name           = "l3_main_3",
 126         .class          = &omap44xx_l3_hwmod_class,
 127         .clkdm_name     = "l3_instr_clkdm",
 128         .prcm = {
 129                 .omap4 = {
 130                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 131                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 132                         .modulemode   = MODULEMODE_HWCTRL,
 133                 },
 134         },
 135 };
 136
 137 /*
 138  * 'l4' class
 139  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 140  */
 141 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 142         .name   = "l4",
 143 };
 144
 145 /* l4_abe */
 146 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 147         .name           = "l4_abe",
 148         .class          = &omap44xx_l4_hwmod_class,
 149         .clkdm_name     = "abe_clkdm",
 150         .prcm = {
 151                 .omap4 = {
 152                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 153                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 154                         .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
 155                         .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 156                 },
 157         },
 158 };
 159
 160 /* l4_cfg */
 161 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 162         .name           = "l4_cfg",
 163         .class          = &omap44xx_l4_hwmod_class,
 164         .clkdm_name     = "l4_cfg_clkdm",
 165         .prcm = {
 166                 .omap4 = {
 167                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 168                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 169                 },
 170         },
 171 };
 172
 173 /* l4_per */
 174 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 175         .name           = "l4_per",
 176         .class          = &omap44xx_l4_hwmod_class,
 177         .clkdm_name     = "l4_per_clkdm",
 178         .prcm = {
 179                 .omap4 = {
 180                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 181                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 182                 },
 183         },
 184 };
 185
 186 /* l4_wkup */
 187 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 188         .name           = "l4_wkup",
 189         .class          = &omap44xx_l4_hwmod_class,
 190         .clkdm_name     = "l4_wkup_clkdm",
 191         .prcm = {
 192                 .omap4 = {
 193                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 194                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 195                 },
 196         },
 197 };
 198
 199 /*
 200  * 'mpu_bus' class
 201  * instance(s): mpu_private
 202  */
 203 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 204         .name   = "mpu_bus",
 205 };
 206
 207 /* mpu_private */
 208 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 209         .name           = "mpu_private",
 210         .class          = &omap44xx_mpu_bus_hwmod_class,
 211         .clkdm_name     = "mpuss_clkdm",
 212         .prcm = {
 213                 .omap4 = {
 214                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 215                 },
 216         },
 217 };
 218
 219 /*
 220  * 'ocp_wp_noc' class
 221  * instance(s): ocp_wp_noc
 222  */
 223 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 224         .name   = "ocp_wp_noc",
 225 };
 226
 227 /* ocp_wp_noc */
 228 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 229         .name           = "ocp_wp_noc",
 230         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 231         .clkdm_name     = "l3_instr_clkdm",
 232         .prcm = {
 233                 .omap4 = {
 234                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 235                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 236                         .modulemode   = MODULEMODE_HWCTRL,
 237                 },
 238         },
 239 };
 240
 241 /*
 242  * Modules omap_hwmod structures
 243  *
 244  * The following IPs are excluded for the moment because:
 245  * - They do not need an explicit SW control using omap_hwmod API.
 246  * - They still need to be validated with the driver
 247  *   properly adapted to omap_hwmod / omap_device
 248  *
 249  * usim
 250  */
 251
 252 /*
 253  * 'aess' class
 254  * audio engine sub system
 255  */
 256
 257 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 258         .rev_offs       = 0x0000,
 259         .sysc_offs      = 0x0010,
 260         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 261         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 262                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 263                            MSTANDBY_SMART_WKUP),
 264         .sysc_fields    = &omap_hwmod_sysc_type2,
 265 };
 266
 267 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 268         .name   = "aess",
 269         .sysc   = &omap44xx_aess_sysc,
 270         .enable_preprogram = omap_hwmod_aess_preprogram,
 271 };
 272
 273 /* aess */
 274 static struct omap_hwmod omap44xx_aess_hwmod = {
 275         .name           = "aess",
 276         .class          = &omap44xx_aess_hwmod_class,
 277         .clkdm_name     = "abe_clkdm",
 278         .main_clk       = "aess_fclk",
 279         .prcm = {
 280                 .omap4 = {
 281                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 282                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 283                         .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
 284                         .modulemode   = MODULEMODE_SWCTRL,
 285                 },
 286         },
 287 };
 288
 289 /*
 290  * 'c2c' class
 291  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 292  * soc
 293  */
 294
 295 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 296         .name   = "c2c",
 297 };
 298
 299 /* c2c */
 300 static struct omap_hwmod omap44xx_c2c_hwmod = {
 301         .name           = "c2c",
 302         .class          = &omap44xx_c2c_hwmod_class,
 303         .clkdm_name     = "d2d_clkdm",
 304         .prcm = {
 305                 .omap4 = {
 306                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
 307                         .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
 308                 },
 309         },
 310 };
 311
 312 /*
 313  * 'counter' class
 314  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 315  */
 316
 317 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 318         .rev_offs       = 0x0000,
 319         .sysc_offs      = 0x0004,
 320         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 321         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 322         .sysc_fields    = &omap_hwmod_sysc_type1,
 323 };
 324
 325 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 326         .name   = "counter",
 327         .sysc   = &omap44xx_counter_sysc,
 328 };
 329
 330 /* counter_32k */
 331 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 332         .name           = "counter_32k",
 333         .class          = &omap44xx_counter_hwmod_class,
 334         .clkdm_name     = "l4_wkup_clkdm",
 335         .flags          = HWMOD_SWSUP_SIDLE,
 336         .main_clk       = "sys_32k_ck",
 337         .prcm = {
 338                 .omap4 = {
 339                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 340                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 341                 },
 342         },
 343 };
 344
 345 /*
 346  * 'ctrl_module' class
 347  * attila core control module + core pad control module + wkup pad control
 348  * module + attila wkup control module
 349  */
 350
 351 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 352         .rev_offs       = 0x0000,
 353         .sysc_offs      = 0x0010,
 354         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 355         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 356                            SIDLE_SMART_WKUP),
 357         .sysc_fields    = &omap_hwmod_sysc_type2,
 358 };
 359
 360 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 361         .name   = "ctrl_module",
 362         .sysc   = &omap44xx_ctrl_module_sysc,
 363 };
 364
 365 /* ctrl_module_core */
 366 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 367         .name           = "ctrl_module_core",
 368         .class          = &omap44xx_ctrl_module_hwmod_class,
 369         .clkdm_name     = "l4_cfg_clkdm",
 370         .prcm = {
 371                 .omap4 = {
 372                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 373                 },
 374         },
 375 };
 376
 377 /* ctrl_module_pad_core */
 378 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 379         .name           = "ctrl_module_pad_core",
 380         .class          = &omap44xx_ctrl_module_hwmod_class,
 381         .clkdm_name     = "l4_cfg_clkdm",
 382         .prcm = {
 383                 .omap4 = {
 384                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 385                 },
 386         },
 387 };
 388
 389 /* ctrl_module_wkup */
 390 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 391         .name           = "ctrl_module_wkup",
 392         .class          = &omap44xx_ctrl_module_hwmod_class,
 393         .clkdm_name     = "l4_wkup_clkdm",
 394         .prcm = {
 395                 .omap4 = {
 396                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 397                 },
 398         },
 399 };
 400
 401 /* ctrl_module_pad_wkup */
 402 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 403         .name           = "ctrl_module_pad_wkup",
 404         .class          = &omap44xx_ctrl_module_hwmod_class,
 405         .clkdm_name     = "l4_wkup_clkdm",
 406         .prcm = {
 407                 .omap4 = {
 408                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 409                 },
 410         },
 411 };
 412
 413 /*
 414  * 'debugss' class
 415  * debug and emulation sub system
 416  */
 417
 418 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 419         .name   = "debugss",
 420 };
 421
 422 /* debugss */
 423 static struct omap_hwmod omap44xx_debugss_hwmod = {
 424         .name           = "debugss",
 425         .class          = &omap44xx_debugss_hwmod_class,
 426         .clkdm_name     = "emu_sys_clkdm",
 427         .main_clk       = "trace_clk_div_ck",
 428         .prcm = {
 429                 .omap4 = {
 430                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 431                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 432                 },
 433         },
 434 };
 435
 436 /*
 437  * 'dma' class
 438  * dma controller for data exchange between memory to memory (i.e. internal or
 439  * external memory) and gp peripherals to memory or memory to gp peripherals
 440  */
 441
 442 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 443         .rev_offs       = 0x0000,
 444         .sysc_offs      = 0x002c,
 445         .syss_offs      = 0x0028,
 446         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 447                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 448                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 449                            SYSS_HAS_RESET_STATUS),
 450         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 451                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 452         .sysc_fields    = &omap_hwmod_sysc_type1,
 453 };
 454
 455 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 456         .name   = "dma",
 457         .sysc   = &omap44xx_dma_sysc,
 458 };
 459
 460 /* dma dev_attr */
 461 static struct omap_dma_dev_attr dma_dev_attr = {
 462         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 463                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 464         .lch_count      = 32,
 465 };
 466
 467 /* dma_system */
 468 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 469         .name           = "dma_system",
 470         .class          = &omap44xx_dma_hwmod_class,
 471         .clkdm_name     = "l3_dma_clkdm",
 472         .main_clk       = "l3_div_ck",
 473         .prcm = {
 474                 .omap4 = {
 475                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 476                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 477                 },
 478         },
 479         .dev_attr       = &dma_dev_attr,
 480 };
 481
 482 /*
 483  * 'dmic' class
 484  * digital microphone controller
 485  */
 486
 487 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 488         .rev_offs       = 0x0000,
 489         .sysc_offs      = 0x0010,
 490         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 491                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 492         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 493                            SIDLE_SMART_WKUP),
 494         .sysc_fields    = &omap_hwmod_sysc_type2,
 495 };
 496
 497 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 498         .name   = "dmic",
 499         .sysc   = &omap44xx_dmic_sysc,
 500 };
 501
 502 /* dmic */
 503 static struct omap_hwmod omap44xx_dmic_hwmod = {
 504         .name           = "dmic",
 505         .class          = &omap44xx_dmic_hwmod_class,
 506         .clkdm_name     = "abe_clkdm",
 507         .main_clk       = "func_dmic_abe_gfclk",
 508         .prcm = {
 509                 .omap4 = {
 510                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 511                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 512                         .modulemode   = MODULEMODE_SWCTRL,
 513                 },
 514         },
 515 };
 516
 517 /*
 518  * 'dsp' class
 519  * dsp sub-system
 520  */
 521
 522 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 523         .name   = "dsp",
 524 };
 525
 526 /* dsp */
 527 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 528         { .name = "dsp", .rst_shift = 0 },
 529 };
 530
 531 static struct omap_hwmod omap44xx_dsp_hwmod = {
 532         .name           = "dsp",
 533         .class          = &omap44xx_dsp_hwmod_class,
 534         .clkdm_name     = "tesla_clkdm",
 535         .rst_lines      = omap44xx_dsp_resets,
 536         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 537         .main_clk       = "dpll_iva_m4x2_ck",
 538         .prcm = {
 539                 .omap4 = {
 540                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 541                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 542                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 543                         .modulemode   = MODULEMODE_HWCTRL,
 544                 },
 545         },
 546 };
 547
 548 /*
 549  * 'dss' class
 550  * display sub-system
 551  */
 552
 553 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 554         .rev_offs       = 0x0000,
 555         .syss_offs      = 0x0014,
 556         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 557 };
 558
 559 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 560         .name   = "dss",
 561         .sysc   = &omap44xx_dss_sysc,
 562         .reset  = omap_dss_reset,
 563 };
 564
 565 /* dss */
 566 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 567         { .role = "sys_clk", .clk = "dss_sys_clk" },
 568         { .role = "tv_clk", .clk = "dss_tv_clk" },
 569         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 570 };
 571
 572 static struct omap_hwmod omap44xx_dss_hwmod = {
 573         .name           = "dss_core",
 574         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 575         .class          = &omap44xx_dss_hwmod_class,
 576         .clkdm_name     = "l3_dss_clkdm",
 577         .main_clk       = "dss_dss_clk",
 578         .prcm = {
 579                 .omap4 = {
 580                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 581                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 582                         .modulemode   = MODULEMODE_SWCTRL,
 583                 },
 584         },
 585         .opt_clks       = dss_opt_clks,
 586         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 587 };
 588
 589 /*
 590  * 'dispc' class
 591  * display controller
 592  */
 593
 594 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 595         .rev_offs       = 0x0000,
 596         .sysc_offs      = 0x0010,
 597         .syss_offs      = 0x0014,
 598         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 599                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 600                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 601                            SYSS_HAS_RESET_STATUS),
 602         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 603                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 604         .sysc_fields    = &omap_hwmod_sysc_type1,
 605 };
 606
 607 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 608         .name   = "dispc",
 609         .sysc   = &omap44xx_dispc_sysc,
 610 };
 611
 612 /* dss_dispc */
 613 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 614         .manager_count          = 3,
 615         .has_framedonetv_irq    = 1
 616 };
 617
 618 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 619         .name           = "dss_dispc",
 620         .class          = &omap44xx_dispc_hwmod_class,
 621         .clkdm_name     = "l3_dss_clkdm",
 622         .main_clk       = "dss_dss_clk",
 623         .prcm = {
 624                 .omap4 = {
 625                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 626                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 627                 },
 628         },
 629         .dev_attr       = &omap44xx_dss_dispc_dev_attr,
 630         .parent_hwmod   = &omap44xx_dss_hwmod,
 631 };
 632
 633 /*
 634  * 'dsi' class
 635  * display serial interface controller
 636  */
 637
 638 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 639         .rev_offs       = 0x0000,
 640         .sysc_offs      = 0x0010,
 641         .syss_offs      = 0x0014,
 642         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 643                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 644                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 645         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 646         .sysc_fields    = &omap_hwmod_sysc_type1,
 647 };
 648
 649 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 650         .name   = "dsi",
 651         .sysc   = &omap44xx_dsi_sysc,
 652 };
 653
 654 /* dss_dsi1 */
 655 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 656         { .role = "sys_clk", .clk = "dss_sys_clk" },
 657 };
 658
 659 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 660         .name           = "dss_dsi1",
 661         .class          = &omap44xx_dsi_hwmod_class,
 662         .clkdm_name     = "l3_dss_clkdm",
 663         .main_clk       = "dss_dss_clk",
 664         .prcm = {
 665                 .omap4 = {
 666                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 667                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 668                 },
 669         },
 670         .opt_clks       = dss_dsi1_opt_clks,
 671         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 672         .parent_hwmod   = &omap44xx_dss_hwmod,
 673 };
 674
 675 /* dss_dsi2 */
 676 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 677         { .role = "sys_clk", .clk = "dss_sys_clk" },
 678 };
 679
 680 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 681         .name           = "dss_dsi2",
 682         .class          = &omap44xx_dsi_hwmod_class,
 683         .clkdm_name     = "l3_dss_clkdm",
 684         .main_clk       = "dss_dss_clk",
 685         .prcm = {
 686                 .omap4 = {
 687                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 688                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 689                 },
 690         },
 691         .opt_clks       = dss_dsi2_opt_clks,
 692         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 693         .parent_hwmod   = &omap44xx_dss_hwmod,
 694 };
 695
 696 /*
 697  * 'hdmi' class
 698  * hdmi controller
 699  */
 700
 701 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 702         .rev_offs       = 0x0000,
 703         .sysc_offs      = 0x0010,
 704         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 705                            SYSC_HAS_SOFTRESET),
 706         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 707                            SIDLE_SMART_WKUP),
 708         .sysc_fields    = &omap_hwmod_sysc_type2,
 709 };
 710
 711 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 712         .name   = "hdmi",
 713         .sysc   = &omap44xx_hdmi_sysc,
 714 };
 715
 716 /* dss_hdmi */
 717 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 718         { .role = "sys_clk", .clk = "dss_sys_clk" },
 719         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 720 };
 721
 722 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 723         .name           = "dss_hdmi",
 724         .class          = &omap44xx_hdmi_hwmod_class,
 725         .clkdm_name     = "l3_dss_clkdm",
 726         /*
 727          * HDMI audio requires to use no-idle mode. Hence,
 728          * set idle mode by software.
 729          */
 730         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_OPT_CLKS_NEEDED,
 731         .main_clk       = "dss_48mhz_clk",
 732         .prcm = {
 733                 .omap4 = {
 734                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 735                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 736                 },
 737         },
 738         .opt_clks       = dss_hdmi_opt_clks,
 739         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 740         .parent_hwmod   = &omap44xx_dss_hwmod,
 741 };
 742
 743 /*
 744  * 'rfbi' class
 745  * remote frame buffer interface
 746  */
 747
 748 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 749         .rev_offs       = 0x0000,
 750         .sysc_offs      = 0x0010,
 751         .syss_offs      = 0x0014,
 752         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 753                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 754         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 755         .sysc_fields    = &omap_hwmod_sysc_type1,
 756 };
 757
 758 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 759         .name   = "rfbi",
 760         .sysc   = &omap44xx_rfbi_sysc,
 761 };
 762
 763 /* dss_rfbi */
 764 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 765         { .role = "ick", .clk = "l3_div_ck" },
 766 };
 767
 768 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 769         .name           = "dss_rfbi",
 770         .class          = &omap44xx_rfbi_hwmod_class,
 771         .clkdm_name     = "l3_dss_clkdm",
 772         .main_clk       = "dss_dss_clk",
 773         .prcm = {
 774                 .omap4 = {
 775                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 776                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 777                 },
 778         },
 779         .opt_clks       = dss_rfbi_opt_clks,
 780         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 781         .parent_hwmod   = &omap44xx_dss_hwmod,
 782 };
 783
 784 /*
 785  * 'venc' class
 786  * video encoder
 787  */
 788
 789 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 790         .name   = "venc",
 791 };
 792
 793 /* dss_venc */
 794 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
 795         { .role = "tv_clk", .clk = "dss_tv_clk" },
 796 };
 797
 798 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 799         .name           = "dss_venc",
 800         .class          = &omap44xx_venc_hwmod_class,
 801         .clkdm_name     = "l3_dss_clkdm",
 802         .main_clk       = "dss_tv_clk",
 803         .flags          = HWMOD_OPT_CLKS_NEEDED,
 804         .prcm = {
 805                 .omap4 = {
 806                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 807                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 808                 },
 809         },
 810         .parent_hwmod   = &omap44xx_dss_hwmod,
 811         .opt_clks       = dss_venc_opt_clks,
 812         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
 813 };
 814
 815 /* sha0 HIB2 (the 'P' (public) device) */
 816 static struct omap_hwmod_class_sysconfig omap44xx_sha0_sysc = {
 817         .rev_offs       = 0x100,
 818         .sysc_offs      = 0x110,
 819         .syss_offs      = 0x114,
 820         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 821 };
 822
 823 static struct omap_hwmod_class omap44xx_sha0_hwmod_class = {
 824         .name           = "sham",
 825         .sysc           = &omap44xx_sha0_sysc,
 826 };
 827
 828 struct omap_hwmod omap44xx_sha0_hwmod = {
 829         .name           = "sham",
 830         .class          = &omap44xx_sha0_hwmod_class,
 831         .clkdm_name     = "l4_secure_clkdm",
 832         .main_clk       = "l3_div_ck",
 833         .prcm           = {
 834                 .omap4 = {
 835                         .clkctrl_offs = OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
 836                         .context_offs = OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
 837                         .modulemode   = MODULEMODE_SWCTRL,
 838                 },
 839         },
 840 };
 841
 842 /*
 843  * 'elm' class
 844  * bch error location module
 845  */
 846
 847 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 848         .rev_offs       = 0x0000,
 849         .sysc_offs      = 0x0010,
 850         .syss_offs      = 0x0014,
 851         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 852                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 853                            SYSS_HAS_RESET_STATUS),
 854         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 855         .sysc_fields    = &omap_hwmod_sysc_type1,
 856 };
 857
 858 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 859         .name   = "elm",
 860         .sysc   = &omap44xx_elm_sysc,
 861 };
 862
 863 /* elm */
 864 static struct omap_hwmod omap44xx_elm_hwmod = {
 865         .name           = "elm",
 866         .class          = &omap44xx_elm_hwmod_class,
 867         .clkdm_name     = "l4_per_clkdm",
 868         .prcm = {
 869                 .omap4 = {
 870                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
 871                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
 872                 },
 873         },
 874 };
 875
 876 /*
 877  * 'emif' class
 878  * external memory interface no1
 879  */
 880
 881 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
 882         .rev_offs       = 0x0000,
 883 };
 884
 885 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
 886         .name   = "emif",
 887         .sysc   = &omap44xx_emif_sysc,
 888 };
 889
 890 /* emif1 */
 891 static struct omap_hwmod omap44xx_emif1_hwmod = {
 892         .name           = "emif1",
 893         .class          = &omap44xx_emif_hwmod_class,
 894         .clkdm_name     = "l3_emif_clkdm",
 895         .flags          = HWMOD_INIT_NO_IDLE,
 896         .main_clk       = "ddrphy_ck",
 897         .prcm = {
 898                 .omap4 = {
 899                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
 900                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
 901                         .modulemode   = MODULEMODE_HWCTRL,
 902                 },
 903         },
 904 };
 905
 906 /* emif2 */
 907 static struct omap_hwmod omap44xx_emif2_hwmod = {
 908         .name           = "emif2",
 909         .class          = &omap44xx_emif_hwmod_class,
 910         .clkdm_name     = "l3_emif_clkdm",
 911         .flags          = HWMOD_INIT_NO_IDLE,
 912         .main_clk       = "ddrphy_ck",
 913         .prcm = {
 914                 .omap4 = {
 915                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
 916                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
 917                         .modulemode   = MODULEMODE_HWCTRL,
 918                 },
 919         },
 920 };
 921
 922 /*
 923     Crypto modules AES0/1 belong to:
 924         PD_L4_PER power domain
 925         CD_L4_SEC clock domain
 926         On the L3, the AES modules are mapped to
 927         L3_CLK2: Peripherals and multimedia sub clock domain
 928 */
 929 static struct omap_hwmod_class_sysconfig omap44xx_aes_sysc = {
 930         .rev_offs       = 0x80,
 931         .sysc_offs      = 0x84,
 932         .syss_offs      = 0x88,
 933         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 934 };
 935
 936 static struct omap_hwmod_class omap44xx_aes_hwmod_class = {
 937         .name           = "aes",
 938         .sysc           = &omap44xx_aes_sysc,
 939 };
 940
 941 static struct omap_hwmod omap44xx_aes1_hwmod = {
 942         .name           = "aes1",
 943         .class          = &omap44xx_aes_hwmod_class,
 944         .clkdm_name     = "l4_secure_clkdm",
 945         .main_clk       = "l3_div_ck",
 946         .prcm           = {
 947                 .omap4  = {
 948                         .context_offs   = OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET,
 949                         .clkctrl_offs   = OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET,
 950                         .modulemode     = MODULEMODE_SWCTRL,
 951                 },
 952         },
 953 };
 954
 955 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes1 = {
 956         .master         = &omap44xx_l4_per_hwmod,
 957         .slave          = &omap44xx_aes1_hwmod,
 958         .clk            = "l3_div_ck",
 959         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 960 };
 961
 962 static struct omap_hwmod omap44xx_aes2_hwmod = {
 963         .name           = "aes2",
 964         .class          = &omap44xx_aes_hwmod_class,
 965         .clkdm_name     = "l4_secure_clkdm",
 966         .main_clk       = "l3_div_ck",
 967         .prcm           = {
 968                 .omap4  = {
 969                         .context_offs   = OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET,
 970                         .clkctrl_offs   = OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET,
 971                         .modulemode     = MODULEMODE_SWCTRL,
 972                 },
 973         },
 974 };
 975
 976 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes2 = {
 977         .master         = &omap44xx_l4_per_hwmod,
 978         .slave          = &omap44xx_aes2_hwmod,
 979         .clk            = "l3_div_ck",
 980         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 981 };
 982
 983 /*
 984  * 'des' class for DES3DES module
 985  */
 986 static struct omap_hwmod_class_sysconfig omap44xx_des_sysc = {
 987         .rev_offs       = 0x30,
 988         .sysc_offs      = 0x34,
 989         .syss_offs      = 0x38,
 990         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 991 };
 992
 993 static struct omap_hwmod_class omap44xx_des_hwmod_class = {
 994         .name           = "des",
 995         .sysc           = &omap44xx_des_sysc,
 996 };
 997
 998 static struct omap_hwmod omap44xx_des_hwmod = {
 999         .name           = "des",
1000         .class          = &omap44xx_des_hwmod_class,
1001         .clkdm_name     = "l4_secure_clkdm",
1002         .main_clk       = "l3_div_ck",
1003         .prcm           = {
1004                 .omap4  = {
1005                         .context_offs   = OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
1006                         .clkctrl_offs   = OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
1007                         .modulemode     = MODULEMODE_SWCTRL,
1008                 },
1009         },
1010 };
1011
1012 struct omap_hwmod_ocp_if omap44xx_l3_main_2__des = {
1013         .master         = &omap44xx_l3_main_2_hwmod,
1014         .slave          = &omap44xx_des_hwmod,
1015         .clk            = "l3_div_ck",
1016         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1017 };
1018
1019 /*
1020  * 'fdif' class
1021  * face detection hw accelerator module
1022  */
1023
1024 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1025         .rev_offs       = 0x0000,
1026         .sysc_offs      = 0x0010,
1027         /*
1028          * FDIF needs 100 OCP clk cycles delay after a softreset before
1029          * accessing sysconfig again.
1030          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1031          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1032          *
1033          * TODO: Indicate errata when available.
1034          */
1035         .srst_udelay    = 2,
1036         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1037                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1038         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1039                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1040         .sysc_fields    = &omap_hwmod_sysc_type2,
1041 };
1042
1043 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1044         .name   = "fdif",
1045         .sysc   = &omap44xx_fdif_sysc,
1046 };
1047
1048 /* fdif */
1049 static struct omap_hwmod omap44xx_fdif_hwmod = {
1050         .name           = "fdif",
1051         .class          = &omap44xx_fdif_hwmod_class,
1052         .clkdm_name     = "iss_clkdm",
1053         .main_clk       = "fdif_fck",
1054         .prcm = {
1055                 .omap4 = {
1056                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1057                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1058                         .modulemode   = MODULEMODE_SWCTRL,
1059                 },
1060         },
1061 };
1062
1063 /*
1064  * 'gpio' class
1065  * general purpose io module
1066  */
1067
1068 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1069         .rev_offs       = 0x0000,
1070         .sysc_offs      = 0x0010,
1071         .syss_offs      = 0x0114,
1072         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1073                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1074                            SYSS_HAS_RESET_STATUS),
1075         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1076                            SIDLE_SMART_WKUP),
1077         .sysc_fields    = &omap_hwmod_sysc_type1,
1078 };
1079
1080 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1081         .name   = "gpio",
1082         .sysc   = &omap44xx_gpio_sysc,
1083         .rev    = 2,
1084 };
1085
1086 /* gpio dev_attr */
1087 static struct omap_gpio_dev_attr gpio_dev_attr = {
1088         .bank_width     = 32,
1089         .dbck_flag      = true,
1090 };
1091
1092 /* gpio1 */
1093 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1094         { .role = "dbclk", .clk = "gpio1_dbclk" },
1095 };
1096
1097 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1098         .name           = "gpio1",
1099         .class          = &omap44xx_gpio_hwmod_class,
1100         .clkdm_name     = "l4_wkup_clkdm",
1101         .main_clk       = "l4_wkup_clk_mux_ck",
1102         .prcm = {
1103                 .omap4 = {
1104                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1105                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1106                         .modulemode   = MODULEMODE_HWCTRL,
1107                 },
1108         },
1109         .opt_clks       = gpio1_opt_clks,
1110         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1111         .dev_attr       = &gpio_dev_attr,
1112 };
1113
1114 /* gpio2 */
1115 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1116         { .role = "dbclk", .clk = "gpio2_dbclk" },
1117 };
1118
1119 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1120         .name           = "gpio2",
1121         .class          = &omap44xx_gpio_hwmod_class,
1122         .clkdm_name     = "l4_per_clkdm",
1123         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1124         .main_clk       = "l4_div_ck",
1125         .prcm = {
1126                 .omap4 = {
1127                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1128                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1129                         .modulemode   = MODULEMODE_HWCTRL,
1130                 },
1131         },
1132         .opt_clks       = gpio2_opt_clks,
1133         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1134         .dev_attr       = &gpio_dev_attr,
1135 };
1136
1137 /* gpio3 */
1138 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1139         { .role = "dbclk", .clk = "gpio3_dbclk" },
1140 };
1141
1142 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1143         .name           = "gpio3",
1144         .class          = &omap44xx_gpio_hwmod_class,
1145         .clkdm_name     = "l4_per_clkdm",
1146         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1147         .main_clk       = "l4_div_ck",
1148         .prcm = {
1149                 .omap4 = {
1150                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1151                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1152                         .modulemode   = MODULEMODE_HWCTRL,
1153                 },
1154         },
1155         .opt_clks       = gpio3_opt_clks,
1156         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1157         .dev_attr       = &gpio_dev_attr,
1158 };
1159
1160 /* gpio4 */
1161 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1162         { .role = "dbclk", .clk = "gpio4_dbclk" },
1163 };
1164
1165 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1166         .name           = "gpio4",
1167         .class          = &omap44xx_gpio_hwmod_class,
1168         .clkdm_name     = "l4_per_clkdm",
1169         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1170         .main_clk       = "l4_div_ck",
1171         .prcm = {
1172                 .omap4 = {
1173                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1174                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1175                         .modulemode   = MODULEMODE_HWCTRL,
1176                 },
1177         },
1178         .opt_clks       = gpio4_opt_clks,
1179         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1180         .dev_attr       = &gpio_dev_attr,
1181 };
1182
1183 /* gpio5 */
1184 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1185         { .role = "dbclk", .clk = "gpio5_dbclk" },
1186 };
1187
1188 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1189         .name           = "gpio5",
1190         .class          = &omap44xx_gpio_hwmod_class,
1191         .clkdm_name     = "l4_per_clkdm",
1192         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1193         .main_clk       = "l4_div_ck",
1194         .prcm = {
1195                 .omap4 = {
1196                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1197                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1198                         .modulemode   = MODULEMODE_HWCTRL,
1199                 },
1200         },
1201         .opt_clks       = gpio5_opt_clks,
1202         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1203         .dev_attr       = &gpio_dev_attr,
1204 };
1205
1206 /* gpio6 */
1207 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1208         { .role = "dbclk", .clk = "gpio6_dbclk" },
1209 };
1210
1211 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1212         .name           = "gpio6",
1213         .class          = &omap44xx_gpio_hwmod_class,
1214         .clkdm_name     = "l4_per_clkdm",
1215         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1216         .main_clk       = "l4_div_ck",
1217         .prcm = {
1218                 .omap4 = {
1219                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1220                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1221                         .modulemode   = MODULEMODE_HWCTRL,
1222                 },
1223         },
1224         .opt_clks       = gpio6_opt_clks,
1225         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1226         .dev_attr       = &gpio_dev_attr,
1227 };
1228
1229 /*
1230  * 'gpmc' class
1231  * general purpose memory controller
1232  */
1233
1234 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1235         .rev_offs       = 0x0000,
1236         .sysc_offs      = 0x0010,
1237         .syss_offs      = 0x0014,
1238         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1239                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1240         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1241         .sysc_fields    = &omap_hwmod_sysc_type1,
1242 };
1243
1244 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1245         .name   = "gpmc",
1246         .sysc   = &omap44xx_gpmc_sysc,
1247 };
1248
1249 /* gpmc */
1250 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1251         .name           = "gpmc",
1252         .class          = &omap44xx_gpmc_hwmod_class,
1253         .clkdm_name     = "l3_2_clkdm",
1254         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
1255         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
1256         .prcm = {
1257                 .omap4 = {
1258                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1259                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1260                         .modulemode   = MODULEMODE_HWCTRL,
1261                 },
1262         },
1263 };
1264
1265 /*
1266  * 'gpu' class
1267  * 2d/3d graphics accelerator
1268  */
1269
1270 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1271         .rev_offs       = 0x1fc00,
1272         .sysc_offs      = 0x1fc10,
1273         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1274         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1275                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1276                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1277         .sysc_fields    = &omap_hwmod_sysc_type2,
1278 };
1279
1280 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1281         .name   = "gpu",
1282         .sysc   = &omap44xx_gpu_sysc,
1283 };
1284
1285 /* gpu */
1286 static struct omap_hwmod omap44xx_gpu_hwmod = {
1287         .name           = "gpu",
1288         .class          = &omap44xx_gpu_hwmod_class,
1289         .clkdm_name     = "l3_gfx_clkdm",
1290         .main_clk       = "sgx_clk_mux",
1291         .prcm = {
1292                 .omap4 = {
1293                         .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1294                         .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1295                         .modulemode   = MODULEMODE_SWCTRL,
1296                 },
1297         },
1298 };
1299
1300 /*
1301  * 'hdq1w' class
1302  * hdq / 1-wire serial interface controller
1303  */
1304
1305 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1306         .rev_offs       = 0x0000,
1307         .sysc_offs      = 0x0014,
1308         .syss_offs      = 0x0018,
1309         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1310                            SYSS_HAS_RESET_STATUS),
1311         .sysc_fields    = &omap_hwmod_sysc_type1,
1312 };
1313
1314 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1315         .name   = "hdq1w",
1316         .sysc   = &omap44xx_hdq1w_sysc,
1317 };
1318
1319 /* hdq1w */
1320 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1321         .name           = "hdq1w",
1322         .class          = &omap44xx_hdq1w_hwmod_class,
1323         .clkdm_name     = "l4_per_clkdm",
1324         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1325         .main_clk       = "func_12m_fclk",
1326         .prcm = {
1327                 .omap4 = {
1328                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1329                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1330                         .modulemode   = MODULEMODE_SWCTRL,
1331                 },
1332         },
1333 };
1334
1335 /*
1336  * 'hsi' class
1337  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1338  * serial if)
1339  */
1340
1341 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1342         .rev_offs       = 0x0000,
1343         .sysc_offs      = 0x0010,
1344         .syss_offs      = 0x0014,
1345         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1346                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1347                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1348         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1349                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1350                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1351         .sysc_fields    = &omap_hwmod_sysc_type1,
1352 };
1353
1354 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1355         .name   = "hsi",
1356         .sysc   = &omap44xx_hsi_sysc,
1357 };
1358
1359 /* hsi */
1360 static struct omap_hwmod omap44xx_hsi_hwmod = {
1361         .name           = "hsi",
1362         .class          = &omap44xx_hsi_hwmod_class,
1363         .clkdm_name     = "l3_init_clkdm",
1364         .main_clk       = "hsi_fck",
1365         .prcm = {
1366                 .omap4 = {
1367                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1368                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1369                         .modulemode   = MODULEMODE_HWCTRL,
1370                 },
1371         },
1372 };
1373
1374 /*
1375  * 'i2c' class
1376  * multimaster high-speed i2c controller
1377  */
1378
1379 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1380         .sysc_offs      = 0x0010,
1381         .syss_offs      = 0x0090,
1382         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1383                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1384                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1385         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1386                            SIDLE_SMART_WKUP),
1387         .sysc_fields    = &omap_hwmod_sysc_type1,
1388 };
1389
1390 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1391         .name   = "i2c",
1392         .sysc   = &omap44xx_i2c_sysc,
1393         .rev    = OMAP_I2C_IP_VERSION_2,
1394         .reset  = &omap_i2c_reset,
1395 };
1396
1397 static struct omap_i2c_dev_attr i2c_dev_attr = {
1398         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1399 };
1400
1401 /* i2c1 */
1402 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1403         .name           = "i2c1",
1404         .class          = &omap44xx_i2c_hwmod_class,
1405         .clkdm_name     = "l4_per_clkdm",
1406         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1407         .main_clk       = "func_96m_fclk",
1408         .prcm = {
1409                 .omap4 = {
1410                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1411                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1412                         .modulemode   = MODULEMODE_SWCTRL,
1413                 },
1414         },
1415         .dev_attr       = &i2c_dev_attr,
1416 };
1417
1418 /* i2c2 */
1419 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1420         .name           = "i2c2",
1421         .class          = &omap44xx_i2c_hwmod_class,
1422         .clkdm_name     = "l4_per_clkdm",
1423         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1424         .main_clk       = "func_96m_fclk",
1425         .prcm = {
1426                 .omap4 = {
1427                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1428                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1429                         .modulemode   = MODULEMODE_SWCTRL,
1430                 },
1431         },
1432         .dev_attr       = &i2c_dev_attr,
1433 };
1434
1435 /* i2c3 */
1436 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1437         .name           = "i2c3",
1438         .class          = &omap44xx_i2c_hwmod_class,
1439         .clkdm_name     = "l4_per_clkdm",
1440         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1441         .main_clk       = "func_96m_fclk",
1442         .prcm = {
1443                 .omap4 = {
1444                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1445                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1446                         .modulemode   = MODULEMODE_SWCTRL,
1447                 },
1448         },
1449         .dev_attr       = &i2c_dev_attr,
1450 };
1451
1452 /* i2c4 */
1453 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1454         .name           = "i2c4",
1455         .class          = &omap44xx_i2c_hwmod_class,
1456         .clkdm_name     = "l4_per_clkdm",
1457         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1458         .main_clk       = "func_96m_fclk",
1459         .prcm = {
1460                 .omap4 = {
1461                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1462                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1463                         .modulemode   = MODULEMODE_SWCTRL,
1464                 },
1465         },
1466         .dev_attr       = &i2c_dev_attr,
1467 };
1468
1469 /*
1470  * 'ipu' class
1471  * imaging processor unit
1472  */
1473
1474 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1475         .name   = "ipu",
1476 };
1477
1478 /* ipu */
1479 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1480         { .name = "cpu0", .rst_shift = 0 },
1481         { .name = "cpu1", .rst_shift = 1 },
1482 };
1483
1484 static struct omap_hwmod omap44xx_ipu_hwmod = {
1485         .name           = "ipu",
1486         .class          = &omap44xx_ipu_hwmod_class,
1487         .clkdm_name     = "ducati_clkdm",
1488         .rst_lines      = omap44xx_ipu_resets,
1489         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1490         .main_clk       = "ducati_clk_mux_ck",
1491         .prcm = {
1492                 .omap4 = {
1493                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1494                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1495                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1496                         .modulemode   = MODULEMODE_HWCTRL,
1497                 },
1498         },
1499 };
1500
1501 /*
1502  * 'iss' class
1503  * external images sensor pixel data processor
1504  */
1505
1506 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1507         .rev_offs       = 0x0000,
1508         .sysc_offs      = 0x0010,
1509         /*
1510          * ISS needs 100 OCP clk cycles delay after a softreset before
1511          * accessing sysconfig again.
1512          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1513          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1514          *
1515          * TODO: Indicate errata when available.
1516          */
1517         .srst_udelay    = 2,
1518         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1519                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1520         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1521                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1522                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1523         .sysc_fields    = &omap_hwmod_sysc_type2,
1524 };
1525
1526 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1527         .name   = "iss",
1528         .sysc   = &omap44xx_iss_sysc,
1529 };
1530
1531 /* iss */
1532 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1533         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1534 };
1535
1536 static struct omap_hwmod omap44xx_iss_hwmod = {
1537         .name           = "iss",
1538         .class          = &omap44xx_iss_hwmod_class,
1539         .clkdm_name     = "iss_clkdm",
1540         .main_clk       = "ducati_clk_mux_ck",
1541         .prcm = {
1542                 .omap4 = {
1543                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1544                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1545                         .modulemode   = MODULEMODE_SWCTRL,
1546                 },
1547         },
1548         .opt_clks       = iss_opt_clks,
1549         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1550 };
1551
1552 /*
1553  * 'iva' class
1554  * multi-standard video encoder/decoder hardware accelerator
1555  */
1556
1557 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1558         .name   = "iva",
1559 };
1560
1561 /* iva */
1562 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1563         { .name = "seq0", .rst_shift = 0 },
1564         { .name = "seq1", .rst_shift = 1 },
1565         { .name = "logic", .rst_shift = 2 },
1566 };
1567
1568 static struct omap_hwmod omap44xx_iva_hwmod = {
1569         .name           = "iva",
1570         .class          = &omap44xx_iva_hwmod_class,
1571         .clkdm_name     = "ivahd_clkdm",
1572         .rst_lines      = omap44xx_iva_resets,
1573         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1574         .main_clk       = "dpll_iva_m5x2_ck",
1575         .prcm = {
1576                 .omap4 = {
1577                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1578                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1579                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1580                         .modulemode   = MODULEMODE_HWCTRL,
1581                 },
1582         },
1583 };
1584
1585 /*
1586  * 'kbd' class
1587  * keyboard controller
1588  */
1589
1590 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1591         .rev_offs       = 0x0000,
1592         .sysc_offs      = 0x0010,
1593         .syss_offs      = 0x0014,
1594         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1595                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1596                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1597                            SYSS_HAS_RESET_STATUS),
1598         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1599         .sysc_fields    = &omap_hwmod_sysc_type1,
1600 };
1601
1602 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1603         .name   = "kbd",
1604         .sysc   = &omap44xx_kbd_sysc,
1605 };
1606
1607 /* kbd */
1608 static struct omap_hwmod omap44xx_kbd_hwmod = {
1609         .name           = "kbd",
1610         .class          = &omap44xx_kbd_hwmod_class,
1611         .clkdm_name     = "l4_wkup_clkdm",
1612         .main_clk       = "sys_32k_ck",
1613         .prcm = {
1614                 .omap4 = {
1615                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1616                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1617                         .modulemode   = MODULEMODE_SWCTRL,
1618                 },
1619         },
1620 };
1621
1622 /*
1623  * 'mailbox' class
1624  * mailbox module allowing communication between the on-chip processors using a
1625  * queued mailbox-interrupt mechanism.
1626  */
1627
1628 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1629         .rev_offs       = 0x0000,
1630         .sysc_offs      = 0x0010,
1631         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1632                            SYSC_HAS_SOFTRESET),
1633         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1634         .sysc_fields    = &omap_hwmod_sysc_type2,
1635 };
1636
1637 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1638         .name   = "mailbox",
1639         .sysc   = &omap44xx_mailbox_sysc,
1640 };
1641
1642 /* mailbox */
1643 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1644         .name           = "mailbox",
1645         .class          = &omap44xx_mailbox_hwmod_class,
1646         .clkdm_name     = "l4_cfg_clkdm",
1647         .prcm = {
1648                 .omap4 = {
1649                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1650                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1651                 },
1652         },
1653 };
1654
1655 /*
1656  * 'mcasp' class
1657  * multi-channel audio serial port controller
1658  */
1659
1660 /* The IP is not compliant to type1 / type2 scheme */
1661 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1662         .sidle_shift    = 0,
1663 };
1664
1665 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1666         .sysc_offs      = 0x0004,
1667         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1668         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1669                            SIDLE_SMART_WKUP),
1670         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1671 };
1672
1673 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1674         .name   = "mcasp",
1675         .sysc   = &omap44xx_mcasp_sysc,
1676 };
1677
1678 /* mcasp */
1679 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1680         .name           = "mcasp",
1681         .class          = &omap44xx_mcasp_hwmod_class,
1682         .clkdm_name     = "abe_clkdm",
1683         .main_clk       = "func_mcasp_abe_gfclk",
1684         .prcm = {
1685                 .omap4 = {
1686                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1687                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1688                         .modulemode   = MODULEMODE_SWCTRL,
1689                 },
1690         },
1691 };
1692
1693 /*
1694  * 'mcbsp' class
1695  * multi channel buffered serial port controller
1696  */
1697
1698 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1699         .sysc_offs      = 0x008c,
1700         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1701                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1702         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1703         .sysc_fields    = &omap_hwmod_sysc_type1,
1704 };
1705
1706 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1707         .name   = "mcbsp",
1708         .sysc   = &omap44xx_mcbsp_sysc,
1709         .rev    = MCBSP_CONFIG_TYPE4,
1710 };
1711
1712 /* mcbsp1 */
1713 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1714         { .role = "pad_fck", .clk = "pad_clks_ck" },
1715         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1716 };
1717
1718 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1719         .name           = "mcbsp1",
1720         .class          = &omap44xx_mcbsp_hwmod_class,
1721         .clkdm_name     = "abe_clkdm",
1722         .main_clk       = "func_mcbsp1_gfclk",
1723         .prcm = {
1724                 .omap4 = {
1725                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1726                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1727                         .modulemode   = MODULEMODE_SWCTRL,
1728                 },
1729         },
1730         .opt_clks       = mcbsp1_opt_clks,
1731         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1732 };
1733
1734 /* mcbsp2 */
1735 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1736         { .role = "pad_fck", .clk = "pad_clks_ck" },
1737         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1738 };
1739
1740 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
1741         .name           = "mcbsp2",
1742         .class          = &omap44xx_mcbsp_hwmod_class,
1743         .clkdm_name     = "abe_clkdm",
1744         .main_clk       = "func_mcbsp2_gfclk",
1745         .prcm = {
1746                 .omap4 = {
1747                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
1748                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1749                         .modulemode   = MODULEMODE_SWCTRL,
1750                 },
1751         },
1752         .opt_clks       = mcbsp2_opt_clks,
1753         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
1754 };
1755
1756 /* mcbsp3 */
1757 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
1758         { .role = "pad_fck", .clk = "pad_clks_ck" },
1759         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
1760 };
1761
1762 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
1763         .name           = "mcbsp3",
1764         .class          = &omap44xx_mcbsp_hwmod_class,
1765         .clkdm_name     = "abe_clkdm",
1766         .main_clk       = "func_mcbsp3_gfclk",
1767         .prcm = {
1768                 .omap4 = {
1769                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
1770                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
1771                         .modulemode   = MODULEMODE_SWCTRL,
1772                 },
1773         },
1774         .opt_clks       = mcbsp3_opt_clks,
1775         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
1776 };
1777
1778 /* mcbsp4 */
1779 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
1780         { .role = "pad_fck", .clk = "pad_clks_ck" },
1781         { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
1782 };
1783
1784 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
1785         .name           = "mcbsp4",
1786         .class          = &omap44xx_mcbsp_hwmod_class,
1787         .clkdm_name     = "l4_per_clkdm",
1788         .main_clk       = "per_mcbsp4_gfclk",
1789         .prcm = {
1790                 .omap4 = {
1791                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
1792                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
1793                         .modulemode   = MODULEMODE_SWCTRL,
1794                 },
1795         },
1796         .opt_clks       = mcbsp4_opt_clks,
1797         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
1798 };
1799
1800 /*
1801  * 'mcpdm' class
1802  * multi channel pdm controller (proprietary interface with phoenix power
1803  * ic)
1804  */
1805
1806 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
1807         .rev_offs       = 0x0000,
1808         .sysc_offs      = 0x0010,
1809         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1810                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1811         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1812                            SIDLE_SMART_WKUP),
1813         .sysc_fields    = &omap_hwmod_sysc_type2,
1814 };
1815
1816 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
1817         .name   = "mcpdm",
1818         .sysc   = &omap44xx_mcpdm_sysc,
1819 };
1820
1821 /* mcpdm */
1822 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
1823         .name           = "mcpdm",
1824         .class          = &omap44xx_mcpdm_hwmod_class,
1825         .clkdm_name     = "abe_clkdm",
1826         /*
1827          * It's suspected that the McPDM requires an off-chip main
1828          * functional clock, controlled via I2C.  This IP block is
1829          * currently reset very early during boot, before I2C is
1830          * available, so it doesn't seem that we have any choice in
1831          * the kernel other than to avoid resetting it.
1832          *
1833          * Also, McPDM needs to be configured to NO_IDLE mode when it
1834          * is in used otherwise vital clocks will be gated which
1835          * results 'slow motion' audio playback.
1836          */
1837         .flags          = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
1838         .main_clk       = "pad_clks_ck",
1839         .prcm = {
1840                 .omap4 = {
1841                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
1842                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
1843                         .modulemode   = MODULEMODE_SWCTRL,
1844                 },
1845         },
1846 };
1847
1848 /*
1849  * 'mcspi' class
1850  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1851  * bus
1852  */
1853
1854 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
1855         .rev_offs       = 0x0000,
1856         .sysc_offs      = 0x0010,
1857         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1858                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1859         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1860                            SIDLE_SMART_WKUP),
1861         .sysc_fields    = &omap_hwmod_sysc_type2,
1862 };
1863
1864 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
1865         .name   = "mcspi",
1866         .sysc   = &omap44xx_mcspi_sysc,
1867         .rev    = OMAP4_MCSPI_REV,
1868 };
1869
1870 /* mcspi1 */
1871 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1872         .num_chipselect = 4,
1873 };
1874
1875 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
1876         .name           = "mcspi1",
1877         .class          = &omap44xx_mcspi_hwmod_class,
1878         .clkdm_name     = "l4_per_clkdm",
1879         .main_clk       = "func_48m_fclk",
1880         .prcm = {
1881                 .omap4 = {
1882                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1883                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1884                         .modulemode   = MODULEMODE_SWCTRL,
1885                 },
1886         },
1887         .dev_attr       = &mcspi1_dev_attr,
1888 };
1889
1890 /* mcspi2 */
1891 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1892         .num_chipselect = 2,
1893 };
1894
1895 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
1896         .name           = "mcspi2",
1897         .class          = &omap44xx_mcspi_hwmod_class,
1898         .clkdm_name     = "l4_per_clkdm",
1899         .main_clk       = "func_48m_fclk",
1900         .prcm = {
1901                 .omap4 = {
1902                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1903                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1904                         .modulemode   = MODULEMODE_SWCTRL,
1905                 },
1906         },
1907         .dev_attr       = &mcspi2_dev_attr,
1908 };
1909
1910 /* mcspi3 */
1911 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1912         .num_chipselect = 2,
1913 };
1914
1915 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
1916         .name           = "mcspi3",
1917         .class          = &omap44xx_mcspi_hwmod_class,
1918         .clkdm_name     = "l4_per_clkdm",
1919         .main_clk       = "func_48m_fclk",
1920         .prcm = {
1921                 .omap4 = {
1922                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1923                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1924                         .modulemode   = MODULEMODE_SWCTRL,
1925                 },
1926         },
1927         .dev_attr       = &mcspi3_dev_attr,
1928 };
1929
1930 /* mcspi4 */
1931 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1932         .num_chipselect = 1,
1933 };
1934
1935 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
1936         .name           = "mcspi4",
1937         .class          = &omap44xx_mcspi_hwmod_class,
1938         .clkdm_name     = "l4_per_clkdm",
1939         .main_clk       = "func_48m_fclk",
1940         .prcm = {
1941                 .omap4 = {
1942                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1943                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1944                         .modulemode   = MODULEMODE_SWCTRL,
1945                 },
1946         },
1947         .dev_attr       = &mcspi4_dev_attr,
1948 };
1949
1950 /*
1951  * 'mmc' class
1952  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
1953  */
1954
1955 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
1956         .rev_offs       = 0x0000,
1957         .sysc_offs      = 0x0010,
1958         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1959                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1960                            SYSC_HAS_SOFTRESET),
1961         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1962                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1963                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1964         .sysc_fields    = &omap_hwmod_sysc_type2,
1965 };
1966
1967 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
1968         .name   = "mmc",
1969         .sysc   = &omap44xx_mmc_sysc,
1970 };
1971
1972 /* mmc1 */
1973 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1974         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1975 };
1976
1977 static struct omap_hwmod omap44xx_mmc1_hwmod = {
1978         .name           = "mmc1",
1979         .class          = &omap44xx_mmc_hwmod_class,
1980         .clkdm_name     = "l3_init_clkdm",
1981         .main_clk       = "hsmmc1_fclk",
1982         .prcm = {
1983                 .omap4 = {
1984                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1985                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1986                         .modulemode   = MODULEMODE_SWCTRL,
1987                 },
1988         },
1989         .dev_attr       = &mmc1_dev_attr,
1990 };
1991
1992 /* mmc2 */
1993 static struct omap_hwmod omap44xx_mmc2_hwmod = {
1994         .name           = "mmc2",
1995         .class          = &omap44xx_mmc_hwmod_class,
1996         .clkdm_name     = "l3_init_clkdm",
1997         .main_clk       = "hsmmc2_fclk",
1998         .prcm = {
1999                 .omap4 = {
2000                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2001                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2002                         .modulemode   = MODULEMODE_SWCTRL,
2003                 },
2004         },
2005 };
2006
2007 /* mmc3 */
2008 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2009         .name           = "mmc3",
2010         .class          = &omap44xx_mmc_hwmod_class,
2011         .clkdm_name     = "l4_per_clkdm",
2012         .main_clk       = "func_48m_fclk",
2013         .prcm = {
2014                 .omap4 = {
2015                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2016                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2017                         .modulemode   = MODULEMODE_SWCTRL,
2018                 },
2019         },
2020 };
2021
2022 /* mmc4 */
2023 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2024         .name           = "mmc4",
2025         .class          = &omap44xx_mmc_hwmod_class,
2026         .clkdm_name     = "l4_per_clkdm",
2027         .main_clk       = "func_48m_fclk",
2028         .prcm = {
2029                 .omap4 = {
2030                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2031                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2032                         .modulemode   = MODULEMODE_SWCTRL,
2033                 },
2034         },
2035 };
2036
2037 /* mmc5 */
2038 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2039         .name           = "mmc5",
2040         .class          = &omap44xx_mmc_hwmod_class,
2041         .clkdm_name     = "l4_per_clkdm",
2042         .main_clk       = "func_48m_fclk",
2043         .prcm = {
2044                 .omap4 = {
2045                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2046                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2047                         .modulemode   = MODULEMODE_SWCTRL,
2048                 },
2049         },
2050 };
2051
2052 /*
2053  * 'mmu' class
2054  * The memory management unit performs virtual to physical address translation
2055  * for its requestors.
2056  */
2057
2058 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2059         .rev_offs       = 0x000,
2060         .sysc_offs      = 0x010,
2061         .syss_offs      = 0x014,
2062         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2063                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2064         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2065         .sysc_fields    = &omap_hwmod_sysc_type1,
2066 };
2067
2068 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2069         .name = "mmu",
2070         .sysc = &mmu_sysc,
2071 };
2072
2073 /* mmu ipu */
2074
2075 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2076 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2077         { .name = "mmu_cache", .rst_shift = 2 },
2078 };
2079
2080 /* l3_main_2 -> mmu_ipu */
2081 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2082         .master         = &omap44xx_l3_main_2_hwmod,
2083         .slave          = &omap44xx_mmu_ipu_hwmod,
2084         .clk            = "l3_div_ck",
2085         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2086 };
2087
2088 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2089         .name           = "mmu_ipu",
2090         .class          = &omap44xx_mmu_hwmod_class,
2091         .clkdm_name     = "ducati_clkdm",
2092         .rst_lines      = omap44xx_mmu_ipu_resets,
2093         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2094         .main_clk       = "ducati_clk_mux_ck",
2095         .prcm = {
2096                 .omap4 = {
2097                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2098                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2099                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2100                         .modulemode   = MODULEMODE_HWCTRL,
2101                 },
2102         },
2103 };
2104
2105 /* mmu dsp */
2106
2107 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2108 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2109         { .name = "mmu_cache", .rst_shift = 1 },
2110 };
2111
2112 /* l4_cfg -> dsp */
2113 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2114         .master         = &omap44xx_l4_cfg_hwmod,
2115         .slave          = &omap44xx_mmu_dsp_hwmod,
2116         .clk            = "l4_div_ck",
2117         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2118 };
2119
2120 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2121         .name           = "mmu_dsp",
2122         .class          = &omap44xx_mmu_hwmod_class,
2123         .clkdm_name     = "tesla_clkdm",
2124         .rst_lines      = omap44xx_mmu_dsp_resets,
2125         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2126         .main_clk       = "dpll_iva_m4x2_ck",
2127         .prcm = {
2128                 .omap4 = {
2129                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2130                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2131                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2132                         .modulemode   = MODULEMODE_HWCTRL,
2133                 },
2134         },
2135 };
2136
2137 /*
2138  * 'mpu' class
2139  * mpu sub-system
2140  */
2141
2142 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2143         .name   = "mpu",
2144 };
2145
2146 /* mpu */
2147 static struct omap_hwmod omap44xx_mpu_hwmod = {
2148         .name           = "mpu",
2149         .class          = &omap44xx_mpu_hwmod_class,
2150         .clkdm_name     = "mpuss_clkdm",
2151         .flags          = HWMOD_INIT_NO_IDLE,
2152         .main_clk       = "dpll_mpu_m2_ck",
2153         .prcm = {
2154                 .omap4 = {
2155                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2156                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2157                 },
2158         },
2159 };
2160
2161 /*
2162  * 'ocmc_ram' class
2163  * top-level core on-chip ram
2164  */
2165
2166 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2167         .name   = "ocmc_ram",
2168 };
2169
2170 /* ocmc_ram */
2171 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2172         .name           = "ocmc_ram",
2173         .class          = &omap44xx_ocmc_ram_hwmod_class,
2174         .clkdm_name     = "l3_2_clkdm",
2175         .prcm = {
2176                 .omap4 = {
2177                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2178                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2179                 },
2180         },
2181 };
2182
2183 /*
2184  * 'ocp2scp' class
2185  * bridge to transform ocp interface protocol to scp (serial control port)
2186  * protocol
2187  */
2188
2189 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2190         .rev_offs       = 0x0000,
2191         .sysc_offs      = 0x0010,
2192         .syss_offs      = 0x0014,
2193         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2194                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2195         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2196         .sysc_fields    = &omap_hwmod_sysc_type1,
2197 };
2198
2199 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2200         .name   = "ocp2scp",
2201         .sysc   = &omap44xx_ocp2scp_sysc,
2202 };
2203
2204 /* ocp2scp_usb_phy */
2205 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2206         .name           = "ocp2scp_usb_phy",
2207         .class          = &omap44xx_ocp2scp_hwmod_class,
2208         .clkdm_name     = "l3_init_clkdm",
2209         /*
2210          * ocp2scp_usb_phy_phy_48m is provided by the OMAP4 PRCM IP
2211          * block as an "optional clock," and normally should never be
2212          * specified as the main_clk for an OMAP IP block.  However it
2213          * turns out that this clock is actually the main clock for
2214          * the ocp2scp_usb_phy IP block:
2215          * http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/119943.html
2216          * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems
2217          * to be the best workaround.
2218          */
2219         .main_clk       = "ocp2scp_usb_phy_phy_48m",
2220         .prcm = {
2221                 .omap4 = {
2222                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2223                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2224                         .modulemode   = MODULEMODE_HWCTRL,
2225                 },
2226         },
2227 };
2228
2229 /*
2230  * 'prcm' class
2231  * power and reset manager (part of the prcm infrastructure) + clock manager 2
2232  * + clock manager 1 (in always on power domain) + local prm in mpu
2233  */
2234
2235 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2236         .name   = "prcm",
2237 };
2238
2239 /* prcm_mpu */
2240 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2241         .name           = "prcm_mpu",
2242         .class          = &omap44xx_prcm_hwmod_class,
2243         .clkdm_name     = "l4_wkup_clkdm",
2244         .flags          = HWMOD_NO_IDLEST,
2245         .prcm = {
2246                 .omap4 = {
2247                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2248                 },
2249         },
2250 };
2251
2252 /* cm_core_aon */
2253 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2254         .name           = "cm_core_aon",
2255         .class          = &omap44xx_prcm_hwmod_class,
2256         .flags          = HWMOD_NO_IDLEST,
2257         .prcm = {
2258                 .omap4 = {
2259                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2260                 },
2261         },
2262 };
2263
2264 /* cm_core */
2265 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2266         .name           = "cm_core",
2267         .class          = &omap44xx_prcm_hwmod_class,
2268         .flags          = HWMOD_NO_IDLEST,
2269         .prcm = {
2270                 .omap4 = {
2271                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2272                 },
2273         },
2274 };
2275
2276 /* prm */
2277 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2278         { .name = "rst_global_warm_sw", .rst_shift = 0 },
2279         { .name = "rst_global_cold_sw", .rst_shift = 1 },
2280 };
2281
2282 static struct omap_hwmod omap44xx_prm_hwmod = {
2283         .name           = "prm",
2284         .class          = &omap44xx_prcm_hwmod_class,
2285         .rst_lines      = omap44xx_prm_resets,
2286         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
2287 };
2288
2289 /*
2290  * 'scrm' class
2291  * system clock and reset manager
2292  */
2293
2294 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2295         .name   = "scrm",
2296 };
2297
2298 /* scrm */
2299 static struct omap_hwmod omap44xx_scrm_hwmod = {
2300         .name           = "scrm",
2301         .class          = &omap44xx_scrm_hwmod_class,
2302         .clkdm_name     = "l4_wkup_clkdm",
2303         .prcm = {
2304                 .omap4 = {
2305                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2306                 },
2307         },
2308 };
2309
2310 /*
2311  * 'sl2if' class
2312  * shared level 2 memory interface
2313  */
2314
2315 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2316         .name   = "sl2if",
2317 };
2318
2319 /* sl2if */
2320 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2321         .name           = "sl2if",
2322         .class          = &omap44xx_sl2if_hwmod_class,
2323         .clkdm_name     = "ivahd_clkdm",
2324         .prcm = {
2325                 .omap4 = {
2326                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2327                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2328                         .modulemode   = MODULEMODE_HWCTRL,
2329                 },
2330         },
2331 };
2332
2333 /*
2334  * 'slimbus' class
2335  * bidirectional, multi-drop, multi-channel two-line serial interface between
2336  * the device and external components
2337  */
2338
2339 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2340         .rev_offs       = 0x0000,
2341         .sysc_offs      = 0x0010,
2342         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2343                            SYSC_HAS_SOFTRESET),
2344         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2345                            SIDLE_SMART_WKUP),
2346         .sysc_fields    = &omap_hwmod_sysc_type2,
2347 };
2348
2349 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2350         .name   = "slimbus",
2351         .sysc   = &omap44xx_slimbus_sysc,
2352 };
2353
2354 /* slimbus1 */
2355 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2356         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2357         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2358         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2359         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2360 };
2361
2362 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2363         .name           = "slimbus1",
2364         .class          = &omap44xx_slimbus_hwmod_class,
2365         .clkdm_name     = "abe_clkdm",
2366         .prcm = {
2367                 .omap4 = {
2368                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2369                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2370                         .modulemode   = MODULEMODE_SWCTRL,
2371                 },
2372         },
2373         .opt_clks       = slimbus1_opt_clks,
2374         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2375 };
2376
2377 /* slimbus2 */
2378 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2379         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2380         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2381         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2382 };
2383
2384 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2385         .name           = "slimbus2",
2386         .class          = &omap44xx_slimbus_hwmod_class,
2387         .clkdm_name     = "l4_per_clkdm",
2388         .prcm = {
2389                 .omap4 = {
2390                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2391                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2392                         .modulemode   = MODULEMODE_SWCTRL,
2393                 },
2394         },
2395         .opt_clks       = slimbus2_opt_clks,
2396         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
2397 };
2398
2399 /*
2400  * 'smartreflex' class
2401  * smartreflex module (monitor silicon performance and outputs a measure of
2402  * performance error)
2403  */
2404
2405 /* The IP is not compliant to type1 / type2 scheme */
2406 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2407         .sidle_shift    = 24,
2408         .enwkup_shift   = 26,
2409 };
2410
2411 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2412         .sysc_offs      = 0x0038,
2413         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2414         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2415                            SIDLE_SMART_WKUP),
2416         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2417 };
2418
2419 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2420         .name   = "smartreflex",
2421         .sysc   = &omap44xx_smartreflex_sysc,
2422         .rev    = 2,
2423 };
2424
2425 /* smartreflex_core */
2426 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2427         .sensor_voltdm_name   = "core",
2428 };
2429
2430 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2431         .name           = "smartreflex_core",
2432         .class          = &omap44xx_smartreflex_hwmod_class,
2433         .clkdm_name     = "l4_ao_clkdm",
2434
2435         .main_clk       = "smartreflex_core_fck",
2436         .prcm = {
2437                 .omap4 = {
2438                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2439                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2440                         .modulemode   = MODULEMODE_SWCTRL,
2441                 },
2442         },
2443         .dev_attr       = &smartreflex_core_dev_attr,
2444 };
2445
2446 /* smartreflex_iva */
2447 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2448         .sensor_voltdm_name     = "iva",
2449 };
2450
2451 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2452         .name           = "smartreflex_iva",
2453         .class          = &omap44xx_smartreflex_hwmod_class,
2454         .clkdm_name     = "l4_ao_clkdm",
2455         .main_clk       = "smartreflex_iva_fck",
2456         .prcm = {
2457                 .omap4 = {
2458                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2459                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2460                         .modulemode   = MODULEMODE_SWCTRL,
2461                 },
2462         },
2463         .dev_attr       = &smartreflex_iva_dev_attr,
2464 };
2465
2466 /* smartreflex_mpu */
2467 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2468         .sensor_voltdm_name     = "mpu",
2469 };
2470
2471 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
2472         .name           = "smartreflex_mpu",
2473         .class          = &omap44xx_smartreflex_hwmod_class,
2474         .clkdm_name     = "l4_ao_clkdm",
2475         .main_clk       = "smartreflex_mpu_fck",
2476         .prcm = {
2477                 .omap4 = {
2478                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
2479                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
2480                         .modulemode   = MODULEMODE_SWCTRL,
2481                 },
2482         },
2483         .dev_attr       = &smartreflex_mpu_dev_attr,
2484 };
2485
2486 /*
2487  * 'spinlock' class
2488  * spinlock provides hardware assistance for synchronizing the processes
2489  * running on multiple processors
2490  */
2491
2492 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
2493         .rev_offs       = 0x0000,
2494         .sysc_offs      = 0x0010,
2495         .syss_offs      = 0x0014,
2496         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2497                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2498                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2499         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2500         .sysc_fields    = &omap_hwmod_sysc_type1,
2501 };
2502
2503 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
2504         .name   = "spinlock",
2505         .sysc   = &omap44xx_spinlock_sysc,
2506 };
2507
2508 /* spinlock */
2509 static struct omap_hwmod omap44xx_spinlock_hwmod = {
2510         .name           = "spinlock",
2511         .class          = &omap44xx_spinlock_hwmod_class,
2512         .clkdm_name     = "l4_cfg_clkdm",
2513         .prcm = {
2514                 .omap4 = {
2515                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
2516                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
2517                 },
2518         },
2519 };
2520
2521 /*
2522  * 'timer' class
2523  * general purpose timer module with accurate 1ms tick
2524  * This class contains several variants: ['timer_1ms', 'timer']
2525  */
2526
2527 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
2528         .rev_offs       = 0x0000,
2529         .sysc_offs      = 0x0010,
2530         .syss_offs      = 0x0014,
2531         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2532                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2533                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2534                            SYSS_HAS_RESET_STATUS),
2535         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2536         .sysc_fields    = &omap_hwmod_sysc_type1,
2537 };
2538
2539 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
2540         .name   = "timer",
2541         .sysc   = &omap44xx_timer_1ms_sysc,
2542 };
2543
2544 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
2545         .rev_offs       = 0x0000,
2546         .sysc_offs      = 0x0010,
2547         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2548                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2549         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2550                            SIDLE_SMART_WKUP),
2551         .sysc_fields    = &omap_hwmod_sysc_type2,
2552 };
2553
2554 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
2555         .name   = "timer",
2556         .sysc   = &omap44xx_timer_sysc,
2557 };
2558
2559 /* always-on timers dev attribute */
2560 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
2561         .timer_capability       = OMAP_TIMER_ALWON,
2562 };
2563
2564 /* pwm timers dev attribute */
2565 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
2566         .timer_capability       = OMAP_TIMER_HAS_PWM,
2567 };
2568
2569 /* timers with DSP interrupt dev attribute */
2570 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
2571         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
2572 };
2573
2574 /* pwm timers with DSP interrupt dev attribute */
2575 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
2576         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
2577 };
2578
2579 /* timer1 */
2580 static struct omap_hwmod omap44xx_timer1_hwmod = {
2581         .name           = "timer1",
2582         .class          = &omap44xx_timer_1ms_hwmod_class,
2583         .clkdm_name     = "l4_wkup_clkdm",
2584         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2585         .main_clk       = "dmt1_clk_mux",
2586         .prcm = {
2587                 .omap4 = {
2588                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2589                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
2590                         .modulemode   = MODULEMODE_SWCTRL,
2591                 },
2592         },
2593         .dev_attr       = &capability_alwon_dev_attr,
2594 };
2595
2596 /* timer2 */
2597 static struct omap_hwmod omap44xx_timer2_hwmod = {
2598         .name           = "timer2",
2599         .class          = &omap44xx_timer_1ms_hwmod_class,
2600         .clkdm_name     = "l4_per_clkdm",
2601         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2602         .main_clk       = "cm2_dm2_mux",
2603         .prcm = {
2604                 .omap4 = {
2605                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
2606                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
2607                         .modulemode   = MODULEMODE_SWCTRL,
2608                 },
2609         },
2610 };
2611
2612 /* timer3 */
2613 static struct omap_hwmod omap44xx_timer3_hwmod = {
2614         .name           = "timer3",
2615         .class          = &omap44xx_timer_hwmod_class,
2616         .clkdm_name     = "l4_per_clkdm",
2617         .main_clk       = "cm2_dm3_mux",
2618         .prcm = {
2619                 .omap4 = {
2620                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
2621                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
2622                         .modulemode   = MODULEMODE_SWCTRL,
2623                 },
2624         },
2625 };
2626
2627 /* timer4 */
2628 static struct omap_hwmod omap44xx_timer4_hwmod = {
2629         .name           = "timer4",
2630         .class          = &omap44xx_timer_hwmod_class,
2631         .clkdm_name     = "l4_per_clkdm",
2632         .main_clk       = "cm2_dm4_mux",
2633         .prcm = {
2634                 .omap4 = {
2635                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
2636                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
2637                         .modulemode   = MODULEMODE_SWCTRL,
2638                 },
2639         },
2640 };
2641
2642 /* timer5 */
2643 static struct omap_hwmod omap44xx_timer5_hwmod = {
2644         .name           = "timer5",
2645         .class          = &omap44xx_timer_hwmod_class,
2646         .clkdm_name     = "abe_clkdm",
2647         .main_clk       = "timer5_sync_mux",
2648         .prcm = {
2649                 .omap4 = {
2650                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
2651                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
2652                         .modulemode   = MODULEMODE_SWCTRL,
2653                 },
2654         },
2655         .dev_attr       = &capability_dsp_dev_attr,
2656 };
2657
2658 /* timer6 */
2659 static struct omap_hwmod omap44xx_timer6_hwmod = {
2660         .name           = "timer6",
2661         .class          = &omap44xx_timer_hwmod_class,
2662         .clkdm_name     = "abe_clkdm",
2663         .main_clk       = "timer6_sync_mux",
2664         .prcm = {
2665                 .omap4 = {
2666                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
2667                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
2668                         .modulemode   = MODULEMODE_SWCTRL,
2669                 },
2670         },
2671         .dev_attr       = &capability_dsp_dev_attr,
2672 };
2673
2674 /* timer7 */
2675 static struct omap_hwmod omap44xx_timer7_hwmod = {
2676         .name           = "timer7",
2677         .class          = &omap44xx_timer_hwmod_class,
2678         .clkdm_name     = "abe_clkdm",
2679         .main_clk       = "timer7_sync_mux",
2680         .prcm = {
2681                 .omap4 = {
2682                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
2683                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
2684                         .modulemode   = MODULEMODE_SWCTRL,
2685                 },
2686         },
2687         .dev_attr       = &capability_dsp_dev_attr,
2688 };
2689
2690 /* timer8 */
2691 static struct omap_hwmod omap44xx_timer8_hwmod = {
2692         .name           = "timer8",
2693         .class          = &omap44xx_timer_hwmod_class,
2694         .clkdm_name     = "abe_clkdm",
2695         .main_clk       = "timer8_sync_mux",
2696         .prcm = {
2697                 .omap4 = {
2698                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
2699                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
2700                         .modulemode   = MODULEMODE_SWCTRL,
2701                 },
2702         },
2703         .dev_attr       = &capability_dsp_pwm_dev_attr,
2704 };
2705
2706 /* timer9 */
2707 static struct omap_hwmod omap44xx_timer9_hwmod = {
2708         .name           = "timer9",
2709         .class          = &omap44xx_timer_hwmod_class,
2710         .clkdm_name     = "l4_per_clkdm",
2711         .main_clk       = "cm2_dm9_mux",
2712         .prcm = {
2713                 .omap4 = {
2714                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
2715                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
2716                         .modulemode   = MODULEMODE_SWCTRL,
2717                 },
2718         },
2719         .dev_attr       = &capability_pwm_dev_attr,
2720 };
2721
2722 /* timer10 */
2723 static struct omap_hwmod omap44xx_timer10_hwmod = {
2724         .name           = "timer10",
2725         .class          = &omap44xx_timer_1ms_hwmod_class,
2726         .clkdm_name     = "l4_per_clkdm",
2727         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2728         .main_clk       = "cm2_dm10_mux",
2729         .prcm = {
2730                 .omap4 = {
2731                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
2732                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
2733                         .modulemode   = MODULEMODE_SWCTRL,
2734                 },
2735         },
2736         .dev_attr       = &capability_pwm_dev_attr,
2737 };
2738
2739 /* timer11 */
2740 static struct omap_hwmod omap44xx_timer11_hwmod = {
2741         .name           = "timer11",
2742         .class          = &omap44xx_timer_hwmod_class,
2743         .clkdm_name     = "l4_per_clkdm",
2744         .main_clk       = "cm2_dm11_mux",
2745         .prcm = {
2746                 .omap4 = {
2747                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
2748                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
2749                         .modulemode   = MODULEMODE_SWCTRL,
2750                 },
2751         },
2752         .dev_attr       = &capability_pwm_dev_attr,
2753 };
2754
2755 /*
2756  * 'uart' class
2757  * universal asynchronous receiver/transmitter (uart)
2758  */
2759
2760 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
2761         .rev_offs       = 0x0050,
2762         .sysc_offs      = 0x0054,
2763         .syss_offs      = 0x0058,
2764         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2765                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2766                            SYSS_HAS_RESET_STATUS),
2767         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2768                            SIDLE_SMART_WKUP),
2769         .sysc_fields    = &omap_hwmod_sysc_type1,
2770 };
2771
2772 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
2773         .name   = "uart",
2774         .sysc   = &omap44xx_uart_sysc,
2775 };
2776
2777 /* uart1 */
2778 static struct omap_hwmod omap44xx_uart1_hwmod = {
2779         .name           = "uart1",
2780         .class          = &omap44xx_uart_hwmod_class,
2781         .clkdm_name     = "l4_per_clkdm",
2782         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2783         .main_clk       = "func_48m_fclk",
2784         .prcm = {
2785                 .omap4 = {
2786                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
2787                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
2788                         .modulemode   = MODULEMODE_SWCTRL,
2789                 },
2790         },
2791 };
2792
2793 /* uart2 */
2794 static struct omap_hwmod omap44xx_uart2_hwmod = {
2795         .name           = "uart2",
2796         .class          = &omap44xx_uart_hwmod_class,
2797         .clkdm_name     = "l4_per_clkdm",
2798         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2799         .main_clk       = "func_48m_fclk",
2800         .prcm = {
2801                 .omap4 = {
2802                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
2803                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
2804                         .modulemode   = MODULEMODE_SWCTRL,
2805                 },
2806         },
2807 };
2808
2809 /* uart3 */
2810 static struct omap_hwmod omap44xx_uart3_hwmod = {
2811         .name           = "uart3",
2812         .class          = &omap44xx_uart_hwmod_class,
2813         .clkdm_name     = "l4_per_clkdm",
2814         .flags          = DEBUG_OMAP4UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
2815         .main_clk       = "func_48m_fclk",
2816         .prcm = {
2817                 .omap4 = {
2818                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
2819                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
2820                         .modulemode   = MODULEMODE_SWCTRL,
2821                 },
2822         },
2823 };
2824
2825 /* uart4 */
2826 static struct omap_hwmod omap44xx_uart4_hwmod = {
2827         .name           = "uart4",
2828         .class          = &omap44xx_uart_hwmod_class,
2829         .clkdm_name     = "l4_per_clkdm",
2830         .flags          = DEBUG_OMAP4UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
2831         .main_clk       = "func_48m_fclk",
2832         .prcm = {
2833                 .omap4 = {
2834                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
2835                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
2836                         .modulemode   = MODULEMODE_SWCTRL,
2837                 },
2838         },
2839 };
2840
2841 /*
2842  * 'usb_host_fs' class
2843  * full-speed usb host controller
2844  */
2845
2846 /* The IP is not compliant to type1 / type2 scheme */
2847 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
2848         .midle_shift    = 4,
2849         .sidle_shift    = 2,
2850         .srst_shift     = 1,
2851 };
2852
2853 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
2854         .rev_offs       = 0x0000,
2855         .sysc_offs      = 0x0210,
2856         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2857                            SYSC_HAS_SOFTRESET),
2858         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2859                            SIDLE_SMART_WKUP),
2860         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
2861 };
2862
2863 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
2864         .name   = "usb_host_fs",
2865         .sysc   = &omap44xx_usb_host_fs_sysc,
2866 };
2867
2868 /* usb_host_fs */
2869 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
2870         .name           = "usb_host_fs",
2871         .class          = &omap44xx_usb_host_fs_hwmod_class,
2872         .clkdm_name     = "l3_init_clkdm",
2873         .main_clk       = "usb_host_fs_fck",
2874         .prcm = {
2875                 .omap4 = {
2876                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
2877                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
2878                         .modulemode   = MODULEMODE_SWCTRL,
2879                 },
2880         },
2881 };
2882
2883 /*
2884  * 'usb_host_hs' class
2885  * high-speed multi-port usb host controller
2886  */
2887
2888 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
2889         .rev_offs       = 0x0000,
2890         .sysc_offs      = 0x0010,
2891         .syss_offs      = 0x0014,
2892         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2893                            SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS),
2894         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2895                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2896                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2897         .sysc_fields    = &omap_hwmod_sysc_type2,
2898 };
2899
2900 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
2901         .name   = "usb_host_hs",
2902         .sysc   = &omap44xx_usb_host_hs_sysc,
2903 };
2904
2905 /* usb_host_hs */
2906 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
2907         .name           = "usb_host_hs",
2908         .class          = &omap44xx_usb_host_hs_hwmod_class,
2909         .clkdm_name     = "l3_init_clkdm",
2910         .main_clk       = "usb_host_hs_fck",
2911         .prcm = {
2912                 .omap4 = {
2913                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
2914                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
2915                         .modulemode   = MODULEMODE_SWCTRL,
2916                 },
2917         },
2918
2919         /*
2920          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
2921          * id: i660
2922          *
2923          * Description:
2924          * In the following configuration :
2925          * - USBHOST module is set to smart-idle mode
2926          * - PRCM asserts idle_req to the USBHOST module ( This typically
2927          *   happens when the system is going to a low power mode : all ports
2928          *   have been suspended, the master part of the USBHOST module has
2929          *   entered the standby state, and SW has cut the functional clocks)
2930          * - an USBHOST interrupt occurs before the module is able to answer
2931          *   idle_ack, typically a remote wakeup IRQ.
2932          * Then the USB HOST module will enter a deadlock situation where it
2933          * is no more accessible nor functional.
2934          *
2935          * Workaround:
2936          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
2937          */
2938
2939         /*
2940          * Errata: USB host EHCI may stall when entering smart-standby mode
2941          * Id: i571
2942          *
2943          * Description:
2944          * When the USBHOST module is set to smart-standby mode, and when it is
2945          * ready to enter the standby state (i.e. all ports are suspended and
2946          * all attached devices are in suspend mode), then it can wrongly assert
2947          * the Mstandby signal too early while there are still some residual OCP
2948          * transactions ongoing. If this condition occurs, the internal state
2949          * machine may go to an undefined state and the USB link may be stuck
2950          * upon the next resume.
2951          *
2952          * Workaround:
2953          * Don't use smart standby; use only force standby,
2954          * hence HWMOD_SWSUP_MSTANDBY
2955          */
2956
2957         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2958 };
2959
2960 /*
2961  * 'usb_otg_hs' class
2962  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
2963  */
2964
2965 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
2966         .rev_offs       = 0x0400,
2967         .sysc_offs      = 0x0404,
2968         .syss_offs      = 0x0408,
2969         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2970                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2971                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2972         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2973                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2974                            MSTANDBY_SMART),
2975         .sysc_fields    = &omap_hwmod_sysc_type1,
2976 };
2977
2978 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
2979         .name   = "usb_otg_hs",
2980         .sysc   = &omap44xx_usb_otg_hs_sysc,
2981 };
2982
2983 /* usb_otg_hs */
2984 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
2985         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
2986 };
2987
2988 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
2989         .name           = "usb_otg_hs",
2990         .class          = &omap44xx_usb_otg_hs_hwmod_class,
2991         .clkdm_name     = "l3_init_clkdm",
2992         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2993         .main_clk       = "usb_otg_hs_ick",
2994         .prcm = {
2995                 .omap4 = {
2996                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
2997                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
2998                         .modulemode   = MODULEMODE_HWCTRL,
2999                 },
3000         },
3001         .opt_clks       = usb_otg_hs_opt_clks,
3002         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
3003 };
3004
3005 /*
3006  * 'usb_tll_hs' class
3007  * usb_tll_hs module is the adapter on the usb_host_hs ports
3008  */
3009
3010 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3011         .rev_offs       = 0x0000,
3012         .sysc_offs      = 0x0010,
3013         .syss_offs      = 0x0014,
3014         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3015                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3016                            SYSC_HAS_AUTOIDLE),
3017         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3018         .sysc_fields    = &omap_hwmod_sysc_type1,
3019 };
3020
3021 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3022         .name   = "usb_tll_hs",
3023         .sysc   = &omap44xx_usb_tll_hs_sysc,
3024 };
3025
3026 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3027         .name           = "usb_tll_hs",
3028         .class          = &omap44xx_usb_tll_hs_hwmod_class,
3029         .clkdm_name     = "l3_init_clkdm",
3030         .main_clk       = "usb_tll_hs_ick",
3031         .prcm = {
3032                 .omap4 = {
3033                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3034                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3035                         .modulemode   = MODULEMODE_HWCTRL,
3036                 },
3037         },
3038 };
3039
3040 /*
3041  * 'wd_timer' class
3042  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3043  * overflow condition
3044  */
3045
3046 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3047         .rev_offs       = 0x0000,
3048         .sysc_offs      = 0x0010,
3049         .syss_offs      = 0x0014,
3050         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3051                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3052         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3053                            SIDLE_SMART_WKUP),
3054         .sysc_fields    = &omap_hwmod_sysc_type1,
3055 };
3056
3057 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3058         .name           = "wd_timer",
3059         .sysc           = &omap44xx_wd_timer_sysc,
3060         .pre_shutdown   = &omap2_wd_timer_disable,
3061         .reset          = &omap2_wd_timer_reset,
3062 };
3063
3064 /* wd_timer2 */
3065 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3066         .name           = "wd_timer2",
3067         .class          = &omap44xx_wd_timer_hwmod_class,
3068         .clkdm_name     = "l4_wkup_clkdm",
3069         .main_clk       = "sys_32k_ck",
3070         .prcm = {
3071                 .omap4 = {
3072                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3073                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3074                         .modulemode   = MODULEMODE_SWCTRL,
3075                 },
3076         },
3077 };
3078
3079 /* wd_timer3 */
3080 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3081         .name           = "wd_timer3",
3082         .class          = &omap44xx_wd_timer_hwmod_class,
3083         .clkdm_name     = "abe_clkdm",
3084         .main_clk       = "sys_32k_ck",
3085         .prcm = {
3086                 .omap4 = {
3087                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3088                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3089                         .modulemode   = MODULEMODE_SWCTRL,
3090                 },
3091         },
3092 };
3093
3094
3095 /*
3096  * interfaces
3097  */
3098
3099 /* l3_main_1 -> dmm */
3100 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3101         .master         = &omap44xx_l3_main_1_hwmod,
3102         .slave          = &omap44xx_dmm_hwmod,
3103         .clk            = "l3_div_ck",
3104         .user           = OCP_USER_SDMA,
3105 };
3106
3107 /* mpu -> dmm */
3108 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3109         .master         = &omap44xx_mpu_hwmod,
3110         .slave          = &omap44xx_dmm_hwmod,
3111         .clk            = "l3_div_ck",
3112         .user           = OCP_USER_MPU,
3113 };
3114
3115 /* iva -> l3_instr */
3116 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3117         .master         = &omap44xx_iva_hwmod,
3118         .slave          = &omap44xx_l3_instr_hwmod,
3119         .clk            = "l3_div_ck",
3120         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3121 };
3122
3123 /* l3_main_3 -> l3_instr */
3124 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3125         .master         = &omap44xx_l3_main_3_hwmod,
3126         .slave          = &omap44xx_l3_instr_hwmod,
3127         .clk            = "l3_div_ck",
3128         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3129 };
3130
3131 /* ocp_wp_noc -> l3_instr */
3132 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3133         .master         = &omap44xx_ocp_wp_noc_hwmod,
3134         .slave          = &omap44xx_l3_instr_hwmod,
3135         .clk            = "l3_div_ck",
3136         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3137 };
3138
3139 /* dsp -> l3_main_1 */
3140 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3141         .master         = &omap44xx_dsp_hwmod,
3142         .slave          = &omap44xx_l3_main_1_hwmod,
3143         .clk            = "l3_div_ck",
3144         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3145 };
3146
3147 /* dss -> l3_main_1 */
3148 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3149         .master         = &omap44xx_dss_hwmod,
3150         .slave          = &omap44xx_l3_main_1_hwmod,
3151         .clk            = "l3_div_ck",
3152         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3153 };
3154
3155 /* l3_main_2 -> l3_main_1 */
3156 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3157         .master         = &omap44xx_l3_main_2_hwmod,
3158         .slave          = &omap44xx_l3_main_1_hwmod,
3159         .clk            = "l3_div_ck",
3160         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3161 };
3162
3163 /* l4_cfg -> l3_main_1 */
3164 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3165         .master         = &omap44xx_l4_cfg_hwmod,
3166         .slave          = &omap44xx_l3_main_1_hwmod,
3167         .clk            = "l4_div_ck",
3168         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3169 };
3170
3171 /* mmc1 -> l3_main_1 */
3172 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3173         .master         = &omap44xx_mmc1_hwmod,
3174         .slave          = &omap44xx_l3_main_1_hwmod,
3175         .clk            = "l3_div_ck",
3176         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3177 };
3178
3179 /* mmc2 -> l3_main_1 */
3180 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3181         .master         = &omap44xx_mmc2_hwmod,
3182         .slave          = &omap44xx_l3_main_1_hwmod,
3183         .clk            = "l3_div_ck",
3184         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3185 };
3186
3187 /* mpu -> l3_main_1 */
3188 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3189         .master         = &omap44xx_mpu_hwmod,
3190         .slave          = &omap44xx_l3_main_1_hwmod,
3191         .clk            = "l3_div_ck",
3192         .user           = OCP_USER_MPU,
3193 };
3194
3195 /* debugss -> l3_main_2 */
3196 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3197         .master         = &omap44xx_debugss_hwmod,
3198         .slave          = &omap44xx_l3_main_2_hwmod,
3199         .clk            = "dbgclk_mux_ck",
3200         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3201 };
3202
3203 /* dma_system -> l3_main_2 */
3204 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3205         .master         = &omap44xx_dma_system_hwmod,
3206         .slave          = &omap44xx_l3_main_2_hwmod,
3207         .clk            = "l3_div_ck",
3208         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3209 };
3210
3211 /* fdif -> l3_main_2 */
3212 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3213         .master         = &omap44xx_fdif_hwmod,
3214         .slave          = &omap44xx_l3_main_2_hwmod,
3215         .clk            = "l3_div_ck",
3216         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3217 };
3218
3219 /* gpu -> l3_main_2 */
3220 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
3221         .master         = &omap44xx_gpu_hwmod,
3222         .slave          = &omap44xx_l3_main_2_hwmod,
3223         .clk            = "l3_div_ck",
3224         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3225 };
3226
3227 /* hsi -> l3_main_2 */
3228 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
3229         .master         = &omap44xx_hsi_hwmod,
3230         .slave          = &omap44xx_l3_main_2_hwmod,
3231         .clk            = "l3_div_ck",
3232         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3233 };
3234
3235 /* ipu -> l3_main_2 */
3236 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
3237         .master         = &omap44xx_ipu_hwmod,
3238         .slave          = &omap44xx_l3_main_2_hwmod,
3239         .clk            = "l3_div_ck",
3240         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3241 };
3242
3243 /* iss -> l3_main_2 */
3244 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
3245         .master         = &omap44xx_iss_hwmod,
3246         .slave          = &omap44xx_l3_main_2_hwmod,
3247         .clk            = "l3_div_ck",
3248         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3249 };
3250
3251 /* iva -> l3_main_2 */
3252 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
3253         .master         = &omap44xx_iva_hwmod,
3254         .slave          = &omap44xx_l3_main_2_hwmod,
3255         .clk            = "l3_div_ck",
3256         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3257 };
3258
3259 /* l3_main_1 -> l3_main_2 */
3260 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
3261         .master         = &omap44xx_l3_main_1_hwmod,
3262         .slave          = &omap44xx_l3_main_2_hwmod,
3263         .clk            = "l3_div_ck",
3264         .user           = OCP_USER_MPU,
3265 };
3266
3267 /* l4_cfg -> l3_main_2 */
3268 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
3269         .master         = &omap44xx_l4_cfg_hwmod,
3270         .slave          = &omap44xx_l3_main_2_hwmod,
3271         .clk            = "l4_div_ck",
3272         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3273 };
3274
3275 /* usb_host_fs -> l3_main_2 */
3276 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
3277         .master         = &omap44xx_usb_host_fs_hwmod,
3278         .slave          = &omap44xx_l3_main_2_hwmod,
3279         .clk            = "l3_div_ck",
3280         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3281 };
3282
3283 /* usb_host_hs -> l3_main_2 */
3284 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
3285         .master         = &omap44xx_usb_host_hs_hwmod,
3286         .slave          = &omap44xx_l3_main_2_hwmod,
3287         .clk            = "l3_div_ck",
3288         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3289 };
3290
3291 /* usb_otg_hs -> l3_main_2 */
3292 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
3293         .master         = &omap44xx_usb_otg_hs_hwmod,
3294         .slave          = &omap44xx_l3_main_2_hwmod,
3295         .clk            = "l3_div_ck",
3296         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3297 };
3298
3299 /* l3_main_1 -> l3_main_3 */
3300 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
3301         .master         = &omap44xx_l3_main_1_hwmod,
3302         .slave          = &omap44xx_l3_main_3_hwmod,
3303         .clk            = "l3_div_ck",
3304         .user           = OCP_USER_MPU,
3305 };
3306
3307 /* l3_main_2 -> l3_main_3 */
3308 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
3309         .master         = &omap44xx_l3_main_2_hwmod,
3310         .slave          = &omap44xx_l3_main_3_hwmod,
3311         .clk            = "l3_div_ck",
3312         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3313 };
3314
3315 /* l4_cfg -> l3_main_3 */
3316 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
3317         .master         = &omap44xx_l4_cfg_hwmod,
3318         .slave          = &omap44xx_l3_main_3_hwmod,
3319         .clk            = "l4_div_ck",
3320         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3321 };
3322
3323 /* aess -> l4_abe */
3324 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
3325         .master         = &omap44xx_aess_hwmod,
3326         .slave          = &omap44xx_l4_abe_hwmod,
3327         .clk            = "ocp_abe_iclk",
3328         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3329 };
3330
3331 /* dsp -> l4_abe */
3332 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
3333         .master         = &omap44xx_dsp_hwmod,
3334         .slave          = &omap44xx_l4_abe_hwmod,
3335         .clk            = "ocp_abe_iclk",
3336         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3337 };
3338
3339 /* l3_main_1 -> l4_abe */
3340 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
3341         .master         = &omap44xx_l3_main_1_hwmod,
3342         .slave          = &omap44xx_l4_abe_hwmod,
3343         .clk            = "l3_div_ck",
3344         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3345 };
3346
3347 /* mpu -> l4_abe */
3348 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
3349         .master         = &omap44xx_mpu_hwmod,
3350         .slave          = &omap44xx_l4_abe_hwmod,
3351         .clk            = "ocp_abe_iclk",
3352         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3353 };
3354
3355 /* l3_main_1 -> l4_cfg */
3356 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
3357         .master         = &omap44xx_l3_main_1_hwmod,
3358         .slave          = &omap44xx_l4_cfg_hwmod,
3359         .clk            = "l3_div_ck",
3360         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3361 };
3362
3363 /* l3_main_2 -> l4_per */
3364 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
3365         .master         = &omap44xx_l3_main_2_hwmod,
3366         .slave          = &omap44xx_l4_per_hwmod,
3367         .clk            = "l3_div_ck",
3368         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3369 };
3370
3371 /* l4_cfg -> l4_wkup */
3372 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
3373         .master         = &omap44xx_l4_cfg_hwmod,
3374         .slave          = &omap44xx_l4_wkup_hwmod,
3375         .clk            = "l4_div_ck",
3376         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3377 };
3378
3379 /* mpu -> mpu_private */
3380 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
3381         .master         = &omap44xx_mpu_hwmod,
3382         .slave          = &omap44xx_mpu_private_hwmod,
3383         .clk            = "l3_div_ck",
3384         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3385 };
3386
3387 /* l4_cfg -> ocp_wp_noc */
3388 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
3389         .master         = &omap44xx_l4_cfg_hwmod,
3390         .slave          = &omap44xx_ocp_wp_noc_hwmod,
3391         .clk            = "l4_div_ck",
3392         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3393 };
3394
3395 /* l4_abe -> aess */
3396 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
3397         .master         = &omap44xx_l4_abe_hwmod,
3398         .slave          = &omap44xx_aess_hwmod,
3399         .clk            = "ocp_abe_iclk",
3400         .user           = OCP_USER_MPU,
3401 };
3402
3403 /* l4_abe -> aess (dma) */
3404 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
3405         .master         = &omap44xx_l4_abe_hwmod,
3406         .slave          = &omap44xx_aess_hwmod,
3407         .clk            = "ocp_abe_iclk",
3408         .user           = OCP_USER_SDMA,
3409 };
3410
3411 /* l3_main_2 -> c2c */
3412 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
3413         .master         = &omap44xx_l3_main_2_hwmod,
3414         .slave          = &omap44xx_c2c_hwmod,
3415         .clk            = "l3_div_ck",
3416         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3417 };
3418
3419 /* l4_wkup -> counter_32k */
3420 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
3421         .master         = &omap44xx_l4_wkup_hwmod,
3422         .slave          = &omap44xx_counter_32k_hwmod,
3423         .clk            = "l4_wkup_clk_mux_ck",
3424         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3425 };
3426
3427 /* l4_cfg -> ctrl_module_core */
3428 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
3429         .master         = &omap44xx_l4_cfg_hwmod,
3430         .slave          = &omap44xx_ctrl_module_core_hwmod,
3431         .clk            = "l4_div_ck",
3432         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3433 };
3434
3435 /* l4_cfg -> ctrl_module_pad_core */
3436 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
3437         .master         = &omap44xx_l4_cfg_hwmod,
3438         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
3439         .clk            = "l4_div_ck",
3440         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3441 };
3442
3443 /* l4_wkup -> ctrl_module_wkup */
3444 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
3445         .master         = &omap44xx_l4_wkup_hwmod,
3446         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
3447         .clk            = "l4_wkup_clk_mux_ck",
3448         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3449 };
3450
3451 /* l4_wkup -> ctrl_module_pad_wkup */
3452 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
3453         .master         = &omap44xx_l4_wkup_hwmod,
3454         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
3455         .clk            = "l4_wkup_clk_mux_ck",
3456         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3457 };
3458
3459 /* l3_instr -> debugss */
3460 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
3461         .master         = &omap44xx_l3_instr_hwmod,
3462         .slave          = &omap44xx_debugss_hwmod,
3463         .clk            = "l3_div_ck",
3464         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3465 };
3466
3467 /* l4_cfg -> dma_system */
3468 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
3469         .master         = &omap44xx_l4_cfg_hwmod,
3470         .slave          = &omap44xx_dma_system_hwmod,
3471         .clk            = "l4_div_ck",
3472         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3473 };
3474
3475 /* l4_abe -> dmic */
3476 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
3477         .master         = &omap44xx_l4_abe_hwmod,
3478         .slave          = &omap44xx_dmic_hwmod,
3479         .clk            = "ocp_abe_iclk",
3480         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3481 };
3482
3483 /* dsp -> iva */
3484 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
3485         .master         = &omap44xx_dsp_hwmod,
3486         .slave          = &omap44xx_iva_hwmod,
3487         .clk            = "dpll_iva_m5x2_ck",
3488         .user           = OCP_USER_DSP,
3489 };
3490
3491 /* dsp -> sl2if */
3492 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
3493         .master         = &omap44xx_dsp_hwmod,
3494         .slave          = &omap44xx_sl2if_hwmod,
3495         .clk            = "dpll_iva_m5x2_ck",
3496         .user           = OCP_USER_DSP,
3497 };
3498
3499 /* l4_cfg -> dsp */
3500 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
3501         .master         = &omap44xx_l4_cfg_hwmod,
3502         .slave          = &omap44xx_dsp_hwmod,
3503         .clk            = "l4_div_ck",
3504         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3505 };
3506
3507 /* l3_main_2 -> dss */
3508 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
3509         .master         = &omap44xx_l3_main_2_hwmod,
3510         .slave          = &omap44xx_dss_hwmod,
3511         .clk            = "l3_div_ck",
3512         .user           = OCP_USER_SDMA,
3513 };
3514
3515 /* l4_per -> dss */
3516 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
3517         .master         = &omap44xx_l4_per_hwmod,
3518         .slave          = &omap44xx_dss_hwmod,
3519         .clk            = "l4_div_ck",
3520         .user           = OCP_USER_MPU,
3521 };
3522
3523 /* l3_main_2 -> dss_dispc */
3524 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
3525         .master         = &omap44xx_l3_main_2_hwmod,
3526         .slave          = &omap44xx_dss_dispc_hwmod,
3527         .clk            = "l3_div_ck",
3528         .user           = OCP_USER_SDMA,
3529 };
3530
3531 /* l4_per -> dss_dispc */
3532 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
3533         .master         = &omap44xx_l4_per_hwmod,
3534         .slave          = &omap44xx_dss_dispc_hwmod,
3535         .clk            = "l4_div_ck",
3536         .user           = OCP_USER_MPU,
3537 };
3538
3539 /* l3_main_2 -> dss_dsi1 */
3540 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
3541         .master         = &omap44xx_l3_main_2_hwmod,
3542         .slave          = &omap44xx_dss_dsi1_hwmod,
3543         .clk            = "l3_div_ck",
3544         .user           = OCP_USER_SDMA,
3545 };
3546
3547 /* l4_per -> dss_dsi1 */
3548 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
3549         .master         = &omap44xx_l4_per_hwmod,
3550         .slave          = &omap44xx_dss_dsi1_hwmod,
3551         .clk            = "l4_div_ck",
3552         .user           = OCP_USER_MPU,
3553 };
3554
3555 /* l3_main_2 -> dss_dsi2 */
3556 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
3557         .master         = &omap44xx_l3_main_2_hwmod,
3558         .slave          = &omap44xx_dss_dsi2_hwmod,
3559         .clk            = "l3_div_ck",
3560         .user           = OCP_USER_SDMA,
3561 };
3562
3563 /* l4_per -> dss_dsi2 */
3564 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
3565         .master         = &omap44xx_l4_per_hwmod,
3566         .slave          = &omap44xx_dss_dsi2_hwmod,
3567         .clk            = "l4_div_ck",
3568         .user           = OCP_USER_MPU,
3569 };
3570
3571 /* l3_main_2 -> dss_hdmi */
3572 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
3573         .master         = &omap44xx_l3_main_2_hwmod,
3574         .slave          = &omap44xx_dss_hdmi_hwmod,
3575         .clk            = "l3_div_ck",
3576         .user           = OCP_USER_SDMA,
3577 };
3578
3579 /* l4_per -> dss_hdmi */
3580 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
3581         .master         = &omap44xx_l4_per_hwmod,
3582         .slave          = &omap44xx_dss_hdmi_hwmod,
3583         .clk            = "l4_div_ck",
3584         .user           = OCP_USER_MPU,
3585 };
3586
3587 /* l3_main_2 -> dss_rfbi */
3588 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
3589         .master         = &omap44xx_l3_main_2_hwmod,
3590         .slave          = &omap44xx_dss_rfbi_hwmod,
3591         .clk            = "l3_div_ck",
3592         .user           = OCP_USER_SDMA,
3593 };
3594
3595 /* l4_per -> dss_rfbi */
3596 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
3597         .master         = &omap44xx_l4_per_hwmod,
3598         .slave          = &omap44xx_dss_rfbi_hwmod,
3599         .clk            = "l4_div_ck",
3600         .user           = OCP_USER_MPU,
3601 };
3602
3603 /* l3_main_2 -> dss_venc */
3604 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
3605         .master         = &omap44xx_l3_main_2_hwmod,
3606         .slave          = &omap44xx_dss_venc_hwmod,
3607         .clk            = "l3_div_ck",
3608         .user           = OCP_USER_SDMA,
3609 };
3610
3611 /* l4_per -> dss_venc */
3612 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
3613         .master         = &omap44xx_l4_per_hwmod,
3614         .slave          = &omap44xx_dss_venc_hwmod,
3615         .clk            = "l4_div_ck",
3616         .user           = OCP_USER_MPU,
3617 };
3618
3619 /* l3_main_2 -> sham */
3620 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sha0 = {
3621         .master         = &omap44xx_l3_main_2_hwmod,
3622         .slave          = &omap44xx_sha0_hwmod,
3623         .clk            = "l3_div_ck",
3624         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3625 };
3626
3627 /* l4_per -> elm */
3628 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
3629         .master         = &omap44xx_l4_per_hwmod,
3630         .slave          = &omap44xx_elm_hwmod,
3631         .clk            = "l4_div_ck",
3632         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3633 };
3634
3635 /* l4_cfg -> fdif */
3636 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
3637         .master         = &omap44xx_l4_cfg_hwmod,
3638         .slave          = &omap44xx_fdif_hwmod,
3639         .clk            = "l4_div_ck",
3640         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3641 };
3642
3643 /* l4_wkup -> gpio1 */
3644 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
3645         .master         = &omap44xx_l4_wkup_hwmod,
3646         .slave          = &omap44xx_gpio1_hwmod,
3647         .clk            = "l4_wkup_clk_mux_ck",
3648         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3649 };
3650
3651 /* l4_per -> gpio2 */
3652 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
3653         .master         = &omap44xx_l4_per_hwmod,
3654         .slave          = &omap44xx_gpio2_hwmod,
3655         .clk            = "l4_div_ck",
3656         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3657 };
3658
3659 /* l4_per -> gpio3 */
3660 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
3661         .master         = &omap44xx_l4_per_hwmod,
3662         .slave          = &omap44xx_gpio3_hwmod,
3663         .clk            = "l4_div_ck",
3664         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3665 };
3666
3667 /* l4_per -> gpio4 */
3668 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
3669         .master         = &omap44xx_l4_per_hwmod,
3670         .slave          = &omap44xx_gpio4_hwmod,
3671         .clk            = "l4_div_ck",
3672         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3673 };
3674
3675 /* l4_per -> gpio5 */
3676 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
3677         .master         = &omap44xx_l4_per_hwmod,
3678         .slave          = &omap44xx_gpio5_hwmod,
3679         .clk            = "l4_div_ck",
3680         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3681 };
3682
3683 /* l4_per -> gpio6 */
3684 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
3685         .master         = &omap44xx_l4_per_hwmod,
3686         .slave          = &omap44xx_gpio6_hwmod,
3687         .clk            = "l4_div_ck",
3688         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3689 };
3690
3691 /* l3_main_2 -> gpmc */
3692 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
3693         .master         = &omap44xx_l3_main_2_hwmod,
3694         .slave          = &omap44xx_gpmc_hwmod,
3695         .clk            = "l3_div_ck",
3696         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3697 };
3698
3699 /* l3_main_2 -> gpu */
3700 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
3701         .master         = &omap44xx_l3_main_2_hwmod,
3702         .slave          = &omap44xx_gpu_hwmod,
3703         .clk            = "l3_div_ck",
3704         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3705 };
3706
3707 /* l4_per -> hdq1w */
3708 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
3709         .master         = &omap44xx_l4_per_hwmod,
3710         .slave          = &omap44xx_hdq1w_hwmod,
3711         .clk            = "l4_div_ck",
3712         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3713 };
3714
3715 /* l4_cfg -> hsi */
3716 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
3717         .master         = &omap44xx_l4_cfg_hwmod,
3718         .slave          = &omap44xx_hsi_hwmod,
3719         .clk            = "l4_div_ck",
3720         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3721 };
3722
3723 /* l4_per -> i2c1 */
3724 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
3725         .master         = &omap44xx_l4_per_hwmod,
3726         .slave          = &omap44xx_i2c1_hwmod,
3727         .clk            = "l4_div_ck",
3728         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3729 };
3730
3731 /* l4_per -> i2c2 */
3732 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
3733         .master         = &omap44xx_l4_per_hwmod,
3734         .slave          = &omap44xx_i2c2_hwmod,
3735         .clk            = "l4_div_ck",
3736         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3737 };
3738
3739 /* l4_per -> i2c3 */
3740 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
3741         .master         = &omap44xx_l4_per_hwmod,
3742         .slave          = &omap44xx_i2c3_hwmod,
3743         .clk            = "l4_div_ck",
3744         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3745 };
3746
3747 /* l4_per -> i2c4 */
3748 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
3749         .master         = &omap44xx_l4_per_hwmod,
3750         .slave          = &omap44xx_i2c4_hwmod,
3751         .clk            = "l4_div_ck",
3752         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3753 };
3754
3755 /* l3_main_2 -> ipu */
3756 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
3757         .master         = &omap44xx_l3_main_2_hwmod,
3758         .slave          = &omap44xx_ipu_hwmod,
3759         .clk            = "l3_div_ck",
3760         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3761 };
3762
3763 /* l3_main_2 -> iss */
3764 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
3765         .master         = &omap44xx_l3_main_2_hwmod,
3766         .slave          = &omap44xx_iss_hwmod,
3767         .clk            = "l3_div_ck",
3768         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3769 };
3770
3771 /* iva -> sl2if */
3772 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
3773         .master         = &omap44xx_iva_hwmod,
3774         .slave          = &omap44xx_sl2if_hwmod,
3775         .clk            = "dpll_iva_m5x2_ck",
3776         .user           = OCP_USER_IVA,
3777 };
3778
3779 /* l3_main_2 -> iva */
3780 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
3781         .master         = &omap44xx_l3_main_2_hwmod,
3782         .slave          = &omap44xx_iva_hwmod,
3783         .clk            = "l3_div_ck",
3784         .user           = OCP_USER_MPU,
3785 };
3786
3787 /* l4_wkup -> kbd */
3788 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
3789         .master         = &omap44xx_l4_wkup_hwmod,
3790         .slave          = &omap44xx_kbd_hwmod,
3791         .clk            = "l4_wkup_clk_mux_ck",
3792         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3793 };
3794
3795 /* l4_cfg -> mailbox */
3796 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
3797         .master         = &omap44xx_l4_cfg_hwmod,
3798         .slave          = &omap44xx_mailbox_hwmod,
3799         .clk            = "l4_div_ck",
3800         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3801 };
3802
3803 /* l4_abe -> mcasp */
3804 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
3805         .master         = &omap44xx_l4_abe_hwmod,
3806         .slave          = &omap44xx_mcasp_hwmod,
3807         .clk            = "ocp_abe_iclk",
3808         .user           = OCP_USER_MPU,
3809 };
3810
3811 /* l4_abe -> mcasp (dma) */
3812 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
3813         .master         = &omap44xx_l4_abe_hwmod,
3814         .slave          = &omap44xx_mcasp_hwmod,
3815         .clk            = "ocp_abe_iclk",
3816         .user           = OCP_USER_SDMA,
3817 };
3818
3819 /* l4_abe -> mcbsp1 */
3820 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
3821         .master         = &omap44xx_l4_abe_hwmod,
3822         .slave          = &omap44xx_mcbsp1_hwmod,
3823         .clk            = "ocp_abe_iclk",
3824         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3825 };
3826
3827 /* l4_abe -> mcbsp2 */
3828 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
3829         .master         = &omap44xx_l4_abe_hwmod,
3830         .slave          = &omap44xx_mcbsp2_hwmod,
3831         .clk            = "ocp_abe_iclk",
3832         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3833 };
3834
3835 /* l4_abe -> mcbsp3 */
3836 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
3837         .master         = &omap44xx_l4_abe_hwmod,
3838         .slave          = &omap44xx_mcbsp3_hwmod,
3839         .clk            = "ocp_abe_iclk",
3840         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3841 };
3842
3843 /* l4_per -> mcbsp4 */
3844 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3845         .master         = &omap44xx_l4_per_hwmod,
3846         .slave          = &omap44xx_mcbsp4_hwmod,
3847         .clk            = "l4_div_ck",
3848         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3849 };
3850
3851 /* l4_abe -> mcpdm */
3852 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3853         .master         = &omap44xx_l4_abe_hwmod,
3854         .slave          = &omap44xx_mcpdm_hwmod,
3855         .clk            = "ocp_abe_iclk",
3856         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3857 };
3858
3859 /* l4_per -> mcspi1 */
3860 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3861         .master         = &omap44xx_l4_per_hwmod,
3862         .slave          = &omap44xx_mcspi1_hwmod,
3863         .clk            = "l4_div_ck",
3864         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3865 };
3866
3867 /* l4_per -> mcspi2 */
3868 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3869         .master         = &omap44xx_l4_per_hwmod,
3870         .slave          = &omap44xx_mcspi2_hwmod,
3871         .clk            = "l4_div_ck",
3872         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3873 };
3874
3875 /* l4_per -> mcspi3 */
3876 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3877         .master         = &omap44xx_l4_per_hwmod,
3878         .slave          = &omap44xx_mcspi3_hwmod,
3879         .clk            = "l4_div_ck",
3880         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3881 };
3882
3883 /* l4_per -> mcspi4 */
3884 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3885         .master         = &omap44xx_l4_per_hwmod,
3886         .slave          = &omap44xx_mcspi4_hwmod,
3887         .clk            = "l4_div_ck",
3888         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3889 };
3890
3891 /* l4_per -> mmc1 */
3892 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3893         .master         = &omap44xx_l4_per_hwmod,
3894         .slave          = &omap44xx_mmc1_hwmod,
3895         .clk            = "l4_div_ck",
3896         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3897 };
3898
3899 /* l4_per -> mmc2 */
3900 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3901         .master         = &omap44xx_l4_per_hwmod,
3902         .slave          = &omap44xx_mmc2_hwmod,
3903         .clk            = "l4_div_ck",
3904         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3905 };
3906
3907 /* l4_per -> mmc3 */
3908 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3909         .master         = &omap44xx_l4_per_hwmod,
3910         .slave          = &omap44xx_mmc3_hwmod,
3911         .clk            = "l4_div_ck",
3912         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3913 };
3914
3915 /* l4_per -> mmc4 */
3916 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3917         .master         = &omap44xx_l4_per_hwmod,
3918         .slave          = &omap44xx_mmc4_hwmod,
3919         .clk            = "l4_div_ck",
3920         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3921 };
3922
3923 /* l4_per -> mmc5 */
3924 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3925         .master         = &omap44xx_l4_per_hwmod,
3926         .slave          = &omap44xx_mmc5_hwmod,
3927         .clk            = "l4_div_ck",
3928         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3929 };
3930
3931 /* l3_main_2 -> ocmc_ram */
3932 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
3933         .master         = &omap44xx_l3_main_2_hwmod,
3934         .slave          = &omap44xx_ocmc_ram_hwmod,
3935         .clk            = "l3_div_ck",
3936         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3937 };
3938
3939 /* l4_cfg -> ocp2scp_usb_phy */
3940 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
3941         .master         = &omap44xx_l4_cfg_hwmod,
3942         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
3943         .clk            = "l4_div_ck",
3944         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3945 };
3946
3947 /* mpu_private -> prcm_mpu */
3948 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
3949         .master         = &omap44xx_mpu_private_hwmod,
3950         .slave          = &omap44xx_prcm_mpu_hwmod,
3951         .clk            = "l3_div_ck",
3952         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3953 };
3954
3955 /* l4_wkup -> cm_core_aon */
3956 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
3957         .master         = &omap44xx_l4_wkup_hwmod,
3958         .slave          = &omap44xx_cm_core_aon_hwmod,
3959         .clk            = "l4_wkup_clk_mux_ck",
3960         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3961 };
3962
3963 /* l4_cfg -> cm_core */
3964 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
3965         .master         = &omap44xx_l4_cfg_hwmod,
3966         .slave          = &omap44xx_cm_core_hwmod,
3967         .clk            = "l4_div_ck",
3968         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3969 };
3970
3971 /* l4_wkup -> prm */
3972 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
3973         .master         = &omap44xx_l4_wkup_hwmod,
3974         .slave          = &omap44xx_prm_hwmod,
3975         .clk            = "l4_wkup_clk_mux_ck",
3976         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3977 };
3978
3979 /* l4_wkup -> scrm */
3980 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
3981         .master         = &omap44xx_l4_wkup_hwmod,
3982         .slave          = &omap44xx_scrm_hwmod,
3983         .clk            = "l4_wkup_clk_mux_ck",
3984         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3985 };
3986
3987 /* l3_main_2 -> sl2if */
3988 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
3989         .master         = &omap44xx_l3_main_2_hwmod,
3990         .slave          = &omap44xx_sl2if_hwmod,
3991         .clk            = "l3_div_ck",
3992         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3993 };
3994
3995 /* l4_abe -> slimbus1 */
3996 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
3997         .master         = &omap44xx_l4_abe_hwmod,
3998         .slave          = &omap44xx_slimbus1_hwmod,
3999         .clk            = "ocp_abe_iclk",
4000         .user           = OCP_USER_MPU,
4001 };
4002
4003 /* l4_abe -> slimbus1 (dma) */
4004 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
4005         .master         = &omap44xx_l4_abe_hwmod,
4006         .slave          = &omap44xx_slimbus1_hwmod,
4007         .clk            = "ocp_abe_iclk",
4008         .user           = OCP_USER_SDMA,
4009 };
4010
4011 /* l4_per -> slimbus2 */
4012 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
4013         .master         = &omap44xx_l4_per_hwmod,
4014         .slave          = &omap44xx_slimbus2_hwmod,
4015         .clk            = "l4_div_ck",
4016         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4017 };
4018
4019 /* l4_cfg -> smartreflex_core */
4020 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
4021         .master         = &omap44xx_l4_cfg_hwmod,
4022         .slave          = &omap44xx_smartreflex_core_hwmod,
4023         .clk            = "l4_div_ck",
4024         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4025 };
4026
4027 /* l4_cfg -> smartreflex_iva */
4028 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
4029         .master         = &omap44xx_l4_cfg_hwmod,
4030         .slave          = &omap44xx_smartreflex_iva_hwmod,
4031         .clk            = "l4_div_ck",
4032         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4033 };
4034
4035 /* l4_cfg -> smartreflex_mpu */
4036 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
4037         .master         = &omap44xx_l4_cfg_hwmod,
4038         .slave          = &omap44xx_smartreflex_mpu_hwmod,
4039         .clk            = "l4_div_ck",
4040         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4041 };
4042
4043 /* l4_cfg -> spinlock */
4044 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
4045         .master         = &omap44xx_l4_cfg_hwmod,
4046         .slave          = &omap44xx_spinlock_hwmod,
4047         .clk            = "l4_div_ck",
4048         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4049 };
4050
4051 /* l4_wkup -> timer1 */
4052 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4053         .master         = &omap44xx_l4_wkup_hwmod,
4054         .slave          = &omap44xx_timer1_hwmod,
4055         .clk            = "l4_wkup_clk_mux_ck",
4056         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4057 };
4058
4059 /* l4_per -> timer2 */
4060 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4061         .master         = &omap44xx_l4_per_hwmod,
4062         .slave          = &omap44xx_timer2_hwmod,
4063         .clk            = "l4_div_ck",
4064         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4065 };
4066
4067 /* l4_per -> timer3 */
4068 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4069         .master         = &omap44xx_l4_per_hwmod,
4070         .slave          = &omap44xx_timer3_hwmod,
4071         .clk            = "l4_div_ck",
4072         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4073 };
4074
4075 /* l4_per -> timer4 */
4076 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4077         .master         = &omap44xx_l4_per_hwmod,
4078         .slave          = &omap44xx_timer4_hwmod,
4079         .clk            = "l4_div_ck",
4080         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4081 };
4082
4083 /* l4_abe -> timer5 */
4084 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4085         .master         = &omap44xx_l4_abe_hwmod,
4086         .slave          = &omap44xx_timer5_hwmod,
4087         .clk            = "ocp_abe_iclk",
4088         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4089 };
4090
4091 /* l4_abe -> timer6 */
4092 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4093         .master         = &omap44xx_l4_abe_hwmod,
4094         .slave          = &omap44xx_timer6_hwmod,
4095         .clk            = "ocp_abe_iclk",
4096         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4097 };
4098
4099 /* l4_abe -> timer7 */
4100 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4101         .master         = &omap44xx_l4_abe_hwmod,
4102         .slave          = &omap44xx_timer7_hwmod,
4103         .clk            = "ocp_abe_iclk",
4104         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4105 };
4106
4107 /* l4_abe -> timer8 */
4108 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4109         .master         = &omap44xx_l4_abe_hwmod,
4110         .slave          = &omap44xx_timer8_hwmod,
4111         .clk            = "ocp_abe_iclk",
4112         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4113 };
4114
4115 /* l4_per -> timer9 */
4116 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4117         .master         = &omap44xx_l4_per_hwmod,
4118         .slave          = &omap44xx_timer9_hwmod,
4119         .clk            = "l4_div_ck",
4120         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4121 };
4122
4123 /* l4_per -> timer10 */
4124 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4125         .master         = &omap44xx_l4_per_hwmod,
4126         .slave          = &omap44xx_timer10_hwmod,
4127         .clk            = "l4_div_ck",
4128         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4129 };
4130
4131 /* l4_per -> timer11 */
4132 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4133         .master         = &omap44xx_l4_per_hwmod,
4134         .slave          = &omap44xx_timer11_hwmod,
4135         .clk            = "l4_div_ck",
4136         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4137 };
4138
4139 /* l4_per -> uart1 */
4140 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4141         .master         = &omap44xx_l4_per_hwmod,
4142         .slave          = &omap44xx_uart1_hwmod,
4143         .clk            = "l4_div_ck",
4144         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4145 };
4146
4147 /* l4_per -> uart2 */
4148 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4149         .master         = &omap44xx_l4_per_hwmod,
4150         .slave          = &omap44xx_uart2_hwmod,
4151         .clk            = "l4_div_ck",
4152         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4153 };
4154
4155 /* l4_per -> uart3 */
4156 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4157         .master         = &omap44xx_l4_per_hwmod,
4158         .slave          = &omap44xx_uart3_hwmod,
4159         .clk            = "l4_div_ck",
4160         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4161 };
4162
4163 /* l4_per -> uart4 */
4164 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
4165         .master         = &omap44xx_l4_per_hwmod,
4166         .slave          = &omap44xx_uart4_hwmod,
4167         .clk            = "l4_div_ck",
4168         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4169 };
4170
4171 /* l4_cfg -> usb_host_fs */
4172 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
4173         .master         = &omap44xx_l4_cfg_hwmod,
4174         .slave          = &omap44xx_usb_host_fs_hwmod,
4175         .clk            = "l4_div_ck",
4176         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4177 };
4178
4179 /* l4_cfg -> usb_host_hs */
4180 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
4181         .master         = &omap44xx_l4_cfg_hwmod,
4182         .slave          = &omap44xx_usb_host_hs_hwmod,
4183         .clk            = "l4_div_ck",
4184         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4185 };
4186
4187 /* l4_cfg -> usb_otg_hs */
4188 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4189         .master         = &omap44xx_l4_cfg_hwmod,
4190         .slave          = &omap44xx_usb_otg_hs_hwmod,
4191         .clk            = "l4_div_ck",
4192         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4193 };
4194
4195 /* l4_cfg -> usb_tll_hs */
4196 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
4197         .master         = &omap44xx_l4_cfg_hwmod,
4198         .slave          = &omap44xx_usb_tll_hs_hwmod,
4199         .clk            = "l4_div_ck",
4200         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4201 };
4202
4203 /* l4_wkup -> wd_timer2 */
4204 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
4205         .master         = &omap44xx_l4_wkup_hwmod,
4206         .slave          = &omap44xx_wd_timer2_hwmod,
4207         .clk            = "l4_wkup_clk_mux_ck",
4208         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4209 };
4210
4211 /* l4_abe -> wd_timer3 */
4212 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
4213         .master         = &omap44xx_l4_abe_hwmod,
4214         .slave          = &omap44xx_wd_timer3_hwmod,
4215         .clk            = "ocp_abe_iclk",
4216         .user           = OCP_USER_MPU,
4217 };
4218
4219 /* l4_abe -> wd_timer3 (dma) */
4220 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
4221         .master         = &omap44xx_l4_abe_hwmod,
4222         .slave          = &omap44xx_wd_timer3_hwmod,
4223         .clk            = "ocp_abe_iclk",
4224         .user           = OCP_USER_SDMA,
4225 };
4226
4227 /* mpu -> emif1 */
4228 static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
4229         .master         = &omap44xx_mpu_hwmod,
4230         .slave          = &omap44xx_emif1_hwmod,
4231         .clk            = "l3_div_ck",
4232         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4233 };
4234
4235 /* mpu -> emif2 */
4236 static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
4237         .master         = &omap44xx_mpu_hwmod,
4238         .slave          = &omap44xx_emif2_hwmod,
4239         .clk            = "l3_div_ck",
4240         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4241 };
4242
4243 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
4244         &omap44xx_l3_main_1__dmm,
4245         &omap44xx_mpu__dmm,
4246         &omap44xx_iva__l3_instr,
4247         &omap44xx_l3_main_3__l3_instr,
4248         &omap44xx_ocp_wp_noc__l3_instr,
4249         &omap44xx_dsp__l3_main_1,
4250         &omap44xx_dss__l3_main_1,
4251         &omap44xx_l3_main_2__l3_main_1,
4252         &omap44xx_l4_cfg__l3_main_1,
4253         &omap44xx_mmc1__l3_main_1,
4254         &omap44xx_mmc2__l3_main_1,
4255         &omap44xx_mpu__l3_main_1,
4256         &omap44xx_debugss__l3_main_2,
4257         &omap44xx_dma_system__l3_main_2,
4258         &omap44xx_fdif__l3_main_2,
4259         &omap44xx_gpu__l3_main_2,
4260         &omap44xx_hsi__l3_main_2,
4261         &omap44xx_ipu__l3_main_2,
4262         &omap44xx_iss__l3_main_2,
4263         &omap44xx_iva__l3_main_2,
4264         &omap44xx_l3_main_1__l3_main_2,
4265         &omap44xx_l4_cfg__l3_main_2,
4266         /* &omap44xx_usb_host_fs__l3_main_2, */
4267         &omap44xx_usb_host_hs__l3_main_2,
4268         &omap44xx_usb_otg_hs__l3_main_2,
4269         &omap44xx_l3_main_1__l3_main_3,
4270         &omap44xx_l3_main_2__l3_main_3,
4271         &omap44xx_l4_cfg__l3_main_3,
4272         &omap44xx_aess__l4_abe,
4273         &omap44xx_dsp__l4_abe,
4274         &omap44xx_l3_main_1__l4_abe,
4275         &omap44xx_mpu__l4_abe,
4276         &omap44xx_l3_main_1__l4_cfg,
4277         &omap44xx_l3_main_2__l4_per,
4278         &omap44xx_l4_cfg__l4_wkup,
4279         &omap44xx_mpu__mpu_private,
4280         &omap44xx_l4_cfg__ocp_wp_noc,
4281         &omap44xx_l4_abe__aess,
4282         &omap44xx_l4_abe__aess_dma,
4283         &omap44xx_l3_main_2__c2c,
4284         &omap44xx_l4_wkup__counter_32k,
4285         &omap44xx_l4_cfg__ctrl_module_core,
4286         &omap44xx_l4_cfg__ctrl_module_pad_core,
4287         &omap44xx_l4_wkup__ctrl_module_wkup,
4288         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
4289         &omap44xx_l3_instr__debugss,
4290         &omap44xx_l4_cfg__dma_system,
4291         &omap44xx_l4_abe__dmic,
4292         &omap44xx_dsp__iva,
4293         /* &omap44xx_dsp__sl2if, */
4294         &omap44xx_l4_cfg__dsp,
4295         &omap44xx_l3_main_2__dss,
4296         &omap44xx_l4_per__dss,
4297         &omap44xx_l3_main_2__dss_dispc,
4298         &omap44xx_l4_per__dss_dispc,
4299         &omap44xx_l3_main_2__dss_dsi1,
4300         &omap44xx_l4_per__dss_dsi1,
4301         &omap44xx_l3_main_2__dss_dsi2,
4302         &omap44xx_l4_per__dss_dsi2,
4303         &omap44xx_l3_main_2__dss_hdmi,
4304         &omap44xx_l4_per__dss_hdmi,
4305         &omap44xx_l3_main_2__dss_rfbi,
4306         &omap44xx_l4_per__dss_rfbi,
4307         &omap44xx_l3_main_2__dss_venc,
4308         &omap44xx_l4_per__dss_venc,
4309         &omap44xx_l4_per__elm,
4310         &omap44xx_l4_cfg__fdif,
4311         &omap44xx_l4_wkup__gpio1,
4312         &omap44xx_l4_per__gpio2,
4313         &omap44xx_l4_per__gpio3,
4314         &omap44xx_l4_per__gpio4,
4315         &omap44xx_l4_per__gpio5,
4316         &omap44xx_l4_per__gpio6,
4317         &omap44xx_l3_main_2__gpmc,
4318         &omap44xx_l3_main_2__gpu,
4319         &omap44xx_l4_per__hdq1w,
4320         &omap44xx_l4_cfg__hsi,
4321         &omap44xx_l4_per__i2c1,
4322         &omap44xx_l4_per__i2c2,
4323         &omap44xx_l4_per__i2c3,
4324         &omap44xx_l4_per__i2c4,
4325         &omap44xx_l3_main_2__ipu,
4326         &omap44xx_l3_main_2__iss,
4327         /* &omap44xx_iva__sl2if, */
4328         &omap44xx_l3_main_2__iva,
4329         &omap44xx_l4_wkup__kbd,
4330         &omap44xx_l4_cfg__mailbox,
4331         &omap44xx_l4_abe__mcasp,
4332         &omap44xx_l4_abe__mcasp_dma,
4333         &omap44xx_l4_abe__mcbsp1,
4334         &omap44xx_l4_abe__mcbsp2,
4335         &omap44xx_l4_abe__mcbsp3,
4336         &omap44xx_l4_per__mcbsp4,
4337         &omap44xx_l4_abe__mcpdm,
4338         &omap44xx_l4_per__mcspi1,
4339         &omap44xx_l4_per__mcspi2,
4340         &omap44xx_l4_per__mcspi3,
4341         &omap44xx_l4_per__mcspi4,
4342         &omap44xx_l4_per__mmc1,
4343         &omap44xx_l4_per__mmc2,
4344         &omap44xx_l4_per__mmc3,
4345         &omap44xx_l4_per__mmc4,
4346         &omap44xx_l4_per__mmc5,
4347         &omap44xx_l3_main_2__mmu_ipu,
4348         &omap44xx_l4_cfg__mmu_dsp,
4349         &omap44xx_l3_main_2__ocmc_ram,
4350         &omap44xx_l4_cfg__ocp2scp_usb_phy,
4351         &omap44xx_mpu_private__prcm_mpu,
4352         &omap44xx_l4_wkup__cm_core_aon,
4353         &omap44xx_l4_cfg__cm_core,
4354         &omap44xx_l4_wkup__prm,
4355         &omap44xx_l4_wkup__scrm,
4356         /* &omap44xx_l3_main_2__sl2if, */
4357         &omap44xx_l4_abe__slimbus1,
4358         &omap44xx_l4_abe__slimbus1_dma,
4359         &omap44xx_l4_per__slimbus2,
4360         &omap44xx_l4_cfg__smartreflex_core,
4361         &omap44xx_l4_cfg__smartreflex_iva,
4362         &omap44xx_l4_cfg__smartreflex_mpu,
4363         &omap44xx_l4_cfg__spinlock,
4364         &omap44xx_l4_wkup__timer1,
4365         &omap44xx_l4_per__timer2,
4366         &omap44xx_l4_per__timer3,
4367         &omap44xx_l4_per__timer4,
4368         &omap44xx_l4_abe__timer5,
4369         &omap44xx_l4_abe__timer6,
4370         &omap44xx_l4_abe__timer7,
4371         &omap44xx_l4_abe__timer8,
4372         &omap44xx_l4_per__timer9,
4373         &omap44xx_l4_per__timer10,
4374         &omap44xx_l4_per__timer11,
4375         &omap44xx_l4_per__uart1,
4376         &omap44xx_l4_per__uart2,
4377         &omap44xx_l4_per__uart3,
4378         &omap44xx_l4_per__uart4,
4379         /* &omap44xx_l4_cfg__usb_host_fs, */
4380         &omap44xx_l4_cfg__usb_host_hs,
4381         &omap44xx_l4_cfg__usb_otg_hs,
4382         &omap44xx_l4_cfg__usb_tll_hs,
4383         &omap44xx_l4_wkup__wd_timer2,
4384         &omap44xx_l4_abe__wd_timer3,
4385         &omap44xx_l4_abe__wd_timer3_dma,
4386         &omap44xx_mpu__emif1,
4387         &omap44xx_mpu__emif2,
4388         &omap44xx_l3_main_2__aes1,
4389         &omap44xx_l3_main_2__aes2,
4390         &omap44xx_l3_main_2__des,
4391         &omap44xx_l3_main_2__sha0,
4392         NULL,
4393 };
4394
4395 int __init omap44xx_hwmod_init(void)
4396 {
4397         omap_hwmod_init();
4398         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
4399 }
4400