2 * Hardware modules present on the OMAP44xx chips
4 * Copyright (C) 2009-2012 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 * Note that this file is currently not in sync with autogeneration scripts.
16 * The above note to be removed, once it is synced up.
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
24 #include <linux/platform_data/gpio-omap.h>
25 #include <linux/platform_data/hsmmc-omap.h>
26 #include <linux/power/smartreflex.h>
27 #include <linux/i2c-omap.h>
29 #include <linux/omap-dma.h>
31 #include <linux/platform_data/spi-omap2-mcspi.h>
32 #include <linux/platform_data/asoc-ti-mcbsp.h>
33 #include <plat/dmtimer.h>
35 #include "omap_hwmod.h"
36 #include "omap_hwmod_common_data.h"
40 #include "prm-regbits-44xx.h"
44 /* Base offset for all OMAP4 interrupts external to MPUSS */
45 #define OMAP44XX_IRQ_GIC_START 32
47 /* Base offset for all OMAP4 dma requests */
48 #define OMAP44XX_DMA_REQ_START 1
58 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
63 static struct omap_hwmod omap44xx_dmm_hwmod = {
65 .class = &omap44xx_dmm_hwmod_class,
66 .clkdm_name = "l3_emif_clkdm",
69 .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
70 .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
77 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
79 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
84 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
86 .class = &omap44xx_l3_hwmod_class,
87 .clkdm_name = "l3_instr_clkdm",
90 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
91 .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
92 .modulemode = MODULEMODE_HWCTRL,
98 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
100 .class = &omap44xx_l3_hwmod_class,
101 .clkdm_name = "l3_1_clkdm",
104 .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
105 .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
111 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
113 .class = &omap44xx_l3_hwmod_class,
114 .clkdm_name = "l3_2_clkdm",
117 .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
118 .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
124 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
126 .class = &omap44xx_l3_hwmod_class,
127 .clkdm_name = "l3_instr_clkdm",
130 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
131 .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
132 .modulemode = MODULEMODE_HWCTRL,
139 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
141 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
146 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
148 .class = &omap44xx_l4_hwmod_class,
149 .clkdm_name = "abe_clkdm",
152 .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
153 .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
154 .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
155 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
161 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
163 .class = &omap44xx_l4_hwmod_class,
164 .clkdm_name = "l4_cfg_clkdm",
167 .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
168 .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
174 static struct omap_hwmod omap44xx_l4_per_hwmod = {
176 .class = &omap44xx_l4_hwmod_class,
177 .clkdm_name = "l4_per_clkdm",
180 .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
181 .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
187 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
189 .class = &omap44xx_l4_hwmod_class,
190 .clkdm_name = "l4_wkup_clkdm",
193 .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
194 .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
201 * instance(s): mpu_private
203 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
208 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
209 .name = "mpu_private",
210 .class = &omap44xx_mpu_bus_hwmod_class,
211 .clkdm_name = "mpuss_clkdm",
214 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
221 * instance(s): ocp_wp_noc
223 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
224 .name = "ocp_wp_noc",
228 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
229 .name = "ocp_wp_noc",
230 .class = &omap44xx_ocp_wp_noc_hwmod_class,
231 .clkdm_name = "l3_instr_clkdm",
234 .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
235 .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
236 .modulemode = MODULEMODE_HWCTRL,
242 * Modules omap_hwmod structures
244 * The following IPs are excluded for the moment because:
245 * - They do not need an explicit SW control using omap_hwmod API.
246 * - They still need to be validated with the driver
247 * properly adapted to omap_hwmod / omap_device
254 * audio engine sub system
257 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
260 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
261 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
262 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
263 MSTANDBY_SMART_WKUP),
264 .sysc_fields = &omap_hwmod_sysc_type2,
267 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
269 .sysc = &omap44xx_aess_sysc,
270 .enable_preprogram = omap_hwmod_aess_preprogram,
274 static struct omap_hwmod omap44xx_aess_hwmod = {
276 .class = &omap44xx_aess_hwmod_class,
277 .clkdm_name = "abe_clkdm",
278 .main_clk = "aess_fclk",
281 .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
282 .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
283 .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
284 .modulemode = MODULEMODE_SWCTRL,
291 * chip 2 chip interface used to plug the ape soc (omap) with an external modem
295 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
300 static struct omap_hwmod omap44xx_c2c_hwmod = {
302 .class = &omap44xx_c2c_hwmod_class,
303 .clkdm_name = "d2d_clkdm",
306 .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
307 .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
314 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
317 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
320 .sysc_flags = SYSC_HAS_SIDLEMODE,
321 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
322 .sysc_fields = &omap_hwmod_sysc_type1,
325 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
327 .sysc = &omap44xx_counter_sysc,
331 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
332 .name = "counter_32k",
333 .class = &omap44xx_counter_hwmod_class,
334 .clkdm_name = "l4_wkup_clkdm",
335 .flags = HWMOD_SWSUP_SIDLE,
336 .main_clk = "sys_32k_ck",
339 .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
340 .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
346 * 'ctrl_module' class
347 * attila core control module + core pad control module + wkup pad control
348 * module + attila wkup control module
351 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
354 .sysc_flags = SYSC_HAS_SIDLEMODE,
355 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
357 .sysc_fields = &omap_hwmod_sysc_type2,
360 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
361 .name = "ctrl_module",
362 .sysc = &omap44xx_ctrl_module_sysc,
365 /* ctrl_module_core */
366 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
367 .name = "ctrl_module_core",
368 .class = &omap44xx_ctrl_module_hwmod_class,
369 .clkdm_name = "l4_cfg_clkdm",
372 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
377 /* ctrl_module_pad_core */
378 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
379 .name = "ctrl_module_pad_core",
380 .class = &omap44xx_ctrl_module_hwmod_class,
381 .clkdm_name = "l4_cfg_clkdm",
384 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
389 /* ctrl_module_wkup */
390 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
391 .name = "ctrl_module_wkup",
392 .class = &omap44xx_ctrl_module_hwmod_class,
393 .clkdm_name = "l4_wkup_clkdm",
396 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
401 /* ctrl_module_pad_wkup */
402 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
403 .name = "ctrl_module_pad_wkup",
404 .class = &omap44xx_ctrl_module_hwmod_class,
405 .clkdm_name = "l4_wkup_clkdm",
408 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
415 * debug and emulation sub system
418 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
423 static struct omap_hwmod omap44xx_debugss_hwmod = {
425 .class = &omap44xx_debugss_hwmod_class,
426 .clkdm_name = "emu_sys_clkdm",
427 .main_clk = "trace_clk_div_ck",
430 .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
431 .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
438 * dma controller for data exchange between memory to memory (i.e. internal or
439 * external memory) and gp peripherals to memory or memory to gp peripherals
442 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
446 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
447 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
448 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
449 SYSS_HAS_RESET_STATUS),
450 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
451 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
452 .sysc_fields = &omap_hwmod_sysc_type1,
455 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
457 .sysc = &omap44xx_dma_sysc,
461 static struct omap_dma_dev_attr dma_dev_attr = {
462 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
463 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
468 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
469 { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
470 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
471 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
472 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
476 static struct omap_hwmod omap44xx_dma_system_hwmod = {
477 .name = "dma_system",
478 .class = &omap44xx_dma_hwmod_class,
479 .clkdm_name = "l3_dma_clkdm",
480 .mpu_irqs = omap44xx_dma_system_irqs,
481 .xlate_irq = omap4_xlate_irq,
482 .main_clk = "l3_div_ck",
485 .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
486 .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
489 .dev_attr = &dma_dev_attr,
494 * digital microphone controller
497 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
500 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
501 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
502 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
504 .sysc_fields = &omap_hwmod_sysc_type2,
507 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
509 .sysc = &omap44xx_dmic_sysc,
513 static struct omap_hwmod omap44xx_dmic_hwmod = {
515 .class = &omap44xx_dmic_hwmod_class,
516 .clkdm_name = "abe_clkdm",
517 .main_clk = "func_dmic_abe_gfclk",
520 .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
521 .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
522 .modulemode = MODULEMODE_SWCTRL,
532 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
537 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
538 { .name = "dsp", .rst_shift = 0 },
541 static struct omap_hwmod omap44xx_dsp_hwmod = {
543 .class = &omap44xx_dsp_hwmod_class,
544 .clkdm_name = "tesla_clkdm",
545 .rst_lines = omap44xx_dsp_resets,
546 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
547 .main_clk = "dpll_iva_m4x2_ck",
550 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
551 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
552 .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
553 .modulemode = MODULEMODE_HWCTRL,
563 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
566 .sysc_flags = SYSS_HAS_RESET_STATUS,
569 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
571 .sysc = &omap44xx_dss_sysc,
572 .reset = omap_dss_reset,
576 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
577 { .role = "sys_clk", .clk = "dss_sys_clk" },
578 { .role = "tv_clk", .clk = "dss_tv_clk" },
579 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
582 static struct omap_hwmod omap44xx_dss_hwmod = {
584 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
585 .class = &omap44xx_dss_hwmod_class,
586 .clkdm_name = "l3_dss_clkdm",
587 .main_clk = "dss_dss_clk",
590 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
591 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
592 .modulemode = MODULEMODE_SWCTRL,
595 .opt_clks = dss_opt_clks,
596 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
604 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
608 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
609 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
610 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
611 SYSS_HAS_RESET_STATUS),
612 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
613 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
614 .sysc_fields = &omap_hwmod_sysc_type1,
617 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
619 .sysc = &omap44xx_dispc_sysc,
623 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
624 { .irq = 25 + OMAP44XX_IRQ_GIC_START },
628 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
629 { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
633 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
635 .has_framedonetv_irq = 1
638 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
640 .class = &omap44xx_dispc_hwmod_class,
641 .clkdm_name = "l3_dss_clkdm",
642 .mpu_irqs = omap44xx_dss_dispc_irqs,
643 .xlate_irq = omap4_xlate_irq,
644 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
645 .main_clk = "dss_dss_clk",
648 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
649 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
652 .dev_attr = &omap44xx_dss_dispc_dev_attr,
653 .parent_hwmod = &omap44xx_dss_hwmod,
658 * display serial interface controller
661 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
665 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
666 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
667 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
668 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
669 .sysc_fields = &omap_hwmod_sysc_type1,
672 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
674 .sysc = &omap44xx_dsi_sysc,
678 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
679 { .irq = 53 + OMAP44XX_IRQ_GIC_START },
683 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
684 { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
688 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
689 { .role = "sys_clk", .clk = "dss_sys_clk" },
692 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
694 .class = &omap44xx_dsi_hwmod_class,
695 .clkdm_name = "l3_dss_clkdm",
696 .mpu_irqs = omap44xx_dss_dsi1_irqs,
697 .xlate_irq = omap4_xlate_irq,
698 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
699 .main_clk = "dss_dss_clk",
702 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
703 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
706 .opt_clks = dss_dsi1_opt_clks,
707 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
708 .parent_hwmod = &omap44xx_dss_hwmod,
712 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
713 { .irq = 84 + OMAP44XX_IRQ_GIC_START },
717 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
718 { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
722 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
723 { .role = "sys_clk", .clk = "dss_sys_clk" },
726 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
728 .class = &omap44xx_dsi_hwmod_class,
729 .clkdm_name = "l3_dss_clkdm",
730 .mpu_irqs = omap44xx_dss_dsi2_irqs,
731 .xlate_irq = omap4_xlate_irq,
732 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
733 .main_clk = "dss_dss_clk",
736 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
737 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
740 .opt_clks = dss_dsi2_opt_clks,
741 .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
742 .parent_hwmod = &omap44xx_dss_hwmod,
750 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
753 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
755 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
757 .sysc_fields = &omap_hwmod_sysc_type2,
760 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
762 .sysc = &omap44xx_hdmi_sysc,
766 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
767 { .irq = 101 + OMAP44XX_IRQ_GIC_START },
771 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
772 { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
776 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
777 { .role = "sys_clk", .clk = "dss_sys_clk" },
780 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
782 .class = &omap44xx_hdmi_hwmod_class,
783 .clkdm_name = "l3_dss_clkdm",
785 * HDMI audio requires to use no-idle mode. Hence,
786 * set idle mode by software.
788 .flags = HWMOD_SWSUP_SIDLE,
789 .mpu_irqs = omap44xx_dss_hdmi_irqs,
790 .xlate_irq = omap4_xlate_irq,
791 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
792 .main_clk = "dss_48mhz_clk",
795 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
796 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
799 .opt_clks = dss_hdmi_opt_clks,
800 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
801 .parent_hwmod = &omap44xx_dss_hwmod,
806 * remote frame buffer interface
809 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
813 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
814 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
815 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
816 .sysc_fields = &omap_hwmod_sysc_type1,
819 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
821 .sysc = &omap44xx_rfbi_sysc,
825 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
826 { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
830 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
831 { .role = "ick", .clk = "l3_div_ck" },
834 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
836 .class = &omap44xx_rfbi_hwmod_class,
837 .clkdm_name = "l3_dss_clkdm",
838 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
839 .main_clk = "dss_dss_clk",
842 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
843 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
846 .opt_clks = dss_rfbi_opt_clks,
847 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
848 .parent_hwmod = &omap44xx_dss_hwmod,
856 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
861 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
863 .class = &omap44xx_venc_hwmod_class,
864 .clkdm_name = "l3_dss_clkdm",
865 .main_clk = "dss_tv_clk",
868 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
869 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
872 .parent_hwmod = &omap44xx_dss_hwmod,
877 * bch error location module
880 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
884 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
885 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
886 SYSS_HAS_RESET_STATUS),
887 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
888 .sysc_fields = &omap_hwmod_sysc_type1,
891 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
893 .sysc = &omap44xx_elm_sysc,
897 static struct omap_hwmod omap44xx_elm_hwmod = {
899 .class = &omap44xx_elm_hwmod_class,
900 .clkdm_name = "l4_per_clkdm",
903 .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
904 .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
911 * external memory interface no1
914 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
918 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
920 .sysc = &omap44xx_emif_sysc,
924 static struct omap_hwmod omap44xx_emif1_hwmod = {
926 .class = &omap44xx_emif_hwmod_class,
927 .clkdm_name = "l3_emif_clkdm",
928 .flags = HWMOD_INIT_NO_IDLE,
929 .main_clk = "ddrphy_ck",
932 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
933 .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
934 .modulemode = MODULEMODE_HWCTRL,
940 static struct omap_hwmod omap44xx_emif2_hwmod = {
942 .class = &omap44xx_emif_hwmod_class,
943 .clkdm_name = "l3_emif_clkdm",
944 .flags = HWMOD_INIT_NO_IDLE,
945 .main_clk = "ddrphy_ck",
948 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
949 .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
950 .modulemode = MODULEMODE_HWCTRL,
957 * face detection hw accelerator module
960 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
964 * FDIF needs 100 OCP clk cycles delay after a softreset before
965 * accessing sysconfig again.
966 * The lowest frequency at the moment for L3 bus is 100 MHz, so
967 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
969 * TODO: Indicate errata when available.
972 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
973 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
974 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
975 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
976 .sysc_fields = &omap_hwmod_sysc_type2,
979 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
981 .sysc = &omap44xx_fdif_sysc,
985 static struct omap_hwmod omap44xx_fdif_hwmod = {
987 .class = &omap44xx_fdif_hwmod_class,
988 .clkdm_name = "iss_clkdm",
989 .main_clk = "fdif_fck",
992 .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
993 .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
994 .modulemode = MODULEMODE_SWCTRL,
1001 * general purpose io module
1004 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1006 .sysc_offs = 0x0010,
1007 .syss_offs = 0x0114,
1008 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1009 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1010 SYSS_HAS_RESET_STATUS),
1011 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1013 .sysc_fields = &omap_hwmod_sysc_type1,
1016 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1018 .sysc = &omap44xx_gpio_sysc,
1023 static struct omap_gpio_dev_attr gpio_dev_attr = {
1029 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1030 { .role = "dbclk", .clk = "gpio1_dbclk" },
1033 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1035 .class = &omap44xx_gpio_hwmod_class,
1036 .clkdm_name = "l4_wkup_clkdm",
1037 .main_clk = "l4_wkup_clk_mux_ck",
1040 .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1041 .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1042 .modulemode = MODULEMODE_HWCTRL,
1045 .opt_clks = gpio1_opt_clks,
1046 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1047 .dev_attr = &gpio_dev_attr,
1051 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1052 { .role = "dbclk", .clk = "gpio2_dbclk" },
1055 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1057 .class = &omap44xx_gpio_hwmod_class,
1058 .clkdm_name = "l4_per_clkdm",
1059 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1060 .main_clk = "l4_div_ck",
1063 .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1064 .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1065 .modulemode = MODULEMODE_HWCTRL,
1068 .opt_clks = gpio2_opt_clks,
1069 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1070 .dev_attr = &gpio_dev_attr,
1074 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1075 { .role = "dbclk", .clk = "gpio3_dbclk" },
1078 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1080 .class = &omap44xx_gpio_hwmod_class,
1081 .clkdm_name = "l4_per_clkdm",
1082 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1083 .main_clk = "l4_div_ck",
1086 .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1087 .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1088 .modulemode = MODULEMODE_HWCTRL,
1091 .opt_clks = gpio3_opt_clks,
1092 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1093 .dev_attr = &gpio_dev_attr,
1097 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1098 { .role = "dbclk", .clk = "gpio4_dbclk" },
1101 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1103 .class = &omap44xx_gpio_hwmod_class,
1104 .clkdm_name = "l4_per_clkdm",
1105 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1106 .main_clk = "l4_div_ck",
1109 .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1110 .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1111 .modulemode = MODULEMODE_HWCTRL,
1114 .opt_clks = gpio4_opt_clks,
1115 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1116 .dev_attr = &gpio_dev_attr,
1120 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1121 { .role = "dbclk", .clk = "gpio5_dbclk" },
1124 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1126 .class = &omap44xx_gpio_hwmod_class,
1127 .clkdm_name = "l4_per_clkdm",
1128 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1129 .main_clk = "l4_div_ck",
1132 .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1133 .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1134 .modulemode = MODULEMODE_HWCTRL,
1137 .opt_clks = gpio5_opt_clks,
1138 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1139 .dev_attr = &gpio_dev_attr,
1143 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1144 { .role = "dbclk", .clk = "gpio6_dbclk" },
1147 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1149 .class = &omap44xx_gpio_hwmod_class,
1150 .clkdm_name = "l4_per_clkdm",
1151 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1152 .main_clk = "l4_div_ck",
1155 .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1156 .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1157 .modulemode = MODULEMODE_HWCTRL,
1160 .opt_clks = gpio6_opt_clks,
1161 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1162 .dev_attr = &gpio_dev_attr,
1167 * general purpose memory controller
1170 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1172 .sysc_offs = 0x0010,
1173 .syss_offs = 0x0014,
1174 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1175 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1176 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1177 .sysc_fields = &omap_hwmod_sysc_type1,
1180 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1182 .sysc = &omap44xx_gpmc_sysc,
1186 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1188 .class = &omap44xx_gpmc_hwmod_class,
1189 .clkdm_name = "l3_2_clkdm",
1190 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
1191 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
1194 .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1195 .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1196 .modulemode = MODULEMODE_HWCTRL,
1203 * 2d/3d graphics accelerator
1206 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1207 .rev_offs = 0x1fc00,
1208 .sysc_offs = 0x1fc10,
1209 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1210 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1211 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1212 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1213 .sysc_fields = &omap_hwmod_sysc_type2,
1216 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1218 .sysc = &omap44xx_gpu_sysc,
1222 static struct omap_hwmod omap44xx_gpu_hwmod = {
1224 .class = &omap44xx_gpu_hwmod_class,
1225 .clkdm_name = "l3_gfx_clkdm",
1226 .main_clk = "sgx_clk_mux",
1229 .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1230 .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1231 .modulemode = MODULEMODE_SWCTRL,
1238 * hdq / 1-wire serial interface controller
1241 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1243 .sysc_offs = 0x0014,
1244 .syss_offs = 0x0018,
1245 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1246 SYSS_HAS_RESET_STATUS),
1247 .sysc_fields = &omap_hwmod_sysc_type1,
1250 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1252 .sysc = &omap44xx_hdq1w_sysc,
1256 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1258 .class = &omap44xx_hdq1w_hwmod_class,
1259 .clkdm_name = "l4_per_clkdm",
1260 .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */
1261 .main_clk = "func_12m_fclk",
1264 .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1265 .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1266 .modulemode = MODULEMODE_SWCTRL,
1273 * mipi high-speed synchronous serial interface (multichannel and full-duplex
1277 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1279 .sysc_offs = 0x0010,
1280 .syss_offs = 0x0014,
1281 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1282 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1283 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1284 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1285 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1286 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1287 .sysc_fields = &omap_hwmod_sysc_type1,
1290 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1292 .sysc = &omap44xx_hsi_sysc,
1296 static struct omap_hwmod omap44xx_hsi_hwmod = {
1298 .class = &omap44xx_hsi_hwmod_class,
1299 .clkdm_name = "l3_init_clkdm",
1300 .main_clk = "hsi_fck",
1303 .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1304 .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1305 .modulemode = MODULEMODE_HWCTRL,
1312 * multimaster high-speed i2c controller
1315 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1316 .sysc_offs = 0x0010,
1317 .syss_offs = 0x0090,
1318 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1319 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1320 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1321 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1323 .sysc_fields = &omap_hwmod_sysc_type1,
1326 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1328 .sysc = &omap44xx_i2c_sysc,
1329 .rev = OMAP_I2C_IP_VERSION_2,
1330 .reset = &omap_i2c_reset,
1333 static struct omap_i2c_dev_attr i2c_dev_attr = {
1334 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1338 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1340 .class = &omap44xx_i2c_hwmod_class,
1341 .clkdm_name = "l4_per_clkdm",
1342 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1343 .main_clk = "func_96m_fclk",
1346 .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1347 .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1348 .modulemode = MODULEMODE_SWCTRL,
1351 .dev_attr = &i2c_dev_attr,
1355 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1357 .class = &omap44xx_i2c_hwmod_class,
1358 .clkdm_name = "l4_per_clkdm",
1359 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1360 .main_clk = "func_96m_fclk",
1363 .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1364 .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1365 .modulemode = MODULEMODE_SWCTRL,
1368 .dev_attr = &i2c_dev_attr,
1372 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1374 .class = &omap44xx_i2c_hwmod_class,
1375 .clkdm_name = "l4_per_clkdm",
1376 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1377 .main_clk = "func_96m_fclk",
1380 .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1381 .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1382 .modulemode = MODULEMODE_SWCTRL,
1385 .dev_attr = &i2c_dev_attr,
1389 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1391 .class = &omap44xx_i2c_hwmod_class,
1392 .clkdm_name = "l4_per_clkdm",
1393 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1394 .main_clk = "func_96m_fclk",
1397 .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1398 .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1399 .modulemode = MODULEMODE_SWCTRL,
1402 .dev_attr = &i2c_dev_attr,
1407 * imaging processor unit
1410 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1415 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1416 { .name = "cpu0", .rst_shift = 0 },
1417 { .name = "cpu1", .rst_shift = 1 },
1420 static struct omap_hwmod omap44xx_ipu_hwmod = {
1422 .class = &omap44xx_ipu_hwmod_class,
1423 .clkdm_name = "ducati_clkdm",
1424 .rst_lines = omap44xx_ipu_resets,
1425 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
1426 .main_clk = "ducati_clk_mux_ck",
1429 .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1430 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1431 .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1432 .modulemode = MODULEMODE_HWCTRL,
1439 * external images sensor pixel data processor
1442 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1444 .sysc_offs = 0x0010,
1446 * ISS needs 100 OCP clk cycles delay after a softreset before
1447 * accessing sysconfig again.
1448 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1449 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1451 * TODO: Indicate errata when available.
1454 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1455 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1456 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1457 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1458 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1459 .sysc_fields = &omap_hwmod_sysc_type2,
1462 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1464 .sysc = &omap44xx_iss_sysc,
1468 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1469 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1472 static struct omap_hwmod omap44xx_iss_hwmod = {
1474 .class = &omap44xx_iss_hwmod_class,
1475 .clkdm_name = "iss_clkdm",
1476 .main_clk = "ducati_clk_mux_ck",
1479 .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1480 .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1481 .modulemode = MODULEMODE_SWCTRL,
1484 .opt_clks = iss_opt_clks,
1485 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
1490 * multi-standard video encoder/decoder hardware accelerator
1493 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1498 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1499 { .name = "seq0", .rst_shift = 0 },
1500 { .name = "seq1", .rst_shift = 1 },
1501 { .name = "logic", .rst_shift = 2 },
1504 static struct omap_hwmod omap44xx_iva_hwmod = {
1506 .class = &omap44xx_iva_hwmod_class,
1507 .clkdm_name = "ivahd_clkdm",
1508 .rst_lines = omap44xx_iva_resets,
1509 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
1510 .main_clk = "dpll_iva_m5x2_ck",
1513 .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1514 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1515 .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1516 .modulemode = MODULEMODE_HWCTRL,
1523 * keyboard controller
1526 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1528 .sysc_offs = 0x0010,
1529 .syss_offs = 0x0014,
1530 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1531 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1532 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1533 SYSS_HAS_RESET_STATUS),
1534 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1535 .sysc_fields = &omap_hwmod_sysc_type1,
1538 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1540 .sysc = &omap44xx_kbd_sysc,
1544 static struct omap_hwmod omap44xx_kbd_hwmod = {
1546 .class = &omap44xx_kbd_hwmod_class,
1547 .clkdm_name = "l4_wkup_clkdm",
1548 .main_clk = "sys_32k_ck",
1551 .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1552 .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1553 .modulemode = MODULEMODE_SWCTRL,
1560 * mailbox module allowing communication between the on-chip processors using a
1561 * queued mailbox-interrupt mechanism.
1564 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1566 .sysc_offs = 0x0010,
1567 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1568 SYSC_HAS_SOFTRESET),
1569 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1570 .sysc_fields = &omap_hwmod_sysc_type2,
1573 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1575 .sysc = &omap44xx_mailbox_sysc,
1579 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1581 .class = &omap44xx_mailbox_hwmod_class,
1582 .clkdm_name = "l4_cfg_clkdm",
1585 .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1586 .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1593 * multi-channel audio serial port controller
1596 /* The IP is not compliant to type1 / type2 scheme */
1597 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1601 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1602 .sysc_offs = 0x0004,
1603 .sysc_flags = SYSC_HAS_SIDLEMODE,
1604 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1606 .sysc_fields = &omap_hwmod_sysc_type_mcasp,
1609 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1611 .sysc = &omap44xx_mcasp_sysc,
1615 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1617 .class = &omap44xx_mcasp_hwmod_class,
1618 .clkdm_name = "abe_clkdm",
1619 .main_clk = "func_mcasp_abe_gfclk",
1622 .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1623 .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1624 .modulemode = MODULEMODE_SWCTRL,
1631 * multi channel buffered serial port controller
1634 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1635 .sysc_offs = 0x008c,
1636 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1637 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1638 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1639 .sysc_fields = &omap_hwmod_sysc_type1,
1642 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1644 .sysc = &omap44xx_mcbsp_sysc,
1645 .rev = MCBSP_CONFIG_TYPE4,
1649 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1650 { .role = "pad_fck", .clk = "pad_clks_ck" },
1651 { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1654 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1656 .class = &omap44xx_mcbsp_hwmod_class,
1657 .clkdm_name = "abe_clkdm",
1658 .main_clk = "func_mcbsp1_gfclk",
1661 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1662 .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1663 .modulemode = MODULEMODE_SWCTRL,
1666 .opt_clks = mcbsp1_opt_clks,
1667 .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
1671 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1672 { .role = "pad_fck", .clk = "pad_clks_ck" },
1673 { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1676 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
1678 .class = &omap44xx_mcbsp_hwmod_class,
1679 .clkdm_name = "abe_clkdm",
1680 .main_clk = "func_mcbsp2_gfclk",
1683 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
1684 .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1685 .modulemode = MODULEMODE_SWCTRL,
1688 .opt_clks = mcbsp2_opt_clks,
1689 .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
1693 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
1694 { .role = "pad_fck", .clk = "pad_clks_ck" },
1695 { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
1698 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
1700 .class = &omap44xx_mcbsp_hwmod_class,
1701 .clkdm_name = "abe_clkdm",
1702 .main_clk = "func_mcbsp3_gfclk",
1705 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
1706 .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
1707 .modulemode = MODULEMODE_SWCTRL,
1710 .opt_clks = mcbsp3_opt_clks,
1711 .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
1715 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
1716 { .role = "pad_fck", .clk = "pad_clks_ck" },
1717 { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
1720 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
1722 .class = &omap44xx_mcbsp_hwmod_class,
1723 .clkdm_name = "l4_per_clkdm",
1724 .main_clk = "per_mcbsp4_gfclk",
1727 .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
1728 .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
1729 .modulemode = MODULEMODE_SWCTRL,
1732 .opt_clks = mcbsp4_opt_clks,
1733 .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks),
1738 * multi channel pdm controller (proprietary interface with phoenix power
1742 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
1744 .sysc_offs = 0x0010,
1745 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1746 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1747 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1749 .sysc_fields = &omap_hwmod_sysc_type2,
1752 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
1754 .sysc = &omap44xx_mcpdm_sysc,
1758 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
1760 .class = &omap44xx_mcpdm_hwmod_class,
1761 .clkdm_name = "abe_clkdm",
1763 * It's suspected that the McPDM requires an off-chip main
1764 * functional clock, controlled via I2C. This IP block is
1765 * currently reset very early during boot, before I2C is
1766 * available, so it doesn't seem that we have any choice in
1767 * the kernel other than to avoid resetting it.
1769 * Also, McPDM needs to be configured to NO_IDLE mode when it
1770 * is in used otherwise vital clocks will be gated which
1771 * results 'slow motion' audio playback.
1773 .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
1774 .main_clk = "pad_clks_ck",
1777 .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
1778 .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
1779 .modulemode = MODULEMODE_SWCTRL,
1786 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1790 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
1792 .sysc_offs = 0x0010,
1793 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1794 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1795 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1797 .sysc_fields = &omap_hwmod_sysc_type2,
1800 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
1802 .sysc = &omap44xx_mcspi_sysc,
1803 .rev = OMAP4_MCSPI_REV,
1807 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
1808 { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
1809 { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
1810 { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
1811 { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
1812 { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
1813 { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
1814 { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
1815 { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
1819 /* mcspi1 dev_attr */
1820 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1821 .num_chipselect = 4,
1824 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
1826 .class = &omap44xx_mcspi_hwmod_class,
1827 .clkdm_name = "l4_per_clkdm",
1828 .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
1829 .main_clk = "func_48m_fclk",
1832 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1833 .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1834 .modulemode = MODULEMODE_SWCTRL,
1837 .dev_attr = &mcspi1_dev_attr,
1841 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
1842 { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
1843 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
1844 { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
1845 { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
1849 /* mcspi2 dev_attr */
1850 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1851 .num_chipselect = 2,
1854 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
1856 .class = &omap44xx_mcspi_hwmod_class,
1857 .clkdm_name = "l4_per_clkdm",
1858 .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
1859 .main_clk = "func_48m_fclk",
1862 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1863 .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1864 .modulemode = MODULEMODE_SWCTRL,
1867 .dev_attr = &mcspi2_dev_attr,
1871 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
1872 { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
1873 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
1874 { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
1875 { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
1879 /* mcspi3 dev_attr */
1880 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1881 .num_chipselect = 2,
1884 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
1886 .class = &omap44xx_mcspi_hwmod_class,
1887 .clkdm_name = "l4_per_clkdm",
1888 .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
1889 .main_clk = "func_48m_fclk",
1892 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1893 .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1894 .modulemode = MODULEMODE_SWCTRL,
1897 .dev_attr = &mcspi3_dev_attr,
1901 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
1902 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
1903 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
1907 /* mcspi4 dev_attr */
1908 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1909 .num_chipselect = 1,
1912 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
1914 .class = &omap44xx_mcspi_hwmod_class,
1915 .clkdm_name = "l4_per_clkdm",
1916 .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
1917 .main_clk = "func_48m_fclk",
1920 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1921 .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1922 .modulemode = MODULEMODE_SWCTRL,
1925 .dev_attr = &mcspi4_dev_attr,
1930 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
1933 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
1935 .sysc_offs = 0x0010,
1936 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1937 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1938 SYSC_HAS_SOFTRESET),
1939 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1940 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1941 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1942 .sysc_fields = &omap_hwmod_sysc_type2,
1945 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
1947 .sysc = &omap44xx_mmc_sysc,
1951 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
1952 { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
1953 { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
1958 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1959 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1962 static struct omap_hwmod omap44xx_mmc1_hwmod = {
1964 .class = &omap44xx_mmc_hwmod_class,
1965 .clkdm_name = "l3_init_clkdm",
1966 .sdma_reqs = omap44xx_mmc1_sdma_reqs,
1967 .main_clk = "hsmmc1_fclk",
1970 .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1971 .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1972 .modulemode = MODULEMODE_SWCTRL,
1975 .dev_attr = &mmc1_dev_attr,
1979 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
1980 { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
1981 { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
1985 static struct omap_hwmod omap44xx_mmc2_hwmod = {
1987 .class = &omap44xx_mmc_hwmod_class,
1988 .clkdm_name = "l3_init_clkdm",
1989 .sdma_reqs = omap44xx_mmc2_sdma_reqs,
1990 .main_clk = "hsmmc2_fclk",
1993 .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1994 .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1995 .modulemode = MODULEMODE_SWCTRL,
2001 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2002 { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2003 { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2007 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2009 .class = &omap44xx_mmc_hwmod_class,
2010 .clkdm_name = "l4_per_clkdm",
2011 .sdma_reqs = omap44xx_mmc3_sdma_reqs,
2012 .main_clk = "func_48m_fclk",
2015 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2016 .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2017 .modulemode = MODULEMODE_SWCTRL,
2023 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2024 { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2025 { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2029 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2031 .class = &omap44xx_mmc_hwmod_class,
2032 .clkdm_name = "l4_per_clkdm",
2033 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
2034 .main_clk = "func_48m_fclk",
2037 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2038 .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2039 .modulemode = MODULEMODE_SWCTRL,
2045 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2046 { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2047 { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2051 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2053 .class = &omap44xx_mmc_hwmod_class,
2054 .clkdm_name = "l4_per_clkdm",
2055 .sdma_reqs = omap44xx_mmc5_sdma_reqs,
2056 .main_clk = "func_48m_fclk",
2059 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2060 .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2061 .modulemode = MODULEMODE_SWCTRL,
2068 * The memory management unit performs virtual to physical address translation
2069 * for its requestors.
2072 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2076 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2077 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2078 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2079 .sysc_fields = &omap_hwmod_sysc_type1,
2082 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2089 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2090 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2091 { .name = "mmu_cache", .rst_shift = 2 },
2094 /* l3_main_2 -> mmu_ipu */
2095 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2096 .master = &omap44xx_l3_main_2_hwmod,
2097 .slave = &omap44xx_mmu_ipu_hwmod,
2099 .user = OCP_USER_MPU | OCP_USER_SDMA,
2102 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2104 .class = &omap44xx_mmu_hwmod_class,
2105 .clkdm_name = "ducati_clkdm",
2106 .rst_lines = omap44xx_mmu_ipu_resets,
2107 .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2108 .main_clk = "ducati_clk_mux_ck",
2111 .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2112 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2113 .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2114 .modulemode = MODULEMODE_HWCTRL,
2121 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2122 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2123 { .name = "mmu_cache", .rst_shift = 1 },
2127 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2128 .master = &omap44xx_l4_cfg_hwmod,
2129 .slave = &omap44xx_mmu_dsp_hwmod,
2131 .user = OCP_USER_MPU | OCP_USER_SDMA,
2134 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2136 .class = &omap44xx_mmu_hwmod_class,
2137 .clkdm_name = "tesla_clkdm",
2138 .rst_lines = omap44xx_mmu_dsp_resets,
2139 .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2140 .main_clk = "dpll_iva_m4x2_ck",
2143 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2144 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2145 .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2146 .modulemode = MODULEMODE_HWCTRL,
2156 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2161 static struct omap_hwmod omap44xx_mpu_hwmod = {
2163 .class = &omap44xx_mpu_hwmod_class,
2164 .clkdm_name = "mpuss_clkdm",
2165 .flags = HWMOD_INIT_NO_IDLE,
2166 .main_clk = "dpll_mpu_m2_ck",
2169 .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2170 .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2177 * top-level core on-chip ram
2180 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2185 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2187 .class = &omap44xx_ocmc_ram_hwmod_class,
2188 .clkdm_name = "l3_2_clkdm",
2191 .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2192 .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2199 * bridge to transform ocp interface protocol to scp (serial control port)
2203 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2205 .sysc_offs = 0x0010,
2206 .syss_offs = 0x0014,
2207 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2208 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2209 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2210 .sysc_fields = &omap_hwmod_sysc_type1,
2213 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2215 .sysc = &omap44xx_ocp2scp_sysc,
2218 /* ocp2scp_usb_phy */
2219 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2220 .name = "ocp2scp_usb_phy",
2221 .class = &omap44xx_ocp2scp_hwmod_class,
2222 .clkdm_name = "l3_init_clkdm",
2224 * ocp2scp_usb_phy_phy_48m is provided by the OMAP4 PRCM IP
2225 * block as an "optional clock," and normally should never be
2226 * specified as the main_clk for an OMAP IP block. However it
2227 * turns out that this clock is actually the main clock for
2228 * the ocp2scp_usb_phy IP block:
2229 * http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/119943.html
2230 * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems
2231 * to be the best workaround.
2233 .main_clk = "ocp2scp_usb_phy_phy_48m",
2236 .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2237 .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2238 .modulemode = MODULEMODE_HWCTRL,
2245 * power and reset manager (part of the prcm infrastructure) + clock manager 2
2246 * + clock manager 1 (in always on power domain) + local prm in mpu
2249 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2254 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2256 .class = &omap44xx_prcm_hwmod_class,
2257 .clkdm_name = "l4_wkup_clkdm",
2258 .flags = HWMOD_NO_IDLEST,
2261 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2267 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2268 .name = "cm_core_aon",
2269 .class = &omap44xx_prcm_hwmod_class,
2270 .flags = HWMOD_NO_IDLEST,
2273 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2279 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2281 .class = &omap44xx_prcm_hwmod_class,
2282 .flags = HWMOD_NO_IDLEST,
2285 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2291 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2292 { .name = "rst_global_warm_sw", .rst_shift = 0 },
2293 { .name = "rst_global_cold_sw", .rst_shift = 1 },
2296 static struct omap_hwmod omap44xx_prm_hwmod = {
2298 .class = &omap44xx_prcm_hwmod_class,
2299 .rst_lines = omap44xx_prm_resets,
2300 .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets),
2305 * system clock and reset manager
2308 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2313 static struct omap_hwmod omap44xx_scrm_hwmod = {
2315 .class = &omap44xx_scrm_hwmod_class,
2316 .clkdm_name = "l4_wkup_clkdm",
2319 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2326 * shared level 2 memory interface
2329 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2334 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2336 .class = &omap44xx_sl2if_hwmod_class,
2337 .clkdm_name = "ivahd_clkdm",
2340 .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2341 .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2342 .modulemode = MODULEMODE_HWCTRL,
2349 * bidirectional, multi-drop, multi-channel two-line serial interface between
2350 * the device and external components
2353 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2355 .sysc_offs = 0x0010,
2356 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2357 SYSC_HAS_SOFTRESET),
2358 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2360 .sysc_fields = &omap_hwmod_sysc_type2,
2363 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2365 .sysc = &omap44xx_slimbus_sysc,
2369 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2370 { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2371 { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2372 { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2373 { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2376 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2378 .class = &omap44xx_slimbus_hwmod_class,
2379 .clkdm_name = "abe_clkdm",
2382 .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2383 .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2384 .modulemode = MODULEMODE_SWCTRL,
2387 .opt_clks = slimbus1_opt_clks,
2388 .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks),
2392 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2393 { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2394 { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2395 { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2398 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2400 .class = &omap44xx_slimbus_hwmod_class,
2401 .clkdm_name = "l4_per_clkdm",
2404 .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2405 .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2406 .modulemode = MODULEMODE_SWCTRL,
2409 .opt_clks = slimbus2_opt_clks,
2410 .opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks),
2414 * 'smartreflex' class
2415 * smartreflex module (monitor silicon performance and outputs a measure of
2416 * performance error)
2419 /* The IP is not compliant to type1 / type2 scheme */
2420 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2425 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2426 .sysc_offs = 0x0038,
2427 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2428 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2430 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
2433 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2434 .name = "smartreflex",
2435 .sysc = &omap44xx_smartreflex_sysc,
2439 /* smartreflex_core */
2440 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2441 .sensor_voltdm_name = "core",
2444 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2445 .name = "smartreflex_core",
2446 .class = &omap44xx_smartreflex_hwmod_class,
2447 .clkdm_name = "l4_ao_clkdm",
2449 .main_clk = "smartreflex_core_fck",
2452 .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2453 .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2454 .modulemode = MODULEMODE_SWCTRL,
2457 .dev_attr = &smartreflex_core_dev_attr,
2460 /* smartreflex_iva */
2461 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2462 .sensor_voltdm_name = "iva",
2465 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2466 .name = "smartreflex_iva",
2467 .class = &omap44xx_smartreflex_hwmod_class,
2468 .clkdm_name = "l4_ao_clkdm",
2469 .main_clk = "smartreflex_iva_fck",
2472 .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2473 .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2474 .modulemode = MODULEMODE_SWCTRL,
2477 .dev_attr = &smartreflex_iva_dev_attr,
2480 /* smartreflex_mpu */
2481 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2482 .sensor_voltdm_name = "mpu",
2485 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
2486 .name = "smartreflex_mpu",
2487 .class = &omap44xx_smartreflex_hwmod_class,
2488 .clkdm_name = "l4_ao_clkdm",
2489 .main_clk = "smartreflex_mpu_fck",
2492 .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
2493 .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
2494 .modulemode = MODULEMODE_SWCTRL,
2497 .dev_attr = &smartreflex_mpu_dev_attr,
2502 * spinlock provides hardware assistance for synchronizing the processes
2503 * running on multiple processors
2506 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
2508 .sysc_offs = 0x0010,
2509 .syss_offs = 0x0014,
2510 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2511 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2512 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2513 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2514 .sysc_fields = &omap_hwmod_sysc_type1,
2517 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
2519 .sysc = &omap44xx_spinlock_sysc,
2523 static struct omap_hwmod omap44xx_spinlock_hwmod = {
2525 .class = &omap44xx_spinlock_hwmod_class,
2526 .clkdm_name = "l4_cfg_clkdm",
2529 .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
2530 .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
2537 * general purpose timer module with accurate 1ms tick
2538 * This class contains several variants: ['timer_1ms', 'timer']
2541 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
2543 .sysc_offs = 0x0010,
2544 .syss_offs = 0x0014,
2545 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2546 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2547 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2548 SYSS_HAS_RESET_STATUS),
2549 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2550 .sysc_fields = &omap_hwmod_sysc_type1,
2553 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
2555 .sysc = &omap44xx_timer_1ms_sysc,
2558 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
2560 .sysc_offs = 0x0010,
2561 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2562 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2563 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2565 .sysc_fields = &omap_hwmod_sysc_type2,
2568 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
2570 .sysc = &omap44xx_timer_sysc,
2573 /* always-on timers dev attribute */
2574 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
2575 .timer_capability = OMAP_TIMER_ALWON,
2578 /* pwm timers dev attribute */
2579 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
2580 .timer_capability = OMAP_TIMER_HAS_PWM,
2583 /* timers with DSP interrupt dev attribute */
2584 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
2585 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
2588 /* pwm timers with DSP interrupt dev attribute */
2589 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
2590 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
2594 static struct omap_hwmod omap44xx_timer1_hwmod = {
2596 .class = &omap44xx_timer_1ms_hwmod_class,
2597 .clkdm_name = "l4_wkup_clkdm",
2598 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2599 .main_clk = "dmt1_clk_mux",
2602 .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2603 .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
2604 .modulemode = MODULEMODE_SWCTRL,
2607 .dev_attr = &capability_alwon_dev_attr,
2611 static struct omap_hwmod omap44xx_timer2_hwmod = {
2613 .class = &omap44xx_timer_1ms_hwmod_class,
2614 .clkdm_name = "l4_per_clkdm",
2615 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2616 .main_clk = "cm2_dm2_mux",
2619 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
2620 .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
2621 .modulemode = MODULEMODE_SWCTRL,
2627 static struct omap_hwmod omap44xx_timer3_hwmod = {
2629 .class = &omap44xx_timer_hwmod_class,
2630 .clkdm_name = "l4_per_clkdm",
2631 .main_clk = "cm2_dm3_mux",
2634 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
2635 .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
2636 .modulemode = MODULEMODE_SWCTRL,
2642 static struct omap_hwmod omap44xx_timer4_hwmod = {
2644 .class = &omap44xx_timer_hwmod_class,
2645 .clkdm_name = "l4_per_clkdm",
2646 .main_clk = "cm2_dm4_mux",
2649 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
2650 .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
2651 .modulemode = MODULEMODE_SWCTRL,
2657 static struct omap_hwmod omap44xx_timer5_hwmod = {
2659 .class = &omap44xx_timer_hwmod_class,
2660 .clkdm_name = "abe_clkdm",
2661 .main_clk = "timer5_sync_mux",
2664 .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
2665 .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
2666 .modulemode = MODULEMODE_SWCTRL,
2669 .dev_attr = &capability_dsp_dev_attr,
2673 static struct omap_hwmod omap44xx_timer6_hwmod = {
2675 .class = &omap44xx_timer_hwmod_class,
2676 .clkdm_name = "abe_clkdm",
2677 .main_clk = "timer6_sync_mux",
2680 .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
2681 .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
2682 .modulemode = MODULEMODE_SWCTRL,
2685 .dev_attr = &capability_dsp_dev_attr,
2689 static struct omap_hwmod omap44xx_timer7_hwmod = {
2691 .class = &omap44xx_timer_hwmod_class,
2692 .clkdm_name = "abe_clkdm",
2693 .main_clk = "timer7_sync_mux",
2696 .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
2697 .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
2698 .modulemode = MODULEMODE_SWCTRL,
2701 .dev_attr = &capability_dsp_dev_attr,
2705 static struct omap_hwmod omap44xx_timer8_hwmod = {
2707 .class = &omap44xx_timer_hwmod_class,
2708 .clkdm_name = "abe_clkdm",
2709 .main_clk = "timer8_sync_mux",
2712 .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
2713 .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
2714 .modulemode = MODULEMODE_SWCTRL,
2717 .dev_attr = &capability_dsp_pwm_dev_attr,
2721 static struct omap_hwmod omap44xx_timer9_hwmod = {
2723 .class = &omap44xx_timer_hwmod_class,
2724 .clkdm_name = "l4_per_clkdm",
2725 .main_clk = "cm2_dm9_mux",
2728 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
2729 .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
2730 .modulemode = MODULEMODE_SWCTRL,
2733 .dev_attr = &capability_pwm_dev_attr,
2737 static struct omap_hwmod omap44xx_timer10_hwmod = {
2739 .class = &omap44xx_timer_1ms_hwmod_class,
2740 .clkdm_name = "l4_per_clkdm",
2741 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2742 .main_clk = "cm2_dm10_mux",
2745 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
2746 .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
2747 .modulemode = MODULEMODE_SWCTRL,
2750 .dev_attr = &capability_pwm_dev_attr,
2754 static struct omap_hwmod omap44xx_timer11_hwmod = {
2756 .class = &omap44xx_timer_hwmod_class,
2757 .clkdm_name = "l4_per_clkdm",
2758 .main_clk = "cm2_dm11_mux",
2761 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
2762 .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
2763 .modulemode = MODULEMODE_SWCTRL,
2766 .dev_attr = &capability_pwm_dev_attr,
2771 * universal asynchronous receiver/transmitter (uart)
2774 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
2776 .sysc_offs = 0x0054,
2777 .syss_offs = 0x0058,
2778 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2779 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2780 SYSS_HAS_RESET_STATUS),
2781 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2783 .sysc_fields = &omap_hwmod_sysc_type1,
2786 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
2788 .sysc = &omap44xx_uart_sysc,
2792 static struct omap_hwmod omap44xx_uart1_hwmod = {
2794 .class = &omap44xx_uart_hwmod_class,
2795 .clkdm_name = "l4_per_clkdm",
2796 .flags = HWMOD_SWSUP_SIDLE_ACT,
2797 .main_clk = "func_48m_fclk",
2800 .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
2801 .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
2802 .modulemode = MODULEMODE_SWCTRL,
2808 static struct omap_hwmod omap44xx_uart2_hwmod = {
2810 .class = &omap44xx_uart_hwmod_class,
2811 .clkdm_name = "l4_per_clkdm",
2812 .flags = HWMOD_SWSUP_SIDLE_ACT,
2813 .main_clk = "func_48m_fclk",
2816 .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
2817 .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
2818 .modulemode = MODULEMODE_SWCTRL,
2824 static struct omap_hwmod omap44xx_uart3_hwmod = {
2826 .class = &omap44xx_uart_hwmod_class,
2827 .clkdm_name = "l4_per_clkdm",
2828 .flags = DEBUG_OMAP4UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
2829 .main_clk = "func_48m_fclk",
2832 .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
2833 .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
2834 .modulemode = MODULEMODE_SWCTRL,
2840 static struct omap_hwmod omap44xx_uart4_hwmod = {
2842 .class = &omap44xx_uart_hwmod_class,
2843 .clkdm_name = "l4_per_clkdm",
2844 .flags = DEBUG_OMAP4UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
2845 .main_clk = "func_48m_fclk",
2848 .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
2849 .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
2850 .modulemode = MODULEMODE_SWCTRL,
2856 * 'usb_host_fs' class
2857 * full-speed usb host controller
2860 /* The IP is not compliant to type1 / type2 scheme */
2861 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
2867 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
2869 .sysc_offs = 0x0210,
2870 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2871 SYSC_HAS_SOFTRESET),
2872 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2874 .sysc_fields = &omap_hwmod_sysc_type_usb_host_fs,
2877 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
2878 .name = "usb_host_fs",
2879 .sysc = &omap44xx_usb_host_fs_sysc,
2883 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
2884 .name = "usb_host_fs",
2885 .class = &omap44xx_usb_host_fs_hwmod_class,
2886 .clkdm_name = "l3_init_clkdm",
2887 .main_clk = "usb_host_fs_fck",
2890 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
2891 .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
2892 .modulemode = MODULEMODE_SWCTRL,
2898 * 'usb_host_hs' class
2899 * high-speed multi-port usb host controller
2902 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
2904 .sysc_offs = 0x0010,
2905 .syss_offs = 0x0014,
2906 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2907 SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS),
2908 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2909 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2910 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2911 .sysc_fields = &omap_hwmod_sysc_type2,
2914 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
2915 .name = "usb_host_hs",
2916 .sysc = &omap44xx_usb_host_hs_sysc,
2920 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
2921 .name = "usb_host_hs",
2922 .class = &omap44xx_usb_host_hs_hwmod_class,
2923 .clkdm_name = "l3_init_clkdm",
2924 .main_clk = "usb_host_hs_fck",
2927 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
2928 .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
2929 .modulemode = MODULEMODE_SWCTRL,
2934 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
2938 * In the following configuration :
2939 * - USBHOST module is set to smart-idle mode
2940 * - PRCM asserts idle_req to the USBHOST module ( This typically
2941 * happens when the system is going to a low power mode : all ports
2942 * have been suspended, the master part of the USBHOST module has
2943 * entered the standby state, and SW has cut the functional clocks)
2944 * - an USBHOST interrupt occurs before the module is able to answer
2945 * idle_ack, typically a remote wakeup IRQ.
2946 * Then the USB HOST module will enter a deadlock situation where it
2947 * is no more accessible nor functional.
2950 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
2954 * Errata: USB host EHCI may stall when entering smart-standby mode
2958 * When the USBHOST module is set to smart-standby mode, and when it is
2959 * ready to enter the standby state (i.e. all ports are suspended and
2960 * all attached devices are in suspend mode), then it can wrongly assert
2961 * the Mstandby signal too early while there are still some residual OCP
2962 * transactions ongoing. If this condition occurs, the internal state
2963 * machine may go to an undefined state and the USB link may be stuck
2964 * upon the next resume.
2967 * Don't use smart standby; use only force standby,
2968 * hence HWMOD_SWSUP_MSTANDBY
2971 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2975 * 'usb_otg_hs' class
2976 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
2979 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
2981 .sysc_offs = 0x0404,
2982 .syss_offs = 0x0408,
2983 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2984 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2985 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2986 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2987 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2989 .sysc_fields = &omap_hwmod_sysc_type1,
2992 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
2993 .name = "usb_otg_hs",
2994 .sysc = &omap44xx_usb_otg_hs_sysc,
2998 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
2999 { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3002 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3003 .name = "usb_otg_hs",
3004 .class = &omap44xx_usb_otg_hs_hwmod_class,
3005 .clkdm_name = "l3_init_clkdm",
3006 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3007 .main_clk = "usb_otg_hs_ick",
3010 .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3011 .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3012 .modulemode = MODULEMODE_HWCTRL,
3015 .opt_clks = usb_otg_hs_opt_clks,
3016 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
3020 * 'usb_tll_hs' class
3021 * usb_tll_hs module is the adapter on the usb_host_hs ports
3024 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3026 .sysc_offs = 0x0010,
3027 .syss_offs = 0x0014,
3028 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3029 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3031 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3032 .sysc_fields = &omap_hwmod_sysc_type1,
3035 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3036 .name = "usb_tll_hs",
3037 .sysc = &omap44xx_usb_tll_hs_sysc,
3040 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3041 .name = "usb_tll_hs",
3042 .class = &omap44xx_usb_tll_hs_hwmod_class,
3043 .clkdm_name = "l3_init_clkdm",
3044 .main_clk = "usb_tll_hs_ick",
3047 .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3048 .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3049 .modulemode = MODULEMODE_HWCTRL,
3056 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3057 * overflow condition
3060 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3062 .sysc_offs = 0x0010,
3063 .syss_offs = 0x0014,
3064 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3065 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3066 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3068 .sysc_fields = &omap_hwmod_sysc_type1,
3071 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3073 .sysc = &omap44xx_wd_timer_sysc,
3074 .pre_shutdown = &omap2_wd_timer_disable,
3075 .reset = &omap2_wd_timer_reset,
3079 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3080 .name = "wd_timer2",
3081 .class = &omap44xx_wd_timer_hwmod_class,
3082 .clkdm_name = "l4_wkup_clkdm",
3083 .main_clk = "sys_32k_ck",
3086 .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3087 .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3088 .modulemode = MODULEMODE_SWCTRL,
3094 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3095 .name = "wd_timer3",
3096 .class = &omap44xx_wd_timer_hwmod_class,
3097 .clkdm_name = "abe_clkdm",
3098 .main_clk = "sys_32k_ck",
3101 .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3102 .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3103 .modulemode = MODULEMODE_SWCTRL,
3113 /* l3_main_1 -> dmm */
3114 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3115 .master = &omap44xx_l3_main_1_hwmod,
3116 .slave = &omap44xx_dmm_hwmod,
3118 .user = OCP_USER_SDMA,
3122 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3123 .master = &omap44xx_mpu_hwmod,
3124 .slave = &omap44xx_dmm_hwmod,
3126 .user = OCP_USER_MPU,
3129 /* iva -> l3_instr */
3130 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3131 .master = &omap44xx_iva_hwmod,
3132 .slave = &omap44xx_l3_instr_hwmod,
3134 .user = OCP_USER_MPU | OCP_USER_SDMA,
3137 /* l3_main_3 -> l3_instr */
3138 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3139 .master = &omap44xx_l3_main_3_hwmod,
3140 .slave = &omap44xx_l3_instr_hwmod,
3142 .user = OCP_USER_MPU | OCP_USER_SDMA,
3145 /* ocp_wp_noc -> l3_instr */
3146 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3147 .master = &omap44xx_ocp_wp_noc_hwmod,
3148 .slave = &omap44xx_l3_instr_hwmod,
3150 .user = OCP_USER_MPU | OCP_USER_SDMA,
3153 /* dsp -> l3_main_1 */
3154 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3155 .master = &omap44xx_dsp_hwmod,
3156 .slave = &omap44xx_l3_main_1_hwmod,
3158 .user = OCP_USER_MPU | OCP_USER_SDMA,
3161 /* dss -> l3_main_1 */
3162 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3163 .master = &omap44xx_dss_hwmod,
3164 .slave = &omap44xx_l3_main_1_hwmod,
3166 .user = OCP_USER_MPU | OCP_USER_SDMA,
3169 /* l3_main_2 -> l3_main_1 */
3170 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3171 .master = &omap44xx_l3_main_2_hwmod,
3172 .slave = &omap44xx_l3_main_1_hwmod,
3174 .user = OCP_USER_MPU | OCP_USER_SDMA,
3177 /* l4_cfg -> l3_main_1 */
3178 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3179 .master = &omap44xx_l4_cfg_hwmod,
3180 .slave = &omap44xx_l3_main_1_hwmod,
3182 .user = OCP_USER_MPU | OCP_USER_SDMA,
3185 /* mmc1 -> l3_main_1 */
3186 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3187 .master = &omap44xx_mmc1_hwmod,
3188 .slave = &omap44xx_l3_main_1_hwmod,
3190 .user = OCP_USER_MPU | OCP_USER_SDMA,
3193 /* mmc2 -> l3_main_1 */
3194 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3195 .master = &omap44xx_mmc2_hwmod,
3196 .slave = &omap44xx_l3_main_1_hwmod,
3198 .user = OCP_USER_MPU | OCP_USER_SDMA,
3201 /* mpu -> l3_main_1 */
3202 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3203 .master = &omap44xx_mpu_hwmod,
3204 .slave = &omap44xx_l3_main_1_hwmod,
3206 .user = OCP_USER_MPU,
3209 /* debugss -> l3_main_2 */
3210 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3211 .master = &omap44xx_debugss_hwmod,
3212 .slave = &omap44xx_l3_main_2_hwmod,
3213 .clk = "dbgclk_mux_ck",
3214 .user = OCP_USER_MPU | OCP_USER_SDMA,
3217 /* dma_system -> l3_main_2 */
3218 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3219 .master = &omap44xx_dma_system_hwmod,
3220 .slave = &omap44xx_l3_main_2_hwmod,
3222 .user = OCP_USER_MPU | OCP_USER_SDMA,
3225 /* fdif -> l3_main_2 */
3226 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3227 .master = &omap44xx_fdif_hwmod,
3228 .slave = &omap44xx_l3_main_2_hwmod,
3230 .user = OCP_USER_MPU | OCP_USER_SDMA,
3233 /* gpu -> l3_main_2 */
3234 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
3235 .master = &omap44xx_gpu_hwmod,
3236 .slave = &omap44xx_l3_main_2_hwmod,
3238 .user = OCP_USER_MPU | OCP_USER_SDMA,
3241 /* hsi -> l3_main_2 */
3242 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
3243 .master = &omap44xx_hsi_hwmod,
3244 .slave = &omap44xx_l3_main_2_hwmod,
3246 .user = OCP_USER_MPU | OCP_USER_SDMA,
3249 /* ipu -> l3_main_2 */
3250 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
3251 .master = &omap44xx_ipu_hwmod,
3252 .slave = &omap44xx_l3_main_2_hwmod,
3254 .user = OCP_USER_MPU | OCP_USER_SDMA,
3257 /* iss -> l3_main_2 */
3258 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
3259 .master = &omap44xx_iss_hwmod,
3260 .slave = &omap44xx_l3_main_2_hwmod,
3262 .user = OCP_USER_MPU | OCP_USER_SDMA,
3265 /* iva -> l3_main_2 */
3266 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
3267 .master = &omap44xx_iva_hwmod,
3268 .slave = &omap44xx_l3_main_2_hwmod,
3270 .user = OCP_USER_MPU | OCP_USER_SDMA,
3273 /* l3_main_1 -> l3_main_2 */
3274 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
3275 .master = &omap44xx_l3_main_1_hwmod,
3276 .slave = &omap44xx_l3_main_2_hwmod,
3278 .user = OCP_USER_MPU,
3281 /* l4_cfg -> l3_main_2 */
3282 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
3283 .master = &omap44xx_l4_cfg_hwmod,
3284 .slave = &omap44xx_l3_main_2_hwmod,
3286 .user = OCP_USER_MPU | OCP_USER_SDMA,
3289 /* usb_host_fs -> l3_main_2 */
3290 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
3291 .master = &omap44xx_usb_host_fs_hwmod,
3292 .slave = &omap44xx_l3_main_2_hwmod,
3294 .user = OCP_USER_MPU | OCP_USER_SDMA,
3297 /* usb_host_hs -> l3_main_2 */
3298 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
3299 .master = &omap44xx_usb_host_hs_hwmod,
3300 .slave = &omap44xx_l3_main_2_hwmod,
3302 .user = OCP_USER_MPU | OCP_USER_SDMA,
3305 /* usb_otg_hs -> l3_main_2 */
3306 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
3307 .master = &omap44xx_usb_otg_hs_hwmod,
3308 .slave = &omap44xx_l3_main_2_hwmod,
3310 .user = OCP_USER_MPU | OCP_USER_SDMA,
3313 /* l3_main_1 -> l3_main_3 */
3314 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
3315 .master = &omap44xx_l3_main_1_hwmod,
3316 .slave = &omap44xx_l3_main_3_hwmod,
3318 .user = OCP_USER_MPU,
3321 /* l3_main_2 -> l3_main_3 */
3322 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
3323 .master = &omap44xx_l3_main_2_hwmod,
3324 .slave = &omap44xx_l3_main_3_hwmod,
3326 .user = OCP_USER_MPU | OCP_USER_SDMA,
3329 /* l4_cfg -> l3_main_3 */
3330 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
3331 .master = &omap44xx_l4_cfg_hwmod,
3332 .slave = &omap44xx_l3_main_3_hwmod,
3334 .user = OCP_USER_MPU | OCP_USER_SDMA,
3337 /* aess -> l4_abe */
3338 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
3339 .master = &omap44xx_aess_hwmod,
3340 .slave = &omap44xx_l4_abe_hwmod,
3341 .clk = "ocp_abe_iclk",
3342 .user = OCP_USER_MPU | OCP_USER_SDMA,
3346 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
3347 .master = &omap44xx_dsp_hwmod,
3348 .slave = &omap44xx_l4_abe_hwmod,
3349 .clk = "ocp_abe_iclk",
3350 .user = OCP_USER_MPU | OCP_USER_SDMA,
3353 /* l3_main_1 -> l4_abe */
3354 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
3355 .master = &omap44xx_l3_main_1_hwmod,
3356 .slave = &omap44xx_l4_abe_hwmod,
3358 .user = OCP_USER_MPU | OCP_USER_SDMA,
3362 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
3363 .master = &omap44xx_mpu_hwmod,
3364 .slave = &omap44xx_l4_abe_hwmod,
3365 .clk = "ocp_abe_iclk",
3366 .user = OCP_USER_MPU | OCP_USER_SDMA,
3369 /* l3_main_1 -> l4_cfg */
3370 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
3371 .master = &omap44xx_l3_main_1_hwmod,
3372 .slave = &omap44xx_l4_cfg_hwmod,
3374 .user = OCP_USER_MPU | OCP_USER_SDMA,
3377 /* l3_main_2 -> l4_per */
3378 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
3379 .master = &omap44xx_l3_main_2_hwmod,
3380 .slave = &omap44xx_l4_per_hwmod,
3382 .user = OCP_USER_MPU | OCP_USER_SDMA,
3385 /* l4_cfg -> l4_wkup */
3386 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
3387 .master = &omap44xx_l4_cfg_hwmod,
3388 .slave = &omap44xx_l4_wkup_hwmod,
3390 .user = OCP_USER_MPU | OCP_USER_SDMA,
3393 /* mpu -> mpu_private */
3394 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
3395 .master = &omap44xx_mpu_hwmod,
3396 .slave = &omap44xx_mpu_private_hwmod,
3398 .user = OCP_USER_MPU | OCP_USER_SDMA,
3401 /* l4_cfg -> ocp_wp_noc */
3402 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
3403 .master = &omap44xx_l4_cfg_hwmod,
3404 .slave = &omap44xx_ocp_wp_noc_hwmod,
3406 .user = OCP_USER_MPU | OCP_USER_SDMA,
3409 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
3412 .pa_start = 0x40180000,
3413 .pa_end = 0x4018ffff
3417 .pa_start = 0x401a0000,
3418 .pa_end = 0x401a1fff
3422 .pa_start = 0x401c0000,
3423 .pa_end = 0x401c5fff
3427 .pa_start = 0x401e0000,
3428 .pa_end = 0x401e1fff
3432 .pa_start = 0x401f1000,
3433 .pa_end = 0x401f13ff,
3434 .flags = ADDR_TYPE_RT
3439 /* l4_abe -> aess */
3440 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
3441 .master = &omap44xx_l4_abe_hwmod,
3442 .slave = &omap44xx_aess_hwmod,
3443 .clk = "ocp_abe_iclk",
3444 .addr = omap44xx_aess_addrs,
3445 .user = OCP_USER_MPU,
3448 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
3451 .pa_start = 0x49080000,
3452 .pa_end = 0x4908ffff
3456 .pa_start = 0x490a0000,
3457 .pa_end = 0x490a1fff
3461 .pa_start = 0x490c0000,
3462 .pa_end = 0x490c5fff
3466 .pa_start = 0x490e0000,
3467 .pa_end = 0x490e1fff
3471 .pa_start = 0x490f1000,
3472 .pa_end = 0x490f13ff,
3473 .flags = ADDR_TYPE_RT
3478 /* l4_abe -> aess (dma) */
3479 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
3480 .master = &omap44xx_l4_abe_hwmod,
3481 .slave = &omap44xx_aess_hwmod,
3482 .clk = "ocp_abe_iclk",
3483 .addr = omap44xx_aess_dma_addrs,
3484 .user = OCP_USER_SDMA,
3487 /* l3_main_2 -> c2c */
3488 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
3489 .master = &omap44xx_l3_main_2_hwmod,
3490 .slave = &omap44xx_c2c_hwmod,
3492 .user = OCP_USER_MPU | OCP_USER_SDMA,
3495 /* l4_wkup -> counter_32k */
3496 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
3497 .master = &omap44xx_l4_wkup_hwmod,
3498 .slave = &omap44xx_counter_32k_hwmod,
3499 .clk = "l4_wkup_clk_mux_ck",
3500 .user = OCP_USER_MPU | OCP_USER_SDMA,
3503 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
3505 .pa_start = 0x4a002000,
3506 .pa_end = 0x4a0027ff,
3507 .flags = ADDR_TYPE_RT
3512 /* l4_cfg -> ctrl_module_core */
3513 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
3514 .master = &omap44xx_l4_cfg_hwmod,
3515 .slave = &omap44xx_ctrl_module_core_hwmod,
3517 .addr = omap44xx_ctrl_module_core_addrs,
3518 .user = OCP_USER_MPU | OCP_USER_SDMA,
3521 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
3523 .pa_start = 0x4a100000,
3524 .pa_end = 0x4a1007ff,
3525 .flags = ADDR_TYPE_RT
3530 /* l4_cfg -> ctrl_module_pad_core */
3531 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
3532 .master = &omap44xx_l4_cfg_hwmod,
3533 .slave = &omap44xx_ctrl_module_pad_core_hwmod,
3535 .addr = omap44xx_ctrl_module_pad_core_addrs,
3536 .user = OCP_USER_MPU | OCP_USER_SDMA,
3539 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
3541 .pa_start = 0x4a30c000,
3542 .pa_end = 0x4a30c7ff,
3543 .flags = ADDR_TYPE_RT
3548 /* l4_wkup -> ctrl_module_wkup */
3549 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
3550 .master = &omap44xx_l4_wkup_hwmod,
3551 .slave = &omap44xx_ctrl_module_wkup_hwmod,
3552 .clk = "l4_wkup_clk_mux_ck",
3553 .addr = omap44xx_ctrl_module_wkup_addrs,
3554 .user = OCP_USER_MPU | OCP_USER_SDMA,
3557 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
3559 .pa_start = 0x4a31e000,
3560 .pa_end = 0x4a31e7ff,
3561 .flags = ADDR_TYPE_RT
3566 /* l4_wkup -> ctrl_module_pad_wkup */
3567 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
3568 .master = &omap44xx_l4_wkup_hwmod,
3569 .slave = &omap44xx_ctrl_module_pad_wkup_hwmod,
3570 .clk = "l4_wkup_clk_mux_ck",
3571 .addr = omap44xx_ctrl_module_pad_wkup_addrs,
3572 .user = OCP_USER_MPU | OCP_USER_SDMA,
3575 /* l3_instr -> debugss */
3576 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
3577 .master = &omap44xx_l3_instr_hwmod,
3578 .slave = &omap44xx_debugss_hwmod,
3580 .user = OCP_USER_MPU | OCP_USER_SDMA,
3583 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
3585 .pa_start = 0x4a056000,
3586 .pa_end = 0x4a056fff,
3587 .flags = ADDR_TYPE_RT
3592 /* l4_cfg -> dma_system */
3593 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
3594 .master = &omap44xx_l4_cfg_hwmod,
3595 .slave = &omap44xx_dma_system_hwmod,
3597 .addr = omap44xx_dma_system_addrs,
3598 .user = OCP_USER_MPU | OCP_USER_SDMA,
3601 /* l4_abe -> dmic */
3602 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
3603 .master = &omap44xx_l4_abe_hwmod,
3604 .slave = &omap44xx_dmic_hwmod,
3605 .clk = "ocp_abe_iclk",
3606 .user = OCP_USER_MPU | OCP_USER_SDMA,
3610 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
3611 .master = &omap44xx_dsp_hwmod,
3612 .slave = &omap44xx_iva_hwmod,
3613 .clk = "dpll_iva_m5x2_ck",
3614 .user = OCP_USER_DSP,
3618 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
3619 .master = &omap44xx_dsp_hwmod,
3620 .slave = &omap44xx_sl2if_hwmod,
3621 .clk = "dpll_iva_m5x2_ck",
3622 .user = OCP_USER_DSP,
3626 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
3627 .master = &omap44xx_l4_cfg_hwmod,
3628 .slave = &omap44xx_dsp_hwmod,
3630 .user = OCP_USER_MPU | OCP_USER_SDMA,
3633 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
3635 .pa_start = 0x58000000,
3636 .pa_end = 0x5800007f,
3637 .flags = ADDR_TYPE_RT
3642 /* l3_main_2 -> dss */
3643 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
3644 .master = &omap44xx_l3_main_2_hwmod,
3645 .slave = &omap44xx_dss_hwmod,
3647 .addr = omap44xx_dss_dma_addrs,
3648 .user = OCP_USER_SDMA,
3651 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
3653 .pa_start = 0x48040000,
3654 .pa_end = 0x4804007f,
3655 .flags = ADDR_TYPE_RT
3661 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
3662 .master = &omap44xx_l4_per_hwmod,
3663 .slave = &omap44xx_dss_hwmod,
3665 .addr = omap44xx_dss_addrs,
3666 .user = OCP_USER_MPU,
3669 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
3671 .pa_start = 0x58001000,
3672 .pa_end = 0x58001fff,
3673 .flags = ADDR_TYPE_RT
3678 /* l3_main_2 -> dss_dispc */
3679 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
3680 .master = &omap44xx_l3_main_2_hwmod,
3681 .slave = &omap44xx_dss_dispc_hwmod,
3683 .addr = omap44xx_dss_dispc_dma_addrs,
3684 .user = OCP_USER_SDMA,
3687 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
3689 .pa_start = 0x48041000,
3690 .pa_end = 0x48041fff,
3691 .flags = ADDR_TYPE_RT
3696 /* l4_per -> dss_dispc */
3697 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
3698 .master = &omap44xx_l4_per_hwmod,
3699 .slave = &omap44xx_dss_dispc_hwmod,
3701 .addr = omap44xx_dss_dispc_addrs,
3702 .user = OCP_USER_MPU,
3705 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
3707 .pa_start = 0x58004000,
3708 .pa_end = 0x580041ff,
3709 .flags = ADDR_TYPE_RT
3714 /* l3_main_2 -> dss_dsi1 */
3715 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
3716 .master = &omap44xx_l3_main_2_hwmod,
3717 .slave = &omap44xx_dss_dsi1_hwmod,
3719 .addr = omap44xx_dss_dsi1_dma_addrs,
3720 .user = OCP_USER_SDMA,
3723 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
3725 .pa_start = 0x48044000,
3726 .pa_end = 0x480441ff,
3727 .flags = ADDR_TYPE_RT
3732 /* l4_per -> dss_dsi1 */
3733 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
3734 .master = &omap44xx_l4_per_hwmod,
3735 .slave = &omap44xx_dss_dsi1_hwmod,
3737 .addr = omap44xx_dss_dsi1_addrs,
3738 .user = OCP_USER_MPU,
3741 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
3743 .pa_start = 0x58005000,
3744 .pa_end = 0x580051ff,
3745 .flags = ADDR_TYPE_RT
3750 /* l3_main_2 -> dss_dsi2 */
3751 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
3752 .master = &omap44xx_l3_main_2_hwmod,
3753 .slave = &omap44xx_dss_dsi2_hwmod,
3755 .addr = omap44xx_dss_dsi2_dma_addrs,
3756 .user = OCP_USER_SDMA,
3759 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
3761 .pa_start = 0x48045000,
3762 .pa_end = 0x480451ff,
3763 .flags = ADDR_TYPE_RT
3768 /* l4_per -> dss_dsi2 */
3769 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
3770 .master = &omap44xx_l4_per_hwmod,
3771 .slave = &omap44xx_dss_dsi2_hwmod,
3773 .addr = omap44xx_dss_dsi2_addrs,
3774 .user = OCP_USER_MPU,
3777 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
3779 .pa_start = 0x58006000,
3780 .pa_end = 0x58006fff,
3781 .flags = ADDR_TYPE_RT
3786 /* l3_main_2 -> dss_hdmi */
3787 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
3788 .master = &omap44xx_l3_main_2_hwmod,
3789 .slave = &omap44xx_dss_hdmi_hwmod,
3791 .addr = omap44xx_dss_hdmi_dma_addrs,
3792 .user = OCP_USER_SDMA,
3795 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
3797 .pa_start = 0x48046000,
3798 .pa_end = 0x48046fff,
3799 .flags = ADDR_TYPE_RT
3804 /* l4_per -> dss_hdmi */
3805 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
3806 .master = &omap44xx_l4_per_hwmod,
3807 .slave = &omap44xx_dss_hdmi_hwmod,
3809 .addr = omap44xx_dss_hdmi_addrs,
3810 .user = OCP_USER_MPU,
3813 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
3815 .pa_start = 0x58002000,
3816 .pa_end = 0x580020ff,
3817 .flags = ADDR_TYPE_RT
3822 /* l3_main_2 -> dss_rfbi */
3823 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
3824 .master = &omap44xx_l3_main_2_hwmod,
3825 .slave = &omap44xx_dss_rfbi_hwmod,
3827 .addr = omap44xx_dss_rfbi_dma_addrs,
3828 .user = OCP_USER_SDMA,
3831 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
3833 .pa_start = 0x48042000,
3834 .pa_end = 0x480420ff,
3835 .flags = ADDR_TYPE_RT
3840 /* l4_per -> dss_rfbi */
3841 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
3842 .master = &omap44xx_l4_per_hwmod,
3843 .slave = &omap44xx_dss_rfbi_hwmod,
3845 .addr = omap44xx_dss_rfbi_addrs,
3846 .user = OCP_USER_MPU,
3849 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
3851 .pa_start = 0x58003000,
3852 .pa_end = 0x580030ff,
3853 .flags = ADDR_TYPE_RT
3858 /* l3_main_2 -> dss_venc */
3859 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
3860 .master = &omap44xx_l3_main_2_hwmod,
3861 .slave = &omap44xx_dss_venc_hwmod,
3863 .addr = omap44xx_dss_venc_dma_addrs,
3864 .user = OCP_USER_SDMA,
3867 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
3869 .pa_start = 0x48043000,
3870 .pa_end = 0x480430ff,
3871 .flags = ADDR_TYPE_RT
3876 /* l4_per -> dss_venc */
3877 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
3878 .master = &omap44xx_l4_per_hwmod,
3879 .slave = &omap44xx_dss_venc_hwmod,
3881 .addr = omap44xx_dss_venc_addrs,
3882 .user = OCP_USER_MPU,
3886 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
3887 .master = &omap44xx_l4_per_hwmod,
3888 .slave = &omap44xx_elm_hwmod,
3890 .user = OCP_USER_MPU | OCP_USER_SDMA,
3893 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
3895 .pa_start = 0x4a10a000,
3896 .pa_end = 0x4a10a1ff,
3897 .flags = ADDR_TYPE_RT
3902 /* l4_cfg -> fdif */
3903 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
3904 .master = &omap44xx_l4_cfg_hwmod,
3905 .slave = &omap44xx_fdif_hwmod,
3907 .addr = omap44xx_fdif_addrs,
3908 .user = OCP_USER_MPU | OCP_USER_SDMA,
3911 /* l4_wkup -> gpio1 */
3912 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
3913 .master = &omap44xx_l4_wkup_hwmod,
3914 .slave = &omap44xx_gpio1_hwmod,
3915 .clk = "l4_wkup_clk_mux_ck",
3916 .user = OCP_USER_MPU | OCP_USER_SDMA,
3919 /* l4_per -> gpio2 */
3920 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
3921 .master = &omap44xx_l4_per_hwmod,
3922 .slave = &omap44xx_gpio2_hwmod,
3924 .user = OCP_USER_MPU | OCP_USER_SDMA,
3927 /* l4_per -> gpio3 */
3928 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
3929 .master = &omap44xx_l4_per_hwmod,
3930 .slave = &omap44xx_gpio3_hwmod,
3932 .user = OCP_USER_MPU | OCP_USER_SDMA,
3935 /* l4_per -> gpio4 */
3936 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
3937 .master = &omap44xx_l4_per_hwmod,
3938 .slave = &omap44xx_gpio4_hwmod,
3940 .user = OCP_USER_MPU | OCP_USER_SDMA,
3943 /* l4_per -> gpio5 */
3944 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
3945 .master = &omap44xx_l4_per_hwmod,
3946 .slave = &omap44xx_gpio5_hwmod,
3948 .user = OCP_USER_MPU | OCP_USER_SDMA,
3951 /* l4_per -> gpio6 */
3952 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
3953 .master = &omap44xx_l4_per_hwmod,
3954 .slave = &omap44xx_gpio6_hwmod,
3956 .user = OCP_USER_MPU | OCP_USER_SDMA,
3959 /* l3_main_2 -> gpmc */
3960 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
3961 .master = &omap44xx_l3_main_2_hwmod,
3962 .slave = &omap44xx_gpmc_hwmod,
3964 .user = OCP_USER_MPU | OCP_USER_SDMA,
3967 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
3969 .pa_start = 0x56000000,
3970 .pa_end = 0x5600ffff,
3971 .flags = ADDR_TYPE_RT
3976 /* l3_main_2 -> gpu */
3977 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
3978 .master = &omap44xx_l3_main_2_hwmod,
3979 .slave = &omap44xx_gpu_hwmod,
3981 .addr = omap44xx_gpu_addrs,
3982 .user = OCP_USER_MPU | OCP_USER_SDMA,
3985 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
3987 .pa_start = 0x480b2000,
3988 .pa_end = 0x480b201f,
3989 .flags = ADDR_TYPE_RT
3994 /* l4_per -> hdq1w */
3995 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
3996 .master = &omap44xx_l4_per_hwmod,
3997 .slave = &omap44xx_hdq1w_hwmod,
3999 .addr = omap44xx_hdq1w_addrs,
4000 .user = OCP_USER_MPU | OCP_USER_SDMA,
4003 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4005 .pa_start = 0x4a058000,
4006 .pa_end = 0x4a05bfff,
4007 .flags = ADDR_TYPE_RT
4013 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4014 .master = &omap44xx_l4_cfg_hwmod,
4015 .slave = &omap44xx_hsi_hwmod,
4017 .addr = omap44xx_hsi_addrs,
4018 .user = OCP_USER_MPU | OCP_USER_SDMA,
4021 /* l4_per -> i2c1 */
4022 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4023 .master = &omap44xx_l4_per_hwmod,
4024 .slave = &omap44xx_i2c1_hwmod,
4026 .user = OCP_USER_MPU | OCP_USER_SDMA,
4029 /* l4_per -> i2c2 */
4030 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
4031 .master = &omap44xx_l4_per_hwmod,
4032 .slave = &omap44xx_i2c2_hwmod,
4034 .user = OCP_USER_MPU | OCP_USER_SDMA,
4037 /* l4_per -> i2c3 */
4038 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
4039 .master = &omap44xx_l4_per_hwmod,
4040 .slave = &omap44xx_i2c3_hwmod,
4042 .user = OCP_USER_MPU | OCP_USER_SDMA,
4045 /* l4_per -> i2c4 */
4046 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
4047 .master = &omap44xx_l4_per_hwmod,
4048 .slave = &omap44xx_i2c4_hwmod,
4050 .user = OCP_USER_MPU | OCP_USER_SDMA,
4053 /* l3_main_2 -> ipu */
4054 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
4055 .master = &omap44xx_l3_main_2_hwmod,
4056 .slave = &omap44xx_ipu_hwmod,
4058 .user = OCP_USER_MPU | OCP_USER_SDMA,
4061 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
4063 .pa_start = 0x52000000,
4064 .pa_end = 0x520000ff,
4065 .flags = ADDR_TYPE_RT
4070 /* l3_main_2 -> iss */
4071 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
4072 .master = &omap44xx_l3_main_2_hwmod,
4073 .slave = &omap44xx_iss_hwmod,
4075 .addr = omap44xx_iss_addrs,
4076 .user = OCP_USER_MPU | OCP_USER_SDMA,
4080 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
4081 .master = &omap44xx_iva_hwmod,
4082 .slave = &omap44xx_sl2if_hwmod,
4083 .clk = "dpll_iva_m5x2_ck",
4084 .user = OCP_USER_IVA,
4087 /* l3_main_2 -> iva */
4088 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
4089 .master = &omap44xx_l3_main_2_hwmod,
4090 .slave = &omap44xx_iva_hwmod,
4092 .user = OCP_USER_MPU,
4095 /* l4_wkup -> kbd */
4096 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
4097 .master = &omap44xx_l4_wkup_hwmod,
4098 .slave = &omap44xx_kbd_hwmod,
4099 .clk = "l4_wkup_clk_mux_ck",
4100 .user = OCP_USER_MPU | OCP_USER_SDMA,
4103 /* l4_cfg -> mailbox */
4104 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
4105 .master = &omap44xx_l4_cfg_hwmod,
4106 .slave = &omap44xx_mailbox_hwmod,
4108 .user = OCP_USER_MPU | OCP_USER_SDMA,
4111 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
4113 .pa_start = 0x40128000,
4114 .pa_end = 0x401283ff,
4115 .flags = ADDR_TYPE_RT
4120 /* l4_abe -> mcasp */
4121 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
4122 .master = &omap44xx_l4_abe_hwmod,
4123 .slave = &omap44xx_mcasp_hwmod,
4124 .clk = "ocp_abe_iclk",
4125 .addr = omap44xx_mcasp_addrs,
4126 .user = OCP_USER_MPU,
4129 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
4131 .pa_start = 0x49028000,
4132 .pa_end = 0x490283ff,
4133 .flags = ADDR_TYPE_RT
4138 /* l4_abe -> mcasp (dma) */
4139 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
4140 .master = &omap44xx_l4_abe_hwmod,
4141 .slave = &omap44xx_mcasp_hwmod,
4142 .clk = "ocp_abe_iclk",
4143 .addr = omap44xx_mcasp_dma_addrs,
4144 .user = OCP_USER_SDMA,
4147 /* l4_abe -> mcbsp1 */
4148 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
4149 .master = &omap44xx_l4_abe_hwmod,
4150 .slave = &omap44xx_mcbsp1_hwmod,
4151 .clk = "ocp_abe_iclk",
4152 .user = OCP_USER_MPU | OCP_USER_SDMA,
4155 /* l4_abe -> mcbsp2 */
4156 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
4157 .master = &omap44xx_l4_abe_hwmod,
4158 .slave = &omap44xx_mcbsp2_hwmod,
4159 .clk = "ocp_abe_iclk",
4160 .user = OCP_USER_MPU | OCP_USER_SDMA,
4163 /* l4_abe -> mcbsp3 */
4164 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
4165 .master = &omap44xx_l4_abe_hwmod,
4166 .slave = &omap44xx_mcbsp3_hwmod,
4167 .clk = "ocp_abe_iclk",
4168 .user = OCP_USER_MPU | OCP_USER_SDMA,
4171 /* l4_per -> mcbsp4 */
4172 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
4173 .master = &omap44xx_l4_per_hwmod,
4174 .slave = &omap44xx_mcbsp4_hwmod,
4176 .user = OCP_USER_MPU | OCP_USER_SDMA,
4179 /* l4_abe -> mcpdm */
4180 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
4181 .master = &omap44xx_l4_abe_hwmod,
4182 .slave = &omap44xx_mcpdm_hwmod,
4183 .clk = "ocp_abe_iclk",
4184 .user = OCP_USER_MPU | OCP_USER_SDMA,
4187 /* l4_per -> mcspi1 */
4188 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
4189 .master = &omap44xx_l4_per_hwmod,
4190 .slave = &omap44xx_mcspi1_hwmod,
4192 .user = OCP_USER_MPU | OCP_USER_SDMA,
4195 /* l4_per -> mcspi2 */
4196 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
4197 .master = &omap44xx_l4_per_hwmod,
4198 .slave = &omap44xx_mcspi2_hwmod,
4200 .user = OCP_USER_MPU | OCP_USER_SDMA,
4203 /* l4_per -> mcspi3 */
4204 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
4205 .master = &omap44xx_l4_per_hwmod,
4206 .slave = &omap44xx_mcspi3_hwmod,
4208 .user = OCP_USER_MPU | OCP_USER_SDMA,
4211 /* l4_per -> mcspi4 */
4212 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
4213 .master = &omap44xx_l4_per_hwmod,
4214 .slave = &omap44xx_mcspi4_hwmod,
4216 .user = OCP_USER_MPU | OCP_USER_SDMA,
4219 /* l4_per -> mmc1 */
4220 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
4221 .master = &omap44xx_l4_per_hwmod,
4222 .slave = &omap44xx_mmc1_hwmod,
4224 .user = OCP_USER_MPU | OCP_USER_SDMA,
4227 /* l4_per -> mmc2 */
4228 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
4229 .master = &omap44xx_l4_per_hwmod,
4230 .slave = &omap44xx_mmc2_hwmod,
4232 .user = OCP_USER_MPU | OCP_USER_SDMA,
4235 /* l4_per -> mmc3 */
4236 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
4237 .master = &omap44xx_l4_per_hwmod,
4238 .slave = &omap44xx_mmc3_hwmod,
4240 .user = OCP_USER_MPU | OCP_USER_SDMA,
4243 /* l4_per -> mmc4 */
4244 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
4245 .master = &omap44xx_l4_per_hwmod,
4246 .slave = &omap44xx_mmc4_hwmod,
4248 .user = OCP_USER_MPU | OCP_USER_SDMA,
4251 /* l4_per -> mmc5 */
4252 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
4253 .master = &omap44xx_l4_per_hwmod,
4254 .slave = &omap44xx_mmc5_hwmod,
4256 .user = OCP_USER_MPU | OCP_USER_SDMA,
4259 /* l3_main_2 -> ocmc_ram */
4260 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
4261 .master = &omap44xx_l3_main_2_hwmod,
4262 .slave = &omap44xx_ocmc_ram_hwmod,
4264 .user = OCP_USER_MPU | OCP_USER_SDMA,
4267 /* l4_cfg -> ocp2scp_usb_phy */
4268 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
4269 .master = &omap44xx_l4_cfg_hwmod,
4270 .slave = &omap44xx_ocp2scp_usb_phy_hwmod,
4272 .user = OCP_USER_MPU | OCP_USER_SDMA,
4275 /* mpu_private -> prcm_mpu */
4276 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
4277 .master = &omap44xx_mpu_private_hwmod,
4278 .slave = &omap44xx_prcm_mpu_hwmod,
4280 .user = OCP_USER_MPU | OCP_USER_SDMA,
4283 /* l4_wkup -> cm_core_aon */
4284 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
4285 .master = &omap44xx_l4_wkup_hwmod,
4286 .slave = &omap44xx_cm_core_aon_hwmod,
4287 .clk = "l4_wkup_clk_mux_ck",
4288 .user = OCP_USER_MPU | OCP_USER_SDMA,
4291 /* l4_cfg -> cm_core */
4292 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
4293 .master = &omap44xx_l4_cfg_hwmod,
4294 .slave = &omap44xx_cm_core_hwmod,
4296 .user = OCP_USER_MPU | OCP_USER_SDMA,
4299 /* l4_wkup -> prm */
4300 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
4301 .master = &omap44xx_l4_wkup_hwmod,
4302 .slave = &omap44xx_prm_hwmod,
4303 .clk = "l4_wkup_clk_mux_ck",
4304 .user = OCP_USER_MPU | OCP_USER_SDMA,
4307 /* l4_wkup -> scrm */
4308 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
4309 .master = &omap44xx_l4_wkup_hwmod,
4310 .slave = &omap44xx_scrm_hwmod,
4311 .clk = "l4_wkup_clk_mux_ck",
4312 .user = OCP_USER_MPU | OCP_USER_SDMA,
4315 /* l3_main_2 -> sl2if */
4316 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
4317 .master = &omap44xx_l3_main_2_hwmod,
4318 .slave = &omap44xx_sl2if_hwmod,
4320 .user = OCP_USER_MPU | OCP_USER_SDMA,
4323 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
4325 .pa_start = 0x4012c000,
4326 .pa_end = 0x4012c3ff,
4327 .flags = ADDR_TYPE_RT
4332 /* l4_abe -> slimbus1 */
4333 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
4334 .master = &omap44xx_l4_abe_hwmod,
4335 .slave = &omap44xx_slimbus1_hwmod,
4336 .clk = "ocp_abe_iclk",
4337 .addr = omap44xx_slimbus1_addrs,
4338 .user = OCP_USER_MPU,
4341 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
4343 .pa_start = 0x4902c000,
4344 .pa_end = 0x4902c3ff,
4345 .flags = ADDR_TYPE_RT
4350 /* l4_abe -> slimbus1 (dma) */
4351 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
4352 .master = &omap44xx_l4_abe_hwmod,
4353 .slave = &omap44xx_slimbus1_hwmod,
4354 .clk = "ocp_abe_iclk",
4355 .addr = omap44xx_slimbus1_dma_addrs,
4356 .user = OCP_USER_SDMA,
4359 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
4361 .pa_start = 0x48076000,
4362 .pa_end = 0x480763ff,
4363 .flags = ADDR_TYPE_RT
4368 /* l4_per -> slimbus2 */
4369 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
4370 .master = &omap44xx_l4_per_hwmod,
4371 .slave = &omap44xx_slimbus2_hwmod,
4373 .addr = omap44xx_slimbus2_addrs,
4374 .user = OCP_USER_MPU | OCP_USER_SDMA,
4377 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
4379 .pa_start = 0x4a0dd000,
4380 .pa_end = 0x4a0dd03f,
4381 .flags = ADDR_TYPE_RT
4386 /* l4_cfg -> smartreflex_core */
4387 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
4388 .master = &omap44xx_l4_cfg_hwmod,
4389 .slave = &omap44xx_smartreflex_core_hwmod,
4391 .addr = omap44xx_smartreflex_core_addrs,
4392 .user = OCP_USER_MPU | OCP_USER_SDMA,
4395 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
4397 .pa_start = 0x4a0db000,
4398 .pa_end = 0x4a0db03f,
4399 .flags = ADDR_TYPE_RT
4404 /* l4_cfg -> smartreflex_iva */
4405 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
4406 .master = &omap44xx_l4_cfg_hwmod,
4407 .slave = &omap44xx_smartreflex_iva_hwmod,
4409 .addr = omap44xx_smartreflex_iva_addrs,
4410 .user = OCP_USER_MPU | OCP_USER_SDMA,
4413 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
4415 .pa_start = 0x4a0d9000,
4416 .pa_end = 0x4a0d903f,
4417 .flags = ADDR_TYPE_RT
4422 /* l4_cfg -> smartreflex_mpu */
4423 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
4424 .master = &omap44xx_l4_cfg_hwmod,
4425 .slave = &omap44xx_smartreflex_mpu_hwmod,
4427 .addr = omap44xx_smartreflex_mpu_addrs,
4428 .user = OCP_USER_MPU | OCP_USER_SDMA,
4431 /* l4_cfg -> spinlock */
4432 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
4433 .master = &omap44xx_l4_cfg_hwmod,
4434 .slave = &omap44xx_spinlock_hwmod,
4436 .user = OCP_USER_MPU | OCP_USER_SDMA,
4439 /* l4_wkup -> timer1 */
4440 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4441 .master = &omap44xx_l4_wkup_hwmod,
4442 .slave = &omap44xx_timer1_hwmod,
4443 .clk = "l4_wkup_clk_mux_ck",
4444 .user = OCP_USER_MPU | OCP_USER_SDMA,
4447 /* l4_per -> timer2 */
4448 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4449 .master = &omap44xx_l4_per_hwmod,
4450 .slave = &omap44xx_timer2_hwmod,
4452 .user = OCP_USER_MPU | OCP_USER_SDMA,
4455 /* l4_per -> timer3 */
4456 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4457 .master = &omap44xx_l4_per_hwmod,
4458 .slave = &omap44xx_timer3_hwmod,
4460 .user = OCP_USER_MPU | OCP_USER_SDMA,
4463 /* l4_per -> timer4 */
4464 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4465 .master = &omap44xx_l4_per_hwmod,
4466 .slave = &omap44xx_timer4_hwmod,
4468 .user = OCP_USER_MPU | OCP_USER_SDMA,
4471 /* l4_abe -> timer5 */
4472 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4473 .master = &omap44xx_l4_abe_hwmod,
4474 .slave = &omap44xx_timer5_hwmod,
4475 .clk = "ocp_abe_iclk",
4476 .user = OCP_USER_MPU | OCP_USER_SDMA,
4479 /* l4_abe -> timer6 */
4480 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4481 .master = &omap44xx_l4_abe_hwmod,
4482 .slave = &omap44xx_timer6_hwmod,
4483 .clk = "ocp_abe_iclk",
4484 .user = OCP_USER_MPU | OCP_USER_SDMA,
4487 /* l4_abe -> timer7 */
4488 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4489 .master = &omap44xx_l4_abe_hwmod,
4490 .slave = &omap44xx_timer7_hwmod,
4491 .clk = "ocp_abe_iclk",
4492 .user = OCP_USER_MPU | OCP_USER_SDMA,
4495 /* l4_abe -> timer8 */
4496 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4497 .master = &omap44xx_l4_abe_hwmod,
4498 .slave = &omap44xx_timer8_hwmod,
4499 .clk = "ocp_abe_iclk",
4500 .user = OCP_USER_MPU | OCP_USER_SDMA,
4503 /* l4_per -> timer9 */
4504 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4505 .master = &omap44xx_l4_per_hwmod,
4506 .slave = &omap44xx_timer9_hwmod,
4508 .user = OCP_USER_MPU | OCP_USER_SDMA,
4511 /* l4_per -> timer10 */
4512 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4513 .master = &omap44xx_l4_per_hwmod,
4514 .slave = &omap44xx_timer10_hwmod,
4516 .user = OCP_USER_MPU | OCP_USER_SDMA,
4519 /* l4_per -> timer11 */
4520 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4521 .master = &omap44xx_l4_per_hwmod,
4522 .slave = &omap44xx_timer11_hwmod,
4524 .user = OCP_USER_MPU | OCP_USER_SDMA,
4527 /* l4_per -> uart1 */
4528 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4529 .master = &omap44xx_l4_per_hwmod,
4530 .slave = &omap44xx_uart1_hwmod,
4532 .user = OCP_USER_MPU | OCP_USER_SDMA,
4535 /* l4_per -> uart2 */
4536 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4537 .master = &omap44xx_l4_per_hwmod,
4538 .slave = &omap44xx_uart2_hwmod,
4540 .user = OCP_USER_MPU | OCP_USER_SDMA,
4543 /* l4_per -> uart3 */
4544 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4545 .master = &omap44xx_l4_per_hwmod,
4546 .slave = &omap44xx_uart3_hwmod,
4548 .user = OCP_USER_MPU | OCP_USER_SDMA,
4551 /* l4_per -> uart4 */
4552 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
4553 .master = &omap44xx_l4_per_hwmod,
4554 .slave = &omap44xx_uart4_hwmod,
4556 .user = OCP_USER_MPU | OCP_USER_SDMA,
4559 /* l4_cfg -> usb_host_fs */
4560 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
4561 .master = &omap44xx_l4_cfg_hwmod,
4562 .slave = &omap44xx_usb_host_fs_hwmod,
4564 .user = OCP_USER_MPU | OCP_USER_SDMA,
4567 /* l4_cfg -> usb_host_hs */
4568 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
4569 .master = &omap44xx_l4_cfg_hwmod,
4570 .slave = &omap44xx_usb_host_hs_hwmod,
4572 .user = OCP_USER_MPU | OCP_USER_SDMA,
4575 /* l4_cfg -> usb_otg_hs */
4576 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4577 .master = &omap44xx_l4_cfg_hwmod,
4578 .slave = &omap44xx_usb_otg_hs_hwmod,
4580 .user = OCP_USER_MPU | OCP_USER_SDMA,
4583 /* l4_cfg -> usb_tll_hs */
4584 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
4585 .master = &omap44xx_l4_cfg_hwmod,
4586 .slave = &omap44xx_usb_tll_hs_hwmod,
4588 .user = OCP_USER_MPU | OCP_USER_SDMA,
4591 /* l4_wkup -> wd_timer2 */
4592 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
4593 .master = &omap44xx_l4_wkup_hwmod,
4594 .slave = &omap44xx_wd_timer2_hwmod,
4595 .clk = "l4_wkup_clk_mux_ck",
4596 .user = OCP_USER_MPU | OCP_USER_SDMA,
4599 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
4601 .pa_start = 0x40130000,
4602 .pa_end = 0x4013007f,
4603 .flags = ADDR_TYPE_RT
4608 /* l4_abe -> wd_timer3 */
4609 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
4610 .master = &omap44xx_l4_abe_hwmod,
4611 .slave = &omap44xx_wd_timer3_hwmod,
4612 .clk = "ocp_abe_iclk",
4613 .addr = omap44xx_wd_timer3_addrs,
4614 .user = OCP_USER_MPU,
4617 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
4619 .pa_start = 0x49030000,
4620 .pa_end = 0x4903007f,
4621 .flags = ADDR_TYPE_RT
4626 /* l4_abe -> wd_timer3 (dma) */
4627 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
4628 .master = &omap44xx_l4_abe_hwmod,
4629 .slave = &omap44xx_wd_timer3_hwmod,
4630 .clk = "ocp_abe_iclk",
4631 .addr = omap44xx_wd_timer3_dma_addrs,
4632 .user = OCP_USER_SDMA,
4636 static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
4637 .master = &omap44xx_mpu_hwmod,
4638 .slave = &omap44xx_emif1_hwmod,
4640 .user = OCP_USER_MPU | OCP_USER_SDMA,
4644 static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
4645 .master = &omap44xx_mpu_hwmod,
4646 .slave = &omap44xx_emif2_hwmod,
4648 .user = OCP_USER_MPU | OCP_USER_SDMA,
4651 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
4652 &omap44xx_l3_main_1__dmm,
4654 &omap44xx_iva__l3_instr,
4655 &omap44xx_l3_main_3__l3_instr,
4656 &omap44xx_ocp_wp_noc__l3_instr,
4657 &omap44xx_dsp__l3_main_1,
4658 &omap44xx_dss__l3_main_1,
4659 &omap44xx_l3_main_2__l3_main_1,
4660 &omap44xx_l4_cfg__l3_main_1,
4661 &omap44xx_mmc1__l3_main_1,
4662 &omap44xx_mmc2__l3_main_1,
4663 &omap44xx_mpu__l3_main_1,
4664 &omap44xx_debugss__l3_main_2,
4665 &omap44xx_dma_system__l3_main_2,
4666 &omap44xx_fdif__l3_main_2,
4667 &omap44xx_gpu__l3_main_2,
4668 &omap44xx_hsi__l3_main_2,
4669 &omap44xx_ipu__l3_main_2,
4670 &omap44xx_iss__l3_main_2,
4671 &omap44xx_iva__l3_main_2,
4672 &omap44xx_l3_main_1__l3_main_2,
4673 &omap44xx_l4_cfg__l3_main_2,
4674 /* &omap44xx_usb_host_fs__l3_main_2, */
4675 &omap44xx_usb_host_hs__l3_main_2,
4676 &omap44xx_usb_otg_hs__l3_main_2,
4677 &omap44xx_l3_main_1__l3_main_3,
4678 &omap44xx_l3_main_2__l3_main_3,
4679 &omap44xx_l4_cfg__l3_main_3,
4680 &omap44xx_aess__l4_abe,
4681 &omap44xx_dsp__l4_abe,
4682 &omap44xx_l3_main_1__l4_abe,
4683 &omap44xx_mpu__l4_abe,
4684 &omap44xx_l3_main_1__l4_cfg,
4685 &omap44xx_l3_main_2__l4_per,
4686 &omap44xx_l4_cfg__l4_wkup,
4687 &omap44xx_mpu__mpu_private,
4688 &omap44xx_l4_cfg__ocp_wp_noc,
4689 &omap44xx_l4_abe__aess,
4690 &omap44xx_l4_abe__aess_dma,
4691 &omap44xx_l3_main_2__c2c,
4692 &omap44xx_l4_wkup__counter_32k,
4693 &omap44xx_l4_cfg__ctrl_module_core,
4694 &omap44xx_l4_cfg__ctrl_module_pad_core,
4695 &omap44xx_l4_wkup__ctrl_module_wkup,
4696 &omap44xx_l4_wkup__ctrl_module_pad_wkup,
4697 &omap44xx_l3_instr__debugss,
4698 &omap44xx_l4_cfg__dma_system,
4699 &omap44xx_l4_abe__dmic,
4701 /* &omap44xx_dsp__sl2if, */
4702 &omap44xx_l4_cfg__dsp,
4703 &omap44xx_l3_main_2__dss,
4704 &omap44xx_l4_per__dss,
4705 &omap44xx_l3_main_2__dss_dispc,
4706 &omap44xx_l4_per__dss_dispc,
4707 &omap44xx_l3_main_2__dss_dsi1,
4708 &omap44xx_l4_per__dss_dsi1,
4709 &omap44xx_l3_main_2__dss_dsi2,
4710 &omap44xx_l4_per__dss_dsi2,
4711 &omap44xx_l3_main_2__dss_hdmi,
4712 &omap44xx_l4_per__dss_hdmi,
4713 &omap44xx_l3_main_2__dss_rfbi,
4714 &omap44xx_l4_per__dss_rfbi,
4715 &omap44xx_l3_main_2__dss_venc,
4716 &omap44xx_l4_per__dss_venc,
4717 &omap44xx_l4_per__elm,
4718 &omap44xx_l4_cfg__fdif,
4719 &omap44xx_l4_wkup__gpio1,
4720 &omap44xx_l4_per__gpio2,
4721 &omap44xx_l4_per__gpio3,
4722 &omap44xx_l4_per__gpio4,
4723 &omap44xx_l4_per__gpio5,
4724 &omap44xx_l4_per__gpio6,
4725 &omap44xx_l3_main_2__gpmc,
4726 &omap44xx_l3_main_2__gpu,
4727 &omap44xx_l4_per__hdq1w,
4728 &omap44xx_l4_cfg__hsi,
4729 &omap44xx_l4_per__i2c1,
4730 &omap44xx_l4_per__i2c2,
4731 &omap44xx_l4_per__i2c3,
4732 &omap44xx_l4_per__i2c4,
4733 &omap44xx_l3_main_2__ipu,
4734 &omap44xx_l3_main_2__iss,
4735 /* &omap44xx_iva__sl2if, */
4736 &omap44xx_l3_main_2__iva,
4737 &omap44xx_l4_wkup__kbd,
4738 &omap44xx_l4_cfg__mailbox,
4739 &omap44xx_l4_abe__mcasp,
4740 &omap44xx_l4_abe__mcasp_dma,
4741 &omap44xx_l4_abe__mcbsp1,
4742 &omap44xx_l4_abe__mcbsp2,
4743 &omap44xx_l4_abe__mcbsp3,
4744 &omap44xx_l4_per__mcbsp4,
4745 &omap44xx_l4_abe__mcpdm,
4746 &omap44xx_l4_per__mcspi1,
4747 &omap44xx_l4_per__mcspi2,
4748 &omap44xx_l4_per__mcspi3,
4749 &omap44xx_l4_per__mcspi4,
4750 &omap44xx_l4_per__mmc1,
4751 &omap44xx_l4_per__mmc2,
4752 &omap44xx_l4_per__mmc3,
4753 &omap44xx_l4_per__mmc4,
4754 &omap44xx_l4_per__mmc5,
4755 &omap44xx_l3_main_2__mmu_ipu,
4756 &omap44xx_l4_cfg__mmu_dsp,
4757 &omap44xx_l3_main_2__ocmc_ram,
4758 &omap44xx_l4_cfg__ocp2scp_usb_phy,
4759 &omap44xx_mpu_private__prcm_mpu,
4760 &omap44xx_l4_wkup__cm_core_aon,
4761 &omap44xx_l4_cfg__cm_core,
4762 &omap44xx_l4_wkup__prm,
4763 &omap44xx_l4_wkup__scrm,
4764 /* &omap44xx_l3_main_2__sl2if, */
4765 &omap44xx_l4_abe__slimbus1,
4766 &omap44xx_l4_abe__slimbus1_dma,
4767 &omap44xx_l4_per__slimbus2,
4768 &omap44xx_l4_cfg__smartreflex_core,
4769 &omap44xx_l4_cfg__smartreflex_iva,
4770 &omap44xx_l4_cfg__smartreflex_mpu,
4771 &omap44xx_l4_cfg__spinlock,
4772 &omap44xx_l4_wkup__timer1,
4773 &omap44xx_l4_per__timer2,
4774 &omap44xx_l4_per__timer3,
4775 &omap44xx_l4_per__timer4,
4776 &omap44xx_l4_abe__timer5,
4777 &omap44xx_l4_abe__timer6,
4778 &omap44xx_l4_abe__timer7,
4779 &omap44xx_l4_abe__timer8,
4780 &omap44xx_l4_per__timer9,
4781 &omap44xx_l4_per__timer10,
4782 &omap44xx_l4_per__timer11,
4783 &omap44xx_l4_per__uart1,
4784 &omap44xx_l4_per__uart2,
4785 &omap44xx_l4_per__uart3,
4786 &omap44xx_l4_per__uart4,
4787 /* &omap44xx_l4_cfg__usb_host_fs, */
4788 &omap44xx_l4_cfg__usb_host_hs,
4789 &omap44xx_l4_cfg__usb_otg_hs,
4790 &omap44xx_l4_cfg__usb_tll_hs,
4791 &omap44xx_l4_wkup__wd_timer2,
4792 &omap44xx_l4_abe__wd_timer3,
4793 &omap44xx_l4_abe__wd_timer3_dma,
4794 &omap44xx_mpu__emif1,
4795 &omap44xx_mpu__emif2,
4799 int __init omap44xx_hwmod_init(void)
4802 return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);