arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  * Note that this file is currently not in sync with autogeneration scripts.
  16  * The above note to be removed, once it is synced up.
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License version 2 as
  20  * published by the Free Software Foundation.
  21  */
  22
  23 #include <linux/io.h>
  24 #include <linux/platform_data/gpio-omap.h>
  25 #include <linux/platform_data/hsmmc-omap.h>
  26 #include <linux/power/smartreflex.h>
  27 #include <linux/i2c-omap.h>
  28
  29 #include <linux/omap-dma.h>
  30
  31 #include <linux/platform_data/spi-omap2-mcspi.h>
  32 #include <linux/platform_data/asoc-ti-mcbsp.h>
  33 #include <plat/dmtimer.h>
  34
  35 #include "omap_hwmod.h"
  36 #include "omap_hwmod_common_data.h"
  37 #include "cm1_44xx.h"
  38 #include "cm2_44xx.h"
  39 #include "prm44xx.h"
  40 #include "prm-regbits-44xx.h"
  41 #include "i2c.h"
  42 #include "wd_timer.h"
  43
  44 /* Base offset for all OMAP4 interrupts external to MPUSS */
  45 #define OMAP44XX_IRQ_GIC_START  32
  46
  47 /* Base offset for all OMAP4 dma requests */
  48 #define OMAP44XX_DMA_REQ_START  1
  49
  50 /*
  51  * IP blocks
  52  */
  53
  54 /*
  55  * 'dmm' class
  56  * instance(s): dmm
  57  */
  58 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  59         .name   = "dmm",
  60 };
  61
  62 /* dmm */
  63 static struct omap_hwmod omap44xx_dmm_hwmod = {
  64         .name           = "dmm",
  65         .class          = &omap44xx_dmm_hwmod_class,
  66         .clkdm_name     = "l3_emif_clkdm",
  67         .prcm = {
  68                 .omap4 = {
  69                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  70                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  71                 },
  72         },
  73 };
  74
  75 /*
  76  * 'l3' class
  77  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  78  */
  79 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
  80         .name   = "l3",
  81 };
  82
  83 /* l3_instr */
  84 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
  85         .name           = "l3_instr",
  86         .class          = &omap44xx_l3_hwmod_class,
  87         .clkdm_name     = "l3_instr_clkdm",
  88         .prcm = {
  89                 .omap4 = {
  90                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  91                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  92                         .modulemode   = MODULEMODE_HWCTRL,
  93                 },
  94         },
  95 };
  96
  97 /* l3_main_1 */
  98 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
  99         .name           = "l3_main_1",
 100         .class          = &omap44xx_l3_hwmod_class,
 101         .clkdm_name     = "l3_1_clkdm",
 102         .prcm = {
 103                 .omap4 = {
 104                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 105                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 106                 },
 107         },
 108 };
 109
 110 /* l3_main_2 */
 111 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 112         .name           = "l3_main_2",
 113         .class          = &omap44xx_l3_hwmod_class,
 114         .clkdm_name     = "l3_2_clkdm",
 115         .prcm = {
 116                 .omap4 = {
 117                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 118                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 119                 },
 120         },
 121 };
 122
 123 /* l3_main_3 */
 124 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 125         .name           = "l3_main_3",
 126         .class          = &omap44xx_l3_hwmod_class,
 127         .clkdm_name     = "l3_instr_clkdm",
 128         .prcm = {
 129                 .omap4 = {
 130                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 131                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 132                         .modulemode   = MODULEMODE_HWCTRL,
 133                 },
 134         },
 135 };
 136
 137 /*
 138  * 'l4' class
 139  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 140  */
 141 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 142         .name   = "l4",
 143 };
 144
 145 /* l4_abe */
 146 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 147         .name           = "l4_abe",
 148         .class          = &omap44xx_l4_hwmod_class,
 149         .clkdm_name     = "abe_clkdm",
 150         .prcm = {
 151                 .omap4 = {
 152                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 153                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 154                         .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
 155                         .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 156                 },
 157         },
 158 };
 159
 160 /* l4_cfg */
 161 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 162         .name           = "l4_cfg",
 163         .class          = &omap44xx_l4_hwmod_class,
 164         .clkdm_name     = "l4_cfg_clkdm",
 165         .prcm = {
 166                 .omap4 = {
 167                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 168                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 169                 },
 170         },
 171 };
 172
 173 /* l4_per */
 174 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 175         .name           = "l4_per",
 176         .class          = &omap44xx_l4_hwmod_class,
 177         .clkdm_name     = "l4_per_clkdm",
 178         .prcm = {
 179                 .omap4 = {
 180                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 181                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 182                 },
 183         },
 184 };
 185
 186 /* l4_wkup */
 187 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 188         .name           = "l4_wkup",
 189         .class          = &omap44xx_l4_hwmod_class,
 190         .clkdm_name     = "l4_wkup_clkdm",
 191         .prcm = {
 192                 .omap4 = {
 193                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 194                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 195                 },
 196         },
 197 };
 198
 199 /*
 200  * 'mpu_bus' class
 201  * instance(s): mpu_private
 202  */
 203 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 204         .name   = "mpu_bus",
 205 };
 206
 207 /* mpu_private */
 208 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 209         .name           = "mpu_private",
 210         .class          = &omap44xx_mpu_bus_hwmod_class,
 211         .clkdm_name     = "mpuss_clkdm",
 212         .prcm = {
 213                 .omap4 = {
 214                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 215                 },
 216         },
 217 };
 218
 219 /*
 220  * 'ocp_wp_noc' class
 221  * instance(s): ocp_wp_noc
 222  */
 223 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 224         .name   = "ocp_wp_noc",
 225 };
 226
 227 /* ocp_wp_noc */
 228 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 229         .name           = "ocp_wp_noc",
 230         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 231         .clkdm_name     = "l3_instr_clkdm",
 232         .prcm = {
 233                 .omap4 = {
 234                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 235                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 236                         .modulemode   = MODULEMODE_HWCTRL,
 237                 },
 238         },
 239 };
 240
 241 /*
 242  * Modules omap_hwmod structures
 243  *
 244  * The following IPs are excluded for the moment because:
 245  * - They do not need an explicit SW control using omap_hwmod API.
 246  * - They still need to be validated with the driver
 247  *   properly adapted to omap_hwmod / omap_device
 248  *
 249  * usim
 250  */
 251
 252 /*
 253  * 'aess' class
 254  * audio engine sub system
 255  */
 256
 257 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 258         .rev_offs       = 0x0000,
 259         .sysc_offs      = 0x0010,
 260         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 261         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 262                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 263                            MSTANDBY_SMART_WKUP),
 264         .sysc_fields    = &omap_hwmod_sysc_type2,
 265 };
 266
 267 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 268         .name   = "aess",
 269         .sysc   = &omap44xx_aess_sysc,
 270         .enable_preprogram = omap_hwmod_aess_preprogram,
 271 };
 272
 273 /* aess */
 274 static struct omap_hwmod omap44xx_aess_hwmod = {
 275         .name           = "aess",
 276         .class          = &omap44xx_aess_hwmod_class,
 277         .clkdm_name     = "abe_clkdm",
 278         .main_clk       = "aess_fclk",
 279         .prcm = {
 280                 .omap4 = {
 281                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 282                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 283                         .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
 284                         .modulemode   = MODULEMODE_SWCTRL,
 285                 },
 286         },
 287 };
 288
 289 /*
 290  * 'c2c' class
 291  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 292  * soc
 293  */
 294
 295 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 296         .name   = "c2c",
 297 };
 298
 299 /* c2c */
 300 static struct omap_hwmod omap44xx_c2c_hwmod = {
 301         .name           = "c2c",
 302         .class          = &omap44xx_c2c_hwmod_class,
 303         .clkdm_name     = "d2d_clkdm",
 304         .prcm = {
 305                 .omap4 = {
 306                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
 307                         .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
 308                 },
 309         },
 310 };
 311
 312 /*
 313  * 'counter' class
 314  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 315  */
 316
 317 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 318         .rev_offs       = 0x0000,
 319         .sysc_offs      = 0x0004,
 320         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 321         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 322         .sysc_fields    = &omap_hwmod_sysc_type1,
 323 };
 324
 325 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 326         .name   = "counter",
 327         .sysc   = &omap44xx_counter_sysc,
 328 };
 329
 330 /* counter_32k */
 331 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 332         .name           = "counter_32k",
 333         .class          = &omap44xx_counter_hwmod_class,
 334         .clkdm_name     = "l4_wkup_clkdm",
 335         .flags          = HWMOD_SWSUP_SIDLE,
 336         .main_clk       = "sys_32k_ck",
 337         .prcm = {
 338                 .omap4 = {
 339                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 340                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 341                 },
 342         },
 343 };
 344
 345 /*
 346  * 'ctrl_module' class
 347  * attila core control module + core pad control module + wkup pad control
 348  * module + attila wkup control module
 349  */
 350
 351 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 352         .rev_offs       = 0x0000,
 353         .sysc_offs      = 0x0010,
 354         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 355         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 356                            SIDLE_SMART_WKUP),
 357         .sysc_fields    = &omap_hwmod_sysc_type2,
 358 };
 359
 360 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 361         .name   = "ctrl_module",
 362         .sysc   = &omap44xx_ctrl_module_sysc,
 363 };
 364
 365 /* ctrl_module_core */
 366 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 367         .name           = "ctrl_module_core",
 368         .class          = &omap44xx_ctrl_module_hwmod_class,
 369         .clkdm_name     = "l4_cfg_clkdm",
 370         .prcm = {
 371                 .omap4 = {
 372                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 373                 },
 374         },
 375 };
 376
 377 /* ctrl_module_pad_core */
 378 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 379         .name           = "ctrl_module_pad_core",
 380         .class          = &omap44xx_ctrl_module_hwmod_class,
 381         .clkdm_name     = "l4_cfg_clkdm",
 382         .prcm = {
 383                 .omap4 = {
 384                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 385                 },
 386         },
 387 };
 388
 389 /* ctrl_module_wkup */
 390 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 391         .name           = "ctrl_module_wkup",
 392         .class          = &omap44xx_ctrl_module_hwmod_class,
 393         .clkdm_name     = "l4_wkup_clkdm",
 394         .prcm = {
 395                 .omap4 = {
 396                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 397                 },
 398         },
 399 };
 400
 401 /* ctrl_module_pad_wkup */
 402 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 403         .name           = "ctrl_module_pad_wkup",
 404         .class          = &omap44xx_ctrl_module_hwmod_class,
 405         .clkdm_name     = "l4_wkup_clkdm",
 406         .prcm = {
 407                 .omap4 = {
 408                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 409                 },
 410         },
 411 };
 412
 413 /*
 414  * 'debugss' class
 415  * debug and emulation sub system
 416  */
 417
 418 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 419         .name   = "debugss",
 420 };
 421
 422 /* debugss */
 423 static struct omap_hwmod omap44xx_debugss_hwmod = {
 424         .name           = "debugss",
 425         .class          = &omap44xx_debugss_hwmod_class,
 426         .clkdm_name     = "emu_sys_clkdm",
 427         .main_clk       = "trace_clk_div_ck",
 428         .prcm = {
 429                 .omap4 = {
 430                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 431                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 432                 },
 433         },
 434 };
 435
 436 /*
 437  * 'dma' class
 438  * dma controller for data exchange between memory to memory (i.e. internal or
 439  * external memory) and gp peripherals to memory or memory to gp peripherals
 440  */
 441
 442 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 443         .rev_offs       = 0x0000,
 444         .sysc_offs      = 0x002c,
 445         .syss_offs      = 0x0028,
 446         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 447                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 448                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 449                            SYSS_HAS_RESET_STATUS),
 450         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 451                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 452         .sysc_fields    = &omap_hwmod_sysc_type1,
 453 };
 454
 455 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 456         .name   = "dma",
 457         .sysc   = &omap44xx_dma_sysc,
 458 };
 459
 460 /* dma dev_attr */
 461 static struct omap_dma_dev_attr dma_dev_attr = {
 462         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 463                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 464         .lch_count      = 32,
 465 };
 466
 467 /* dma_system */
 468 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 469         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 470         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 471         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 472         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 473         { .irq = -1 }
 474 };
 475
 476 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 477         .name           = "dma_system",
 478         .class          = &omap44xx_dma_hwmod_class,
 479         .clkdm_name     = "l3_dma_clkdm",
 480         .mpu_irqs       = omap44xx_dma_system_irqs,
 481         .xlate_irq      = omap4_xlate_irq,
 482         .main_clk       = "l3_div_ck",
 483         .prcm = {
 484                 .omap4 = {
 485                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 486                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 487                 },
 488         },
 489         .dev_attr       = &dma_dev_attr,
 490 };
 491
 492 /*
 493  * 'dmic' class
 494  * digital microphone controller
 495  */
 496
 497 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 498         .rev_offs       = 0x0000,
 499         .sysc_offs      = 0x0010,
 500         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 501                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 502         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 503                            SIDLE_SMART_WKUP),
 504         .sysc_fields    = &omap_hwmod_sysc_type2,
 505 };
 506
 507 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 508         .name   = "dmic",
 509         .sysc   = &omap44xx_dmic_sysc,
 510 };
 511
 512 /* dmic */
 513 static struct omap_hwmod omap44xx_dmic_hwmod = {
 514         .name           = "dmic",
 515         .class          = &omap44xx_dmic_hwmod_class,
 516         .clkdm_name     = "abe_clkdm",
 517         .main_clk       = "func_dmic_abe_gfclk",
 518         .prcm = {
 519                 .omap4 = {
 520                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 521                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 522                         .modulemode   = MODULEMODE_SWCTRL,
 523                 },
 524         },
 525 };
 526
 527 /*
 528  * 'dsp' class
 529  * dsp sub-system
 530  */
 531
 532 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 533         .name   = "dsp",
 534 };
 535
 536 /* dsp */
 537 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 538         { .name = "dsp", .rst_shift = 0 },
 539 };
 540
 541 static struct omap_hwmod omap44xx_dsp_hwmod = {
 542         .name           = "dsp",
 543         .class          = &omap44xx_dsp_hwmod_class,
 544         .clkdm_name     = "tesla_clkdm",
 545         .rst_lines      = omap44xx_dsp_resets,
 546         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 547         .main_clk       = "dpll_iva_m4x2_ck",
 548         .prcm = {
 549                 .omap4 = {
 550                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 551                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 552                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 553                         .modulemode   = MODULEMODE_HWCTRL,
 554                 },
 555         },
 556 };
 557
 558 /*
 559  * 'dss' class
 560  * display sub-system
 561  */
 562
 563 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 564         .rev_offs       = 0x0000,
 565         .syss_offs      = 0x0014,
 566         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 567 };
 568
 569 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 570         .name   = "dss",
 571         .sysc   = &omap44xx_dss_sysc,
 572         .reset  = omap_dss_reset,
 573 };
 574
 575 /* dss */
 576 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 577         { .role = "sys_clk", .clk = "dss_sys_clk" },
 578         { .role = "tv_clk", .clk = "dss_tv_clk" },
 579         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 580 };
 581
 582 static struct omap_hwmod omap44xx_dss_hwmod = {
 583         .name           = "dss_core",
 584         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 585         .class          = &omap44xx_dss_hwmod_class,
 586         .clkdm_name     = "l3_dss_clkdm",
 587         .main_clk       = "dss_dss_clk",
 588         .prcm = {
 589                 .omap4 = {
 590                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 591                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 592                         .modulemode   = MODULEMODE_SWCTRL,
 593                 },
 594         },
 595         .opt_clks       = dss_opt_clks,
 596         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 597 };
 598
 599 /*
 600  * 'dispc' class
 601  * display controller
 602  */
 603
 604 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 605         .rev_offs       = 0x0000,
 606         .sysc_offs      = 0x0010,
 607         .syss_offs      = 0x0014,
 608         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 609                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 610                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 611                            SYSS_HAS_RESET_STATUS),
 612         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 613                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 614         .sysc_fields    = &omap_hwmod_sysc_type1,
 615 };
 616
 617 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 618         .name   = "dispc",
 619         .sysc   = &omap44xx_dispc_sysc,
 620 };
 621
 622 /* dss_dispc */
 623 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
 624         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
 625         { .irq = -1 }
 626 };
 627
 628 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
 629         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
 630         { .dma_req = -1 }
 631 };
 632
 633 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 634         .manager_count          = 3,
 635         .has_framedonetv_irq    = 1
 636 };
 637
 638 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 639         .name           = "dss_dispc",
 640         .class          = &omap44xx_dispc_hwmod_class,
 641         .clkdm_name     = "l3_dss_clkdm",
 642         .mpu_irqs       = omap44xx_dss_dispc_irqs,
 643         .xlate_irq      = omap4_xlate_irq,
 644         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
 645         .main_clk       = "dss_dss_clk",
 646         .prcm = {
 647                 .omap4 = {
 648                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 649                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 650                 },
 651         },
 652         .dev_attr       = &omap44xx_dss_dispc_dev_attr,
 653         .parent_hwmod   = &omap44xx_dss_hwmod,
 654 };
 655
 656 /*
 657  * 'dsi' class
 658  * display serial interface controller
 659  */
 660
 661 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 662         .rev_offs       = 0x0000,
 663         .sysc_offs      = 0x0010,
 664         .syss_offs      = 0x0014,
 665         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 666                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 667                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 668         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 669         .sysc_fields    = &omap_hwmod_sysc_type1,
 670 };
 671
 672 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 673         .name   = "dsi",
 674         .sysc   = &omap44xx_dsi_sysc,
 675 };
 676
 677 /* dss_dsi1 */
 678 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
 679         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
 680         { .irq = -1 }
 681 };
 682
 683 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
 684         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
 685         { .dma_req = -1 }
 686 };
 687
 688 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 689         { .role = "sys_clk", .clk = "dss_sys_clk" },
 690 };
 691
 692 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 693         .name           = "dss_dsi1",
 694         .class          = &omap44xx_dsi_hwmod_class,
 695         .clkdm_name     = "l3_dss_clkdm",
 696         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
 697         .xlate_irq      = omap4_xlate_irq,
 698         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
 699         .main_clk       = "dss_dss_clk",
 700         .prcm = {
 701                 .omap4 = {
 702                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 703                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 704                 },
 705         },
 706         .opt_clks       = dss_dsi1_opt_clks,
 707         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 708         .parent_hwmod   = &omap44xx_dss_hwmod,
 709 };
 710
 711 /* dss_dsi2 */
 712 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
 713         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
 714         { .irq = -1 }
 715 };
 716
 717 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
 718         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
 719         { .dma_req = -1 }
 720 };
 721
 722 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 723         { .role = "sys_clk", .clk = "dss_sys_clk" },
 724 };
 725
 726 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 727         .name           = "dss_dsi2",
 728         .class          = &omap44xx_dsi_hwmod_class,
 729         .clkdm_name     = "l3_dss_clkdm",
 730         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
 731         .xlate_irq      = omap4_xlate_irq,
 732         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
 733         .main_clk       = "dss_dss_clk",
 734         .prcm = {
 735                 .omap4 = {
 736                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 737                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 738                 },
 739         },
 740         .opt_clks       = dss_dsi2_opt_clks,
 741         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 742         .parent_hwmod   = &omap44xx_dss_hwmod,
 743 };
 744
 745 /*
 746  * 'hdmi' class
 747  * hdmi controller
 748  */
 749
 750 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 751         .rev_offs       = 0x0000,
 752         .sysc_offs      = 0x0010,
 753         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 754                            SYSC_HAS_SOFTRESET),
 755         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 756                            SIDLE_SMART_WKUP),
 757         .sysc_fields    = &omap_hwmod_sysc_type2,
 758 };
 759
 760 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 761         .name   = "hdmi",
 762         .sysc   = &omap44xx_hdmi_sysc,
 763 };
 764
 765 /* dss_hdmi */
 766 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
 767         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
 768         { .irq = -1 }
 769 };
 770
 771 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
 772         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
 773         { .dma_req = -1 }
 774 };
 775
 776 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 777         { .role = "sys_clk", .clk = "dss_sys_clk" },
 778 };
 779
 780 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 781         .name           = "dss_hdmi",
 782         .class          = &omap44xx_hdmi_hwmod_class,
 783         .clkdm_name     = "l3_dss_clkdm",
 784         /*
 785          * HDMI audio requires to use no-idle mode. Hence,
 786          * set idle mode by software.
 787          */
 788         .flags          = HWMOD_SWSUP_SIDLE,
 789         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
 790         .xlate_irq      = omap4_xlate_irq,
 791         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
 792         .main_clk       = "dss_48mhz_clk",
 793         .prcm = {
 794                 .omap4 = {
 795                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 796                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 797                 },
 798         },
 799         .opt_clks       = dss_hdmi_opt_clks,
 800         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 801         .parent_hwmod   = &omap44xx_dss_hwmod,
 802 };
 803
 804 /*
 805  * 'rfbi' class
 806  * remote frame buffer interface
 807  */
 808
 809 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 810         .rev_offs       = 0x0000,
 811         .sysc_offs      = 0x0010,
 812         .syss_offs      = 0x0014,
 813         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 814                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 815         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 816         .sysc_fields    = &omap_hwmod_sysc_type1,
 817 };
 818
 819 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 820         .name   = "rfbi",
 821         .sysc   = &omap44xx_rfbi_sysc,
 822 };
 823
 824 /* dss_rfbi */
 825 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
 826         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
 827         { .dma_req = -1 }
 828 };
 829
 830 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 831         { .role = "ick", .clk = "l3_div_ck" },
 832 };
 833
 834 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 835         .name           = "dss_rfbi",
 836         .class          = &omap44xx_rfbi_hwmod_class,
 837         .clkdm_name     = "l3_dss_clkdm",
 838         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
 839         .main_clk       = "dss_dss_clk",
 840         .prcm = {
 841                 .omap4 = {
 842                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 843                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 844                 },
 845         },
 846         .opt_clks       = dss_rfbi_opt_clks,
 847         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 848         .parent_hwmod   = &omap44xx_dss_hwmod,
 849 };
 850
 851 /*
 852  * 'venc' class
 853  * video encoder
 854  */
 855
 856 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 857         .name   = "venc",
 858 };
 859
 860 /* dss_venc */
 861 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 862         .name           = "dss_venc",
 863         .class          = &omap44xx_venc_hwmod_class,
 864         .clkdm_name     = "l3_dss_clkdm",
 865         .main_clk       = "dss_tv_clk",
 866         .prcm = {
 867                 .omap4 = {
 868                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 869                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 870                 },
 871         },
 872         .parent_hwmod   = &omap44xx_dss_hwmod,
 873 };
 874
 875 /*
 876  * 'elm' class
 877  * bch error location module
 878  */
 879
 880 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 881         .rev_offs       = 0x0000,
 882         .sysc_offs      = 0x0010,
 883         .syss_offs      = 0x0014,
 884         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 885                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 886                            SYSS_HAS_RESET_STATUS),
 887         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 888         .sysc_fields    = &omap_hwmod_sysc_type1,
 889 };
 890
 891 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 892         .name   = "elm",
 893         .sysc   = &omap44xx_elm_sysc,
 894 };
 895
 896 /* elm */
 897 static struct omap_hwmod omap44xx_elm_hwmod = {
 898         .name           = "elm",
 899         .class          = &omap44xx_elm_hwmod_class,
 900         .clkdm_name     = "l4_per_clkdm",
 901         .prcm = {
 902                 .omap4 = {
 903                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
 904                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
 905                 },
 906         },
 907 };
 908
 909 /*
 910  * 'emif' class
 911  * external memory interface no1
 912  */
 913
 914 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
 915         .rev_offs       = 0x0000,
 916 };
 917
 918 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
 919         .name   = "emif",
 920         .sysc   = &omap44xx_emif_sysc,
 921 };
 922
 923 /* emif1 */
 924 static struct omap_hwmod omap44xx_emif1_hwmod = {
 925         .name           = "emif1",
 926         .class          = &omap44xx_emif_hwmod_class,
 927         .clkdm_name     = "l3_emif_clkdm",
 928         .flags          = HWMOD_INIT_NO_IDLE,
 929         .main_clk       = "ddrphy_ck",
 930         .prcm = {
 931                 .omap4 = {
 932                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
 933                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
 934                         .modulemode   = MODULEMODE_HWCTRL,
 935                 },
 936         },
 937 };
 938
 939 /* emif2 */
 940 static struct omap_hwmod omap44xx_emif2_hwmod = {
 941         .name           = "emif2",
 942         .class          = &omap44xx_emif_hwmod_class,
 943         .clkdm_name     = "l3_emif_clkdm",
 944         .flags          = HWMOD_INIT_NO_IDLE,
 945         .main_clk       = "ddrphy_ck",
 946         .prcm = {
 947                 .omap4 = {
 948                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
 949                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
 950                         .modulemode   = MODULEMODE_HWCTRL,
 951                 },
 952         },
 953 };
 954
 955 /*
 956  * 'fdif' class
 957  * face detection hw accelerator module
 958  */
 959
 960 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
 961         .rev_offs       = 0x0000,
 962         .sysc_offs      = 0x0010,
 963         /*
 964          * FDIF needs 100 OCP clk cycles delay after a softreset before
 965          * accessing sysconfig again.
 966          * The lowest frequency at the moment for L3 bus is 100 MHz, so
 967          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
 968          *
 969          * TODO: Indicate errata when available.
 970          */
 971         .srst_udelay    = 2,
 972         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
 973                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 974         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 975                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 976         .sysc_fields    = &omap_hwmod_sysc_type2,
 977 };
 978
 979 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
 980         .name   = "fdif",
 981         .sysc   = &omap44xx_fdif_sysc,
 982 };
 983
 984 /* fdif */
 985 static struct omap_hwmod omap44xx_fdif_hwmod = {
 986         .name           = "fdif",
 987         .class          = &omap44xx_fdif_hwmod_class,
 988         .clkdm_name     = "iss_clkdm",
 989         .main_clk       = "fdif_fck",
 990         .prcm = {
 991                 .omap4 = {
 992                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
 993                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
 994                         .modulemode   = MODULEMODE_SWCTRL,
 995                 },
 996         },
 997 };
 998
 999 /*
1000  * 'gpio' class
1001  * general purpose io module
1002  */
1003
1004 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1005         .rev_offs       = 0x0000,
1006         .sysc_offs      = 0x0010,
1007         .syss_offs      = 0x0114,
1008         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1009                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1010                            SYSS_HAS_RESET_STATUS),
1011         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1012                            SIDLE_SMART_WKUP),
1013         .sysc_fields    = &omap_hwmod_sysc_type1,
1014 };
1015
1016 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1017         .name   = "gpio",
1018         .sysc   = &omap44xx_gpio_sysc,
1019         .rev    = 2,
1020 };
1021
1022 /* gpio dev_attr */
1023 static struct omap_gpio_dev_attr gpio_dev_attr = {
1024         .bank_width     = 32,
1025         .dbck_flag      = true,
1026 };
1027
1028 /* gpio1 */
1029 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1030         { .role = "dbclk", .clk = "gpio1_dbclk" },
1031 };
1032
1033 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1034         .name           = "gpio1",
1035         .class          = &omap44xx_gpio_hwmod_class,
1036         .clkdm_name     = "l4_wkup_clkdm",
1037         .main_clk       = "l4_wkup_clk_mux_ck",
1038         .prcm = {
1039                 .omap4 = {
1040                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1041                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1042                         .modulemode   = MODULEMODE_HWCTRL,
1043                 },
1044         },
1045         .opt_clks       = gpio1_opt_clks,
1046         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1047         .dev_attr       = &gpio_dev_attr,
1048 };
1049
1050 /* gpio2 */
1051 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1052         { .role = "dbclk", .clk = "gpio2_dbclk" },
1053 };
1054
1055 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1056         .name           = "gpio2",
1057         .class          = &omap44xx_gpio_hwmod_class,
1058         .clkdm_name     = "l4_per_clkdm",
1059         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1060         .main_clk       = "l4_div_ck",
1061         .prcm = {
1062                 .omap4 = {
1063                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1064                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1065                         .modulemode   = MODULEMODE_HWCTRL,
1066                 },
1067         },
1068         .opt_clks       = gpio2_opt_clks,
1069         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1070         .dev_attr       = &gpio_dev_attr,
1071 };
1072
1073 /* gpio3 */
1074 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1075         { .role = "dbclk", .clk = "gpio3_dbclk" },
1076 };
1077
1078 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1079         .name           = "gpio3",
1080         .class          = &omap44xx_gpio_hwmod_class,
1081         .clkdm_name     = "l4_per_clkdm",
1082         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1083         .main_clk       = "l4_div_ck",
1084         .prcm = {
1085                 .omap4 = {
1086                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1087                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1088                         .modulemode   = MODULEMODE_HWCTRL,
1089                 },
1090         },
1091         .opt_clks       = gpio3_opt_clks,
1092         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1093         .dev_attr       = &gpio_dev_attr,
1094 };
1095
1096 /* gpio4 */
1097 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1098         { .role = "dbclk", .clk = "gpio4_dbclk" },
1099 };
1100
1101 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1102         .name           = "gpio4",
1103         .class          = &omap44xx_gpio_hwmod_class,
1104         .clkdm_name     = "l4_per_clkdm",
1105         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1106         .main_clk       = "l4_div_ck",
1107         .prcm = {
1108                 .omap4 = {
1109                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1110                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1111                         .modulemode   = MODULEMODE_HWCTRL,
1112                 },
1113         },
1114         .opt_clks       = gpio4_opt_clks,
1115         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1116         .dev_attr       = &gpio_dev_attr,
1117 };
1118
1119 /* gpio5 */
1120 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1121         { .role = "dbclk", .clk = "gpio5_dbclk" },
1122 };
1123
1124 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1125         .name           = "gpio5",
1126         .class          = &omap44xx_gpio_hwmod_class,
1127         .clkdm_name     = "l4_per_clkdm",
1128         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1129         .main_clk       = "l4_div_ck",
1130         .prcm = {
1131                 .omap4 = {
1132                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1133                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1134                         .modulemode   = MODULEMODE_HWCTRL,
1135                 },
1136         },
1137         .opt_clks       = gpio5_opt_clks,
1138         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1139         .dev_attr       = &gpio_dev_attr,
1140 };
1141
1142 /* gpio6 */
1143 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1144         { .role = "dbclk", .clk = "gpio6_dbclk" },
1145 };
1146
1147 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1148         .name           = "gpio6",
1149         .class          = &omap44xx_gpio_hwmod_class,
1150         .clkdm_name     = "l4_per_clkdm",
1151         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1152         .main_clk       = "l4_div_ck",
1153         .prcm = {
1154                 .omap4 = {
1155                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1156                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1157                         .modulemode   = MODULEMODE_HWCTRL,
1158                 },
1159         },
1160         .opt_clks       = gpio6_opt_clks,
1161         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1162         .dev_attr       = &gpio_dev_attr,
1163 };
1164
1165 /*
1166  * 'gpmc' class
1167  * general purpose memory controller
1168  */
1169
1170 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1171         .rev_offs       = 0x0000,
1172         .sysc_offs      = 0x0010,
1173         .syss_offs      = 0x0014,
1174         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1175                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1176         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1177         .sysc_fields    = &omap_hwmod_sysc_type1,
1178 };
1179
1180 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1181         .name   = "gpmc",
1182         .sysc   = &omap44xx_gpmc_sysc,
1183 };
1184
1185 /* gpmc */
1186 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1187         .name           = "gpmc",
1188         .class          = &omap44xx_gpmc_hwmod_class,
1189         .clkdm_name     = "l3_2_clkdm",
1190         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
1191         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
1192         .prcm = {
1193                 .omap4 = {
1194                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1195                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1196                         .modulemode   = MODULEMODE_HWCTRL,
1197                 },
1198         },
1199 };
1200
1201 /*
1202  * 'gpu' class
1203  * 2d/3d graphics accelerator
1204  */
1205
1206 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1207         .rev_offs       = 0x1fc00,
1208         .sysc_offs      = 0x1fc10,
1209         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1210         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1211                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1212                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1213         .sysc_fields    = &omap_hwmod_sysc_type2,
1214 };
1215
1216 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1217         .name   = "gpu",
1218         .sysc   = &omap44xx_gpu_sysc,
1219 };
1220
1221 /* gpu */
1222 static struct omap_hwmod omap44xx_gpu_hwmod = {
1223         .name           = "gpu",
1224         .class          = &omap44xx_gpu_hwmod_class,
1225         .clkdm_name     = "l3_gfx_clkdm",
1226         .main_clk       = "sgx_clk_mux",
1227         .prcm = {
1228                 .omap4 = {
1229                         .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1230                         .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1231                         .modulemode   = MODULEMODE_SWCTRL,
1232                 },
1233         },
1234 };
1235
1236 /*
1237  * 'hdq1w' class
1238  * hdq / 1-wire serial interface controller
1239  */
1240
1241 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1242         .rev_offs       = 0x0000,
1243         .sysc_offs      = 0x0014,
1244         .syss_offs      = 0x0018,
1245         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1246                            SYSS_HAS_RESET_STATUS),
1247         .sysc_fields    = &omap_hwmod_sysc_type1,
1248 };
1249
1250 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1251         .name   = "hdq1w",
1252         .sysc   = &omap44xx_hdq1w_sysc,
1253 };
1254
1255 /* hdq1w */
1256 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1257         .name           = "hdq1w",
1258         .class          = &omap44xx_hdq1w_hwmod_class,
1259         .clkdm_name     = "l4_per_clkdm",
1260         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1261         .main_clk       = "func_12m_fclk",
1262         .prcm = {
1263                 .omap4 = {
1264                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1265                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1266                         .modulemode   = MODULEMODE_SWCTRL,
1267                 },
1268         },
1269 };
1270
1271 /*
1272  * 'hsi' class
1273  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1274  * serial if)
1275  */
1276
1277 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1278         .rev_offs       = 0x0000,
1279         .sysc_offs      = 0x0010,
1280         .syss_offs      = 0x0014,
1281         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1282                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1283                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1284         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1285                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1286                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1287         .sysc_fields    = &omap_hwmod_sysc_type1,
1288 };
1289
1290 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1291         .name   = "hsi",
1292         .sysc   = &omap44xx_hsi_sysc,
1293 };
1294
1295 /* hsi */
1296 static struct omap_hwmod omap44xx_hsi_hwmod = {
1297         .name           = "hsi",
1298         .class          = &omap44xx_hsi_hwmod_class,
1299         .clkdm_name     = "l3_init_clkdm",
1300         .main_clk       = "hsi_fck",
1301         .prcm = {
1302                 .omap4 = {
1303                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1304                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1305                         .modulemode   = MODULEMODE_HWCTRL,
1306                 },
1307         },
1308 };
1309
1310 /*
1311  * 'i2c' class
1312  * multimaster high-speed i2c controller
1313  */
1314
1315 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1316         .sysc_offs      = 0x0010,
1317         .syss_offs      = 0x0090,
1318         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1319                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1320                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1321         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1322                            SIDLE_SMART_WKUP),
1323         .sysc_fields    = &omap_hwmod_sysc_type1,
1324 };
1325
1326 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1327         .name   = "i2c",
1328         .sysc   = &omap44xx_i2c_sysc,
1329         .rev    = OMAP_I2C_IP_VERSION_2,
1330         .reset  = &omap_i2c_reset,
1331 };
1332
1333 static struct omap_i2c_dev_attr i2c_dev_attr = {
1334         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1335 };
1336
1337 /* i2c1 */
1338 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1339         .name           = "i2c1",
1340         .class          = &omap44xx_i2c_hwmod_class,
1341         .clkdm_name     = "l4_per_clkdm",
1342         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1343         .main_clk       = "func_96m_fclk",
1344         .prcm = {
1345                 .omap4 = {
1346                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1347                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1348                         .modulemode   = MODULEMODE_SWCTRL,
1349                 },
1350         },
1351         .dev_attr       = &i2c_dev_attr,
1352 };
1353
1354 /* i2c2 */
1355 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1356         .name           = "i2c2",
1357         .class          = &omap44xx_i2c_hwmod_class,
1358         .clkdm_name     = "l4_per_clkdm",
1359         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1360         .main_clk       = "func_96m_fclk",
1361         .prcm = {
1362                 .omap4 = {
1363                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1364                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1365                         .modulemode   = MODULEMODE_SWCTRL,
1366                 },
1367         },
1368         .dev_attr       = &i2c_dev_attr,
1369 };
1370
1371 /* i2c3 */
1372 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1373         .name           = "i2c3",
1374         .class          = &omap44xx_i2c_hwmod_class,
1375         .clkdm_name     = "l4_per_clkdm",
1376         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1377         .main_clk       = "func_96m_fclk",
1378         .prcm = {
1379                 .omap4 = {
1380                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1381                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1382                         .modulemode   = MODULEMODE_SWCTRL,
1383                 },
1384         },
1385         .dev_attr       = &i2c_dev_attr,
1386 };
1387
1388 /* i2c4 */
1389 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1390         .name           = "i2c4",
1391         .class          = &omap44xx_i2c_hwmod_class,
1392         .clkdm_name     = "l4_per_clkdm",
1393         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1394         .main_clk       = "func_96m_fclk",
1395         .prcm = {
1396                 .omap4 = {
1397                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1398                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1399                         .modulemode   = MODULEMODE_SWCTRL,
1400                 },
1401         },
1402         .dev_attr       = &i2c_dev_attr,
1403 };
1404
1405 /*
1406  * 'ipu' class
1407  * imaging processor unit
1408  */
1409
1410 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1411         .name   = "ipu",
1412 };
1413
1414 /* ipu */
1415 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1416         { .name = "cpu0", .rst_shift = 0 },
1417         { .name = "cpu1", .rst_shift = 1 },
1418 };
1419
1420 static struct omap_hwmod omap44xx_ipu_hwmod = {
1421         .name           = "ipu",
1422         .class          = &omap44xx_ipu_hwmod_class,
1423         .clkdm_name     = "ducati_clkdm",
1424         .rst_lines      = omap44xx_ipu_resets,
1425         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1426         .main_clk       = "ducati_clk_mux_ck",
1427         .prcm = {
1428                 .omap4 = {
1429                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1430                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1431                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1432                         .modulemode   = MODULEMODE_HWCTRL,
1433                 },
1434         },
1435 };
1436
1437 /*
1438  * 'iss' class
1439  * external images sensor pixel data processor
1440  */
1441
1442 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1443         .rev_offs       = 0x0000,
1444         .sysc_offs      = 0x0010,
1445         /*
1446          * ISS needs 100 OCP clk cycles delay after a softreset before
1447          * accessing sysconfig again.
1448          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1449          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1450          *
1451          * TODO: Indicate errata when available.
1452          */
1453         .srst_udelay    = 2,
1454         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1455                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1456         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1457                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1458                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1459         .sysc_fields    = &omap_hwmod_sysc_type2,
1460 };
1461
1462 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1463         .name   = "iss",
1464         .sysc   = &omap44xx_iss_sysc,
1465 };
1466
1467 /* iss */
1468 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1469         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1470 };
1471
1472 static struct omap_hwmod omap44xx_iss_hwmod = {
1473         .name           = "iss",
1474         .class          = &omap44xx_iss_hwmod_class,
1475         .clkdm_name     = "iss_clkdm",
1476         .main_clk       = "ducati_clk_mux_ck",
1477         .prcm = {
1478                 .omap4 = {
1479                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1480                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1481                         .modulemode   = MODULEMODE_SWCTRL,
1482                 },
1483         },
1484         .opt_clks       = iss_opt_clks,
1485         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1486 };
1487
1488 /*
1489  * 'iva' class
1490  * multi-standard video encoder/decoder hardware accelerator
1491  */
1492
1493 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1494         .name   = "iva",
1495 };
1496
1497 /* iva */
1498 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1499         { .name = "seq0", .rst_shift = 0 },
1500         { .name = "seq1", .rst_shift = 1 },
1501         { .name = "logic", .rst_shift = 2 },
1502 };
1503
1504 static struct omap_hwmod omap44xx_iva_hwmod = {
1505         .name           = "iva",
1506         .class          = &omap44xx_iva_hwmod_class,
1507         .clkdm_name     = "ivahd_clkdm",
1508         .rst_lines      = omap44xx_iva_resets,
1509         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1510         .main_clk       = "dpll_iva_m5x2_ck",
1511         .prcm = {
1512                 .omap4 = {
1513                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1514                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1515                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1516                         .modulemode   = MODULEMODE_HWCTRL,
1517                 },
1518         },
1519 };
1520
1521 /*
1522  * 'kbd' class
1523  * keyboard controller
1524  */
1525
1526 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1527         .rev_offs       = 0x0000,
1528         .sysc_offs      = 0x0010,
1529         .syss_offs      = 0x0014,
1530         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1531                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1532                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1533                            SYSS_HAS_RESET_STATUS),
1534         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1535         .sysc_fields    = &omap_hwmod_sysc_type1,
1536 };
1537
1538 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1539         .name   = "kbd",
1540         .sysc   = &omap44xx_kbd_sysc,
1541 };
1542
1543 /* kbd */
1544 static struct omap_hwmod omap44xx_kbd_hwmod = {
1545         .name           = "kbd",
1546         .class          = &omap44xx_kbd_hwmod_class,
1547         .clkdm_name     = "l4_wkup_clkdm",
1548         .main_clk       = "sys_32k_ck",
1549         .prcm = {
1550                 .omap4 = {
1551                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1552                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1553                         .modulemode   = MODULEMODE_SWCTRL,
1554                 },
1555         },
1556 };
1557
1558 /*
1559  * 'mailbox' class
1560  * mailbox module allowing communication between the on-chip processors using a
1561  * queued mailbox-interrupt mechanism.
1562  */
1563
1564 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1565         .rev_offs       = 0x0000,
1566         .sysc_offs      = 0x0010,
1567         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1568                            SYSC_HAS_SOFTRESET),
1569         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1570         .sysc_fields    = &omap_hwmod_sysc_type2,
1571 };
1572
1573 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1574         .name   = "mailbox",
1575         .sysc   = &omap44xx_mailbox_sysc,
1576 };
1577
1578 /* mailbox */
1579 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1580         .name           = "mailbox",
1581         .class          = &omap44xx_mailbox_hwmod_class,
1582         .clkdm_name     = "l4_cfg_clkdm",
1583         .prcm = {
1584                 .omap4 = {
1585                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1586                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1587                 },
1588         },
1589 };
1590
1591 /*
1592  * 'mcasp' class
1593  * multi-channel audio serial port controller
1594  */
1595
1596 /* The IP is not compliant to type1 / type2 scheme */
1597 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1598         .sidle_shift    = 0,
1599 };
1600
1601 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1602         .sysc_offs      = 0x0004,
1603         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1604         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1605                            SIDLE_SMART_WKUP),
1606         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1607 };
1608
1609 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1610         .name   = "mcasp",
1611         .sysc   = &omap44xx_mcasp_sysc,
1612 };
1613
1614 /* mcasp */
1615 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1616         .name           = "mcasp",
1617         .class          = &omap44xx_mcasp_hwmod_class,
1618         .clkdm_name     = "abe_clkdm",
1619         .main_clk       = "func_mcasp_abe_gfclk",
1620         .prcm = {
1621                 .omap4 = {
1622                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1623                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1624                         .modulemode   = MODULEMODE_SWCTRL,
1625                 },
1626         },
1627 };
1628
1629 /*
1630  * 'mcbsp' class
1631  * multi channel buffered serial port controller
1632  */
1633
1634 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1635         .sysc_offs      = 0x008c,
1636         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1637                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1638         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1639         .sysc_fields    = &omap_hwmod_sysc_type1,
1640 };
1641
1642 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1643         .name   = "mcbsp",
1644         .sysc   = &omap44xx_mcbsp_sysc,
1645         .rev    = MCBSP_CONFIG_TYPE4,
1646 };
1647
1648 /* mcbsp1 */
1649 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1650         { .role = "pad_fck", .clk = "pad_clks_ck" },
1651         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1652 };
1653
1654 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1655         .name           = "mcbsp1",
1656         .class          = &omap44xx_mcbsp_hwmod_class,
1657         .clkdm_name     = "abe_clkdm",
1658         .main_clk       = "func_mcbsp1_gfclk",
1659         .prcm = {
1660                 .omap4 = {
1661                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1662                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1663                         .modulemode   = MODULEMODE_SWCTRL,
1664                 },
1665         },
1666         .opt_clks       = mcbsp1_opt_clks,
1667         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1668 };
1669
1670 /* mcbsp2 */
1671 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1672         { .role = "pad_fck", .clk = "pad_clks_ck" },
1673         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1674 };
1675
1676 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
1677         .name           = "mcbsp2",
1678         .class          = &omap44xx_mcbsp_hwmod_class,
1679         .clkdm_name     = "abe_clkdm",
1680         .main_clk       = "func_mcbsp2_gfclk",
1681         .prcm = {
1682                 .omap4 = {
1683                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
1684                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1685                         .modulemode   = MODULEMODE_SWCTRL,
1686                 },
1687         },
1688         .opt_clks       = mcbsp2_opt_clks,
1689         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
1690 };
1691
1692 /* mcbsp3 */
1693 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
1694         { .role = "pad_fck", .clk = "pad_clks_ck" },
1695         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
1696 };
1697
1698 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
1699         .name           = "mcbsp3",
1700         .class          = &omap44xx_mcbsp_hwmod_class,
1701         .clkdm_name     = "abe_clkdm",
1702         .main_clk       = "func_mcbsp3_gfclk",
1703         .prcm = {
1704                 .omap4 = {
1705                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
1706                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
1707                         .modulemode   = MODULEMODE_SWCTRL,
1708                 },
1709         },
1710         .opt_clks       = mcbsp3_opt_clks,
1711         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
1712 };
1713
1714 /* mcbsp4 */
1715 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
1716         { .role = "pad_fck", .clk = "pad_clks_ck" },
1717         { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
1718 };
1719
1720 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
1721         .name           = "mcbsp4",
1722         .class          = &omap44xx_mcbsp_hwmod_class,
1723         .clkdm_name     = "l4_per_clkdm",
1724         .main_clk       = "per_mcbsp4_gfclk",
1725         .prcm = {
1726                 .omap4 = {
1727                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
1728                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
1729                         .modulemode   = MODULEMODE_SWCTRL,
1730                 },
1731         },
1732         .opt_clks       = mcbsp4_opt_clks,
1733         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
1734 };
1735
1736 /*
1737  * 'mcpdm' class
1738  * multi channel pdm controller (proprietary interface with phoenix power
1739  * ic)
1740  */
1741
1742 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
1743         .rev_offs       = 0x0000,
1744         .sysc_offs      = 0x0010,
1745         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1746                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1747         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1748                            SIDLE_SMART_WKUP),
1749         .sysc_fields    = &omap_hwmod_sysc_type2,
1750 };
1751
1752 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
1753         .name   = "mcpdm",
1754         .sysc   = &omap44xx_mcpdm_sysc,
1755 };
1756
1757 /* mcpdm */
1758 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
1759         .name           = "mcpdm",
1760         .class          = &omap44xx_mcpdm_hwmod_class,
1761         .clkdm_name     = "abe_clkdm",
1762         /*
1763          * It's suspected that the McPDM requires an off-chip main
1764          * functional clock, controlled via I2C.  This IP block is
1765          * currently reset very early during boot, before I2C is
1766          * available, so it doesn't seem that we have any choice in
1767          * the kernel other than to avoid resetting it.
1768          *
1769          * Also, McPDM needs to be configured to NO_IDLE mode when it
1770          * is in used otherwise vital clocks will be gated which
1771          * results 'slow motion' audio playback.
1772          */
1773         .flags          = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
1774         .main_clk       = "pad_clks_ck",
1775         .prcm = {
1776                 .omap4 = {
1777                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
1778                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
1779                         .modulemode   = MODULEMODE_SWCTRL,
1780                 },
1781         },
1782 };
1783
1784 /*
1785  * 'mcspi' class
1786  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1787  * bus
1788  */
1789
1790 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
1791         .rev_offs       = 0x0000,
1792         .sysc_offs      = 0x0010,
1793         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1794                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1795         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1796                            SIDLE_SMART_WKUP),
1797         .sysc_fields    = &omap_hwmod_sysc_type2,
1798 };
1799
1800 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
1801         .name   = "mcspi",
1802         .sysc   = &omap44xx_mcspi_sysc,
1803         .rev    = OMAP4_MCSPI_REV,
1804 };
1805
1806 /* mcspi1 */
1807 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
1808         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
1809         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
1810         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
1811         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
1812         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
1813         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
1814         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
1815         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
1816         { .dma_req = -1 }
1817 };
1818
1819 /* mcspi1 dev_attr */
1820 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1821         .num_chipselect = 4,
1822 };
1823
1824 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
1825         .name           = "mcspi1",
1826         .class          = &omap44xx_mcspi_hwmod_class,
1827         .clkdm_name     = "l4_per_clkdm",
1828         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
1829         .main_clk       = "func_48m_fclk",
1830         .prcm = {
1831                 .omap4 = {
1832                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1833                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1834                         .modulemode   = MODULEMODE_SWCTRL,
1835                 },
1836         },
1837         .dev_attr       = &mcspi1_dev_attr,
1838 };
1839
1840 /* mcspi2 */
1841 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
1842         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
1843         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
1844         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
1845         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
1846         { .dma_req = -1 }
1847 };
1848
1849 /* mcspi2 dev_attr */
1850 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1851         .num_chipselect = 2,
1852 };
1853
1854 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
1855         .name           = "mcspi2",
1856         .class          = &omap44xx_mcspi_hwmod_class,
1857         .clkdm_name     = "l4_per_clkdm",
1858         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
1859         .main_clk       = "func_48m_fclk",
1860         .prcm = {
1861                 .omap4 = {
1862                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1863                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1864                         .modulemode   = MODULEMODE_SWCTRL,
1865                 },
1866         },
1867         .dev_attr       = &mcspi2_dev_attr,
1868 };
1869
1870 /* mcspi3 */
1871 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
1872         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
1873         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
1874         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
1875         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
1876         { .dma_req = -1 }
1877 };
1878
1879 /* mcspi3 dev_attr */
1880 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1881         .num_chipselect = 2,
1882 };
1883
1884 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
1885         .name           = "mcspi3",
1886         .class          = &omap44xx_mcspi_hwmod_class,
1887         .clkdm_name     = "l4_per_clkdm",
1888         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
1889         .main_clk       = "func_48m_fclk",
1890         .prcm = {
1891                 .omap4 = {
1892                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1893                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1894                         .modulemode   = MODULEMODE_SWCTRL,
1895                 },
1896         },
1897         .dev_attr       = &mcspi3_dev_attr,
1898 };
1899
1900 /* mcspi4 */
1901 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
1902         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
1903         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
1904         { .dma_req = -1 }
1905 };
1906
1907 /* mcspi4 dev_attr */
1908 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1909         .num_chipselect = 1,
1910 };
1911
1912 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
1913         .name           = "mcspi4",
1914         .class          = &omap44xx_mcspi_hwmod_class,
1915         .clkdm_name     = "l4_per_clkdm",
1916         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
1917         .main_clk       = "func_48m_fclk",
1918         .prcm = {
1919                 .omap4 = {
1920                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1921                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1922                         .modulemode   = MODULEMODE_SWCTRL,
1923                 },
1924         },
1925         .dev_attr       = &mcspi4_dev_attr,
1926 };
1927
1928 /*
1929  * 'mmc' class
1930  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
1931  */
1932
1933 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
1934         .rev_offs       = 0x0000,
1935         .sysc_offs      = 0x0010,
1936         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1937                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1938                            SYSC_HAS_SOFTRESET),
1939         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1940                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1941                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1942         .sysc_fields    = &omap_hwmod_sysc_type2,
1943 };
1944
1945 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
1946         .name   = "mmc",
1947         .sysc   = &omap44xx_mmc_sysc,
1948 };
1949
1950 /* mmc1 */
1951 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
1952         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
1953         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
1954         { .dma_req = -1 }
1955 };
1956
1957 /* mmc1 dev_attr */
1958 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1959         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1960 };
1961
1962 static struct omap_hwmod omap44xx_mmc1_hwmod = {
1963         .name           = "mmc1",
1964         .class          = &omap44xx_mmc_hwmod_class,
1965         .clkdm_name     = "l3_init_clkdm",
1966         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
1967         .main_clk       = "hsmmc1_fclk",
1968         .prcm = {
1969                 .omap4 = {
1970                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1971                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1972                         .modulemode   = MODULEMODE_SWCTRL,
1973                 },
1974         },
1975         .dev_attr       = &mmc1_dev_attr,
1976 };
1977
1978 /* mmc2 */
1979 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
1980         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
1981         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
1982         { .dma_req = -1 }
1983 };
1984
1985 static struct omap_hwmod omap44xx_mmc2_hwmod = {
1986         .name           = "mmc2",
1987         .class          = &omap44xx_mmc_hwmod_class,
1988         .clkdm_name     = "l3_init_clkdm",
1989         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
1990         .main_clk       = "hsmmc2_fclk",
1991         .prcm = {
1992                 .omap4 = {
1993                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1994                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1995                         .modulemode   = MODULEMODE_SWCTRL,
1996                 },
1997         },
1998 };
1999
2000 /* mmc3 */
2001 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2002         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2003         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2004         { .dma_req = -1 }
2005 };
2006
2007 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2008         .name           = "mmc3",
2009         .class          = &omap44xx_mmc_hwmod_class,
2010         .clkdm_name     = "l4_per_clkdm",
2011         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
2012         .main_clk       = "func_48m_fclk",
2013         .prcm = {
2014                 .omap4 = {
2015                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2016                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2017                         .modulemode   = MODULEMODE_SWCTRL,
2018                 },
2019         },
2020 };
2021
2022 /* mmc4 */
2023 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2024         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2025         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2026         { .dma_req = -1 }
2027 };
2028
2029 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2030         .name           = "mmc4",
2031         .class          = &omap44xx_mmc_hwmod_class,
2032         .clkdm_name     = "l4_per_clkdm",
2033         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
2034         .main_clk       = "func_48m_fclk",
2035         .prcm = {
2036                 .omap4 = {
2037                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2038                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2039                         .modulemode   = MODULEMODE_SWCTRL,
2040                 },
2041         },
2042 };
2043
2044 /* mmc5 */
2045 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2046         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2047         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2048         { .dma_req = -1 }
2049 };
2050
2051 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2052         .name           = "mmc5",
2053         .class          = &omap44xx_mmc_hwmod_class,
2054         .clkdm_name     = "l4_per_clkdm",
2055         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
2056         .main_clk       = "func_48m_fclk",
2057         .prcm = {
2058                 .omap4 = {
2059                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2060                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2061                         .modulemode   = MODULEMODE_SWCTRL,
2062                 },
2063         },
2064 };
2065
2066 /*
2067  * 'mmu' class
2068  * The memory management unit performs virtual to physical address translation
2069  * for its requestors.
2070  */
2071
2072 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2073         .rev_offs       = 0x000,
2074         .sysc_offs      = 0x010,
2075         .syss_offs      = 0x014,
2076         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2077                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2078         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2079         .sysc_fields    = &omap_hwmod_sysc_type1,
2080 };
2081
2082 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2083         .name = "mmu",
2084         .sysc = &mmu_sysc,
2085 };
2086
2087 /* mmu ipu */
2088
2089 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2090 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2091         { .name = "mmu_cache", .rst_shift = 2 },
2092 };
2093
2094 /* l3_main_2 -> mmu_ipu */
2095 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2096         .master         = &omap44xx_l3_main_2_hwmod,
2097         .slave          = &omap44xx_mmu_ipu_hwmod,
2098         .clk            = "l3_div_ck",
2099         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2100 };
2101
2102 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2103         .name           = "mmu_ipu",
2104         .class          = &omap44xx_mmu_hwmod_class,
2105         .clkdm_name     = "ducati_clkdm",
2106         .rst_lines      = omap44xx_mmu_ipu_resets,
2107         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2108         .main_clk       = "ducati_clk_mux_ck",
2109         .prcm = {
2110                 .omap4 = {
2111                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2112                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2113                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2114                         .modulemode   = MODULEMODE_HWCTRL,
2115                 },
2116         },
2117 };
2118
2119 /* mmu dsp */
2120
2121 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2122 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2123         { .name = "mmu_cache", .rst_shift = 1 },
2124 };
2125
2126 /* l4_cfg -> dsp */
2127 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2128         .master         = &omap44xx_l4_cfg_hwmod,
2129         .slave          = &omap44xx_mmu_dsp_hwmod,
2130         .clk            = "l4_div_ck",
2131         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2132 };
2133
2134 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2135         .name           = "mmu_dsp",
2136         .class          = &omap44xx_mmu_hwmod_class,
2137         .clkdm_name     = "tesla_clkdm",
2138         .rst_lines      = omap44xx_mmu_dsp_resets,
2139         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2140         .main_clk       = "dpll_iva_m4x2_ck",
2141         .prcm = {
2142                 .omap4 = {
2143                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2144                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2145                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2146                         .modulemode   = MODULEMODE_HWCTRL,
2147                 },
2148         },
2149 };
2150
2151 /*
2152  * 'mpu' class
2153  * mpu sub-system
2154  */
2155
2156 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2157         .name   = "mpu",
2158 };
2159
2160 /* mpu */
2161 static struct omap_hwmod omap44xx_mpu_hwmod = {
2162         .name           = "mpu",
2163         .class          = &omap44xx_mpu_hwmod_class,
2164         .clkdm_name     = "mpuss_clkdm",
2165         .flags          = HWMOD_INIT_NO_IDLE,
2166         .main_clk       = "dpll_mpu_m2_ck",
2167         .prcm = {
2168                 .omap4 = {
2169                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2170                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2171                 },
2172         },
2173 };
2174
2175 /*
2176  * 'ocmc_ram' class
2177  * top-level core on-chip ram
2178  */
2179
2180 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2181         .name   = "ocmc_ram",
2182 };
2183
2184 /* ocmc_ram */
2185 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2186         .name           = "ocmc_ram",
2187         .class          = &omap44xx_ocmc_ram_hwmod_class,
2188         .clkdm_name     = "l3_2_clkdm",
2189         .prcm = {
2190                 .omap4 = {
2191                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2192                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2193                 },
2194         },
2195 };
2196
2197 /*
2198  * 'ocp2scp' class
2199  * bridge to transform ocp interface protocol to scp (serial control port)
2200  * protocol
2201  */
2202
2203 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2204         .rev_offs       = 0x0000,
2205         .sysc_offs      = 0x0010,
2206         .syss_offs      = 0x0014,
2207         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2208                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2209         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2210         .sysc_fields    = &omap_hwmod_sysc_type1,
2211 };
2212
2213 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2214         .name   = "ocp2scp",
2215         .sysc   = &omap44xx_ocp2scp_sysc,
2216 };
2217
2218 /* ocp2scp_usb_phy */
2219 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2220         .name           = "ocp2scp_usb_phy",
2221         .class          = &omap44xx_ocp2scp_hwmod_class,
2222         .clkdm_name     = "l3_init_clkdm",
2223         /*
2224          * ocp2scp_usb_phy_phy_48m is provided by the OMAP4 PRCM IP
2225          * block as an "optional clock," and normally should never be
2226          * specified as the main_clk for an OMAP IP block.  However it
2227          * turns out that this clock is actually the main clock for
2228          * the ocp2scp_usb_phy IP block:
2229          * http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/119943.html
2230          * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems
2231          * to be the best workaround.
2232          */
2233         .main_clk       = "ocp2scp_usb_phy_phy_48m",
2234         .prcm = {
2235                 .omap4 = {
2236                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2237                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2238                         .modulemode   = MODULEMODE_HWCTRL,
2239                 },
2240         },
2241 };
2242
2243 /*
2244  * 'prcm' class
2245  * power and reset manager (part of the prcm infrastructure) + clock manager 2
2246  * + clock manager 1 (in always on power domain) + local prm in mpu
2247  */
2248
2249 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2250         .name   = "prcm",
2251 };
2252
2253 /* prcm_mpu */
2254 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2255         .name           = "prcm_mpu",
2256         .class          = &omap44xx_prcm_hwmod_class,
2257         .clkdm_name     = "l4_wkup_clkdm",
2258         .flags          = HWMOD_NO_IDLEST,
2259         .prcm = {
2260                 .omap4 = {
2261                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2262                 },
2263         },
2264 };
2265
2266 /* cm_core_aon */
2267 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2268         .name           = "cm_core_aon",
2269         .class          = &omap44xx_prcm_hwmod_class,
2270         .flags          = HWMOD_NO_IDLEST,
2271         .prcm = {
2272                 .omap4 = {
2273                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2274                 },
2275         },
2276 };
2277
2278 /* cm_core */
2279 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2280         .name           = "cm_core",
2281         .class          = &omap44xx_prcm_hwmod_class,
2282         .flags          = HWMOD_NO_IDLEST,
2283         .prcm = {
2284                 .omap4 = {
2285                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2286                 },
2287         },
2288 };
2289
2290 /* prm */
2291 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2292         { .name = "rst_global_warm_sw", .rst_shift = 0 },
2293         { .name = "rst_global_cold_sw", .rst_shift = 1 },
2294 };
2295
2296 static struct omap_hwmod omap44xx_prm_hwmod = {
2297         .name           = "prm",
2298         .class          = &omap44xx_prcm_hwmod_class,
2299         .rst_lines      = omap44xx_prm_resets,
2300         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
2301 };
2302
2303 /*
2304  * 'scrm' class
2305  * system clock and reset manager
2306  */
2307
2308 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2309         .name   = "scrm",
2310 };
2311
2312 /* scrm */
2313 static struct omap_hwmod omap44xx_scrm_hwmod = {
2314         .name           = "scrm",
2315         .class          = &omap44xx_scrm_hwmod_class,
2316         .clkdm_name     = "l4_wkup_clkdm",
2317         .prcm = {
2318                 .omap4 = {
2319                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2320                 },
2321         },
2322 };
2323
2324 /*
2325  * 'sl2if' class
2326  * shared level 2 memory interface
2327  */
2328
2329 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2330         .name   = "sl2if",
2331 };
2332
2333 /* sl2if */
2334 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2335         .name           = "sl2if",
2336         .class          = &omap44xx_sl2if_hwmod_class,
2337         .clkdm_name     = "ivahd_clkdm",
2338         .prcm = {
2339                 .omap4 = {
2340                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2341                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2342                         .modulemode   = MODULEMODE_HWCTRL,
2343                 },
2344         },
2345 };
2346
2347 /*
2348  * 'slimbus' class
2349  * bidirectional, multi-drop, multi-channel two-line serial interface between
2350  * the device and external components
2351  */
2352
2353 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2354         .rev_offs       = 0x0000,
2355         .sysc_offs      = 0x0010,
2356         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2357                            SYSC_HAS_SOFTRESET),
2358         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2359                            SIDLE_SMART_WKUP),
2360         .sysc_fields    = &omap_hwmod_sysc_type2,
2361 };
2362
2363 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2364         .name   = "slimbus",
2365         .sysc   = &omap44xx_slimbus_sysc,
2366 };
2367
2368 /* slimbus1 */
2369 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2370         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2371         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2372         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2373         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2374 };
2375
2376 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2377         .name           = "slimbus1",
2378         .class          = &omap44xx_slimbus_hwmod_class,
2379         .clkdm_name     = "abe_clkdm",
2380         .prcm = {
2381                 .omap4 = {
2382                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2383                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2384                         .modulemode   = MODULEMODE_SWCTRL,
2385                 },
2386         },
2387         .opt_clks       = slimbus1_opt_clks,
2388         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2389 };
2390
2391 /* slimbus2 */
2392 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2393         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2394         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2395         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2396 };
2397
2398 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2399         .name           = "slimbus2",
2400         .class          = &omap44xx_slimbus_hwmod_class,
2401         .clkdm_name     = "l4_per_clkdm",
2402         .prcm = {
2403                 .omap4 = {
2404                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2405                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2406                         .modulemode   = MODULEMODE_SWCTRL,
2407                 },
2408         },
2409         .opt_clks       = slimbus2_opt_clks,
2410         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
2411 };
2412
2413 /*
2414  * 'smartreflex' class
2415  * smartreflex module (monitor silicon performance and outputs a measure of
2416  * performance error)
2417  */
2418
2419 /* The IP is not compliant to type1 / type2 scheme */
2420 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2421         .sidle_shift    = 24,
2422         .enwkup_shift   = 26,
2423 };
2424
2425 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2426         .sysc_offs      = 0x0038,
2427         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2428         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2429                            SIDLE_SMART_WKUP),
2430         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2431 };
2432
2433 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2434         .name   = "smartreflex",
2435         .sysc   = &omap44xx_smartreflex_sysc,
2436         .rev    = 2,
2437 };
2438
2439 /* smartreflex_core */
2440 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2441         .sensor_voltdm_name   = "core",
2442 };
2443
2444 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2445         .name           = "smartreflex_core",
2446         .class          = &omap44xx_smartreflex_hwmod_class,
2447         .clkdm_name     = "l4_ao_clkdm",
2448
2449         .main_clk       = "smartreflex_core_fck",
2450         .prcm = {
2451                 .omap4 = {
2452                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2453                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2454                         .modulemode   = MODULEMODE_SWCTRL,
2455                 },
2456         },
2457         .dev_attr       = &smartreflex_core_dev_attr,
2458 };
2459
2460 /* smartreflex_iva */
2461 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2462         .sensor_voltdm_name     = "iva",
2463 };
2464
2465 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2466         .name           = "smartreflex_iva",
2467         .class          = &omap44xx_smartreflex_hwmod_class,
2468         .clkdm_name     = "l4_ao_clkdm",
2469         .main_clk       = "smartreflex_iva_fck",
2470         .prcm = {
2471                 .omap4 = {
2472                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2473                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2474                         .modulemode   = MODULEMODE_SWCTRL,
2475                 },
2476         },
2477         .dev_attr       = &smartreflex_iva_dev_attr,
2478 };
2479
2480 /* smartreflex_mpu */
2481 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2482         .sensor_voltdm_name     = "mpu",
2483 };
2484
2485 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
2486         .name           = "smartreflex_mpu",
2487         .class          = &omap44xx_smartreflex_hwmod_class,
2488         .clkdm_name     = "l4_ao_clkdm",
2489         .main_clk       = "smartreflex_mpu_fck",
2490         .prcm = {
2491                 .omap4 = {
2492                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
2493                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
2494                         .modulemode   = MODULEMODE_SWCTRL,
2495                 },
2496         },
2497         .dev_attr       = &smartreflex_mpu_dev_attr,
2498 };
2499
2500 /*
2501  * 'spinlock' class
2502  * spinlock provides hardware assistance for synchronizing the processes
2503  * running on multiple processors
2504  */
2505
2506 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
2507         .rev_offs       = 0x0000,
2508         .sysc_offs      = 0x0010,
2509         .syss_offs      = 0x0014,
2510         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2511                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2512                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2513         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2514         .sysc_fields    = &omap_hwmod_sysc_type1,
2515 };
2516
2517 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
2518         .name   = "spinlock",
2519         .sysc   = &omap44xx_spinlock_sysc,
2520 };
2521
2522 /* spinlock */
2523 static struct omap_hwmod omap44xx_spinlock_hwmod = {
2524         .name           = "spinlock",
2525         .class          = &omap44xx_spinlock_hwmod_class,
2526         .clkdm_name     = "l4_cfg_clkdm",
2527         .prcm = {
2528                 .omap4 = {
2529                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
2530                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
2531                 },
2532         },
2533 };
2534
2535 /*
2536  * 'timer' class
2537  * general purpose timer module with accurate 1ms tick
2538  * This class contains several variants: ['timer_1ms', 'timer']
2539  */
2540
2541 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
2542         .rev_offs       = 0x0000,
2543         .sysc_offs      = 0x0010,
2544         .syss_offs      = 0x0014,
2545         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2546                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2547                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2548                            SYSS_HAS_RESET_STATUS),
2549         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2550         .sysc_fields    = &omap_hwmod_sysc_type1,
2551 };
2552
2553 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
2554         .name   = "timer",
2555         .sysc   = &omap44xx_timer_1ms_sysc,
2556 };
2557
2558 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
2559         .rev_offs       = 0x0000,
2560         .sysc_offs      = 0x0010,
2561         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2562                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2563         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2564                            SIDLE_SMART_WKUP),
2565         .sysc_fields    = &omap_hwmod_sysc_type2,
2566 };
2567
2568 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
2569         .name   = "timer",
2570         .sysc   = &omap44xx_timer_sysc,
2571 };
2572
2573 /* always-on timers dev attribute */
2574 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
2575         .timer_capability       = OMAP_TIMER_ALWON,
2576 };
2577
2578 /* pwm timers dev attribute */
2579 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
2580         .timer_capability       = OMAP_TIMER_HAS_PWM,
2581 };
2582
2583 /* timers with DSP interrupt dev attribute */
2584 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
2585         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
2586 };
2587
2588 /* pwm timers with DSP interrupt dev attribute */
2589 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
2590         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
2591 };
2592
2593 /* timer1 */
2594 static struct omap_hwmod omap44xx_timer1_hwmod = {
2595         .name           = "timer1",
2596         .class          = &omap44xx_timer_1ms_hwmod_class,
2597         .clkdm_name     = "l4_wkup_clkdm",
2598         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2599         .main_clk       = "dmt1_clk_mux",
2600         .prcm = {
2601                 .omap4 = {
2602                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2603                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
2604                         .modulemode   = MODULEMODE_SWCTRL,
2605                 },
2606         },
2607         .dev_attr       = &capability_alwon_dev_attr,
2608 };
2609
2610 /* timer2 */
2611 static struct omap_hwmod omap44xx_timer2_hwmod = {
2612         .name           = "timer2",
2613         .class          = &omap44xx_timer_1ms_hwmod_class,
2614         .clkdm_name     = "l4_per_clkdm",
2615         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2616         .main_clk       = "cm2_dm2_mux",
2617         .prcm = {
2618                 .omap4 = {
2619                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
2620                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
2621                         .modulemode   = MODULEMODE_SWCTRL,
2622                 },
2623         },
2624 };
2625
2626 /* timer3 */
2627 static struct omap_hwmod omap44xx_timer3_hwmod = {
2628         .name           = "timer3",
2629         .class          = &omap44xx_timer_hwmod_class,
2630         .clkdm_name     = "l4_per_clkdm",
2631         .main_clk       = "cm2_dm3_mux",
2632         .prcm = {
2633                 .omap4 = {
2634                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
2635                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
2636                         .modulemode   = MODULEMODE_SWCTRL,
2637                 },
2638         },
2639 };
2640
2641 /* timer4 */
2642 static struct omap_hwmod omap44xx_timer4_hwmod = {
2643         .name           = "timer4",
2644         .class          = &omap44xx_timer_hwmod_class,
2645         .clkdm_name     = "l4_per_clkdm",
2646         .main_clk       = "cm2_dm4_mux",
2647         .prcm = {
2648                 .omap4 = {
2649                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
2650                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
2651                         .modulemode   = MODULEMODE_SWCTRL,
2652                 },
2653         },
2654 };
2655
2656 /* timer5 */
2657 static struct omap_hwmod omap44xx_timer5_hwmod = {
2658         .name           = "timer5",
2659         .class          = &omap44xx_timer_hwmod_class,
2660         .clkdm_name     = "abe_clkdm",
2661         .main_clk       = "timer5_sync_mux",
2662         .prcm = {
2663                 .omap4 = {
2664                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
2665                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
2666                         .modulemode   = MODULEMODE_SWCTRL,
2667                 },
2668         },
2669         .dev_attr       = &capability_dsp_dev_attr,
2670 };
2671
2672 /* timer6 */
2673 static struct omap_hwmod omap44xx_timer6_hwmod = {
2674         .name           = "timer6",
2675         .class          = &omap44xx_timer_hwmod_class,
2676         .clkdm_name     = "abe_clkdm",
2677         .main_clk       = "timer6_sync_mux",
2678         .prcm = {
2679                 .omap4 = {
2680                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
2681                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
2682                         .modulemode   = MODULEMODE_SWCTRL,
2683                 },
2684         },
2685         .dev_attr       = &capability_dsp_dev_attr,
2686 };
2687
2688 /* timer7 */
2689 static struct omap_hwmod omap44xx_timer7_hwmod = {
2690         .name           = "timer7",
2691         .class          = &omap44xx_timer_hwmod_class,
2692         .clkdm_name     = "abe_clkdm",
2693         .main_clk       = "timer7_sync_mux",
2694         .prcm = {
2695                 .omap4 = {
2696                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
2697                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
2698                         .modulemode   = MODULEMODE_SWCTRL,
2699                 },
2700         },
2701         .dev_attr       = &capability_dsp_dev_attr,
2702 };
2703
2704 /* timer8 */
2705 static struct omap_hwmod omap44xx_timer8_hwmod = {
2706         .name           = "timer8",
2707         .class          = &omap44xx_timer_hwmod_class,
2708         .clkdm_name     = "abe_clkdm",
2709         .main_clk       = "timer8_sync_mux",
2710         .prcm = {
2711                 .omap4 = {
2712                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
2713                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
2714                         .modulemode   = MODULEMODE_SWCTRL,
2715                 },
2716         },
2717         .dev_attr       = &capability_dsp_pwm_dev_attr,
2718 };
2719
2720 /* timer9 */
2721 static struct omap_hwmod omap44xx_timer9_hwmod = {
2722         .name           = "timer9",
2723         .class          = &omap44xx_timer_hwmod_class,
2724         .clkdm_name     = "l4_per_clkdm",
2725         .main_clk       = "cm2_dm9_mux",
2726         .prcm = {
2727                 .omap4 = {
2728                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
2729                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
2730                         .modulemode   = MODULEMODE_SWCTRL,
2731                 },
2732         },
2733         .dev_attr       = &capability_pwm_dev_attr,
2734 };
2735
2736 /* timer10 */
2737 static struct omap_hwmod omap44xx_timer10_hwmod = {
2738         .name           = "timer10",
2739         .class          = &omap44xx_timer_1ms_hwmod_class,
2740         .clkdm_name     = "l4_per_clkdm",
2741         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2742         .main_clk       = "cm2_dm10_mux",
2743         .prcm = {
2744                 .omap4 = {
2745                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
2746                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
2747                         .modulemode   = MODULEMODE_SWCTRL,
2748                 },
2749         },
2750         .dev_attr       = &capability_pwm_dev_attr,
2751 };
2752
2753 /* timer11 */
2754 static struct omap_hwmod omap44xx_timer11_hwmod = {
2755         .name           = "timer11",
2756         .class          = &omap44xx_timer_hwmod_class,
2757         .clkdm_name     = "l4_per_clkdm",
2758         .main_clk       = "cm2_dm11_mux",
2759         .prcm = {
2760                 .omap4 = {
2761                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
2762                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
2763                         .modulemode   = MODULEMODE_SWCTRL,
2764                 },
2765         },
2766         .dev_attr       = &capability_pwm_dev_attr,
2767 };
2768
2769 /*
2770  * 'uart' class
2771  * universal asynchronous receiver/transmitter (uart)
2772  */
2773
2774 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
2775         .rev_offs       = 0x0050,
2776         .sysc_offs      = 0x0054,
2777         .syss_offs      = 0x0058,
2778         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2779                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2780                            SYSS_HAS_RESET_STATUS),
2781         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2782                            SIDLE_SMART_WKUP),
2783         .sysc_fields    = &omap_hwmod_sysc_type1,
2784 };
2785
2786 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
2787         .name   = "uart",
2788         .sysc   = &omap44xx_uart_sysc,
2789 };
2790
2791 /* uart1 */
2792 static struct omap_hwmod omap44xx_uart1_hwmod = {
2793         .name           = "uart1",
2794         .class          = &omap44xx_uart_hwmod_class,
2795         .clkdm_name     = "l4_per_clkdm",
2796         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2797         .main_clk       = "func_48m_fclk",
2798         .prcm = {
2799                 .omap4 = {
2800                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
2801                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
2802                         .modulemode   = MODULEMODE_SWCTRL,
2803                 },
2804         },
2805 };
2806
2807 /* uart2 */
2808 static struct omap_hwmod omap44xx_uart2_hwmod = {
2809         .name           = "uart2",
2810         .class          = &omap44xx_uart_hwmod_class,
2811         .clkdm_name     = "l4_per_clkdm",
2812         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2813         .main_clk       = "func_48m_fclk",
2814         .prcm = {
2815                 .omap4 = {
2816                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
2817                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
2818                         .modulemode   = MODULEMODE_SWCTRL,
2819                 },
2820         },
2821 };
2822
2823 /* uart3 */
2824 static struct omap_hwmod omap44xx_uart3_hwmod = {
2825         .name           = "uart3",
2826         .class          = &omap44xx_uart_hwmod_class,
2827         .clkdm_name     = "l4_per_clkdm",
2828         .flags          = DEBUG_OMAP4UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
2829         .main_clk       = "func_48m_fclk",
2830         .prcm = {
2831                 .omap4 = {
2832                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
2833                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
2834                         .modulemode   = MODULEMODE_SWCTRL,
2835                 },
2836         },
2837 };
2838
2839 /* uart4 */
2840 static struct omap_hwmod omap44xx_uart4_hwmod = {
2841         .name           = "uart4",
2842         .class          = &omap44xx_uart_hwmod_class,
2843         .clkdm_name     = "l4_per_clkdm",
2844         .flags          = DEBUG_OMAP4UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
2845         .main_clk       = "func_48m_fclk",
2846         .prcm = {
2847                 .omap4 = {
2848                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
2849                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
2850                         .modulemode   = MODULEMODE_SWCTRL,
2851                 },
2852         },
2853 };
2854
2855 /*
2856  * 'usb_host_fs' class
2857  * full-speed usb host controller
2858  */
2859
2860 /* The IP is not compliant to type1 / type2 scheme */
2861 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
2862         .midle_shift    = 4,
2863         .sidle_shift    = 2,
2864         .srst_shift     = 1,
2865 };
2866
2867 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
2868         .rev_offs       = 0x0000,
2869         .sysc_offs      = 0x0210,
2870         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2871                            SYSC_HAS_SOFTRESET),
2872         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2873                            SIDLE_SMART_WKUP),
2874         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
2875 };
2876
2877 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
2878         .name   = "usb_host_fs",
2879         .sysc   = &omap44xx_usb_host_fs_sysc,
2880 };
2881
2882 /* usb_host_fs */
2883 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
2884         .name           = "usb_host_fs",
2885         .class          = &omap44xx_usb_host_fs_hwmod_class,
2886         .clkdm_name     = "l3_init_clkdm",
2887         .main_clk       = "usb_host_fs_fck",
2888         .prcm = {
2889                 .omap4 = {
2890                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
2891                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
2892                         .modulemode   = MODULEMODE_SWCTRL,
2893                 },
2894         },
2895 };
2896
2897 /*
2898  * 'usb_host_hs' class
2899  * high-speed multi-port usb host controller
2900  */
2901
2902 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
2903         .rev_offs       = 0x0000,
2904         .sysc_offs      = 0x0010,
2905         .syss_offs      = 0x0014,
2906         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2907                            SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS),
2908         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2909                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2910                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2911         .sysc_fields    = &omap_hwmod_sysc_type2,
2912 };
2913
2914 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
2915         .name   = "usb_host_hs",
2916         .sysc   = &omap44xx_usb_host_hs_sysc,
2917 };
2918
2919 /* usb_host_hs */
2920 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
2921         .name           = "usb_host_hs",
2922         .class          = &omap44xx_usb_host_hs_hwmod_class,
2923         .clkdm_name     = "l3_init_clkdm",
2924         .main_clk       = "usb_host_hs_fck",
2925         .prcm = {
2926                 .omap4 = {
2927                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
2928                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
2929                         .modulemode   = MODULEMODE_SWCTRL,
2930                 },
2931         },
2932
2933         /*
2934          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
2935          * id: i660
2936          *
2937          * Description:
2938          * In the following configuration :
2939          * - USBHOST module is set to smart-idle mode
2940          * - PRCM asserts idle_req to the USBHOST module ( This typically
2941          *   happens when the system is going to a low power mode : all ports
2942          *   have been suspended, the master part of the USBHOST module has
2943          *   entered the standby state, and SW has cut the functional clocks)
2944          * - an USBHOST interrupt occurs before the module is able to answer
2945          *   idle_ack, typically a remote wakeup IRQ.
2946          * Then the USB HOST module will enter a deadlock situation where it
2947          * is no more accessible nor functional.
2948          *
2949          * Workaround:
2950          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
2951          */
2952
2953         /*
2954          * Errata: USB host EHCI may stall when entering smart-standby mode
2955          * Id: i571
2956          *
2957          * Description:
2958          * When the USBHOST module is set to smart-standby mode, and when it is
2959          * ready to enter the standby state (i.e. all ports are suspended and
2960          * all attached devices are in suspend mode), then it can wrongly assert
2961          * the Mstandby signal too early while there are still some residual OCP
2962          * transactions ongoing. If this condition occurs, the internal state
2963          * machine may go to an undefined state and the USB link may be stuck
2964          * upon the next resume.
2965          *
2966          * Workaround:
2967          * Don't use smart standby; use only force standby,
2968          * hence HWMOD_SWSUP_MSTANDBY
2969          */
2970
2971         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2972 };
2973
2974 /*
2975  * 'usb_otg_hs' class
2976  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
2977  */
2978
2979 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
2980         .rev_offs       = 0x0400,
2981         .sysc_offs      = 0x0404,
2982         .syss_offs      = 0x0408,
2983         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2984                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2985                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2986         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2987                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2988                            MSTANDBY_SMART),
2989         .sysc_fields    = &omap_hwmod_sysc_type1,
2990 };
2991
2992 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
2993         .name   = "usb_otg_hs",
2994         .sysc   = &omap44xx_usb_otg_hs_sysc,
2995 };
2996
2997 /* usb_otg_hs */
2998 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
2999         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3000 };
3001
3002 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3003         .name           = "usb_otg_hs",
3004         .class          = &omap44xx_usb_otg_hs_hwmod_class,
3005         .clkdm_name     = "l3_init_clkdm",
3006         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3007         .main_clk       = "usb_otg_hs_ick",
3008         .prcm = {
3009                 .omap4 = {
3010                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3011                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3012                         .modulemode   = MODULEMODE_HWCTRL,
3013                 },
3014         },
3015         .opt_clks       = usb_otg_hs_opt_clks,
3016         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
3017 };
3018
3019 /*
3020  * 'usb_tll_hs' class
3021  * usb_tll_hs module is the adapter on the usb_host_hs ports
3022  */
3023
3024 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3025         .rev_offs       = 0x0000,
3026         .sysc_offs      = 0x0010,
3027         .syss_offs      = 0x0014,
3028         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3029                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3030                            SYSC_HAS_AUTOIDLE),
3031         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3032         .sysc_fields    = &omap_hwmod_sysc_type1,
3033 };
3034
3035 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3036         .name   = "usb_tll_hs",
3037         .sysc   = &omap44xx_usb_tll_hs_sysc,
3038 };
3039
3040 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3041         .name           = "usb_tll_hs",
3042         .class          = &omap44xx_usb_tll_hs_hwmod_class,
3043         .clkdm_name     = "l3_init_clkdm",
3044         .main_clk       = "usb_tll_hs_ick",
3045         .prcm = {
3046                 .omap4 = {
3047                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3048                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3049                         .modulemode   = MODULEMODE_HWCTRL,
3050                 },
3051         },
3052 };
3053
3054 /*
3055  * 'wd_timer' class
3056  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3057  * overflow condition
3058  */
3059
3060 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3061         .rev_offs       = 0x0000,
3062         .sysc_offs      = 0x0010,
3063         .syss_offs      = 0x0014,
3064         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3065                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3066         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3067                            SIDLE_SMART_WKUP),
3068         .sysc_fields    = &omap_hwmod_sysc_type1,
3069 };
3070
3071 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3072         .name           = "wd_timer",
3073         .sysc           = &omap44xx_wd_timer_sysc,
3074         .pre_shutdown   = &omap2_wd_timer_disable,
3075         .reset          = &omap2_wd_timer_reset,
3076 };
3077
3078 /* wd_timer2 */
3079 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3080         .name           = "wd_timer2",
3081         .class          = &omap44xx_wd_timer_hwmod_class,
3082         .clkdm_name     = "l4_wkup_clkdm",
3083         .main_clk       = "sys_32k_ck",
3084         .prcm = {
3085                 .omap4 = {
3086                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3087                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3088                         .modulemode   = MODULEMODE_SWCTRL,
3089                 },
3090         },
3091 };
3092
3093 /* wd_timer3 */
3094 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3095         .name           = "wd_timer3",
3096         .class          = &omap44xx_wd_timer_hwmod_class,
3097         .clkdm_name     = "abe_clkdm",
3098         .main_clk       = "sys_32k_ck",
3099         .prcm = {
3100                 .omap4 = {
3101                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3102                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3103                         .modulemode   = MODULEMODE_SWCTRL,
3104                 },
3105         },
3106 };
3107
3108
3109 /*
3110  * interfaces
3111  */
3112
3113 /* l3_main_1 -> dmm */
3114 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3115         .master         = &omap44xx_l3_main_1_hwmod,
3116         .slave          = &omap44xx_dmm_hwmod,
3117         .clk            = "l3_div_ck",
3118         .user           = OCP_USER_SDMA,
3119 };
3120
3121 /* mpu -> dmm */
3122 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3123         .master         = &omap44xx_mpu_hwmod,
3124         .slave          = &omap44xx_dmm_hwmod,
3125         .clk            = "l3_div_ck",
3126         .user           = OCP_USER_MPU,
3127 };
3128
3129 /* iva -> l3_instr */
3130 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3131         .master         = &omap44xx_iva_hwmod,
3132         .slave          = &omap44xx_l3_instr_hwmod,
3133         .clk            = "l3_div_ck",
3134         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3135 };
3136
3137 /* l3_main_3 -> l3_instr */
3138 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3139         .master         = &omap44xx_l3_main_3_hwmod,
3140         .slave          = &omap44xx_l3_instr_hwmod,
3141         .clk            = "l3_div_ck",
3142         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3143 };
3144
3145 /* ocp_wp_noc -> l3_instr */
3146 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3147         .master         = &omap44xx_ocp_wp_noc_hwmod,
3148         .slave          = &omap44xx_l3_instr_hwmod,
3149         .clk            = "l3_div_ck",
3150         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3151 };
3152
3153 /* dsp -> l3_main_1 */
3154 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3155         .master         = &omap44xx_dsp_hwmod,
3156         .slave          = &omap44xx_l3_main_1_hwmod,
3157         .clk            = "l3_div_ck",
3158         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3159 };
3160
3161 /* dss -> l3_main_1 */
3162 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3163         .master         = &omap44xx_dss_hwmod,
3164         .slave          = &omap44xx_l3_main_1_hwmod,
3165         .clk            = "l3_div_ck",
3166         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3167 };
3168
3169 /* l3_main_2 -> l3_main_1 */
3170 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3171         .master         = &omap44xx_l3_main_2_hwmod,
3172         .slave          = &omap44xx_l3_main_1_hwmod,
3173         .clk            = "l3_div_ck",
3174         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3175 };
3176
3177 /* l4_cfg -> l3_main_1 */
3178 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3179         .master         = &omap44xx_l4_cfg_hwmod,
3180         .slave          = &omap44xx_l3_main_1_hwmod,
3181         .clk            = "l4_div_ck",
3182         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3183 };
3184
3185 /* mmc1 -> l3_main_1 */
3186 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3187         .master         = &omap44xx_mmc1_hwmod,
3188         .slave          = &omap44xx_l3_main_1_hwmod,
3189         .clk            = "l3_div_ck",
3190         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3191 };
3192
3193 /* mmc2 -> l3_main_1 */
3194 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3195         .master         = &omap44xx_mmc2_hwmod,
3196         .slave          = &omap44xx_l3_main_1_hwmod,
3197         .clk            = "l3_div_ck",
3198         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3199 };
3200
3201 /* mpu -> l3_main_1 */
3202 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3203         .master         = &omap44xx_mpu_hwmod,
3204         .slave          = &omap44xx_l3_main_1_hwmod,
3205         .clk            = "l3_div_ck",
3206         .user           = OCP_USER_MPU,
3207 };
3208
3209 /* debugss -> l3_main_2 */
3210 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3211         .master         = &omap44xx_debugss_hwmod,
3212         .slave          = &omap44xx_l3_main_2_hwmod,
3213         .clk            = "dbgclk_mux_ck",
3214         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3215 };
3216
3217 /* dma_system -> l3_main_2 */
3218 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3219         .master         = &omap44xx_dma_system_hwmod,
3220         .slave          = &omap44xx_l3_main_2_hwmod,
3221         .clk            = "l3_div_ck",
3222         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3223 };
3224
3225 /* fdif -> l3_main_2 */
3226 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3227         .master         = &omap44xx_fdif_hwmod,
3228         .slave          = &omap44xx_l3_main_2_hwmod,
3229         .clk            = "l3_div_ck",
3230         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3231 };
3232
3233 /* gpu -> l3_main_2 */
3234 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
3235         .master         = &omap44xx_gpu_hwmod,
3236         .slave          = &omap44xx_l3_main_2_hwmod,
3237         .clk            = "l3_div_ck",
3238         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3239 };
3240
3241 /* hsi -> l3_main_2 */
3242 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
3243         .master         = &omap44xx_hsi_hwmod,
3244         .slave          = &omap44xx_l3_main_2_hwmod,
3245         .clk            = "l3_div_ck",
3246         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3247 };
3248
3249 /* ipu -> l3_main_2 */
3250 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
3251         .master         = &omap44xx_ipu_hwmod,
3252         .slave          = &omap44xx_l3_main_2_hwmod,
3253         .clk            = "l3_div_ck",
3254         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3255 };
3256
3257 /* iss -> l3_main_2 */
3258 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
3259         .master         = &omap44xx_iss_hwmod,
3260         .slave          = &omap44xx_l3_main_2_hwmod,
3261         .clk            = "l3_div_ck",
3262         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3263 };
3264
3265 /* iva -> l3_main_2 */
3266 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
3267         .master         = &omap44xx_iva_hwmod,
3268         .slave          = &omap44xx_l3_main_2_hwmod,
3269         .clk            = "l3_div_ck",
3270         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3271 };
3272
3273 /* l3_main_1 -> l3_main_2 */
3274 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
3275         .master         = &omap44xx_l3_main_1_hwmod,
3276         .slave          = &omap44xx_l3_main_2_hwmod,
3277         .clk            = "l3_div_ck",
3278         .user           = OCP_USER_MPU,
3279 };
3280
3281 /* l4_cfg -> l3_main_2 */
3282 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
3283         .master         = &omap44xx_l4_cfg_hwmod,
3284         .slave          = &omap44xx_l3_main_2_hwmod,
3285         .clk            = "l4_div_ck",
3286         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3287 };
3288
3289 /* usb_host_fs -> l3_main_2 */
3290 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
3291         .master         = &omap44xx_usb_host_fs_hwmod,
3292         .slave          = &omap44xx_l3_main_2_hwmod,
3293         .clk            = "l3_div_ck",
3294         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3295 };
3296
3297 /* usb_host_hs -> l3_main_2 */
3298 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
3299         .master         = &omap44xx_usb_host_hs_hwmod,
3300         .slave          = &omap44xx_l3_main_2_hwmod,
3301         .clk            = "l3_div_ck",
3302         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3303 };
3304
3305 /* usb_otg_hs -> l3_main_2 */
3306 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
3307         .master         = &omap44xx_usb_otg_hs_hwmod,
3308         .slave          = &omap44xx_l3_main_2_hwmod,
3309         .clk            = "l3_div_ck",
3310         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3311 };
3312
3313 /* l3_main_1 -> l3_main_3 */
3314 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
3315         .master         = &omap44xx_l3_main_1_hwmod,
3316         .slave          = &omap44xx_l3_main_3_hwmod,
3317         .clk            = "l3_div_ck",
3318         .user           = OCP_USER_MPU,
3319 };
3320
3321 /* l3_main_2 -> l3_main_3 */
3322 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
3323         .master         = &omap44xx_l3_main_2_hwmod,
3324         .slave          = &omap44xx_l3_main_3_hwmod,
3325         .clk            = "l3_div_ck",
3326         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3327 };
3328
3329 /* l4_cfg -> l3_main_3 */
3330 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
3331         .master         = &omap44xx_l4_cfg_hwmod,
3332         .slave          = &omap44xx_l3_main_3_hwmod,
3333         .clk            = "l4_div_ck",
3334         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3335 };
3336
3337 /* aess -> l4_abe */
3338 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
3339         .master         = &omap44xx_aess_hwmod,
3340         .slave          = &omap44xx_l4_abe_hwmod,
3341         .clk            = "ocp_abe_iclk",
3342         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3343 };
3344
3345 /* dsp -> l4_abe */
3346 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
3347         .master         = &omap44xx_dsp_hwmod,
3348         .slave          = &omap44xx_l4_abe_hwmod,
3349         .clk            = "ocp_abe_iclk",
3350         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3351 };
3352
3353 /* l3_main_1 -> l4_abe */
3354 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
3355         .master         = &omap44xx_l3_main_1_hwmod,
3356         .slave          = &omap44xx_l4_abe_hwmod,
3357         .clk            = "l3_div_ck",
3358         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3359 };
3360
3361 /* mpu -> l4_abe */
3362 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
3363         .master         = &omap44xx_mpu_hwmod,
3364         .slave          = &omap44xx_l4_abe_hwmod,
3365         .clk            = "ocp_abe_iclk",
3366         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3367 };
3368
3369 /* l3_main_1 -> l4_cfg */
3370 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
3371         .master         = &omap44xx_l3_main_1_hwmod,
3372         .slave          = &omap44xx_l4_cfg_hwmod,
3373         .clk            = "l3_div_ck",
3374         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3375 };
3376
3377 /* l3_main_2 -> l4_per */
3378 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
3379         .master         = &omap44xx_l3_main_2_hwmod,
3380         .slave          = &omap44xx_l4_per_hwmod,
3381         .clk            = "l3_div_ck",
3382         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3383 };
3384
3385 /* l4_cfg -> l4_wkup */
3386 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
3387         .master         = &omap44xx_l4_cfg_hwmod,
3388         .slave          = &omap44xx_l4_wkup_hwmod,
3389         .clk            = "l4_div_ck",
3390         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3391 };
3392
3393 /* mpu -> mpu_private */
3394 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
3395         .master         = &omap44xx_mpu_hwmod,
3396         .slave          = &omap44xx_mpu_private_hwmod,
3397         .clk            = "l3_div_ck",
3398         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3399 };
3400
3401 /* l4_cfg -> ocp_wp_noc */
3402 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
3403         .master         = &omap44xx_l4_cfg_hwmod,
3404         .slave          = &omap44xx_ocp_wp_noc_hwmod,
3405         .clk            = "l4_div_ck",
3406         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3407 };
3408
3409 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
3410         {
3411                 .name           = "dmem",
3412                 .pa_start       = 0x40180000,
3413                 .pa_end         = 0x4018ffff
3414         },
3415         {
3416                 .name           = "cmem",
3417                 .pa_start       = 0x401a0000,
3418                 .pa_end         = 0x401a1fff
3419         },
3420         {
3421                 .name           = "smem",
3422                 .pa_start       = 0x401c0000,
3423                 .pa_end         = 0x401c5fff
3424         },
3425         {
3426                 .name           = "pmem",
3427                 .pa_start       = 0x401e0000,
3428                 .pa_end         = 0x401e1fff
3429         },
3430         {
3431                 .name           = "mpu",
3432                 .pa_start       = 0x401f1000,
3433                 .pa_end         = 0x401f13ff,
3434                 .flags          = ADDR_TYPE_RT
3435         },
3436         { }
3437 };
3438
3439 /* l4_abe -> aess */
3440 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
3441         .master         = &omap44xx_l4_abe_hwmod,
3442         .slave          = &omap44xx_aess_hwmod,
3443         .clk            = "ocp_abe_iclk",
3444         .addr           = omap44xx_aess_addrs,
3445         .user           = OCP_USER_MPU,
3446 };
3447
3448 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
3449         {
3450                 .name           = "dmem_dma",
3451                 .pa_start       = 0x49080000,
3452                 .pa_end         = 0x4908ffff
3453         },
3454         {
3455                 .name           = "cmem_dma",
3456                 .pa_start       = 0x490a0000,
3457                 .pa_end         = 0x490a1fff
3458         },
3459         {
3460                 .name           = "smem_dma",
3461                 .pa_start       = 0x490c0000,
3462                 .pa_end         = 0x490c5fff
3463         },
3464         {
3465                 .name           = "pmem_dma",
3466                 .pa_start       = 0x490e0000,
3467                 .pa_end         = 0x490e1fff
3468         },
3469         {
3470                 .name           = "dma",
3471                 .pa_start       = 0x490f1000,
3472                 .pa_end         = 0x490f13ff,
3473                 .flags          = ADDR_TYPE_RT
3474         },
3475         { }
3476 };
3477
3478 /* l4_abe -> aess (dma) */
3479 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
3480         .master         = &omap44xx_l4_abe_hwmod,
3481         .slave          = &omap44xx_aess_hwmod,
3482         .clk            = "ocp_abe_iclk",
3483         .addr           = omap44xx_aess_dma_addrs,
3484         .user           = OCP_USER_SDMA,
3485 };
3486
3487 /* l3_main_2 -> c2c */
3488 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
3489         .master         = &omap44xx_l3_main_2_hwmod,
3490         .slave          = &omap44xx_c2c_hwmod,
3491         .clk            = "l3_div_ck",
3492         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3493 };
3494
3495 /* l4_wkup -> counter_32k */
3496 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
3497         .master         = &omap44xx_l4_wkup_hwmod,
3498         .slave          = &omap44xx_counter_32k_hwmod,
3499         .clk            = "l4_wkup_clk_mux_ck",
3500         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3501 };
3502
3503 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
3504         {
3505                 .pa_start       = 0x4a002000,
3506                 .pa_end         = 0x4a0027ff,
3507                 .flags          = ADDR_TYPE_RT
3508         },
3509         { }
3510 };
3511
3512 /* l4_cfg -> ctrl_module_core */
3513 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
3514         .master         = &omap44xx_l4_cfg_hwmod,
3515         .slave          = &omap44xx_ctrl_module_core_hwmod,
3516         .clk            = "l4_div_ck",
3517         .addr           = omap44xx_ctrl_module_core_addrs,
3518         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3519 };
3520
3521 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
3522         {
3523                 .pa_start       = 0x4a100000,
3524                 .pa_end         = 0x4a1007ff,
3525                 .flags          = ADDR_TYPE_RT
3526         },
3527         { }
3528 };
3529
3530 /* l4_cfg -> ctrl_module_pad_core */
3531 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
3532         .master         = &omap44xx_l4_cfg_hwmod,
3533         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
3534         .clk            = "l4_div_ck",
3535         .addr           = omap44xx_ctrl_module_pad_core_addrs,
3536         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3537 };
3538
3539 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
3540         {
3541                 .pa_start       = 0x4a30c000,
3542                 .pa_end         = 0x4a30c7ff,
3543                 .flags          = ADDR_TYPE_RT
3544         },
3545         { }
3546 };
3547
3548 /* l4_wkup -> ctrl_module_wkup */
3549 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
3550         .master         = &omap44xx_l4_wkup_hwmod,
3551         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
3552         .clk            = "l4_wkup_clk_mux_ck",
3553         .addr           = omap44xx_ctrl_module_wkup_addrs,
3554         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3555 };
3556
3557 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
3558         {
3559                 .pa_start       = 0x4a31e000,
3560                 .pa_end         = 0x4a31e7ff,
3561                 .flags          = ADDR_TYPE_RT
3562         },
3563         { }
3564 };
3565
3566 /* l4_wkup -> ctrl_module_pad_wkup */
3567 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
3568         .master         = &omap44xx_l4_wkup_hwmod,
3569         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
3570         .clk            = "l4_wkup_clk_mux_ck",
3571         .addr           = omap44xx_ctrl_module_pad_wkup_addrs,
3572         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3573 };
3574
3575 /* l3_instr -> debugss */
3576 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
3577         .master         = &omap44xx_l3_instr_hwmod,
3578         .slave          = &omap44xx_debugss_hwmod,
3579         .clk            = "l3_div_ck",
3580         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3581 };
3582
3583 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
3584         {
3585                 .pa_start       = 0x4a056000,
3586                 .pa_end         = 0x4a056fff,
3587                 .flags          = ADDR_TYPE_RT
3588         },
3589         { }
3590 };
3591
3592 /* l4_cfg -> dma_system */
3593 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
3594         .master         = &omap44xx_l4_cfg_hwmod,
3595         .slave          = &omap44xx_dma_system_hwmod,
3596         .clk            = "l4_div_ck",
3597         .addr           = omap44xx_dma_system_addrs,
3598         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3599 };
3600
3601 /* l4_abe -> dmic */
3602 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
3603         .master         = &omap44xx_l4_abe_hwmod,
3604         .slave          = &omap44xx_dmic_hwmod,
3605         .clk            = "ocp_abe_iclk",
3606         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3607 };
3608
3609 /* dsp -> iva */
3610 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
3611         .master         = &omap44xx_dsp_hwmod,
3612         .slave          = &omap44xx_iva_hwmod,
3613         .clk            = "dpll_iva_m5x2_ck",
3614         .user           = OCP_USER_DSP,
3615 };
3616
3617 /* dsp -> sl2if */
3618 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
3619         .master         = &omap44xx_dsp_hwmod,
3620         .slave          = &omap44xx_sl2if_hwmod,
3621         .clk            = "dpll_iva_m5x2_ck",
3622         .user           = OCP_USER_DSP,
3623 };
3624
3625 /* l4_cfg -> dsp */
3626 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
3627         .master         = &omap44xx_l4_cfg_hwmod,
3628         .slave          = &omap44xx_dsp_hwmod,
3629         .clk            = "l4_div_ck",
3630         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3631 };
3632
3633 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
3634         {
3635                 .pa_start       = 0x58000000,
3636                 .pa_end         = 0x5800007f,
3637                 .flags          = ADDR_TYPE_RT
3638         },
3639         { }
3640 };
3641
3642 /* l3_main_2 -> dss */
3643 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
3644         .master         = &omap44xx_l3_main_2_hwmod,
3645         .slave          = &omap44xx_dss_hwmod,
3646         .clk            = "l3_div_ck",
3647         .addr           = omap44xx_dss_dma_addrs,
3648         .user           = OCP_USER_SDMA,
3649 };
3650
3651 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
3652         {
3653                 .pa_start       = 0x48040000,
3654                 .pa_end         = 0x4804007f,
3655                 .flags          = ADDR_TYPE_RT
3656         },
3657         { }
3658 };
3659
3660 /* l4_per -> dss */
3661 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
3662         .master         = &omap44xx_l4_per_hwmod,
3663         .slave          = &omap44xx_dss_hwmod,
3664         .clk            = "l4_div_ck",
3665         .addr           = omap44xx_dss_addrs,
3666         .user           = OCP_USER_MPU,
3667 };
3668
3669 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
3670         {
3671                 .pa_start       = 0x58001000,
3672                 .pa_end         = 0x58001fff,
3673                 .flags          = ADDR_TYPE_RT
3674         },
3675         { }
3676 };
3677
3678 /* l3_main_2 -> dss_dispc */
3679 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
3680         .master         = &omap44xx_l3_main_2_hwmod,
3681         .slave          = &omap44xx_dss_dispc_hwmod,
3682         .clk            = "l3_div_ck",
3683         .addr           = omap44xx_dss_dispc_dma_addrs,
3684         .user           = OCP_USER_SDMA,
3685 };
3686
3687 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
3688         {
3689                 .pa_start       = 0x48041000,
3690                 .pa_end         = 0x48041fff,
3691                 .flags          = ADDR_TYPE_RT
3692         },
3693         { }
3694 };
3695
3696 /* l4_per -> dss_dispc */
3697 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
3698         .master         = &omap44xx_l4_per_hwmod,
3699         .slave          = &omap44xx_dss_dispc_hwmod,
3700         .clk            = "l4_div_ck",
3701         .addr           = omap44xx_dss_dispc_addrs,
3702         .user           = OCP_USER_MPU,
3703 };
3704
3705 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
3706         {
3707                 .pa_start       = 0x58004000,
3708                 .pa_end         = 0x580041ff,
3709                 .flags          = ADDR_TYPE_RT
3710         },
3711         { }
3712 };
3713
3714 /* l3_main_2 -> dss_dsi1 */
3715 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
3716         .master         = &omap44xx_l3_main_2_hwmod,
3717         .slave          = &omap44xx_dss_dsi1_hwmod,
3718         .clk            = "l3_div_ck",
3719         .addr           = omap44xx_dss_dsi1_dma_addrs,
3720         .user           = OCP_USER_SDMA,
3721 };
3722
3723 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
3724         {
3725                 .pa_start       = 0x48044000,
3726                 .pa_end         = 0x480441ff,
3727                 .flags          = ADDR_TYPE_RT
3728         },
3729         { }
3730 };
3731
3732 /* l4_per -> dss_dsi1 */
3733 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
3734         .master         = &omap44xx_l4_per_hwmod,
3735         .slave          = &omap44xx_dss_dsi1_hwmod,
3736         .clk            = "l4_div_ck",
3737         .addr           = omap44xx_dss_dsi1_addrs,
3738         .user           = OCP_USER_MPU,
3739 };
3740
3741 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
3742         {
3743                 .pa_start       = 0x58005000,
3744                 .pa_end         = 0x580051ff,
3745                 .flags          = ADDR_TYPE_RT
3746         },
3747         { }
3748 };
3749
3750 /* l3_main_2 -> dss_dsi2 */
3751 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
3752         .master         = &omap44xx_l3_main_2_hwmod,
3753         .slave          = &omap44xx_dss_dsi2_hwmod,
3754         .clk            = "l3_div_ck",
3755         .addr           = omap44xx_dss_dsi2_dma_addrs,
3756         .user           = OCP_USER_SDMA,
3757 };
3758
3759 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
3760         {
3761                 .pa_start       = 0x48045000,
3762                 .pa_end         = 0x480451ff,
3763                 .flags          = ADDR_TYPE_RT
3764         },
3765         { }
3766 };
3767
3768 /* l4_per -> dss_dsi2 */
3769 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
3770         .master         = &omap44xx_l4_per_hwmod,
3771         .slave          = &omap44xx_dss_dsi2_hwmod,
3772         .clk            = "l4_div_ck",
3773         .addr           = omap44xx_dss_dsi2_addrs,
3774         .user           = OCP_USER_MPU,
3775 };
3776
3777 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
3778         {
3779                 .pa_start       = 0x58006000,
3780                 .pa_end         = 0x58006fff,
3781                 .flags          = ADDR_TYPE_RT
3782         },
3783         { }
3784 };
3785
3786 /* l3_main_2 -> dss_hdmi */
3787 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
3788         .master         = &omap44xx_l3_main_2_hwmod,
3789         .slave          = &omap44xx_dss_hdmi_hwmod,
3790         .clk            = "l3_div_ck",
3791         .addr           = omap44xx_dss_hdmi_dma_addrs,
3792         .user           = OCP_USER_SDMA,
3793 };
3794
3795 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
3796         {
3797                 .pa_start       = 0x48046000,
3798                 .pa_end         = 0x48046fff,
3799                 .flags          = ADDR_TYPE_RT
3800         },
3801         { }
3802 };
3803
3804 /* l4_per -> dss_hdmi */
3805 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
3806         .master         = &omap44xx_l4_per_hwmod,
3807         .slave          = &omap44xx_dss_hdmi_hwmod,
3808         .clk            = "l4_div_ck",
3809         .addr           = omap44xx_dss_hdmi_addrs,
3810         .user           = OCP_USER_MPU,
3811 };
3812
3813 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
3814         {
3815                 .pa_start       = 0x58002000,
3816                 .pa_end         = 0x580020ff,
3817                 .flags          = ADDR_TYPE_RT
3818         },
3819         { }
3820 };
3821
3822 /* l3_main_2 -> dss_rfbi */
3823 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
3824         .master         = &omap44xx_l3_main_2_hwmod,
3825         .slave          = &omap44xx_dss_rfbi_hwmod,
3826         .clk            = "l3_div_ck",
3827         .addr           = omap44xx_dss_rfbi_dma_addrs,
3828         .user           = OCP_USER_SDMA,
3829 };
3830
3831 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
3832         {
3833                 .pa_start       = 0x48042000,
3834                 .pa_end         = 0x480420ff,
3835                 .flags          = ADDR_TYPE_RT
3836         },
3837         { }
3838 };
3839
3840 /* l4_per -> dss_rfbi */
3841 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
3842         .master         = &omap44xx_l4_per_hwmod,
3843         .slave          = &omap44xx_dss_rfbi_hwmod,
3844         .clk            = "l4_div_ck",
3845         .addr           = omap44xx_dss_rfbi_addrs,
3846         .user           = OCP_USER_MPU,
3847 };
3848
3849 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
3850         {
3851                 .pa_start       = 0x58003000,
3852                 .pa_end         = 0x580030ff,
3853                 .flags          = ADDR_TYPE_RT
3854         },
3855         { }
3856 };
3857
3858 /* l3_main_2 -> dss_venc */
3859 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
3860         .master         = &omap44xx_l3_main_2_hwmod,
3861         .slave          = &omap44xx_dss_venc_hwmod,
3862         .clk            = "l3_div_ck",
3863         .addr           = omap44xx_dss_venc_dma_addrs,
3864         .user           = OCP_USER_SDMA,
3865 };
3866
3867 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
3868         {
3869                 .pa_start       = 0x48043000,
3870                 .pa_end         = 0x480430ff,
3871                 .flags          = ADDR_TYPE_RT
3872         },
3873         { }
3874 };
3875
3876 /* l4_per -> dss_venc */
3877 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
3878         .master         = &omap44xx_l4_per_hwmod,
3879         .slave          = &omap44xx_dss_venc_hwmod,
3880         .clk            = "l4_div_ck",
3881         .addr           = omap44xx_dss_venc_addrs,
3882         .user           = OCP_USER_MPU,
3883 };
3884
3885 /* l4_per -> elm */
3886 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
3887         .master         = &omap44xx_l4_per_hwmod,
3888         .slave          = &omap44xx_elm_hwmod,
3889         .clk            = "l4_div_ck",
3890         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3891 };
3892
3893 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
3894         {
3895                 .pa_start       = 0x4a10a000,
3896                 .pa_end         = 0x4a10a1ff,
3897                 .flags          = ADDR_TYPE_RT
3898         },
3899         { }
3900 };
3901
3902 /* l4_cfg -> fdif */
3903 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
3904         .master         = &omap44xx_l4_cfg_hwmod,
3905         .slave          = &omap44xx_fdif_hwmod,
3906         .clk            = "l4_div_ck",
3907         .addr           = omap44xx_fdif_addrs,
3908         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3909 };
3910
3911 /* l4_wkup -> gpio1 */
3912 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
3913         .master         = &omap44xx_l4_wkup_hwmod,
3914         .slave          = &omap44xx_gpio1_hwmod,
3915         .clk            = "l4_wkup_clk_mux_ck",
3916         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3917 };
3918
3919 /* l4_per -> gpio2 */
3920 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
3921         .master         = &omap44xx_l4_per_hwmod,
3922         .slave          = &omap44xx_gpio2_hwmod,
3923         .clk            = "l4_div_ck",
3924         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3925 };
3926
3927 /* l4_per -> gpio3 */
3928 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
3929         .master         = &omap44xx_l4_per_hwmod,
3930         .slave          = &omap44xx_gpio3_hwmod,
3931         .clk            = "l4_div_ck",
3932         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3933 };
3934
3935 /* l4_per -> gpio4 */
3936 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
3937         .master         = &omap44xx_l4_per_hwmod,
3938         .slave          = &omap44xx_gpio4_hwmod,
3939         .clk            = "l4_div_ck",
3940         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3941 };
3942
3943 /* l4_per -> gpio5 */
3944 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
3945         .master         = &omap44xx_l4_per_hwmod,
3946         .slave          = &omap44xx_gpio5_hwmod,
3947         .clk            = "l4_div_ck",
3948         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3949 };
3950
3951 /* l4_per -> gpio6 */
3952 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
3953         .master         = &omap44xx_l4_per_hwmod,
3954         .slave          = &omap44xx_gpio6_hwmod,
3955         .clk            = "l4_div_ck",
3956         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3957 };
3958
3959 /* l3_main_2 -> gpmc */
3960 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
3961         .master         = &omap44xx_l3_main_2_hwmod,
3962         .slave          = &omap44xx_gpmc_hwmod,
3963         .clk            = "l3_div_ck",
3964         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3965 };
3966
3967 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
3968         {
3969                 .pa_start       = 0x56000000,
3970                 .pa_end         = 0x5600ffff,
3971                 .flags          = ADDR_TYPE_RT
3972         },
3973         { }
3974 };
3975
3976 /* l3_main_2 -> gpu */
3977 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
3978         .master         = &omap44xx_l3_main_2_hwmod,
3979         .slave          = &omap44xx_gpu_hwmod,
3980         .clk            = "l3_div_ck",
3981         .addr           = omap44xx_gpu_addrs,
3982         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3983 };
3984
3985 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
3986         {
3987                 .pa_start       = 0x480b2000,
3988                 .pa_end         = 0x480b201f,
3989                 .flags          = ADDR_TYPE_RT
3990         },
3991         { }
3992 };
3993
3994 /* l4_per -> hdq1w */
3995 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
3996         .master         = &omap44xx_l4_per_hwmod,
3997         .slave          = &omap44xx_hdq1w_hwmod,
3998         .clk            = "l4_div_ck",
3999         .addr           = omap44xx_hdq1w_addrs,
4000         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4001 };
4002
4003 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4004         {
4005                 .pa_start       = 0x4a058000,
4006                 .pa_end         = 0x4a05bfff,
4007                 .flags          = ADDR_TYPE_RT
4008         },
4009         { }
4010 };
4011
4012 /* l4_cfg -> hsi */
4013 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4014         .master         = &omap44xx_l4_cfg_hwmod,
4015         .slave          = &omap44xx_hsi_hwmod,
4016         .clk            = "l4_div_ck",
4017         .addr           = omap44xx_hsi_addrs,
4018         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4019 };
4020
4021 /* l4_per -> i2c1 */
4022 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4023         .master         = &omap44xx_l4_per_hwmod,
4024         .slave          = &omap44xx_i2c1_hwmod,
4025         .clk            = "l4_div_ck",
4026         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4027 };
4028
4029 /* l4_per -> i2c2 */
4030 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
4031         .master         = &omap44xx_l4_per_hwmod,
4032         .slave          = &omap44xx_i2c2_hwmod,
4033         .clk            = "l4_div_ck",
4034         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4035 };
4036
4037 /* l4_per -> i2c3 */
4038 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
4039         .master         = &omap44xx_l4_per_hwmod,
4040         .slave          = &omap44xx_i2c3_hwmod,
4041         .clk            = "l4_div_ck",
4042         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4043 };
4044
4045 /* l4_per -> i2c4 */
4046 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
4047         .master         = &omap44xx_l4_per_hwmod,
4048         .slave          = &omap44xx_i2c4_hwmod,
4049         .clk            = "l4_div_ck",
4050         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4051 };
4052
4053 /* l3_main_2 -> ipu */
4054 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
4055         .master         = &omap44xx_l3_main_2_hwmod,
4056         .slave          = &omap44xx_ipu_hwmod,
4057         .clk            = "l3_div_ck",
4058         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4059 };
4060
4061 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
4062         {
4063                 .pa_start       = 0x52000000,
4064                 .pa_end         = 0x520000ff,
4065                 .flags          = ADDR_TYPE_RT
4066         },
4067         { }
4068 };
4069
4070 /* l3_main_2 -> iss */
4071 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
4072         .master         = &omap44xx_l3_main_2_hwmod,
4073         .slave          = &omap44xx_iss_hwmod,
4074         .clk            = "l3_div_ck",
4075         .addr           = omap44xx_iss_addrs,
4076         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4077 };
4078
4079 /* iva -> sl2if */
4080 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
4081         .master         = &omap44xx_iva_hwmod,
4082         .slave          = &omap44xx_sl2if_hwmod,
4083         .clk            = "dpll_iva_m5x2_ck",
4084         .user           = OCP_USER_IVA,
4085 };
4086
4087 /* l3_main_2 -> iva */
4088 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
4089         .master         = &omap44xx_l3_main_2_hwmod,
4090         .slave          = &omap44xx_iva_hwmod,
4091         .clk            = "l3_div_ck",
4092         .user           = OCP_USER_MPU,
4093 };
4094
4095 /* l4_wkup -> kbd */
4096 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
4097         .master         = &omap44xx_l4_wkup_hwmod,
4098         .slave          = &omap44xx_kbd_hwmod,
4099         .clk            = "l4_wkup_clk_mux_ck",
4100         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4101 };
4102
4103 /* l4_cfg -> mailbox */
4104 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
4105         .master         = &omap44xx_l4_cfg_hwmod,
4106         .slave          = &omap44xx_mailbox_hwmod,
4107         .clk            = "l4_div_ck",
4108         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4109 };
4110
4111 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
4112         {
4113                 .pa_start       = 0x40128000,
4114                 .pa_end         = 0x401283ff,
4115                 .flags          = ADDR_TYPE_RT
4116         },
4117         { }
4118 };
4119
4120 /* l4_abe -> mcasp */
4121 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
4122         .master         = &omap44xx_l4_abe_hwmod,
4123         .slave          = &omap44xx_mcasp_hwmod,
4124         .clk            = "ocp_abe_iclk",
4125         .addr           = omap44xx_mcasp_addrs,
4126         .user           = OCP_USER_MPU,
4127 };
4128
4129 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
4130         {
4131                 .pa_start       = 0x49028000,
4132                 .pa_end         = 0x490283ff,
4133                 .flags          = ADDR_TYPE_RT
4134         },
4135         { }
4136 };
4137
4138 /* l4_abe -> mcasp (dma) */
4139 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
4140         .master         = &omap44xx_l4_abe_hwmod,
4141         .slave          = &omap44xx_mcasp_hwmod,
4142         .clk            = "ocp_abe_iclk",
4143         .addr           = omap44xx_mcasp_dma_addrs,
4144         .user           = OCP_USER_SDMA,
4145 };
4146
4147 /* l4_abe -> mcbsp1 */
4148 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
4149         .master         = &omap44xx_l4_abe_hwmod,
4150         .slave          = &omap44xx_mcbsp1_hwmod,
4151         .clk            = "ocp_abe_iclk",
4152         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4153 };
4154
4155 /* l4_abe -> mcbsp2 */
4156 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
4157         .master         = &omap44xx_l4_abe_hwmod,
4158         .slave          = &omap44xx_mcbsp2_hwmod,
4159         .clk            = "ocp_abe_iclk",
4160         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4161 };
4162
4163 /* l4_abe -> mcbsp3 */
4164 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
4165         .master         = &omap44xx_l4_abe_hwmod,
4166         .slave          = &omap44xx_mcbsp3_hwmod,
4167         .clk            = "ocp_abe_iclk",
4168         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4169 };
4170
4171 /* l4_per -> mcbsp4 */
4172 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
4173         .master         = &omap44xx_l4_per_hwmod,
4174         .slave          = &omap44xx_mcbsp4_hwmod,
4175         .clk            = "l4_div_ck",
4176         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4177 };
4178
4179 /* l4_abe -> mcpdm */
4180 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
4181         .master         = &omap44xx_l4_abe_hwmod,
4182         .slave          = &omap44xx_mcpdm_hwmod,
4183         .clk            = "ocp_abe_iclk",
4184         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4185 };
4186
4187 /* l4_per -> mcspi1 */
4188 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
4189         .master         = &omap44xx_l4_per_hwmod,
4190         .slave          = &omap44xx_mcspi1_hwmod,
4191         .clk            = "l4_div_ck",
4192         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4193 };
4194
4195 /* l4_per -> mcspi2 */
4196 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
4197         .master         = &omap44xx_l4_per_hwmod,
4198         .slave          = &omap44xx_mcspi2_hwmod,
4199         .clk            = "l4_div_ck",
4200         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4201 };
4202
4203 /* l4_per -> mcspi3 */
4204 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
4205         .master         = &omap44xx_l4_per_hwmod,
4206         .slave          = &omap44xx_mcspi3_hwmod,
4207         .clk            = "l4_div_ck",
4208         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4209 };
4210
4211 /* l4_per -> mcspi4 */
4212 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
4213         .master         = &omap44xx_l4_per_hwmod,
4214         .slave          = &omap44xx_mcspi4_hwmod,
4215         .clk            = "l4_div_ck",
4216         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4217 };
4218
4219 /* l4_per -> mmc1 */
4220 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
4221         .master         = &omap44xx_l4_per_hwmod,
4222         .slave          = &omap44xx_mmc1_hwmod,
4223         .clk            = "l4_div_ck",
4224         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4225 };
4226
4227 /* l4_per -> mmc2 */
4228 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
4229         .master         = &omap44xx_l4_per_hwmod,
4230         .slave          = &omap44xx_mmc2_hwmod,
4231         .clk            = "l4_div_ck",
4232         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4233 };
4234
4235 /* l4_per -> mmc3 */
4236 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
4237         .master         = &omap44xx_l4_per_hwmod,
4238         .slave          = &omap44xx_mmc3_hwmod,
4239         .clk            = "l4_div_ck",
4240         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4241 };
4242
4243 /* l4_per -> mmc4 */
4244 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
4245         .master         = &omap44xx_l4_per_hwmod,
4246         .slave          = &omap44xx_mmc4_hwmod,
4247         .clk            = "l4_div_ck",
4248         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4249 };
4250
4251 /* l4_per -> mmc5 */
4252 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
4253         .master         = &omap44xx_l4_per_hwmod,
4254         .slave          = &omap44xx_mmc5_hwmod,
4255         .clk            = "l4_div_ck",
4256         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4257 };
4258
4259 /* l3_main_2 -> ocmc_ram */
4260 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
4261         .master         = &omap44xx_l3_main_2_hwmod,
4262         .slave          = &omap44xx_ocmc_ram_hwmod,
4263         .clk            = "l3_div_ck",
4264         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4265 };
4266
4267 /* l4_cfg -> ocp2scp_usb_phy */
4268 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
4269         .master         = &omap44xx_l4_cfg_hwmod,
4270         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
4271         .clk            = "l4_div_ck",
4272         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4273 };
4274
4275 /* mpu_private -> prcm_mpu */
4276 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
4277         .master         = &omap44xx_mpu_private_hwmod,
4278         .slave          = &omap44xx_prcm_mpu_hwmod,
4279         .clk            = "l3_div_ck",
4280         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4281 };
4282
4283 /* l4_wkup -> cm_core_aon */
4284 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
4285         .master         = &omap44xx_l4_wkup_hwmod,
4286         .slave          = &omap44xx_cm_core_aon_hwmod,
4287         .clk            = "l4_wkup_clk_mux_ck",
4288         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4289 };
4290
4291 /* l4_cfg -> cm_core */
4292 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
4293         .master         = &omap44xx_l4_cfg_hwmod,
4294         .slave          = &omap44xx_cm_core_hwmod,
4295         .clk            = "l4_div_ck",
4296         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4297 };
4298
4299 /* l4_wkup -> prm */
4300 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
4301         .master         = &omap44xx_l4_wkup_hwmod,
4302         .slave          = &omap44xx_prm_hwmod,
4303         .clk            = "l4_wkup_clk_mux_ck",
4304         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4305 };
4306
4307 /* l4_wkup -> scrm */
4308 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
4309         .master         = &omap44xx_l4_wkup_hwmod,
4310         .slave          = &omap44xx_scrm_hwmod,
4311         .clk            = "l4_wkup_clk_mux_ck",
4312         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4313 };
4314
4315 /* l3_main_2 -> sl2if */
4316 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
4317         .master         = &omap44xx_l3_main_2_hwmod,
4318         .slave          = &omap44xx_sl2if_hwmod,
4319         .clk            = "l3_div_ck",
4320         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4321 };
4322
4323 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
4324         {
4325                 .pa_start       = 0x4012c000,
4326                 .pa_end         = 0x4012c3ff,
4327                 .flags          = ADDR_TYPE_RT
4328         },
4329         { }
4330 };
4331
4332 /* l4_abe -> slimbus1 */
4333 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
4334         .master         = &omap44xx_l4_abe_hwmod,
4335         .slave          = &omap44xx_slimbus1_hwmod,
4336         .clk            = "ocp_abe_iclk",
4337         .addr           = omap44xx_slimbus1_addrs,
4338         .user           = OCP_USER_MPU,
4339 };
4340
4341 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
4342         {
4343                 .pa_start       = 0x4902c000,
4344                 .pa_end         = 0x4902c3ff,
4345                 .flags          = ADDR_TYPE_RT
4346         },
4347         { }
4348 };
4349
4350 /* l4_abe -> slimbus1 (dma) */
4351 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
4352         .master         = &omap44xx_l4_abe_hwmod,
4353         .slave          = &omap44xx_slimbus1_hwmod,
4354         .clk            = "ocp_abe_iclk",
4355         .addr           = omap44xx_slimbus1_dma_addrs,
4356         .user           = OCP_USER_SDMA,
4357 };
4358
4359 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
4360         {
4361                 .pa_start       = 0x48076000,
4362                 .pa_end         = 0x480763ff,
4363                 .flags          = ADDR_TYPE_RT
4364         },
4365         { }
4366 };
4367
4368 /* l4_per -> slimbus2 */
4369 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
4370         .master         = &omap44xx_l4_per_hwmod,
4371         .slave          = &omap44xx_slimbus2_hwmod,
4372         .clk            = "l4_div_ck",
4373         .addr           = omap44xx_slimbus2_addrs,
4374         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4375 };
4376
4377 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
4378         {
4379                 .pa_start       = 0x4a0dd000,
4380                 .pa_end         = 0x4a0dd03f,
4381                 .flags          = ADDR_TYPE_RT
4382         },
4383         { }
4384 };
4385
4386 /* l4_cfg -> smartreflex_core */
4387 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
4388         .master         = &omap44xx_l4_cfg_hwmod,
4389         .slave          = &omap44xx_smartreflex_core_hwmod,
4390         .clk            = "l4_div_ck",
4391         .addr           = omap44xx_smartreflex_core_addrs,
4392         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4393 };
4394
4395 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
4396         {
4397                 .pa_start       = 0x4a0db000,
4398                 .pa_end         = 0x4a0db03f,
4399                 .flags          = ADDR_TYPE_RT
4400         },
4401         { }
4402 };
4403
4404 /* l4_cfg -> smartreflex_iva */
4405 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
4406         .master         = &omap44xx_l4_cfg_hwmod,
4407         .slave          = &omap44xx_smartreflex_iva_hwmod,
4408         .clk            = "l4_div_ck",
4409         .addr           = omap44xx_smartreflex_iva_addrs,
4410         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4411 };
4412
4413 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
4414         {
4415                 .pa_start       = 0x4a0d9000,
4416                 .pa_end         = 0x4a0d903f,
4417                 .flags          = ADDR_TYPE_RT
4418         },
4419         { }
4420 };
4421
4422 /* l4_cfg -> smartreflex_mpu */
4423 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
4424         .master         = &omap44xx_l4_cfg_hwmod,
4425         .slave          = &omap44xx_smartreflex_mpu_hwmod,
4426         .clk            = "l4_div_ck",
4427         .addr           = omap44xx_smartreflex_mpu_addrs,
4428         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4429 };
4430
4431 /* l4_cfg -> spinlock */
4432 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
4433         .master         = &omap44xx_l4_cfg_hwmod,
4434         .slave          = &omap44xx_spinlock_hwmod,
4435         .clk            = "l4_div_ck",
4436         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4437 };
4438
4439 /* l4_wkup -> timer1 */
4440 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4441         .master         = &omap44xx_l4_wkup_hwmod,
4442         .slave          = &omap44xx_timer1_hwmod,
4443         .clk            = "l4_wkup_clk_mux_ck",
4444         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4445 };
4446
4447 /* l4_per -> timer2 */
4448 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4449         .master         = &omap44xx_l4_per_hwmod,
4450         .slave          = &omap44xx_timer2_hwmod,
4451         .clk            = "l4_div_ck",
4452         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4453 };
4454
4455 /* l4_per -> timer3 */
4456 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4457         .master         = &omap44xx_l4_per_hwmod,
4458         .slave          = &omap44xx_timer3_hwmod,
4459         .clk            = "l4_div_ck",
4460         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4461 };
4462
4463 /* l4_per -> timer4 */
4464 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4465         .master         = &omap44xx_l4_per_hwmod,
4466         .slave          = &omap44xx_timer4_hwmod,
4467         .clk            = "l4_div_ck",
4468         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4469 };
4470
4471 /* l4_abe -> timer5 */
4472 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4473         .master         = &omap44xx_l4_abe_hwmod,
4474         .slave          = &omap44xx_timer5_hwmod,
4475         .clk            = "ocp_abe_iclk",
4476         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4477 };
4478
4479 /* l4_abe -> timer6 */
4480 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4481         .master         = &omap44xx_l4_abe_hwmod,
4482         .slave          = &omap44xx_timer6_hwmod,
4483         .clk            = "ocp_abe_iclk",
4484         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4485 };
4486
4487 /* l4_abe -> timer7 */
4488 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4489         .master         = &omap44xx_l4_abe_hwmod,
4490         .slave          = &omap44xx_timer7_hwmod,
4491         .clk            = "ocp_abe_iclk",
4492         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4493 };
4494
4495 /* l4_abe -> timer8 */
4496 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4497         .master         = &omap44xx_l4_abe_hwmod,
4498         .slave          = &omap44xx_timer8_hwmod,
4499         .clk            = "ocp_abe_iclk",
4500         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4501 };
4502
4503 /* l4_per -> timer9 */
4504 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4505         .master         = &omap44xx_l4_per_hwmod,
4506         .slave          = &omap44xx_timer9_hwmod,
4507         .clk            = "l4_div_ck",
4508         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4509 };
4510
4511 /* l4_per -> timer10 */
4512 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4513         .master         = &omap44xx_l4_per_hwmod,
4514         .slave          = &omap44xx_timer10_hwmod,
4515         .clk            = "l4_div_ck",
4516         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4517 };
4518
4519 /* l4_per -> timer11 */
4520 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4521         .master         = &omap44xx_l4_per_hwmod,
4522         .slave          = &omap44xx_timer11_hwmod,
4523         .clk            = "l4_div_ck",
4524         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4525 };
4526
4527 /* l4_per -> uart1 */
4528 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4529         .master         = &omap44xx_l4_per_hwmod,
4530         .slave          = &omap44xx_uart1_hwmod,
4531         .clk            = "l4_div_ck",
4532         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4533 };
4534
4535 /* l4_per -> uart2 */
4536 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4537         .master         = &omap44xx_l4_per_hwmod,
4538         .slave          = &omap44xx_uart2_hwmod,
4539         .clk            = "l4_div_ck",
4540         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4541 };
4542
4543 /* l4_per -> uart3 */
4544 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4545         .master         = &omap44xx_l4_per_hwmod,
4546         .slave          = &omap44xx_uart3_hwmod,
4547         .clk            = "l4_div_ck",
4548         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4549 };
4550
4551 /* l4_per -> uart4 */
4552 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
4553         .master         = &omap44xx_l4_per_hwmod,
4554         .slave          = &omap44xx_uart4_hwmod,
4555         .clk            = "l4_div_ck",
4556         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4557 };
4558
4559 /* l4_cfg -> usb_host_fs */
4560 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
4561         .master         = &omap44xx_l4_cfg_hwmod,
4562         .slave          = &omap44xx_usb_host_fs_hwmod,
4563         .clk            = "l4_div_ck",
4564         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4565 };
4566
4567 /* l4_cfg -> usb_host_hs */
4568 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
4569         .master         = &omap44xx_l4_cfg_hwmod,
4570         .slave          = &omap44xx_usb_host_hs_hwmod,
4571         .clk            = "l4_div_ck",
4572         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4573 };
4574
4575 /* l4_cfg -> usb_otg_hs */
4576 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4577         .master         = &omap44xx_l4_cfg_hwmod,
4578         .slave          = &omap44xx_usb_otg_hs_hwmod,
4579         .clk            = "l4_div_ck",
4580         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4581 };
4582
4583 /* l4_cfg -> usb_tll_hs */
4584 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
4585         .master         = &omap44xx_l4_cfg_hwmod,
4586         .slave          = &omap44xx_usb_tll_hs_hwmod,
4587         .clk            = "l4_div_ck",
4588         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4589 };
4590
4591 /* l4_wkup -> wd_timer2 */
4592 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
4593         .master         = &omap44xx_l4_wkup_hwmod,
4594         .slave          = &omap44xx_wd_timer2_hwmod,
4595         .clk            = "l4_wkup_clk_mux_ck",
4596         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4597 };
4598
4599 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
4600         {
4601                 .pa_start       = 0x40130000,
4602                 .pa_end         = 0x4013007f,
4603                 .flags          = ADDR_TYPE_RT
4604         },
4605         { }
4606 };
4607
4608 /* l4_abe -> wd_timer3 */
4609 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
4610         .master         = &omap44xx_l4_abe_hwmod,
4611         .slave          = &omap44xx_wd_timer3_hwmod,
4612         .clk            = "ocp_abe_iclk",
4613         .addr           = omap44xx_wd_timer3_addrs,
4614         .user           = OCP_USER_MPU,
4615 };
4616
4617 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
4618         {
4619                 .pa_start       = 0x49030000,
4620                 .pa_end         = 0x4903007f,
4621                 .flags          = ADDR_TYPE_RT
4622         },
4623         { }
4624 };
4625
4626 /* l4_abe -> wd_timer3 (dma) */
4627 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
4628         .master         = &omap44xx_l4_abe_hwmod,
4629         .slave          = &omap44xx_wd_timer3_hwmod,
4630         .clk            = "ocp_abe_iclk",
4631         .addr           = omap44xx_wd_timer3_dma_addrs,
4632         .user           = OCP_USER_SDMA,
4633 };
4634
4635 /* mpu -> emif1 */
4636 static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
4637         .master         = &omap44xx_mpu_hwmod,
4638         .slave          = &omap44xx_emif1_hwmod,
4639         .clk            = "l3_div_ck",
4640         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4641 };
4642
4643 /* mpu -> emif2 */
4644 static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
4645         .master         = &omap44xx_mpu_hwmod,
4646         .slave          = &omap44xx_emif2_hwmod,
4647         .clk            = "l3_div_ck",
4648         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4649 };
4650
4651 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
4652         &omap44xx_l3_main_1__dmm,
4653         &omap44xx_mpu__dmm,
4654         &omap44xx_iva__l3_instr,
4655         &omap44xx_l3_main_3__l3_instr,
4656         &omap44xx_ocp_wp_noc__l3_instr,
4657         &omap44xx_dsp__l3_main_1,
4658         &omap44xx_dss__l3_main_1,
4659         &omap44xx_l3_main_2__l3_main_1,
4660         &omap44xx_l4_cfg__l3_main_1,
4661         &omap44xx_mmc1__l3_main_1,
4662         &omap44xx_mmc2__l3_main_1,
4663         &omap44xx_mpu__l3_main_1,
4664         &omap44xx_debugss__l3_main_2,
4665         &omap44xx_dma_system__l3_main_2,
4666         &omap44xx_fdif__l3_main_2,
4667         &omap44xx_gpu__l3_main_2,
4668         &omap44xx_hsi__l3_main_2,
4669         &omap44xx_ipu__l3_main_2,
4670         &omap44xx_iss__l3_main_2,
4671         &omap44xx_iva__l3_main_2,
4672         &omap44xx_l3_main_1__l3_main_2,
4673         &omap44xx_l4_cfg__l3_main_2,
4674         /* &omap44xx_usb_host_fs__l3_main_2, */
4675         &omap44xx_usb_host_hs__l3_main_2,
4676         &omap44xx_usb_otg_hs__l3_main_2,
4677         &omap44xx_l3_main_1__l3_main_3,
4678         &omap44xx_l3_main_2__l3_main_3,
4679         &omap44xx_l4_cfg__l3_main_3,
4680         &omap44xx_aess__l4_abe,
4681         &omap44xx_dsp__l4_abe,
4682         &omap44xx_l3_main_1__l4_abe,
4683         &omap44xx_mpu__l4_abe,
4684         &omap44xx_l3_main_1__l4_cfg,
4685         &omap44xx_l3_main_2__l4_per,
4686         &omap44xx_l4_cfg__l4_wkup,
4687         &omap44xx_mpu__mpu_private,
4688         &omap44xx_l4_cfg__ocp_wp_noc,
4689         &omap44xx_l4_abe__aess,
4690         &omap44xx_l4_abe__aess_dma,
4691         &omap44xx_l3_main_2__c2c,
4692         &omap44xx_l4_wkup__counter_32k,
4693         &omap44xx_l4_cfg__ctrl_module_core,
4694         &omap44xx_l4_cfg__ctrl_module_pad_core,
4695         &omap44xx_l4_wkup__ctrl_module_wkup,
4696         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
4697         &omap44xx_l3_instr__debugss,
4698         &omap44xx_l4_cfg__dma_system,
4699         &omap44xx_l4_abe__dmic,
4700         &omap44xx_dsp__iva,
4701         /* &omap44xx_dsp__sl2if, */
4702         &omap44xx_l4_cfg__dsp,
4703         &omap44xx_l3_main_2__dss,
4704         &omap44xx_l4_per__dss,
4705         &omap44xx_l3_main_2__dss_dispc,
4706         &omap44xx_l4_per__dss_dispc,
4707         &omap44xx_l3_main_2__dss_dsi1,
4708         &omap44xx_l4_per__dss_dsi1,
4709         &omap44xx_l3_main_2__dss_dsi2,
4710         &omap44xx_l4_per__dss_dsi2,
4711         &omap44xx_l3_main_2__dss_hdmi,
4712         &omap44xx_l4_per__dss_hdmi,
4713         &omap44xx_l3_main_2__dss_rfbi,
4714         &omap44xx_l4_per__dss_rfbi,
4715         &omap44xx_l3_main_2__dss_venc,
4716         &omap44xx_l4_per__dss_venc,
4717         &omap44xx_l4_per__elm,
4718         &omap44xx_l4_cfg__fdif,
4719         &omap44xx_l4_wkup__gpio1,
4720         &omap44xx_l4_per__gpio2,
4721         &omap44xx_l4_per__gpio3,
4722         &omap44xx_l4_per__gpio4,
4723         &omap44xx_l4_per__gpio5,
4724         &omap44xx_l4_per__gpio6,
4725         &omap44xx_l3_main_2__gpmc,
4726         &omap44xx_l3_main_2__gpu,
4727         &omap44xx_l4_per__hdq1w,
4728         &omap44xx_l4_cfg__hsi,
4729         &omap44xx_l4_per__i2c1,
4730         &omap44xx_l4_per__i2c2,
4731         &omap44xx_l4_per__i2c3,
4732         &omap44xx_l4_per__i2c4,
4733         &omap44xx_l3_main_2__ipu,
4734         &omap44xx_l3_main_2__iss,
4735         /* &omap44xx_iva__sl2if, */
4736         &omap44xx_l3_main_2__iva,
4737         &omap44xx_l4_wkup__kbd,
4738         &omap44xx_l4_cfg__mailbox,
4739         &omap44xx_l4_abe__mcasp,
4740         &omap44xx_l4_abe__mcasp_dma,
4741         &omap44xx_l4_abe__mcbsp1,
4742         &omap44xx_l4_abe__mcbsp2,
4743         &omap44xx_l4_abe__mcbsp3,
4744         &omap44xx_l4_per__mcbsp4,
4745         &omap44xx_l4_abe__mcpdm,
4746         &omap44xx_l4_per__mcspi1,
4747         &omap44xx_l4_per__mcspi2,
4748         &omap44xx_l4_per__mcspi3,
4749         &omap44xx_l4_per__mcspi4,
4750         &omap44xx_l4_per__mmc1,
4751         &omap44xx_l4_per__mmc2,
4752         &omap44xx_l4_per__mmc3,
4753         &omap44xx_l4_per__mmc4,
4754         &omap44xx_l4_per__mmc5,
4755         &omap44xx_l3_main_2__mmu_ipu,
4756         &omap44xx_l4_cfg__mmu_dsp,
4757         &omap44xx_l3_main_2__ocmc_ram,
4758         &omap44xx_l4_cfg__ocp2scp_usb_phy,
4759         &omap44xx_mpu_private__prcm_mpu,
4760         &omap44xx_l4_wkup__cm_core_aon,
4761         &omap44xx_l4_cfg__cm_core,
4762         &omap44xx_l4_wkup__prm,
4763         &omap44xx_l4_wkup__scrm,
4764         /* &omap44xx_l3_main_2__sl2if, */
4765         &omap44xx_l4_abe__slimbus1,
4766         &omap44xx_l4_abe__slimbus1_dma,
4767         &omap44xx_l4_per__slimbus2,
4768         &omap44xx_l4_cfg__smartreflex_core,
4769         &omap44xx_l4_cfg__smartreflex_iva,
4770         &omap44xx_l4_cfg__smartreflex_mpu,
4771         &omap44xx_l4_cfg__spinlock,
4772         &omap44xx_l4_wkup__timer1,
4773         &omap44xx_l4_per__timer2,
4774         &omap44xx_l4_per__timer3,
4775         &omap44xx_l4_per__timer4,
4776         &omap44xx_l4_abe__timer5,
4777         &omap44xx_l4_abe__timer6,
4778         &omap44xx_l4_abe__timer7,
4779         &omap44xx_l4_abe__timer8,
4780         &omap44xx_l4_per__timer9,
4781         &omap44xx_l4_per__timer10,
4782         &omap44xx_l4_per__timer11,
4783         &omap44xx_l4_per__uart1,
4784         &omap44xx_l4_per__uart2,
4785         &omap44xx_l4_per__uart3,
4786         &omap44xx_l4_per__uart4,
4787         /* &omap44xx_l4_cfg__usb_host_fs, */
4788         &omap44xx_l4_cfg__usb_host_hs,
4789         &omap44xx_l4_cfg__usb_otg_hs,
4790         &omap44xx_l4_cfg__usb_tll_hs,
4791         &omap44xx_l4_wkup__wd_timer2,
4792         &omap44xx_l4_abe__wd_timer3,
4793         &omap44xx_l4_abe__wd_timer3_dma,
4794         &omap44xx_mpu__emif1,
4795         &omap44xx_mpu__emif2,
4796         NULL,
4797 };
4798
4799 int __init omap44xx_hwmod_init(void)
4800 {
4801         omap_hwmod_init();
4802         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
4803 }
4804