arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  * Note that this file is currently not in sync with autogeneration scripts.
  16  * The above note to be removed, once it is synced up.
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License version 2 as
  20  * published by the Free Software Foundation.
  21  */
  22
  23 #include <linux/io.h>
  24 #include <linux/platform_data/gpio-omap.h>
  25 #include <linux/platform_data/hsmmc-omap.h>
  26 #include <linux/power/smartreflex.h>
  27 #include <linux/i2c-omap.h>
  28
  29 #include <linux/omap-dma.h>
  30
  31 #include <linux/platform_data/spi-omap2-mcspi.h>
  32 #include <linux/platform_data/asoc-ti-mcbsp.h>
  33 #include <plat/dmtimer.h>
  34
  35 #include "omap_hwmod.h"
  36 #include "omap_hwmod_common_data.h"
  37 #include "cm1_44xx.h"
  38 #include "cm2_44xx.h"
  39 #include "prm44xx.h"
  40 #include "prm-regbits-44xx.h"
  41 #include "i2c.h"
  42 #include "wd_timer.h"
  43
  44 /* Base offset for all OMAP4 interrupts external to MPUSS */
  45 #define OMAP44XX_IRQ_GIC_START  32
  46
  47 /* Base offset for all OMAP4 dma requests */
  48 #define OMAP44XX_DMA_REQ_START  1
  49
  50 /*
  51  * IP blocks
  52  */
  53
  54 /*
  55  * 'dmm' class
  56  * instance(s): dmm
  57  */
  58 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  59         .name   = "dmm",
  60 };
  61
  62 /* dmm */
  63 static struct omap_hwmod omap44xx_dmm_hwmod = {
  64         .name           = "dmm",
  65         .class          = &omap44xx_dmm_hwmod_class,
  66         .clkdm_name     = "l3_emif_clkdm",
  67         .prcm = {
  68                 .omap4 = {
  69                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  70                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  71                 },
  72         },
  73 };
  74
  75 /*
  76  * 'l3' class
  77  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  78  */
  79 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
  80         .name   = "l3",
  81 };
  82
  83 /* l3_instr */
  84 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
  85         .name           = "l3_instr",
  86         .class          = &omap44xx_l3_hwmod_class,
  87         .clkdm_name     = "l3_instr_clkdm",
  88         .prcm = {
  89                 .omap4 = {
  90                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  91                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  92                         .modulemode   = MODULEMODE_HWCTRL,
  93                 },
  94         },
  95 };
  96
  97 /* l3_main_1 */
  98 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
  99         .name           = "l3_main_1",
 100         .class          = &omap44xx_l3_hwmod_class,
 101         .clkdm_name     = "l3_1_clkdm",
 102         .prcm = {
 103                 .omap4 = {
 104                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 105                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 106                 },
 107         },
 108 };
 109
 110 /* l3_main_2 */
 111 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 112         .name           = "l3_main_2",
 113         .class          = &omap44xx_l3_hwmod_class,
 114         .clkdm_name     = "l3_2_clkdm",
 115         .prcm = {
 116                 .omap4 = {
 117                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 118                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 119                 },
 120         },
 121 };
 122
 123 /* l3_main_3 */
 124 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 125         .name           = "l3_main_3",
 126         .class          = &omap44xx_l3_hwmod_class,
 127         .clkdm_name     = "l3_instr_clkdm",
 128         .prcm = {
 129                 .omap4 = {
 130                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 131                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 132                         .modulemode   = MODULEMODE_HWCTRL,
 133                 },
 134         },
 135 };
 136
 137 /*
 138  * 'l4' class
 139  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 140  */
 141 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 142         .name   = "l4",
 143 };
 144
 145 /* l4_abe */
 146 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 147         .name           = "l4_abe",
 148         .class          = &omap44xx_l4_hwmod_class,
 149         .clkdm_name     = "abe_clkdm",
 150         .prcm = {
 151                 .omap4 = {
 152                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 153                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 154                         .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
 155                         .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 156                 },
 157         },
 158 };
 159
 160 /* l4_cfg */
 161 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 162         .name           = "l4_cfg",
 163         .class          = &omap44xx_l4_hwmod_class,
 164         .clkdm_name     = "l4_cfg_clkdm",
 165         .prcm = {
 166                 .omap4 = {
 167                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 168                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 169                 },
 170         },
 171 };
 172
 173 /* l4_per */
 174 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 175         .name           = "l4_per",
 176         .class          = &omap44xx_l4_hwmod_class,
 177         .clkdm_name     = "l4_per_clkdm",
 178         .prcm = {
 179                 .omap4 = {
 180                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 181                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 182                 },
 183         },
 184 };
 185
 186 /* l4_wkup */
 187 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 188         .name           = "l4_wkup",
 189         .class          = &omap44xx_l4_hwmod_class,
 190         .clkdm_name     = "l4_wkup_clkdm",
 191         .prcm = {
 192                 .omap4 = {
 193                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 194                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 195                 },
 196         },
 197 };
 198
 199 /*
 200  * 'mpu_bus' class
 201  * instance(s): mpu_private
 202  */
 203 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 204         .name   = "mpu_bus",
 205 };
 206
 207 /* mpu_private */
 208 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 209         .name           = "mpu_private",
 210         .class          = &omap44xx_mpu_bus_hwmod_class,
 211         .clkdm_name     = "mpuss_clkdm",
 212         .prcm = {
 213                 .omap4 = {
 214                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 215                 },
 216         },
 217 };
 218
 219 /*
 220  * 'ocp_wp_noc' class
 221  * instance(s): ocp_wp_noc
 222  */
 223 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 224         .name   = "ocp_wp_noc",
 225 };
 226
 227 /* ocp_wp_noc */
 228 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 229         .name           = "ocp_wp_noc",
 230         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 231         .clkdm_name     = "l3_instr_clkdm",
 232         .prcm = {
 233                 .omap4 = {
 234                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 235                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 236                         .modulemode   = MODULEMODE_HWCTRL,
 237                 },
 238         },
 239 };
 240
 241 /*
 242  * Modules omap_hwmod structures
 243  *
 244  * The following IPs are excluded for the moment because:
 245  * - They do not need an explicit SW control using omap_hwmod API.
 246  * - They still need to be validated with the driver
 247  *   properly adapted to omap_hwmod / omap_device
 248  *
 249  * usim
 250  */
 251
 252 /*
 253  * 'aess' class
 254  * audio engine sub system
 255  */
 256
 257 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 258         .rev_offs       = 0x0000,
 259         .sysc_offs      = 0x0010,
 260         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 261         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 262                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 263                            MSTANDBY_SMART_WKUP),
 264         .sysc_fields    = &omap_hwmod_sysc_type2,
 265 };
 266
 267 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 268         .name   = "aess",
 269         .sysc   = &omap44xx_aess_sysc,
 270         .enable_preprogram = omap_hwmod_aess_preprogram,
 271 };
 272
 273 /* aess */
 274 static struct omap_hwmod omap44xx_aess_hwmod = {
 275         .name           = "aess",
 276         .class          = &omap44xx_aess_hwmod_class,
 277         .clkdm_name     = "abe_clkdm",
 278         .main_clk       = "aess_fclk",
 279         .prcm = {
 280                 .omap4 = {
 281                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 282                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 283                         .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
 284                         .modulemode   = MODULEMODE_SWCTRL,
 285                 },
 286         },
 287 };
 288
 289 /*
 290  * 'c2c' class
 291  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 292  * soc
 293  */
 294
 295 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 296         .name   = "c2c",
 297 };
 298
 299 /* c2c */
 300 static struct omap_hwmod omap44xx_c2c_hwmod = {
 301         .name           = "c2c",
 302         .class          = &omap44xx_c2c_hwmod_class,
 303         .clkdm_name     = "d2d_clkdm",
 304         .prcm = {
 305                 .omap4 = {
 306                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
 307                         .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
 308                 },
 309         },
 310 };
 311
 312 /*
 313  * 'counter' class
 314  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 315  */
 316
 317 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 318         .rev_offs       = 0x0000,
 319         .sysc_offs      = 0x0004,
 320         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 321         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 322         .sysc_fields    = &omap_hwmod_sysc_type1,
 323 };
 324
 325 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 326         .name   = "counter",
 327         .sysc   = &omap44xx_counter_sysc,
 328 };
 329
 330 /* counter_32k */
 331 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 332         .name           = "counter_32k",
 333         .class          = &omap44xx_counter_hwmod_class,
 334         .clkdm_name     = "l4_wkup_clkdm",
 335         .flags          = HWMOD_SWSUP_SIDLE,
 336         .main_clk       = "sys_32k_ck",
 337         .prcm = {
 338                 .omap4 = {
 339                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 340                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 341                 },
 342         },
 343 };
 344
 345 /*
 346  * 'ctrl_module' class
 347  * attila core control module + core pad control module + wkup pad control
 348  * module + attila wkup control module
 349  */
 350
 351 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 352         .rev_offs       = 0x0000,
 353         .sysc_offs      = 0x0010,
 354         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 355         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 356                            SIDLE_SMART_WKUP),
 357         .sysc_fields    = &omap_hwmod_sysc_type2,
 358 };
 359
 360 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 361         .name   = "ctrl_module",
 362         .sysc   = &omap44xx_ctrl_module_sysc,
 363 };
 364
 365 /* ctrl_module_core */
 366 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 367         .name           = "ctrl_module_core",
 368         .class          = &omap44xx_ctrl_module_hwmod_class,
 369         .clkdm_name     = "l4_cfg_clkdm",
 370         .prcm = {
 371                 .omap4 = {
 372                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 373                 },
 374         },
 375 };
 376
 377 /* ctrl_module_pad_core */
 378 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 379         .name           = "ctrl_module_pad_core",
 380         .class          = &omap44xx_ctrl_module_hwmod_class,
 381         .clkdm_name     = "l4_cfg_clkdm",
 382         .prcm = {
 383                 .omap4 = {
 384                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 385                 },
 386         },
 387 };
 388
 389 /* ctrl_module_wkup */
 390 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 391         .name           = "ctrl_module_wkup",
 392         .class          = &omap44xx_ctrl_module_hwmod_class,
 393         .clkdm_name     = "l4_wkup_clkdm",
 394         .prcm = {
 395                 .omap4 = {
 396                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 397                 },
 398         },
 399 };
 400
 401 /* ctrl_module_pad_wkup */
 402 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 403         .name           = "ctrl_module_pad_wkup",
 404         .class          = &omap44xx_ctrl_module_hwmod_class,
 405         .clkdm_name     = "l4_wkup_clkdm",
 406         .prcm = {
 407                 .omap4 = {
 408                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 409                 },
 410         },
 411 };
 412
 413 /*
 414  * 'debugss' class
 415  * debug and emulation sub system
 416  */
 417
 418 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 419         .name   = "debugss",
 420 };
 421
 422 /* debugss */
 423 static struct omap_hwmod omap44xx_debugss_hwmod = {
 424         .name           = "debugss",
 425         .class          = &omap44xx_debugss_hwmod_class,
 426         .clkdm_name     = "emu_sys_clkdm",
 427         .main_clk       = "trace_clk_div_ck",
 428         .prcm = {
 429                 .omap4 = {
 430                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 431                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 432                 },
 433         },
 434 };
 435
 436 /*
 437  * 'dma' class
 438  * dma controller for data exchange between memory to memory (i.e. internal or
 439  * external memory) and gp peripherals to memory or memory to gp peripherals
 440  */
 441
 442 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 443         .rev_offs       = 0x0000,
 444         .sysc_offs      = 0x002c,
 445         .syss_offs      = 0x0028,
 446         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 447                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 448                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 449                            SYSS_HAS_RESET_STATUS),
 450         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 451                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 452         .sysc_fields    = &omap_hwmod_sysc_type1,
 453 };
 454
 455 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 456         .name   = "dma",
 457         .sysc   = &omap44xx_dma_sysc,
 458 };
 459
 460 /* dma dev_attr */
 461 static struct omap_dma_dev_attr dma_dev_attr = {
 462         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 463                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 464         .lch_count      = 32,
 465 };
 466
 467 /* dma_system */
 468 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 469         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 470         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 471         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 472         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 473         { .irq = -1 }
 474 };
 475
 476 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 477         .name           = "dma_system",
 478         .class          = &omap44xx_dma_hwmod_class,
 479         .clkdm_name     = "l3_dma_clkdm",
 480         .mpu_irqs       = omap44xx_dma_system_irqs,
 481         .xlate_irq      = omap4_xlate_irq,
 482         .main_clk       = "l3_div_ck",
 483         .prcm = {
 484                 .omap4 = {
 485                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 486                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 487                 },
 488         },
 489         .dev_attr       = &dma_dev_attr,
 490 };
 491
 492 /*
 493  * 'dmic' class
 494  * digital microphone controller
 495  */
 496
 497 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 498         .rev_offs       = 0x0000,
 499         .sysc_offs      = 0x0010,
 500         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 501                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 502         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 503                            SIDLE_SMART_WKUP),
 504         .sysc_fields    = &omap_hwmod_sysc_type2,
 505 };
 506
 507 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 508         .name   = "dmic",
 509         .sysc   = &omap44xx_dmic_sysc,
 510 };
 511
 512 /* dmic */
 513 static struct omap_hwmod omap44xx_dmic_hwmod = {
 514         .name           = "dmic",
 515         .class          = &omap44xx_dmic_hwmod_class,
 516         .clkdm_name     = "abe_clkdm",
 517         .main_clk       = "func_dmic_abe_gfclk",
 518         .prcm = {
 519                 .omap4 = {
 520                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 521                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 522                         .modulemode   = MODULEMODE_SWCTRL,
 523                 },
 524         },
 525 };
 526
 527 /*
 528  * 'dsp' class
 529  * dsp sub-system
 530  */
 531
 532 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 533         .name   = "dsp",
 534 };
 535
 536 /* dsp */
 537 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 538         { .name = "dsp", .rst_shift = 0 },
 539 };
 540
 541 static struct omap_hwmod omap44xx_dsp_hwmod = {
 542         .name           = "dsp",
 543         .class          = &omap44xx_dsp_hwmod_class,
 544         .clkdm_name     = "tesla_clkdm",
 545         .rst_lines      = omap44xx_dsp_resets,
 546         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 547         .main_clk       = "dpll_iva_m4x2_ck",
 548         .prcm = {
 549                 .omap4 = {
 550                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 551                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 552                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 553                         .modulemode   = MODULEMODE_HWCTRL,
 554                 },
 555         },
 556 };
 557
 558 /*
 559  * 'dss' class
 560  * display sub-system
 561  */
 562
 563 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 564         .rev_offs       = 0x0000,
 565         .syss_offs      = 0x0014,
 566         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 567 };
 568
 569 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 570         .name   = "dss",
 571         .sysc   = &omap44xx_dss_sysc,
 572         .reset  = omap_dss_reset,
 573 };
 574
 575 /* dss */
 576 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 577         { .role = "sys_clk", .clk = "dss_sys_clk" },
 578         { .role = "tv_clk", .clk = "dss_tv_clk" },
 579         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 580 };
 581
 582 static struct omap_hwmod omap44xx_dss_hwmod = {
 583         .name           = "dss_core",
 584         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 585         .class          = &omap44xx_dss_hwmod_class,
 586         .clkdm_name     = "l3_dss_clkdm",
 587         .main_clk       = "dss_dss_clk",
 588         .prcm = {
 589                 .omap4 = {
 590                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 591                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 592                         .modulemode   = MODULEMODE_SWCTRL,
 593                 },
 594         },
 595         .opt_clks       = dss_opt_clks,
 596         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 597 };
 598
 599 /*
 600  * 'dispc' class
 601  * display controller
 602  */
 603
 604 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 605         .rev_offs       = 0x0000,
 606         .sysc_offs      = 0x0010,
 607         .syss_offs      = 0x0014,
 608         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 609                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 610                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 611                            SYSS_HAS_RESET_STATUS),
 612         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 613                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 614         .sysc_fields    = &omap_hwmod_sysc_type1,
 615 };
 616
 617 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 618         .name   = "dispc",
 619         .sysc   = &omap44xx_dispc_sysc,
 620 };
 621
 622 /* dss_dispc */
 623 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
 624         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
 625         { .irq = -1 }
 626 };
 627
 628 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
 629         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
 630         { .dma_req = -1 }
 631 };
 632
 633 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 634         .manager_count          = 3,
 635         .has_framedonetv_irq    = 1
 636 };
 637
 638 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 639         .name           = "dss_dispc",
 640         .class          = &omap44xx_dispc_hwmod_class,
 641         .clkdm_name     = "l3_dss_clkdm",
 642         .mpu_irqs       = omap44xx_dss_dispc_irqs,
 643         .xlate_irq      = omap4_xlate_irq,
 644         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
 645         .main_clk       = "dss_dss_clk",
 646         .prcm = {
 647                 .omap4 = {
 648                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 649                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 650                 },
 651         },
 652         .dev_attr       = &omap44xx_dss_dispc_dev_attr,
 653         .parent_hwmod   = &omap44xx_dss_hwmod,
 654 };
 655
 656 /*
 657  * 'dsi' class
 658  * display serial interface controller
 659  */
 660
 661 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 662         .rev_offs       = 0x0000,
 663         .sysc_offs      = 0x0010,
 664         .syss_offs      = 0x0014,
 665         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 666                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 667                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 668         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 669         .sysc_fields    = &omap_hwmod_sysc_type1,
 670 };
 671
 672 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 673         .name   = "dsi",
 674         .sysc   = &omap44xx_dsi_sysc,
 675 };
 676
 677 /* dss_dsi1 */
 678 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
 679         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
 680         { .irq = -1 }
 681 };
 682
 683 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
 684         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
 685         { .dma_req = -1 }
 686 };
 687
 688 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 689         { .role = "sys_clk", .clk = "dss_sys_clk" },
 690 };
 691
 692 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 693         .name           = "dss_dsi1",
 694         .class          = &omap44xx_dsi_hwmod_class,
 695         .clkdm_name     = "l3_dss_clkdm",
 696         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
 697         .xlate_irq      = omap4_xlate_irq,
 698         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
 699         .main_clk       = "dss_dss_clk",
 700         .prcm = {
 701                 .omap4 = {
 702                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 703                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 704                 },
 705         },
 706         .opt_clks       = dss_dsi1_opt_clks,
 707         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 708         .parent_hwmod   = &omap44xx_dss_hwmod,
 709 };
 710
 711 /* dss_dsi2 */
 712 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
 713         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
 714         { .irq = -1 }
 715 };
 716
 717 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
 718         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
 719         { .dma_req = -1 }
 720 };
 721
 722 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 723         { .role = "sys_clk", .clk = "dss_sys_clk" },
 724 };
 725
 726 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 727         .name           = "dss_dsi2",
 728         .class          = &omap44xx_dsi_hwmod_class,
 729         .clkdm_name     = "l3_dss_clkdm",
 730         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
 731         .xlate_irq      = omap4_xlate_irq,
 732         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
 733         .main_clk       = "dss_dss_clk",
 734         .prcm = {
 735                 .omap4 = {
 736                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 737                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 738                 },
 739         },
 740         .opt_clks       = dss_dsi2_opt_clks,
 741         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 742         .parent_hwmod   = &omap44xx_dss_hwmod,
 743 };
 744
 745 /*
 746  * 'hdmi' class
 747  * hdmi controller
 748  */
 749
 750 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 751         .rev_offs       = 0x0000,
 752         .sysc_offs      = 0x0010,
 753         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 754                            SYSC_HAS_SOFTRESET),
 755         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 756                            SIDLE_SMART_WKUP),
 757         .sysc_fields    = &omap_hwmod_sysc_type2,
 758 };
 759
 760 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 761         .name   = "hdmi",
 762         .sysc   = &omap44xx_hdmi_sysc,
 763 };
 764
 765 /* dss_hdmi */
 766 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
 767         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
 768         { .irq = -1 }
 769 };
 770
 771 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
 772         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
 773         { .dma_req = -1 }
 774 };
 775
 776 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 777         { .role = "sys_clk", .clk = "dss_sys_clk" },
 778         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 779 };
 780
 781 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 782         .name           = "dss_hdmi",
 783         .class          = &omap44xx_hdmi_hwmod_class,
 784         .clkdm_name     = "l3_dss_clkdm",
 785         /*
 786          * HDMI audio requires to use no-idle mode. Hence,
 787          * set idle mode by software.
 788          */
 789         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_OPT_CLKS_NEEDED,
 790         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
 791         .xlate_irq      = omap4_xlate_irq,
 792         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
 793         .main_clk       = "dss_48mhz_clk",
 794         .prcm = {
 795                 .omap4 = {
 796                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 797                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 798                 },
 799         },
 800         .opt_clks       = dss_hdmi_opt_clks,
 801         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 802         .parent_hwmod   = &omap44xx_dss_hwmod,
 803 };
 804
 805 /*
 806  * 'rfbi' class
 807  * remote frame buffer interface
 808  */
 809
 810 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 811         .rev_offs       = 0x0000,
 812         .sysc_offs      = 0x0010,
 813         .syss_offs      = 0x0014,
 814         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 815                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 816         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 817         .sysc_fields    = &omap_hwmod_sysc_type1,
 818 };
 819
 820 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 821         .name   = "rfbi",
 822         .sysc   = &omap44xx_rfbi_sysc,
 823 };
 824
 825 /* dss_rfbi */
 826 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
 827         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
 828         { .dma_req = -1 }
 829 };
 830
 831 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 832         { .role = "ick", .clk = "l3_div_ck" },
 833 };
 834
 835 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 836         .name           = "dss_rfbi",
 837         .class          = &omap44xx_rfbi_hwmod_class,
 838         .clkdm_name     = "l3_dss_clkdm",
 839         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
 840         .main_clk       = "dss_dss_clk",
 841         .prcm = {
 842                 .omap4 = {
 843                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 844                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 845                 },
 846         },
 847         .opt_clks       = dss_rfbi_opt_clks,
 848         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 849         .parent_hwmod   = &omap44xx_dss_hwmod,
 850 };
 851
 852 /*
 853  * 'venc' class
 854  * video encoder
 855  */
 856
 857 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 858         .name   = "venc",
 859 };
 860
 861 /* dss_venc */
 862 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
 863         { .role = "tv_clk", .clk = "dss_tv_clk" },
 864 };
 865
 866 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 867         .name           = "dss_venc",
 868         .class          = &omap44xx_venc_hwmod_class,
 869         .clkdm_name     = "l3_dss_clkdm",
 870         .main_clk       = "dss_tv_clk",
 871         .flags          = HWMOD_OPT_CLKS_NEEDED,
 872         .prcm = {
 873                 .omap4 = {
 874                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 875                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 876                 },
 877         },
 878         .parent_hwmod   = &omap44xx_dss_hwmod,
 879         .opt_clks       = dss_venc_opt_clks,
 880         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
 881 };
 882
 883 /* sha0 HIB2 (the 'P' (public) device) */
 884 static struct omap_hwmod_class_sysconfig omap44xx_sha0_sysc = {
 885         .rev_offs       = 0x100,
 886         .sysc_offs      = 0x110,
 887         .syss_offs      = 0x114,
 888         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 889 };
 890
 891 static struct omap_hwmod_class omap44xx_sha0_hwmod_class = {
 892         .name           = "sham",
 893         .sysc           = &omap44xx_sha0_sysc,
 894 };
 895
 896 struct omap_hwmod omap44xx_sha0_hwmod = {
 897         .name           = "sham",
 898         .class          = &omap44xx_sha0_hwmod_class,
 899         .clkdm_name     = "l4_secure_clkdm",
 900         .main_clk       = "l3_div_ck",
 901         .prcm           = {
 902                 .omap4 = {
 903                         .clkctrl_offs = OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
 904                         .context_offs = OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
 905                         .modulemode   = MODULEMODE_SWCTRL,
 906                 },
 907         },
 908 };
 909
 910 /*
 911  * 'elm' class
 912  * bch error location module
 913  */
 914
 915 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 916         .rev_offs       = 0x0000,
 917         .sysc_offs      = 0x0010,
 918         .syss_offs      = 0x0014,
 919         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 920                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 921                            SYSS_HAS_RESET_STATUS),
 922         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 923         .sysc_fields    = &omap_hwmod_sysc_type1,
 924 };
 925
 926 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 927         .name   = "elm",
 928         .sysc   = &omap44xx_elm_sysc,
 929 };
 930
 931 /* elm */
 932 static struct omap_hwmod omap44xx_elm_hwmod = {
 933         .name           = "elm",
 934         .class          = &omap44xx_elm_hwmod_class,
 935         .clkdm_name     = "l4_per_clkdm",
 936         .prcm = {
 937                 .omap4 = {
 938                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
 939                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
 940                 },
 941         },
 942 };
 943
 944 /*
 945  * 'emif' class
 946  * external memory interface no1
 947  */
 948
 949 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
 950         .rev_offs       = 0x0000,
 951 };
 952
 953 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
 954         .name   = "emif",
 955         .sysc   = &omap44xx_emif_sysc,
 956 };
 957
 958 /* emif1 */
 959 static struct omap_hwmod omap44xx_emif1_hwmod = {
 960         .name           = "emif1",
 961         .class          = &omap44xx_emif_hwmod_class,
 962         .clkdm_name     = "l3_emif_clkdm",
 963         .flags          = HWMOD_INIT_NO_IDLE,
 964         .main_clk       = "ddrphy_ck",
 965         .prcm = {
 966                 .omap4 = {
 967                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
 968                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
 969                         .modulemode   = MODULEMODE_HWCTRL,
 970                 },
 971         },
 972 };
 973
 974 /* emif2 */
 975 static struct omap_hwmod omap44xx_emif2_hwmod = {
 976         .name           = "emif2",
 977         .class          = &omap44xx_emif_hwmod_class,
 978         .clkdm_name     = "l3_emif_clkdm",
 979         .flags          = HWMOD_INIT_NO_IDLE,
 980         .main_clk       = "ddrphy_ck",
 981         .prcm = {
 982                 .omap4 = {
 983                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
 984                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
 985                         .modulemode   = MODULEMODE_HWCTRL,
 986                 },
 987         },
 988 };
 989
 990 /*
 991     Crypto modules AES0/1 belong to:
 992         PD_L4_PER power domain
 993         CD_L4_SEC clock domain
 994         On the L3, the AES modules are mapped to
 995         L3_CLK2: Peripherals and multimedia sub clock domain
 996 */
 997 static struct omap_hwmod_class_sysconfig omap44xx_aes_sysc = {
 998         .rev_offs       = 0x80,
 999         .sysc_offs      = 0x84,
1000         .syss_offs      = 0x88,
1001         .sysc_flags     = SYSS_HAS_RESET_STATUS,
1002 };
1003
1004 static struct omap_hwmod_class omap44xx_aes_hwmod_class = {
1005         .name           = "aes",
1006         .sysc           = &omap44xx_aes_sysc,
1007 };
1008
1009 static struct omap_hwmod omap44xx_aes1_hwmod = {
1010         .name           = "aes1",
1011         .class          = &omap44xx_aes_hwmod_class,
1012         .clkdm_name     = "l4_secure_clkdm",
1013         .main_clk       = "l3_div_ck",
1014         .prcm           = {
1015                 .omap4  = {
1016                         .context_offs   = OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET,
1017                         .clkctrl_offs   = OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET,
1018                         .modulemode     = MODULEMODE_SWCTRL,
1019                 },
1020         },
1021 };
1022
1023 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes1 = {
1024         .master         = &omap44xx_l4_per_hwmod,
1025         .slave          = &omap44xx_aes1_hwmod,
1026         .clk            = "l3_div_ck",
1027         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1028 };
1029
1030 static struct omap_hwmod omap44xx_aes2_hwmod = {
1031         .name           = "aes2",
1032         .class          = &omap44xx_aes_hwmod_class,
1033         .clkdm_name     = "l4_secure_clkdm",
1034         .main_clk       = "l3_div_ck",
1035         .prcm           = {
1036                 .omap4  = {
1037                         .context_offs   = OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET,
1038                         .clkctrl_offs   = OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET,
1039                         .modulemode     = MODULEMODE_SWCTRL,
1040                 },
1041         },
1042 };
1043
1044 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes2 = {
1045         .master         = &omap44xx_l4_per_hwmod,
1046         .slave          = &omap44xx_aes2_hwmod,
1047         .clk            = "l3_div_ck",
1048         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1049 };
1050
1051 /*
1052  * 'des' class for DES3DES module
1053  */
1054 static struct omap_hwmod_class_sysconfig omap44xx_des_sysc = {
1055         .rev_offs       = 0x30,
1056         .sysc_offs      = 0x34,
1057         .syss_offs      = 0x38,
1058         .sysc_flags     = SYSS_HAS_RESET_STATUS,
1059 };
1060
1061 static struct omap_hwmod_class omap44xx_des_hwmod_class = {
1062         .name           = "des",
1063         .sysc           = &omap44xx_des_sysc,
1064 };
1065
1066 static struct omap_hwmod omap44xx_des_hwmod = {
1067         .name           = "des",
1068         .class          = &omap44xx_des_hwmod_class,
1069         .clkdm_name     = "l4_secure_clkdm",
1070         .main_clk       = "l3_div_ck",
1071         .prcm           = {
1072                 .omap4  = {
1073                         .context_offs   = OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
1074                         .clkctrl_offs   = OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
1075                         .modulemode     = MODULEMODE_SWCTRL,
1076                 },
1077         },
1078 };
1079
1080 struct omap_hwmod_ocp_if omap44xx_l3_main_2__des = {
1081         .master         = &omap44xx_l3_main_2_hwmod,
1082         .slave          = &omap44xx_des_hwmod,
1083         .clk            = "l3_div_ck",
1084         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1085 };
1086
1087 /*
1088  * 'fdif' class
1089  * face detection hw accelerator module
1090  */
1091
1092 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1093         .rev_offs       = 0x0000,
1094         .sysc_offs      = 0x0010,
1095         /*
1096          * FDIF needs 100 OCP clk cycles delay after a softreset before
1097          * accessing sysconfig again.
1098          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1099          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1100          *
1101          * TODO: Indicate errata when available.
1102          */
1103         .srst_udelay    = 2,
1104         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1105                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1106         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1107                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1108         .sysc_fields    = &omap_hwmod_sysc_type2,
1109 };
1110
1111 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1112         .name   = "fdif",
1113         .sysc   = &omap44xx_fdif_sysc,
1114 };
1115
1116 /* fdif */
1117 static struct omap_hwmod omap44xx_fdif_hwmod = {
1118         .name           = "fdif",
1119         .class          = &omap44xx_fdif_hwmod_class,
1120         .clkdm_name     = "iss_clkdm",
1121         .main_clk       = "fdif_fck",
1122         .prcm = {
1123                 .omap4 = {
1124                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1125                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1126                         .modulemode   = MODULEMODE_SWCTRL,
1127                 },
1128         },
1129 };
1130
1131 /*
1132  * 'gpio' class
1133  * general purpose io module
1134  */
1135
1136 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1137         .rev_offs       = 0x0000,
1138         .sysc_offs      = 0x0010,
1139         .syss_offs      = 0x0114,
1140         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1141                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1142                            SYSS_HAS_RESET_STATUS),
1143         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1144                            SIDLE_SMART_WKUP),
1145         .sysc_fields    = &omap_hwmod_sysc_type1,
1146 };
1147
1148 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1149         .name   = "gpio",
1150         .sysc   = &omap44xx_gpio_sysc,
1151         .rev    = 2,
1152 };
1153
1154 /* gpio dev_attr */
1155 static struct omap_gpio_dev_attr gpio_dev_attr = {
1156         .bank_width     = 32,
1157         .dbck_flag      = true,
1158 };
1159
1160 /* gpio1 */
1161 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1162         { .role = "dbclk", .clk = "gpio1_dbclk" },
1163 };
1164
1165 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1166         .name           = "gpio1",
1167         .class          = &omap44xx_gpio_hwmod_class,
1168         .clkdm_name     = "l4_wkup_clkdm",
1169         .main_clk       = "l4_wkup_clk_mux_ck",
1170         .prcm = {
1171                 .omap4 = {
1172                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1173                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1174                         .modulemode   = MODULEMODE_HWCTRL,
1175                 },
1176         },
1177         .opt_clks       = gpio1_opt_clks,
1178         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1179         .dev_attr       = &gpio_dev_attr,
1180 };
1181
1182 /* gpio2 */
1183 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1184         { .role = "dbclk", .clk = "gpio2_dbclk" },
1185 };
1186
1187 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1188         .name           = "gpio2",
1189         .class          = &omap44xx_gpio_hwmod_class,
1190         .clkdm_name     = "l4_per_clkdm",
1191         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1192         .main_clk       = "l4_div_ck",
1193         .prcm = {
1194                 .omap4 = {
1195                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1196                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1197                         .modulemode   = MODULEMODE_HWCTRL,
1198                 },
1199         },
1200         .opt_clks       = gpio2_opt_clks,
1201         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1202         .dev_attr       = &gpio_dev_attr,
1203 };
1204
1205 /* gpio3 */
1206 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1207         { .role = "dbclk", .clk = "gpio3_dbclk" },
1208 };
1209
1210 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1211         .name           = "gpio3",
1212         .class          = &omap44xx_gpio_hwmod_class,
1213         .clkdm_name     = "l4_per_clkdm",
1214         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1215         .main_clk       = "l4_div_ck",
1216         .prcm = {
1217                 .omap4 = {
1218                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1219                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1220                         .modulemode   = MODULEMODE_HWCTRL,
1221                 },
1222         },
1223         .opt_clks       = gpio3_opt_clks,
1224         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1225         .dev_attr       = &gpio_dev_attr,
1226 };
1227
1228 /* gpio4 */
1229 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1230         { .role = "dbclk", .clk = "gpio4_dbclk" },
1231 };
1232
1233 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1234         .name           = "gpio4",
1235         .class          = &omap44xx_gpio_hwmod_class,
1236         .clkdm_name     = "l4_per_clkdm",
1237         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1238         .main_clk       = "l4_div_ck",
1239         .prcm = {
1240                 .omap4 = {
1241                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1242                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1243                         .modulemode   = MODULEMODE_HWCTRL,
1244                 },
1245         },
1246         .opt_clks       = gpio4_opt_clks,
1247         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1248         .dev_attr       = &gpio_dev_attr,
1249 };
1250
1251 /* gpio5 */
1252 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1253         { .role = "dbclk", .clk = "gpio5_dbclk" },
1254 };
1255
1256 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1257         .name           = "gpio5",
1258         .class          = &omap44xx_gpio_hwmod_class,
1259         .clkdm_name     = "l4_per_clkdm",
1260         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1261         .main_clk       = "l4_div_ck",
1262         .prcm = {
1263                 .omap4 = {
1264                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1265                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1266                         .modulemode   = MODULEMODE_HWCTRL,
1267                 },
1268         },
1269         .opt_clks       = gpio5_opt_clks,
1270         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1271         .dev_attr       = &gpio_dev_attr,
1272 };
1273
1274 /* gpio6 */
1275 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1276         { .role = "dbclk", .clk = "gpio6_dbclk" },
1277 };
1278
1279 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1280         .name           = "gpio6",
1281         .class          = &omap44xx_gpio_hwmod_class,
1282         .clkdm_name     = "l4_per_clkdm",
1283         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1284         .main_clk       = "l4_div_ck",
1285         .prcm = {
1286                 .omap4 = {
1287                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1288                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1289                         .modulemode   = MODULEMODE_HWCTRL,
1290                 },
1291         },
1292         .opt_clks       = gpio6_opt_clks,
1293         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1294         .dev_attr       = &gpio_dev_attr,
1295 };
1296
1297 /*
1298  * 'gpmc' class
1299  * general purpose memory controller
1300  */
1301
1302 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1303         .rev_offs       = 0x0000,
1304         .sysc_offs      = 0x0010,
1305         .syss_offs      = 0x0014,
1306         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1307                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1308         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1309         .sysc_fields    = &omap_hwmod_sysc_type1,
1310 };
1311
1312 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1313         .name   = "gpmc",
1314         .sysc   = &omap44xx_gpmc_sysc,
1315 };
1316
1317 /* gpmc */
1318 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1319         .name           = "gpmc",
1320         .class          = &omap44xx_gpmc_hwmod_class,
1321         .clkdm_name     = "l3_2_clkdm",
1322         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
1323         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
1324         .prcm = {
1325                 .omap4 = {
1326                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1327                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1328                         .modulemode   = MODULEMODE_HWCTRL,
1329                 },
1330         },
1331 };
1332
1333 /*
1334  * 'gpu' class
1335  * 2d/3d graphics accelerator
1336  */
1337
1338 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1339         .rev_offs       = 0x1fc00,
1340         .sysc_offs      = 0x1fc10,
1341         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1342         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1343                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1344                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1345         .sysc_fields    = &omap_hwmod_sysc_type2,
1346 };
1347
1348 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1349         .name   = "gpu",
1350         .sysc   = &omap44xx_gpu_sysc,
1351 };
1352
1353 /* gpu */
1354 static struct omap_hwmod omap44xx_gpu_hwmod = {
1355         .name           = "gpu",
1356         .class          = &omap44xx_gpu_hwmod_class,
1357         .clkdm_name     = "l3_gfx_clkdm",
1358         .main_clk       = "sgx_clk_mux",
1359         .prcm = {
1360                 .omap4 = {
1361                         .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1362                         .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1363                         .modulemode   = MODULEMODE_SWCTRL,
1364                 },
1365         },
1366 };
1367
1368 /*
1369  * 'hdq1w' class
1370  * hdq / 1-wire serial interface controller
1371  */
1372
1373 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1374         .rev_offs       = 0x0000,
1375         .sysc_offs      = 0x0014,
1376         .syss_offs      = 0x0018,
1377         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1378                            SYSS_HAS_RESET_STATUS),
1379         .sysc_fields    = &omap_hwmod_sysc_type1,
1380 };
1381
1382 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1383         .name   = "hdq1w",
1384         .sysc   = &omap44xx_hdq1w_sysc,
1385 };
1386
1387 /* hdq1w */
1388 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1389         .name           = "hdq1w",
1390         .class          = &omap44xx_hdq1w_hwmod_class,
1391         .clkdm_name     = "l4_per_clkdm",
1392         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1393         .main_clk       = "func_12m_fclk",
1394         .prcm = {
1395                 .omap4 = {
1396                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1397                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1398                         .modulemode   = MODULEMODE_SWCTRL,
1399                 },
1400         },
1401 };
1402
1403 /*
1404  * 'hsi' class
1405  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1406  * serial if)
1407  */
1408
1409 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1410         .rev_offs       = 0x0000,
1411         .sysc_offs      = 0x0010,
1412         .syss_offs      = 0x0014,
1413         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1414                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1415                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1416         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1417                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1418                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1419         .sysc_fields    = &omap_hwmod_sysc_type1,
1420 };
1421
1422 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1423         .name   = "hsi",
1424         .sysc   = &omap44xx_hsi_sysc,
1425 };
1426
1427 /* hsi */
1428 static struct omap_hwmod omap44xx_hsi_hwmod = {
1429         .name           = "hsi",
1430         .class          = &omap44xx_hsi_hwmod_class,
1431         .clkdm_name     = "l3_init_clkdm",
1432         .main_clk       = "hsi_fck",
1433         .prcm = {
1434                 .omap4 = {
1435                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1436                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1437                         .modulemode   = MODULEMODE_HWCTRL,
1438                 },
1439         },
1440 };
1441
1442 /*
1443  * 'i2c' class
1444  * multimaster high-speed i2c controller
1445  */
1446
1447 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1448         .sysc_offs      = 0x0010,
1449         .syss_offs      = 0x0090,
1450         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1451                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1452                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1453         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1454                            SIDLE_SMART_WKUP),
1455         .sysc_fields    = &omap_hwmod_sysc_type1,
1456 };
1457
1458 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1459         .name   = "i2c",
1460         .sysc   = &omap44xx_i2c_sysc,
1461         .rev    = OMAP_I2C_IP_VERSION_2,
1462         .reset  = &omap_i2c_reset,
1463 };
1464
1465 static struct omap_i2c_dev_attr i2c_dev_attr = {
1466         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1467 };
1468
1469 /* i2c1 */
1470 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1471         .name           = "i2c1",
1472         .class          = &omap44xx_i2c_hwmod_class,
1473         .clkdm_name     = "l4_per_clkdm",
1474         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1475         .main_clk       = "func_96m_fclk",
1476         .prcm = {
1477                 .omap4 = {
1478                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1479                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1480                         .modulemode   = MODULEMODE_SWCTRL,
1481                 },
1482         },
1483         .dev_attr       = &i2c_dev_attr,
1484 };
1485
1486 /* i2c2 */
1487 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1488         .name           = "i2c2",
1489         .class          = &omap44xx_i2c_hwmod_class,
1490         .clkdm_name     = "l4_per_clkdm",
1491         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1492         .main_clk       = "func_96m_fclk",
1493         .prcm = {
1494                 .omap4 = {
1495                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1496                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1497                         .modulemode   = MODULEMODE_SWCTRL,
1498                 },
1499         },
1500         .dev_attr       = &i2c_dev_attr,
1501 };
1502
1503 /* i2c3 */
1504 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1505         .name           = "i2c3",
1506         .class          = &omap44xx_i2c_hwmod_class,
1507         .clkdm_name     = "l4_per_clkdm",
1508         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1509         .main_clk       = "func_96m_fclk",
1510         .prcm = {
1511                 .omap4 = {
1512                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1513                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1514                         .modulemode   = MODULEMODE_SWCTRL,
1515                 },
1516         },
1517         .dev_attr       = &i2c_dev_attr,
1518 };
1519
1520 /* i2c4 */
1521 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1522         .name           = "i2c4",
1523         .class          = &omap44xx_i2c_hwmod_class,
1524         .clkdm_name     = "l4_per_clkdm",
1525         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1526         .main_clk       = "func_96m_fclk",
1527         .prcm = {
1528                 .omap4 = {
1529                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1530                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1531                         .modulemode   = MODULEMODE_SWCTRL,
1532                 },
1533         },
1534         .dev_attr       = &i2c_dev_attr,
1535 };
1536
1537 /*
1538  * 'ipu' class
1539  * imaging processor unit
1540  */
1541
1542 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1543         .name   = "ipu",
1544 };
1545
1546 /* ipu */
1547 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1548         { .name = "cpu0", .rst_shift = 0 },
1549         { .name = "cpu1", .rst_shift = 1 },
1550 };
1551
1552 static struct omap_hwmod omap44xx_ipu_hwmod = {
1553         .name           = "ipu",
1554         .class          = &omap44xx_ipu_hwmod_class,
1555         .clkdm_name     = "ducati_clkdm",
1556         .rst_lines      = omap44xx_ipu_resets,
1557         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1558         .main_clk       = "ducati_clk_mux_ck",
1559         .prcm = {
1560                 .omap4 = {
1561                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1562                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1563                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1564                         .modulemode   = MODULEMODE_HWCTRL,
1565                 },
1566         },
1567 };
1568
1569 /*
1570  * 'iss' class
1571  * external images sensor pixel data processor
1572  */
1573
1574 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1575         .rev_offs       = 0x0000,
1576         .sysc_offs      = 0x0010,
1577         /*
1578          * ISS needs 100 OCP clk cycles delay after a softreset before
1579          * accessing sysconfig again.
1580          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1581          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1582          *
1583          * TODO: Indicate errata when available.
1584          */
1585         .srst_udelay    = 2,
1586         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1587                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1588         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1589                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1590                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1591         .sysc_fields    = &omap_hwmod_sysc_type2,
1592 };
1593
1594 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1595         .name   = "iss",
1596         .sysc   = &omap44xx_iss_sysc,
1597 };
1598
1599 /* iss */
1600 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1601         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1602 };
1603
1604 static struct omap_hwmod omap44xx_iss_hwmod = {
1605         .name           = "iss",
1606         .class          = &omap44xx_iss_hwmod_class,
1607         .clkdm_name     = "iss_clkdm",
1608         .main_clk       = "ducati_clk_mux_ck",
1609         .prcm = {
1610                 .omap4 = {
1611                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1612                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1613                         .modulemode   = MODULEMODE_SWCTRL,
1614                 },
1615         },
1616         .opt_clks       = iss_opt_clks,
1617         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1618 };
1619
1620 /*
1621  * 'iva' class
1622  * multi-standard video encoder/decoder hardware accelerator
1623  */
1624
1625 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1626         .name   = "iva",
1627 };
1628
1629 /* iva */
1630 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1631         { .name = "seq0", .rst_shift = 0 },
1632         { .name = "seq1", .rst_shift = 1 },
1633         { .name = "logic", .rst_shift = 2 },
1634 };
1635
1636 static struct omap_hwmod omap44xx_iva_hwmod = {
1637         .name           = "iva",
1638         .class          = &omap44xx_iva_hwmod_class,
1639         .clkdm_name     = "ivahd_clkdm",
1640         .rst_lines      = omap44xx_iva_resets,
1641         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1642         .main_clk       = "dpll_iva_m5x2_ck",
1643         .prcm = {
1644                 .omap4 = {
1645                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1646                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1647                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1648                         .modulemode   = MODULEMODE_HWCTRL,
1649                 },
1650         },
1651 };
1652
1653 /*
1654  * 'kbd' class
1655  * keyboard controller
1656  */
1657
1658 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1659         .rev_offs       = 0x0000,
1660         .sysc_offs      = 0x0010,
1661         .syss_offs      = 0x0014,
1662         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1663                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1664                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1665                            SYSS_HAS_RESET_STATUS),
1666         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1667         .sysc_fields    = &omap_hwmod_sysc_type1,
1668 };
1669
1670 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1671         .name   = "kbd",
1672         .sysc   = &omap44xx_kbd_sysc,
1673 };
1674
1675 /* kbd */
1676 static struct omap_hwmod omap44xx_kbd_hwmod = {
1677         .name           = "kbd",
1678         .class          = &omap44xx_kbd_hwmod_class,
1679         .clkdm_name     = "l4_wkup_clkdm",
1680         .main_clk       = "sys_32k_ck",
1681         .prcm = {
1682                 .omap4 = {
1683                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1684                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1685                         .modulemode   = MODULEMODE_SWCTRL,
1686                 },
1687         },
1688 };
1689
1690 /*
1691  * 'mailbox' class
1692  * mailbox module allowing communication between the on-chip processors using a
1693  * queued mailbox-interrupt mechanism.
1694  */
1695
1696 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1697         .rev_offs       = 0x0000,
1698         .sysc_offs      = 0x0010,
1699         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1700                            SYSC_HAS_SOFTRESET),
1701         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1702         .sysc_fields    = &omap_hwmod_sysc_type2,
1703 };
1704
1705 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1706         .name   = "mailbox",
1707         .sysc   = &omap44xx_mailbox_sysc,
1708 };
1709
1710 /* mailbox */
1711 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1712         .name           = "mailbox",
1713         .class          = &omap44xx_mailbox_hwmod_class,
1714         .clkdm_name     = "l4_cfg_clkdm",
1715         .prcm = {
1716                 .omap4 = {
1717                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1718                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1719                 },
1720         },
1721 };
1722
1723 /*
1724  * 'mcasp' class
1725  * multi-channel audio serial port controller
1726  */
1727
1728 /* The IP is not compliant to type1 / type2 scheme */
1729 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1730         .sidle_shift    = 0,
1731 };
1732
1733 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1734         .sysc_offs      = 0x0004,
1735         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1736         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1737                            SIDLE_SMART_WKUP),
1738         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1739 };
1740
1741 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1742         .name   = "mcasp",
1743         .sysc   = &omap44xx_mcasp_sysc,
1744 };
1745
1746 /* mcasp */
1747 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1748         .name           = "mcasp",
1749         .class          = &omap44xx_mcasp_hwmod_class,
1750         .clkdm_name     = "abe_clkdm",
1751         .main_clk       = "func_mcasp_abe_gfclk",
1752         .prcm = {
1753                 .omap4 = {
1754                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1755                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1756                         .modulemode   = MODULEMODE_SWCTRL,
1757                 },
1758         },
1759 };
1760
1761 /*
1762  * 'mcbsp' class
1763  * multi channel buffered serial port controller
1764  */
1765
1766 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1767         .sysc_offs      = 0x008c,
1768         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1769                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1770         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1771         .sysc_fields    = &omap_hwmod_sysc_type1,
1772 };
1773
1774 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1775         .name   = "mcbsp",
1776         .sysc   = &omap44xx_mcbsp_sysc,
1777         .rev    = MCBSP_CONFIG_TYPE4,
1778 };
1779
1780 /* mcbsp1 */
1781 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1782         { .role = "pad_fck", .clk = "pad_clks_ck" },
1783         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1784 };
1785
1786 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1787         .name           = "mcbsp1",
1788         .class          = &omap44xx_mcbsp_hwmod_class,
1789         .clkdm_name     = "abe_clkdm",
1790         .main_clk       = "func_mcbsp1_gfclk",
1791         .prcm = {
1792                 .omap4 = {
1793                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1794                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1795                         .modulemode   = MODULEMODE_SWCTRL,
1796                 },
1797         },
1798         .opt_clks       = mcbsp1_opt_clks,
1799         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1800 };
1801
1802 /* mcbsp2 */
1803 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1804         { .role = "pad_fck", .clk = "pad_clks_ck" },
1805         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1806 };
1807
1808 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
1809         .name           = "mcbsp2",
1810         .class          = &omap44xx_mcbsp_hwmod_class,
1811         .clkdm_name     = "abe_clkdm",
1812         .main_clk       = "func_mcbsp2_gfclk",
1813         .prcm = {
1814                 .omap4 = {
1815                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
1816                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1817                         .modulemode   = MODULEMODE_SWCTRL,
1818                 },
1819         },
1820         .opt_clks       = mcbsp2_opt_clks,
1821         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
1822 };
1823
1824 /* mcbsp3 */
1825 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
1826         { .role = "pad_fck", .clk = "pad_clks_ck" },
1827         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
1828 };
1829
1830 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
1831         .name           = "mcbsp3",
1832         .class          = &omap44xx_mcbsp_hwmod_class,
1833         .clkdm_name     = "abe_clkdm",
1834         .main_clk       = "func_mcbsp3_gfclk",
1835         .prcm = {
1836                 .omap4 = {
1837                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
1838                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
1839                         .modulemode   = MODULEMODE_SWCTRL,
1840                 },
1841         },
1842         .opt_clks       = mcbsp3_opt_clks,
1843         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
1844 };
1845
1846 /* mcbsp4 */
1847 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
1848         { .role = "pad_fck", .clk = "pad_clks_ck" },
1849         { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
1850 };
1851
1852 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
1853         .name           = "mcbsp4",
1854         .class          = &omap44xx_mcbsp_hwmod_class,
1855         .clkdm_name     = "l4_per_clkdm",
1856         .main_clk       = "per_mcbsp4_gfclk",
1857         .prcm = {
1858                 .omap4 = {
1859                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
1860                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
1861                         .modulemode   = MODULEMODE_SWCTRL,
1862                 },
1863         },
1864         .opt_clks       = mcbsp4_opt_clks,
1865         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
1866 };
1867
1868 /*
1869  * 'mcpdm' class
1870  * multi channel pdm controller (proprietary interface with phoenix power
1871  * ic)
1872  */
1873
1874 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
1875         .rev_offs       = 0x0000,
1876         .sysc_offs      = 0x0010,
1877         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1878                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1879         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1880                            SIDLE_SMART_WKUP),
1881         .sysc_fields    = &omap_hwmod_sysc_type2,
1882 };
1883
1884 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
1885         .name   = "mcpdm",
1886         .sysc   = &omap44xx_mcpdm_sysc,
1887 };
1888
1889 /* mcpdm */
1890 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
1891         .name           = "mcpdm",
1892         .class          = &omap44xx_mcpdm_hwmod_class,
1893         .clkdm_name     = "abe_clkdm",
1894         /*
1895          * It's suspected that the McPDM requires an off-chip main
1896          * functional clock, controlled via I2C.  This IP block is
1897          * currently reset very early during boot, before I2C is
1898          * available, so it doesn't seem that we have any choice in
1899          * the kernel other than to avoid resetting it.
1900          *
1901          * Also, McPDM needs to be configured to NO_IDLE mode when it
1902          * is in used otherwise vital clocks will be gated which
1903          * results 'slow motion' audio playback.
1904          */
1905         .flags          = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
1906         .main_clk       = "pad_clks_ck",
1907         .prcm = {
1908                 .omap4 = {
1909                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
1910                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
1911                         .modulemode   = MODULEMODE_SWCTRL,
1912                 },
1913         },
1914 };
1915
1916 /*
1917  * 'mcspi' class
1918  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1919  * bus
1920  */
1921
1922 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
1923         .rev_offs       = 0x0000,
1924         .sysc_offs      = 0x0010,
1925         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1926                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1927         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1928                            SIDLE_SMART_WKUP),
1929         .sysc_fields    = &omap_hwmod_sysc_type2,
1930 };
1931
1932 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
1933         .name   = "mcspi",
1934         .sysc   = &omap44xx_mcspi_sysc,
1935         .rev    = OMAP4_MCSPI_REV,
1936 };
1937
1938 /* mcspi1 */
1939 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
1940         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
1941         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
1942         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
1943         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
1944         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
1945         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
1946         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
1947         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
1948         { .dma_req = -1 }
1949 };
1950
1951 /* mcspi1 dev_attr */
1952 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1953         .num_chipselect = 4,
1954 };
1955
1956 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
1957         .name           = "mcspi1",
1958         .class          = &omap44xx_mcspi_hwmod_class,
1959         .clkdm_name     = "l4_per_clkdm",
1960         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
1961         .main_clk       = "func_48m_fclk",
1962         .prcm = {
1963                 .omap4 = {
1964                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1965                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1966                         .modulemode   = MODULEMODE_SWCTRL,
1967                 },
1968         },
1969         .dev_attr       = &mcspi1_dev_attr,
1970 };
1971
1972 /* mcspi2 */
1973 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
1974         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
1975         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
1976         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
1977         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
1978         { .dma_req = -1 }
1979 };
1980
1981 /* mcspi2 dev_attr */
1982 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1983         .num_chipselect = 2,
1984 };
1985
1986 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
1987         .name           = "mcspi2",
1988         .class          = &omap44xx_mcspi_hwmod_class,
1989         .clkdm_name     = "l4_per_clkdm",
1990         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
1991         .main_clk       = "func_48m_fclk",
1992         .prcm = {
1993                 .omap4 = {
1994                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1995                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1996                         .modulemode   = MODULEMODE_SWCTRL,
1997                 },
1998         },
1999         .dev_attr       = &mcspi2_dev_attr,
2000 };
2001
2002 /* mcspi3 */
2003 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2004         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2005         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2006         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2007         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2008         { .dma_req = -1 }
2009 };
2010
2011 /* mcspi3 dev_attr */
2012 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2013         .num_chipselect = 2,
2014 };
2015
2016 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2017         .name           = "mcspi3",
2018         .class          = &omap44xx_mcspi_hwmod_class,
2019         .clkdm_name     = "l4_per_clkdm",
2020         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
2021         .main_clk       = "func_48m_fclk",
2022         .prcm = {
2023                 .omap4 = {
2024                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2025                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2026                         .modulemode   = MODULEMODE_SWCTRL,
2027                 },
2028         },
2029         .dev_attr       = &mcspi3_dev_attr,
2030 };
2031
2032 /* mcspi4 */
2033 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2034         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2035         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2036         { .dma_req = -1 }
2037 };
2038
2039 /* mcspi4 dev_attr */
2040 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2041         .num_chipselect = 1,
2042 };
2043
2044 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2045         .name           = "mcspi4",
2046         .class          = &omap44xx_mcspi_hwmod_class,
2047         .clkdm_name     = "l4_per_clkdm",
2048         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
2049         .main_clk       = "func_48m_fclk",
2050         .prcm = {
2051                 .omap4 = {
2052                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2053                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2054                         .modulemode   = MODULEMODE_SWCTRL,
2055                 },
2056         },
2057         .dev_attr       = &mcspi4_dev_attr,
2058 };
2059
2060 /*
2061  * 'mmc' class
2062  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2063  */
2064
2065 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2066         .rev_offs       = 0x0000,
2067         .sysc_offs      = 0x0010,
2068         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2069                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2070                            SYSC_HAS_SOFTRESET),
2071         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2072                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2073                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2074         .sysc_fields    = &omap_hwmod_sysc_type2,
2075 };
2076
2077 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2078         .name   = "mmc",
2079         .sysc   = &omap44xx_mmc_sysc,
2080 };
2081
2082 /* mmc1 */
2083 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2084         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2085         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2086         { .dma_req = -1 }
2087 };
2088
2089 /* mmc1 dev_attr */
2090 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
2091         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2092 };
2093
2094 static struct omap_hwmod omap44xx_mmc1_hwmod = {
2095         .name           = "mmc1",
2096         .class          = &omap44xx_mmc_hwmod_class,
2097         .clkdm_name     = "l3_init_clkdm",
2098         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
2099         .main_clk       = "hsmmc1_fclk",
2100         .prcm = {
2101                 .omap4 = {
2102                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2103                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2104                         .modulemode   = MODULEMODE_SWCTRL,
2105                 },
2106         },
2107         .dev_attr       = &mmc1_dev_attr,
2108 };
2109
2110 /* mmc2 */
2111 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2112         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2113         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2114         { .dma_req = -1 }
2115 };
2116
2117 static struct omap_hwmod omap44xx_mmc2_hwmod = {
2118         .name           = "mmc2",
2119         .class          = &omap44xx_mmc_hwmod_class,
2120         .clkdm_name     = "l3_init_clkdm",
2121         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
2122         .main_clk       = "hsmmc2_fclk",
2123         .prcm = {
2124                 .omap4 = {
2125                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2126                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2127                         .modulemode   = MODULEMODE_SWCTRL,
2128                 },
2129         },
2130 };
2131
2132 /* mmc3 */
2133 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2134         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2135         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2136         { .dma_req = -1 }
2137 };
2138
2139 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2140         .name           = "mmc3",
2141         .class          = &omap44xx_mmc_hwmod_class,
2142         .clkdm_name     = "l4_per_clkdm",
2143         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
2144         .main_clk       = "func_48m_fclk",
2145         .prcm = {
2146                 .omap4 = {
2147                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2148                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2149                         .modulemode   = MODULEMODE_SWCTRL,
2150                 },
2151         },
2152 };
2153
2154 /* mmc4 */
2155 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2156         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2157         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2158         { .dma_req = -1 }
2159 };
2160
2161 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2162         .name           = "mmc4",
2163         .class          = &omap44xx_mmc_hwmod_class,
2164         .clkdm_name     = "l4_per_clkdm",
2165         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
2166         .main_clk       = "func_48m_fclk",
2167         .prcm = {
2168                 .omap4 = {
2169                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2170                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2171                         .modulemode   = MODULEMODE_SWCTRL,
2172                 },
2173         },
2174 };
2175
2176 /* mmc5 */
2177 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2178         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2179         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2180         { .dma_req = -1 }
2181 };
2182
2183 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2184         .name           = "mmc5",
2185         .class          = &omap44xx_mmc_hwmod_class,
2186         .clkdm_name     = "l4_per_clkdm",
2187         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
2188         .main_clk       = "func_48m_fclk",
2189         .prcm = {
2190                 .omap4 = {
2191                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2192                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2193                         .modulemode   = MODULEMODE_SWCTRL,
2194                 },
2195         },
2196 };
2197
2198 /*
2199  * 'mmu' class
2200  * The memory management unit performs virtual to physical address translation
2201  * for its requestors.
2202  */
2203
2204 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2205         .rev_offs       = 0x000,
2206         .sysc_offs      = 0x010,
2207         .syss_offs      = 0x014,
2208         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2209                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2210         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2211         .sysc_fields    = &omap_hwmod_sysc_type1,
2212 };
2213
2214 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2215         .name = "mmu",
2216         .sysc = &mmu_sysc,
2217 };
2218
2219 /* mmu ipu */
2220
2221 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2222 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2223         { .name = "mmu_cache", .rst_shift = 2 },
2224 };
2225
2226 /* l3_main_2 -> mmu_ipu */
2227 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2228         .master         = &omap44xx_l3_main_2_hwmod,
2229         .slave          = &omap44xx_mmu_ipu_hwmod,
2230         .clk            = "l3_div_ck",
2231         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2232 };
2233
2234 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2235         .name           = "mmu_ipu",
2236         .class          = &omap44xx_mmu_hwmod_class,
2237         .clkdm_name     = "ducati_clkdm",
2238         .rst_lines      = omap44xx_mmu_ipu_resets,
2239         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2240         .main_clk       = "ducati_clk_mux_ck",
2241         .prcm = {
2242                 .omap4 = {
2243                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2244                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2245                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2246                         .modulemode   = MODULEMODE_HWCTRL,
2247                 },
2248         },
2249 };
2250
2251 /* mmu dsp */
2252
2253 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2254 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2255         { .name = "mmu_cache", .rst_shift = 1 },
2256 };
2257
2258 /* l4_cfg -> dsp */
2259 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2260         .master         = &omap44xx_l4_cfg_hwmod,
2261         .slave          = &omap44xx_mmu_dsp_hwmod,
2262         .clk            = "l4_div_ck",
2263         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2264 };
2265
2266 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2267         .name           = "mmu_dsp",
2268         .class          = &omap44xx_mmu_hwmod_class,
2269         .clkdm_name     = "tesla_clkdm",
2270         .rst_lines      = omap44xx_mmu_dsp_resets,
2271         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2272         .main_clk       = "dpll_iva_m4x2_ck",
2273         .prcm = {
2274                 .omap4 = {
2275                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2276                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2277                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2278                         .modulemode   = MODULEMODE_HWCTRL,
2279                 },
2280         },
2281 };
2282
2283 /*
2284  * 'mpu' class
2285  * mpu sub-system
2286  */
2287
2288 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2289         .name   = "mpu",
2290 };
2291
2292 /* mpu */
2293 static struct omap_hwmod omap44xx_mpu_hwmod = {
2294         .name           = "mpu",
2295         .class          = &omap44xx_mpu_hwmod_class,
2296         .clkdm_name     = "mpuss_clkdm",
2297         .flags          = HWMOD_INIT_NO_IDLE,
2298         .main_clk       = "dpll_mpu_m2_ck",
2299         .prcm = {
2300                 .omap4 = {
2301                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2302                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2303                 },
2304         },
2305 };
2306
2307 /*
2308  * 'ocmc_ram' class
2309  * top-level core on-chip ram
2310  */
2311
2312 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2313         .name   = "ocmc_ram",
2314 };
2315
2316 /* ocmc_ram */
2317 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2318         .name           = "ocmc_ram",
2319         .class          = &omap44xx_ocmc_ram_hwmod_class,
2320         .clkdm_name     = "l3_2_clkdm",
2321         .prcm = {
2322                 .omap4 = {
2323                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2324                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2325                 },
2326         },
2327 };
2328
2329 /*
2330  * 'ocp2scp' class
2331  * bridge to transform ocp interface protocol to scp (serial control port)
2332  * protocol
2333  */
2334
2335 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2336         .rev_offs       = 0x0000,
2337         .sysc_offs      = 0x0010,
2338         .syss_offs      = 0x0014,
2339         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2340                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2341         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2342         .sysc_fields    = &omap_hwmod_sysc_type1,
2343 };
2344
2345 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2346         .name   = "ocp2scp",
2347         .sysc   = &omap44xx_ocp2scp_sysc,
2348 };
2349
2350 /* ocp2scp_usb_phy */
2351 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2352         .name           = "ocp2scp_usb_phy",
2353         .class          = &omap44xx_ocp2scp_hwmod_class,
2354         .clkdm_name     = "l3_init_clkdm",
2355         /*
2356          * ocp2scp_usb_phy_phy_48m is provided by the OMAP4 PRCM IP
2357          * block as an "optional clock," and normally should never be
2358          * specified as the main_clk for an OMAP IP block.  However it
2359          * turns out that this clock is actually the main clock for
2360          * the ocp2scp_usb_phy IP block:
2361          * http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/119943.html
2362          * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems
2363          * to be the best workaround.
2364          */
2365         .main_clk       = "ocp2scp_usb_phy_phy_48m",
2366         .prcm = {
2367                 .omap4 = {
2368                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2369                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2370                         .modulemode   = MODULEMODE_HWCTRL,
2371                 },
2372         },
2373 };
2374
2375 /*
2376  * 'prcm' class
2377  * power and reset manager (part of the prcm infrastructure) + clock manager 2
2378  * + clock manager 1 (in always on power domain) + local prm in mpu
2379  */
2380
2381 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2382         .name   = "prcm",
2383 };
2384
2385 /* prcm_mpu */
2386 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2387         .name           = "prcm_mpu",
2388         .class          = &omap44xx_prcm_hwmod_class,
2389         .clkdm_name     = "l4_wkup_clkdm",
2390         .flags          = HWMOD_NO_IDLEST,
2391         .prcm = {
2392                 .omap4 = {
2393                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2394                 },
2395         },
2396 };
2397
2398 /* cm_core_aon */
2399 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2400         .name           = "cm_core_aon",
2401         .class          = &omap44xx_prcm_hwmod_class,
2402         .flags          = HWMOD_NO_IDLEST,
2403         .prcm = {
2404                 .omap4 = {
2405                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2406                 },
2407         },
2408 };
2409
2410 /* cm_core */
2411 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2412         .name           = "cm_core",
2413         .class          = &omap44xx_prcm_hwmod_class,
2414         .flags          = HWMOD_NO_IDLEST,
2415         .prcm = {
2416                 .omap4 = {
2417                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2418                 },
2419         },
2420 };
2421
2422 /* prm */
2423 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2424         { .name = "rst_global_warm_sw", .rst_shift = 0 },
2425         { .name = "rst_global_cold_sw", .rst_shift = 1 },
2426 };
2427
2428 static struct omap_hwmod omap44xx_prm_hwmod = {
2429         .name           = "prm",
2430         .class          = &omap44xx_prcm_hwmod_class,
2431         .rst_lines      = omap44xx_prm_resets,
2432         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
2433 };
2434
2435 /*
2436  * 'scrm' class
2437  * system clock and reset manager
2438  */
2439
2440 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2441         .name   = "scrm",
2442 };
2443
2444 /* scrm */
2445 static struct omap_hwmod omap44xx_scrm_hwmod = {
2446         .name           = "scrm",
2447         .class          = &omap44xx_scrm_hwmod_class,
2448         .clkdm_name     = "l4_wkup_clkdm",
2449         .prcm = {
2450                 .omap4 = {
2451                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2452                 },
2453         },
2454 };
2455
2456 /*
2457  * 'sl2if' class
2458  * shared level 2 memory interface
2459  */
2460
2461 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2462         .name   = "sl2if",
2463 };
2464
2465 /* sl2if */
2466 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2467         .name           = "sl2if",
2468         .class          = &omap44xx_sl2if_hwmod_class,
2469         .clkdm_name     = "ivahd_clkdm",
2470         .prcm = {
2471                 .omap4 = {
2472                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2473                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2474                         .modulemode   = MODULEMODE_HWCTRL,
2475                 },
2476         },
2477 };
2478
2479 /*
2480  * 'slimbus' class
2481  * bidirectional, multi-drop, multi-channel two-line serial interface between
2482  * the device and external components
2483  */
2484
2485 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2486         .rev_offs       = 0x0000,
2487         .sysc_offs      = 0x0010,
2488         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2489                            SYSC_HAS_SOFTRESET),
2490         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2491                            SIDLE_SMART_WKUP),
2492         .sysc_fields    = &omap_hwmod_sysc_type2,
2493 };
2494
2495 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2496         .name   = "slimbus",
2497         .sysc   = &omap44xx_slimbus_sysc,
2498 };
2499
2500 /* slimbus1 */
2501 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2502         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2503         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2504         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2505         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2506 };
2507
2508 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2509         .name           = "slimbus1",
2510         .class          = &omap44xx_slimbus_hwmod_class,
2511         .clkdm_name     = "abe_clkdm",
2512         .prcm = {
2513                 .omap4 = {
2514                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2515                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2516                         .modulemode   = MODULEMODE_SWCTRL,
2517                 },
2518         },
2519         .opt_clks       = slimbus1_opt_clks,
2520         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2521 };
2522
2523 /* slimbus2 */
2524 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2525         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2526         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2527         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2528 };
2529
2530 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2531         .name           = "slimbus2",
2532         .class          = &omap44xx_slimbus_hwmod_class,
2533         .clkdm_name     = "l4_per_clkdm",
2534         .prcm = {
2535                 .omap4 = {
2536                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2537                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2538                         .modulemode   = MODULEMODE_SWCTRL,
2539                 },
2540         },
2541         .opt_clks       = slimbus2_opt_clks,
2542         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
2543 };
2544
2545 /*
2546  * 'smartreflex' class
2547  * smartreflex module (monitor silicon performance and outputs a measure of
2548  * performance error)
2549  */
2550
2551 /* The IP is not compliant to type1 / type2 scheme */
2552 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2553         .sidle_shift    = 24,
2554         .enwkup_shift   = 26,
2555 };
2556
2557 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2558         .sysc_offs      = 0x0038,
2559         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2560         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2561                            SIDLE_SMART_WKUP),
2562         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2563 };
2564
2565 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2566         .name   = "smartreflex",
2567         .sysc   = &omap44xx_smartreflex_sysc,
2568         .rev    = 2,
2569 };
2570
2571 /* smartreflex_core */
2572 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2573         .sensor_voltdm_name   = "core",
2574 };
2575
2576 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2577         .name           = "smartreflex_core",
2578         .class          = &omap44xx_smartreflex_hwmod_class,
2579         .clkdm_name     = "l4_ao_clkdm",
2580
2581         .main_clk       = "smartreflex_core_fck",
2582         .prcm = {
2583                 .omap4 = {
2584                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2585                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2586                         .modulemode   = MODULEMODE_SWCTRL,
2587                 },
2588         },
2589         .dev_attr       = &smartreflex_core_dev_attr,
2590 };
2591
2592 /* smartreflex_iva */
2593 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2594         .sensor_voltdm_name     = "iva",
2595 };
2596
2597 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2598         .name           = "smartreflex_iva",
2599         .class          = &omap44xx_smartreflex_hwmod_class,
2600         .clkdm_name     = "l4_ao_clkdm",
2601         .main_clk       = "smartreflex_iva_fck",
2602         .prcm = {
2603                 .omap4 = {
2604                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2605                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2606                         .modulemode   = MODULEMODE_SWCTRL,
2607                 },
2608         },
2609         .dev_attr       = &smartreflex_iva_dev_attr,
2610 };
2611
2612 /* smartreflex_mpu */
2613 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2614         .sensor_voltdm_name     = "mpu",
2615 };
2616
2617 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
2618         .name           = "smartreflex_mpu",
2619         .class          = &omap44xx_smartreflex_hwmod_class,
2620         .clkdm_name     = "l4_ao_clkdm",
2621         .main_clk       = "smartreflex_mpu_fck",
2622         .prcm = {
2623                 .omap4 = {
2624                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
2625                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
2626                         .modulemode   = MODULEMODE_SWCTRL,
2627                 },
2628         },
2629         .dev_attr       = &smartreflex_mpu_dev_attr,
2630 };
2631
2632 /*
2633  * 'spinlock' class
2634  * spinlock provides hardware assistance for synchronizing the processes
2635  * running on multiple processors
2636  */
2637
2638 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
2639         .rev_offs       = 0x0000,
2640         .sysc_offs      = 0x0010,
2641         .syss_offs      = 0x0014,
2642         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2643                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2644                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2645         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2646         .sysc_fields    = &omap_hwmod_sysc_type1,
2647 };
2648
2649 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
2650         .name   = "spinlock",
2651         .sysc   = &omap44xx_spinlock_sysc,
2652 };
2653
2654 /* spinlock */
2655 static struct omap_hwmod omap44xx_spinlock_hwmod = {
2656         .name           = "spinlock",
2657         .class          = &omap44xx_spinlock_hwmod_class,
2658         .clkdm_name     = "l4_cfg_clkdm",
2659         .prcm = {
2660                 .omap4 = {
2661                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
2662                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
2663                 },
2664         },
2665 };
2666
2667 /*
2668  * 'timer' class
2669  * general purpose timer module with accurate 1ms tick
2670  * This class contains several variants: ['timer_1ms', 'timer']
2671  */
2672
2673 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
2674         .rev_offs       = 0x0000,
2675         .sysc_offs      = 0x0010,
2676         .syss_offs      = 0x0014,
2677         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2678                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2679                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2680                            SYSS_HAS_RESET_STATUS),
2681         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2682         .sysc_fields    = &omap_hwmod_sysc_type1,
2683 };
2684
2685 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
2686         .name   = "timer",
2687         .sysc   = &omap44xx_timer_1ms_sysc,
2688 };
2689
2690 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
2691         .rev_offs       = 0x0000,
2692         .sysc_offs      = 0x0010,
2693         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2694                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2695         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2696                            SIDLE_SMART_WKUP),
2697         .sysc_fields    = &omap_hwmod_sysc_type2,
2698 };
2699
2700 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
2701         .name   = "timer",
2702         .sysc   = &omap44xx_timer_sysc,
2703 };
2704
2705 /* always-on timers dev attribute */
2706 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
2707         .timer_capability       = OMAP_TIMER_ALWON,
2708 };
2709
2710 /* pwm timers dev attribute */
2711 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
2712         .timer_capability       = OMAP_TIMER_HAS_PWM,
2713 };
2714
2715 /* timers with DSP interrupt dev attribute */
2716 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
2717         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
2718 };
2719
2720 /* pwm timers with DSP interrupt dev attribute */
2721 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
2722         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
2723 };
2724
2725 /* timer1 */
2726 static struct omap_hwmod omap44xx_timer1_hwmod = {
2727         .name           = "timer1",
2728         .class          = &omap44xx_timer_1ms_hwmod_class,
2729         .clkdm_name     = "l4_wkup_clkdm",
2730         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2731         .main_clk       = "dmt1_clk_mux",
2732         .prcm = {
2733                 .omap4 = {
2734                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2735                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
2736                         .modulemode   = MODULEMODE_SWCTRL,
2737                 },
2738         },
2739         .dev_attr       = &capability_alwon_dev_attr,
2740 };
2741
2742 /* timer2 */
2743 static struct omap_hwmod omap44xx_timer2_hwmod = {
2744         .name           = "timer2",
2745         .class          = &omap44xx_timer_1ms_hwmod_class,
2746         .clkdm_name     = "l4_per_clkdm",
2747         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2748         .main_clk       = "cm2_dm2_mux",
2749         .prcm = {
2750                 .omap4 = {
2751                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
2752                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
2753                         .modulemode   = MODULEMODE_SWCTRL,
2754                 },
2755         },
2756 };
2757
2758 /* timer3 */
2759 static struct omap_hwmod omap44xx_timer3_hwmod = {
2760         .name           = "timer3",
2761         .class          = &omap44xx_timer_hwmod_class,
2762         .clkdm_name     = "l4_per_clkdm",
2763         .main_clk       = "cm2_dm3_mux",
2764         .prcm = {
2765                 .omap4 = {
2766                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
2767                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
2768                         .modulemode   = MODULEMODE_SWCTRL,
2769                 },
2770         },
2771 };
2772
2773 /* timer4 */
2774 static struct omap_hwmod omap44xx_timer4_hwmod = {
2775         .name           = "timer4",
2776         .class          = &omap44xx_timer_hwmod_class,
2777         .clkdm_name     = "l4_per_clkdm",
2778         .main_clk       = "cm2_dm4_mux",
2779         .prcm = {
2780                 .omap4 = {
2781                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
2782                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
2783                         .modulemode   = MODULEMODE_SWCTRL,
2784                 },
2785         },
2786 };
2787
2788 /* timer5 */
2789 static struct omap_hwmod omap44xx_timer5_hwmod = {
2790         .name           = "timer5",
2791         .class          = &omap44xx_timer_hwmod_class,
2792         .clkdm_name     = "abe_clkdm",
2793         .main_clk       = "timer5_sync_mux",
2794         .prcm = {
2795                 .omap4 = {
2796                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
2797                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
2798                         .modulemode   = MODULEMODE_SWCTRL,
2799                 },
2800         },
2801         .dev_attr       = &capability_dsp_dev_attr,
2802 };
2803
2804 /* timer6 */
2805 static struct omap_hwmod omap44xx_timer6_hwmod = {
2806         .name           = "timer6",
2807         .class          = &omap44xx_timer_hwmod_class,
2808         .clkdm_name     = "abe_clkdm",
2809         .main_clk       = "timer6_sync_mux",
2810         .prcm = {
2811                 .omap4 = {
2812                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
2813                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
2814                         .modulemode   = MODULEMODE_SWCTRL,
2815                 },
2816         },
2817         .dev_attr       = &capability_dsp_dev_attr,
2818 };
2819
2820 /* timer7 */
2821 static struct omap_hwmod omap44xx_timer7_hwmod = {
2822         .name           = "timer7",
2823         .class          = &omap44xx_timer_hwmod_class,
2824         .clkdm_name     = "abe_clkdm",
2825         .main_clk       = "timer7_sync_mux",
2826         .prcm = {
2827                 .omap4 = {
2828                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
2829                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
2830                         .modulemode   = MODULEMODE_SWCTRL,
2831                 },
2832         },
2833         .dev_attr       = &capability_dsp_dev_attr,
2834 };
2835
2836 /* timer8 */
2837 static struct omap_hwmod omap44xx_timer8_hwmod = {
2838         .name           = "timer8",
2839         .class          = &omap44xx_timer_hwmod_class,
2840         .clkdm_name     = "abe_clkdm",
2841         .main_clk       = "timer8_sync_mux",
2842         .prcm = {
2843                 .omap4 = {
2844                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
2845                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
2846                         .modulemode   = MODULEMODE_SWCTRL,
2847                 },
2848         },
2849         .dev_attr       = &capability_dsp_pwm_dev_attr,
2850 };
2851
2852 /* timer9 */
2853 static struct omap_hwmod omap44xx_timer9_hwmod = {
2854         .name           = "timer9",
2855         .class          = &omap44xx_timer_hwmod_class,
2856         .clkdm_name     = "l4_per_clkdm",
2857         .main_clk       = "cm2_dm9_mux",
2858         .prcm = {
2859                 .omap4 = {
2860                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
2861                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
2862                         .modulemode   = MODULEMODE_SWCTRL,
2863                 },
2864         },
2865         .dev_attr       = &capability_pwm_dev_attr,
2866 };
2867
2868 /* timer10 */
2869 static struct omap_hwmod omap44xx_timer10_hwmod = {
2870         .name           = "timer10",
2871         .class          = &omap44xx_timer_1ms_hwmod_class,
2872         .clkdm_name     = "l4_per_clkdm",
2873         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2874         .main_clk       = "cm2_dm10_mux",
2875         .prcm = {
2876                 .omap4 = {
2877                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
2878                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
2879                         .modulemode   = MODULEMODE_SWCTRL,
2880                 },
2881         },
2882         .dev_attr       = &capability_pwm_dev_attr,
2883 };
2884
2885 /* timer11 */
2886 static struct omap_hwmod omap44xx_timer11_hwmod = {
2887         .name           = "timer11",
2888         .class          = &omap44xx_timer_hwmod_class,
2889         .clkdm_name     = "l4_per_clkdm",
2890         .main_clk       = "cm2_dm11_mux",
2891         .prcm = {
2892                 .omap4 = {
2893                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
2894                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
2895                         .modulemode   = MODULEMODE_SWCTRL,
2896                 },
2897         },
2898         .dev_attr       = &capability_pwm_dev_attr,
2899 };
2900
2901 /*
2902  * 'uart' class
2903  * universal asynchronous receiver/transmitter (uart)
2904  */
2905
2906 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
2907         .rev_offs       = 0x0050,
2908         .sysc_offs      = 0x0054,
2909         .syss_offs      = 0x0058,
2910         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2911                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2912                            SYSS_HAS_RESET_STATUS),
2913         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2914                            SIDLE_SMART_WKUP),
2915         .sysc_fields    = &omap_hwmod_sysc_type1,
2916 };
2917
2918 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
2919         .name   = "uart",
2920         .sysc   = &omap44xx_uart_sysc,
2921 };
2922
2923 /* uart1 */
2924 static struct omap_hwmod omap44xx_uart1_hwmod = {
2925         .name           = "uart1",
2926         .class          = &omap44xx_uart_hwmod_class,
2927         .clkdm_name     = "l4_per_clkdm",
2928         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2929         .main_clk       = "func_48m_fclk",
2930         .prcm = {
2931                 .omap4 = {
2932                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
2933                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
2934                         .modulemode   = MODULEMODE_SWCTRL,
2935                 },
2936         },
2937 };
2938
2939 /* uart2 */
2940 static struct omap_hwmod omap44xx_uart2_hwmod = {
2941         .name           = "uart2",
2942         .class          = &omap44xx_uart_hwmod_class,
2943         .clkdm_name     = "l4_per_clkdm",
2944         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2945         .main_clk       = "func_48m_fclk",
2946         .prcm = {
2947                 .omap4 = {
2948                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
2949                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
2950                         .modulemode   = MODULEMODE_SWCTRL,
2951                 },
2952         },
2953 };
2954
2955 /* uart3 */
2956 static struct omap_hwmod omap44xx_uart3_hwmod = {
2957         .name           = "uart3",
2958         .class          = &omap44xx_uart_hwmod_class,
2959         .clkdm_name     = "l4_per_clkdm",
2960         .flags          = DEBUG_OMAP4UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
2961         .main_clk       = "func_48m_fclk",
2962         .prcm = {
2963                 .omap4 = {
2964                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
2965                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
2966                         .modulemode   = MODULEMODE_SWCTRL,
2967                 },
2968         },
2969 };
2970
2971 /* uart4 */
2972 static struct omap_hwmod omap44xx_uart4_hwmod = {
2973         .name           = "uart4",
2974         .class          = &omap44xx_uart_hwmod_class,
2975         .clkdm_name     = "l4_per_clkdm",
2976         .flags          = DEBUG_OMAP4UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
2977         .main_clk       = "func_48m_fclk",
2978         .prcm = {
2979                 .omap4 = {
2980                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
2981                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
2982                         .modulemode   = MODULEMODE_SWCTRL,
2983                 },
2984         },
2985 };
2986
2987 /*
2988  * 'usb_host_fs' class
2989  * full-speed usb host controller
2990  */
2991
2992 /* The IP is not compliant to type1 / type2 scheme */
2993 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
2994         .midle_shift    = 4,
2995         .sidle_shift    = 2,
2996         .srst_shift     = 1,
2997 };
2998
2999 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3000         .rev_offs       = 0x0000,
3001         .sysc_offs      = 0x0210,
3002         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3003                            SYSC_HAS_SOFTRESET),
3004         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3005                            SIDLE_SMART_WKUP),
3006         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
3007 };
3008
3009 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3010         .name   = "usb_host_fs",
3011         .sysc   = &omap44xx_usb_host_fs_sysc,
3012 };
3013
3014 /* usb_host_fs */
3015 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3016         .name           = "usb_host_fs",
3017         .class          = &omap44xx_usb_host_fs_hwmod_class,
3018         .clkdm_name     = "l3_init_clkdm",
3019         .main_clk       = "usb_host_fs_fck",
3020         .prcm = {
3021                 .omap4 = {
3022                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3023                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3024                         .modulemode   = MODULEMODE_SWCTRL,
3025                 },
3026         },
3027 };
3028
3029 /*
3030  * 'usb_host_hs' class
3031  * high-speed multi-port usb host controller
3032  */
3033
3034 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
3035         .rev_offs       = 0x0000,
3036         .sysc_offs      = 0x0010,
3037         .syss_offs      = 0x0014,
3038         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3039                            SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS),
3040         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3041                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3042                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3043         .sysc_fields    = &omap_hwmod_sysc_type2,
3044 };
3045
3046 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3047         .name   = "usb_host_hs",
3048         .sysc   = &omap44xx_usb_host_hs_sysc,
3049 };
3050
3051 /* usb_host_hs */
3052 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3053         .name           = "usb_host_hs",
3054         .class          = &omap44xx_usb_host_hs_hwmod_class,
3055         .clkdm_name     = "l3_init_clkdm",
3056         .main_clk       = "usb_host_hs_fck",
3057         .prcm = {
3058                 .omap4 = {
3059                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
3060                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
3061                         .modulemode   = MODULEMODE_SWCTRL,
3062                 },
3063         },
3064
3065         /*
3066          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3067          * id: i660
3068          *
3069          * Description:
3070          * In the following configuration :
3071          * - USBHOST module is set to smart-idle mode
3072          * - PRCM asserts idle_req to the USBHOST module ( This typically
3073          *   happens when the system is going to a low power mode : all ports
3074          *   have been suspended, the master part of the USBHOST module has
3075          *   entered the standby state, and SW has cut the functional clocks)
3076          * - an USBHOST interrupt occurs before the module is able to answer
3077          *   idle_ack, typically a remote wakeup IRQ.
3078          * Then the USB HOST module will enter a deadlock situation where it
3079          * is no more accessible nor functional.
3080          *
3081          * Workaround:
3082          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3083          */
3084
3085         /*
3086          * Errata: USB host EHCI may stall when entering smart-standby mode
3087          * Id: i571
3088          *
3089          * Description:
3090          * When the USBHOST module is set to smart-standby mode, and when it is
3091          * ready to enter the standby state (i.e. all ports are suspended and
3092          * all attached devices are in suspend mode), then it can wrongly assert
3093          * the Mstandby signal too early while there are still some residual OCP
3094          * transactions ongoing. If this condition occurs, the internal state
3095          * machine may go to an undefined state and the USB link may be stuck
3096          * upon the next resume.
3097          *
3098          * Workaround:
3099          * Don't use smart standby; use only force standby,
3100          * hence HWMOD_SWSUP_MSTANDBY
3101          */
3102
3103         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3104 };
3105
3106 /*
3107  * 'usb_otg_hs' class
3108  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3109  */
3110
3111 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3112         .rev_offs       = 0x0400,
3113         .sysc_offs      = 0x0404,
3114         .syss_offs      = 0x0408,
3115         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3116                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3117                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3118         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3119                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3120                            MSTANDBY_SMART),
3121         .sysc_fields    = &omap_hwmod_sysc_type1,
3122 };
3123
3124 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3125         .name   = "usb_otg_hs",
3126         .sysc   = &omap44xx_usb_otg_hs_sysc,
3127 };
3128
3129 /* usb_otg_hs */
3130 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3131         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3132 };
3133
3134 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3135         .name           = "usb_otg_hs",
3136         .class          = &omap44xx_usb_otg_hs_hwmod_class,
3137         .clkdm_name     = "l3_init_clkdm",
3138         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3139         .main_clk       = "usb_otg_hs_ick",
3140         .prcm = {
3141                 .omap4 = {
3142                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3143                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3144                         .modulemode   = MODULEMODE_HWCTRL,
3145                 },
3146         },
3147         .opt_clks       = usb_otg_hs_opt_clks,
3148         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
3149 };
3150
3151 /*
3152  * 'usb_tll_hs' class
3153  * usb_tll_hs module is the adapter on the usb_host_hs ports
3154  */
3155
3156 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3157         .rev_offs       = 0x0000,
3158         .sysc_offs      = 0x0010,
3159         .syss_offs      = 0x0014,
3160         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3161                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3162                            SYSC_HAS_AUTOIDLE),
3163         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3164         .sysc_fields    = &omap_hwmod_sysc_type1,
3165 };
3166
3167 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3168         .name   = "usb_tll_hs",
3169         .sysc   = &omap44xx_usb_tll_hs_sysc,
3170 };
3171
3172 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3173         .name           = "usb_tll_hs",
3174         .class          = &omap44xx_usb_tll_hs_hwmod_class,
3175         .clkdm_name     = "l3_init_clkdm",
3176         .main_clk       = "usb_tll_hs_ick",
3177         .prcm = {
3178                 .omap4 = {
3179                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3180                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3181                         .modulemode   = MODULEMODE_HWCTRL,
3182                 },
3183         },
3184 };
3185
3186 /*
3187  * 'wd_timer' class
3188  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3189  * overflow condition
3190  */
3191
3192 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3193         .rev_offs       = 0x0000,
3194         .sysc_offs      = 0x0010,
3195         .syss_offs      = 0x0014,
3196         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3197                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3198         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3199                            SIDLE_SMART_WKUP),
3200         .sysc_fields    = &omap_hwmod_sysc_type1,
3201 };
3202
3203 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3204         .name           = "wd_timer",
3205         .sysc           = &omap44xx_wd_timer_sysc,
3206         .pre_shutdown   = &omap2_wd_timer_disable,
3207         .reset          = &omap2_wd_timer_reset,
3208 };
3209
3210 /* wd_timer2 */
3211 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3212         .name           = "wd_timer2",
3213         .class          = &omap44xx_wd_timer_hwmod_class,
3214         .clkdm_name     = "l4_wkup_clkdm",
3215         .main_clk       = "sys_32k_ck",
3216         .prcm = {
3217                 .omap4 = {
3218                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3219                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3220                         .modulemode   = MODULEMODE_SWCTRL,
3221                 },
3222         },
3223 };
3224
3225 /* wd_timer3 */
3226 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3227         .name           = "wd_timer3",
3228         .class          = &omap44xx_wd_timer_hwmod_class,
3229         .clkdm_name     = "abe_clkdm",
3230         .main_clk       = "sys_32k_ck",
3231         .prcm = {
3232                 .omap4 = {
3233                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3234                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3235                         .modulemode   = MODULEMODE_SWCTRL,
3236                 },
3237         },
3238 };
3239
3240
3241 /*
3242  * interfaces
3243  */
3244
3245 /* l3_main_1 -> dmm */
3246 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3247         .master         = &omap44xx_l3_main_1_hwmod,
3248         .slave          = &omap44xx_dmm_hwmod,
3249         .clk            = "l3_div_ck",
3250         .user           = OCP_USER_SDMA,
3251 };
3252
3253 /* mpu -> dmm */
3254 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3255         .master         = &omap44xx_mpu_hwmod,
3256         .slave          = &omap44xx_dmm_hwmod,
3257         .clk            = "l3_div_ck",
3258         .user           = OCP_USER_MPU,
3259 };
3260
3261 /* iva -> l3_instr */
3262 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3263         .master         = &omap44xx_iva_hwmod,
3264         .slave          = &omap44xx_l3_instr_hwmod,
3265         .clk            = "l3_div_ck",
3266         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3267 };
3268
3269 /* l3_main_3 -> l3_instr */
3270 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3271         .master         = &omap44xx_l3_main_3_hwmod,
3272         .slave          = &omap44xx_l3_instr_hwmod,
3273         .clk            = "l3_div_ck",
3274         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3275 };
3276
3277 /* ocp_wp_noc -> l3_instr */
3278 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3279         .master         = &omap44xx_ocp_wp_noc_hwmod,
3280         .slave          = &omap44xx_l3_instr_hwmod,
3281         .clk            = "l3_div_ck",
3282         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3283 };
3284
3285 /* dsp -> l3_main_1 */
3286 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3287         .master         = &omap44xx_dsp_hwmod,
3288         .slave          = &omap44xx_l3_main_1_hwmod,
3289         .clk            = "l3_div_ck",
3290         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3291 };
3292
3293 /* dss -> l3_main_1 */
3294 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3295         .master         = &omap44xx_dss_hwmod,
3296         .slave          = &omap44xx_l3_main_1_hwmod,
3297         .clk            = "l3_div_ck",
3298         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3299 };
3300
3301 /* l3_main_2 -> l3_main_1 */
3302 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3303         .master         = &omap44xx_l3_main_2_hwmod,
3304         .slave          = &omap44xx_l3_main_1_hwmod,
3305         .clk            = "l3_div_ck",
3306         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3307 };
3308
3309 /* l4_cfg -> l3_main_1 */
3310 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3311         .master         = &omap44xx_l4_cfg_hwmod,
3312         .slave          = &omap44xx_l3_main_1_hwmod,
3313         .clk            = "l4_div_ck",
3314         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3315 };
3316
3317 /* mmc1 -> l3_main_1 */
3318 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3319         .master         = &omap44xx_mmc1_hwmod,
3320         .slave          = &omap44xx_l3_main_1_hwmod,
3321         .clk            = "l3_div_ck",
3322         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3323 };
3324
3325 /* mmc2 -> l3_main_1 */
3326 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3327         .master         = &omap44xx_mmc2_hwmod,
3328         .slave          = &omap44xx_l3_main_1_hwmod,
3329         .clk            = "l3_div_ck",
3330         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3331 };
3332
3333 /* mpu -> l3_main_1 */
3334 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3335         .master         = &omap44xx_mpu_hwmod,
3336         .slave          = &omap44xx_l3_main_1_hwmod,
3337         .clk            = "l3_div_ck",
3338         .user           = OCP_USER_MPU,
3339 };
3340
3341 /* debugss -> l3_main_2 */
3342 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3343         .master         = &omap44xx_debugss_hwmod,
3344         .slave          = &omap44xx_l3_main_2_hwmod,
3345         .clk            = "dbgclk_mux_ck",
3346         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3347 };
3348
3349 /* dma_system -> l3_main_2 */
3350 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3351         .master         = &omap44xx_dma_system_hwmod,
3352         .slave          = &omap44xx_l3_main_2_hwmod,
3353         .clk            = "l3_div_ck",
3354         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3355 };
3356
3357 /* fdif -> l3_main_2 */
3358 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3359         .master         = &omap44xx_fdif_hwmod,
3360         .slave          = &omap44xx_l3_main_2_hwmod,
3361         .clk            = "l3_div_ck",
3362         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3363 };
3364
3365 /* gpu -> l3_main_2 */
3366 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
3367         .master         = &omap44xx_gpu_hwmod,
3368         .slave          = &omap44xx_l3_main_2_hwmod,
3369         .clk            = "l3_div_ck",
3370         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3371 };
3372
3373 /* hsi -> l3_main_2 */
3374 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
3375         .master         = &omap44xx_hsi_hwmod,
3376         .slave          = &omap44xx_l3_main_2_hwmod,
3377         .clk            = "l3_div_ck",
3378         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3379 };
3380
3381 /* ipu -> l3_main_2 */
3382 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
3383         .master         = &omap44xx_ipu_hwmod,
3384         .slave          = &omap44xx_l3_main_2_hwmod,
3385         .clk            = "l3_div_ck",
3386         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3387 };
3388
3389 /* iss -> l3_main_2 */
3390 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
3391         .master         = &omap44xx_iss_hwmod,
3392         .slave          = &omap44xx_l3_main_2_hwmod,
3393         .clk            = "l3_div_ck",
3394         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3395 };
3396
3397 /* iva -> l3_main_2 */
3398 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
3399         .master         = &omap44xx_iva_hwmod,
3400         .slave          = &omap44xx_l3_main_2_hwmod,
3401         .clk            = "l3_div_ck",
3402         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3403 };
3404
3405 /* l3_main_1 -> l3_main_2 */
3406 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
3407         .master         = &omap44xx_l3_main_1_hwmod,
3408         .slave          = &omap44xx_l3_main_2_hwmod,
3409         .clk            = "l3_div_ck",
3410         .user           = OCP_USER_MPU,
3411 };
3412
3413 /* l4_cfg -> l3_main_2 */
3414 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
3415         .master         = &omap44xx_l4_cfg_hwmod,
3416         .slave          = &omap44xx_l3_main_2_hwmod,
3417         .clk            = "l4_div_ck",
3418         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3419 };
3420
3421 /* usb_host_fs -> l3_main_2 */
3422 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
3423         .master         = &omap44xx_usb_host_fs_hwmod,
3424         .slave          = &omap44xx_l3_main_2_hwmod,
3425         .clk            = "l3_div_ck",
3426         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3427 };
3428
3429 /* usb_host_hs -> l3_main_2 */
3430 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
3431         .master         = &omap44xx_usb_host_hs_hwmod,
3432         .slave          = &omap44xx_l3_main_2_hwmod,
3433         .clk            = "l3_div_ck",
3434         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3435 };
3436
3437 /* usb_otg_hs -> l3_main_2 */
3438 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
3439         .master         = &omap44xx_usb_otg_hs_hwmod,
3440         .slave          = &omap44xx_l3_main_2_hwmod,
3441         .clk            = "l3_div_ck",
3442         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3443 };
3444
3445 /* l3_main_1 -> l3_main_3 */
3446 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
3447         .master         = &omap44xx_l3_main_1_hwmod,
3448         .slave          = &omap44xx_l3_main_3_hwmod,
3449         .clk            = "l3_div_ck",
3450         .user           = OCP_USER_MPU,
3451 };
3452
3453 /* l3_main_2 -> l3_main_3 */
3454 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
3455         .master         = &omap44xx_l3_main_2_hwmod,
3456         .slave          = &omap44xx_l3_main_3_hwmod,
3457         .clk            = "l3_div_ck",
3458         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3459 };
3460
3461 /* l4_cfg -> l3_main_3 */
3462 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
3463         .master         = &omap44xx_l4_cfg_hwmod,
3464         .slave          = &omap44xx_l3_main_3_hwmod,
3465         .clk            = "l4_div_ck",
3466         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3467 };
3468
3469 /* aess -> l4_abe */
3470 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
3471         .master         = &omap44xx_aess_hwmod,
3472         .slave          = &omap44xx_l4_abe_hwmod,
3473         .clk            = "ocp_abe_iclk",
3474         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3475 };
3476
3477 /* dsp -> l4_abe */
3478 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
3479         .master         = &omap44xx_dsp_hwmod,
3480         .slave          = &omap44xx_l4_abe_hwmod,
3481         .clk            = "ocp_abe_iclk",
3482         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3483 };
3484
3485 /* l3_main_1 -> l4_abe */
3486 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
3487         .master         = &omap44xx_l3_main_1_hwmod,
3488         .slave          = &omap44xx_l4_abe_hwmod,
3489         .clk            = "l3_div_ck",
3490         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3491 };
3492
3493 /* mpu -> l4_abe */
3494 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
3495         .master         = &omap44xx_mpu_hwmod,
3496         .slave          = &omap44xx_l4_abe_hwmod,
3497         .clk            = "ocp_abe_iclk",
3498         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3499 };
3500
3501 /* l3_main_1 -> l4_cfg */
3502 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
3503         .master         = &omap44xx_l3_main_1_hwmod,
3504         .slave          = &omap44xx_l4_cfg_hwmod,
3505         .clk            = "l3_div_ck",
3506         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3507 };
3508
3509 /* l3_main_2 -> l4_per */
3510 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
3511         .master         = &omap44xx_l3_main_2_hwmod,
3512         .slave          = &omap44xx_l4_per_hwmod,
3513         .clk            = "l3_div_ck",
3514         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3515 };
3516
3517 /* l4_cfg -> l4_wkup */
3518 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
3519         .master         = &omap44xx_l4_cfg_hwmod,
3520         .slave          = &omap44xx_l4_wkup_hwmod,
3521         .clk            = "l4_div_ck",
3522         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3523 };
3524
3525 /* mpu -> mpu_private */
3526 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
3527         .master         = &omap44xx_mpu_hwmod,
3528         .slave          = &omap44xx_mpu_private_hwmod,
3529         .clk            = "l3_div_ck",
3530         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3531 };
3532
3533 /* l4_cfg -> ocp_wp_noc */
3534 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
3535         .master         = &omap44xx_l4_cfg_hwmod,
3536         .slave          = &omap44xx_ocp_wp_noc_hwmod,
3537         .clk            = "l4_div_ck",
3538         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3539 };
3540
3541 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
3542         {
3543                 .name           = "dmem",
3544                 .pa_start       = 0x40180000,
3545                 .pa_end         = 0x4018ffff
3546         },
3547         {
3548                 .name           = "cmem",
3549                 .pa_start       = 0x401a0000,
3550                 .pa_end         = 0x401a1fff
3551         },
3552         {
3553                 .name           = "smem",
3554                 .pa_start       = 0x401c0000,
3555                 .pa_end         = 0x401c5fff
3556         },
3557         {
3558                 .name           = "pmem",
3559                 .pa_start       = 0x401e0000,
3560                 .pa_end         = 0x401e1fff
3561         },
3562         {
3563                 .name           = "mpu",
3564                 .pa_start       = 0x401f1000,
3565                 .pa_end         = 0x401f13ff,
3566                 .flags          = ADDR_TYPE_RT
3567         },
3568         { }
3569 };
3570
3571 /* l4_abe -> aess */
3572 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
3573         .master         = &omap44xx_l4_abe_hwmod,
3574         .slave          = &omap44xx_aess_hwmod,
3575         .clk            = "ocp_abe_iclk",
3576         .addr           = omap44xx_aess_addrs,
3577         .user           = OCP_USER_MPU,
3578 };
3579
3580 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
3581         {
3582                 .name           = "dmem_dma",
3583                 .pa_start       = 0x49080000,
3584                 .pa_end         = 0x4908ffff
3585         },
3586         {
3587                 .name           = "cmem_dma",
3588                 .pa_start       = 0x490a0000,
3589                 .pa_end         = 0x490a1fff
3590         },
3591         {
3592                 .name           = "smem_dma",
3593                 .pa_start       = 0x490c0000,
3594                 .pa_end         = 0x490c5fff
3595         },
3596         {
3597                 .name           = "pmem_dma",
3598                 .pa_start       = 0x490e0000,
3599                 .pa_end         = 0x490e1fff
3600         },
3601         {
3602                 .name           = "dma",
3603                 .pa_start       = 0x490f1000,
3604                 .pa_end         = 0x490f13ff,
3605                 .flags          = ADDR_TYPE_RT
3606         },
3607         { }
3608 };
3609
3610 /* l4_abe -> aess (dma) */
3611 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
3612         .master         = &omap44xx_l4_abe_hwmod,
3613         .slave          = &omap44xx_aess_hwmod,
3614         .clk            = "ocp_abe_iclk",
3615         .addr           = omap44xx_aess_dma_addrs,
3616         .user           = OCP_USER_SDMA,
3617 };
3618
3619 /* l3_main_2 -> c2c */
3620 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
3621         .master         = &omap44xx_l3_main_2_hwmod,
3622         .slave          = &omap44xx_c2c_hwmod,
3623         .clk            = "l3_div_ck",
3624         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3625 };
3626
3627 /* l4_wkup -> counter_32k */
3628 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
3629         .master         = &omap44xx_l4_wkup_hwmod,
3630         .slave          = &omap44xx_counter_32k_hwmod,
3631         .clk            = "l4_wkup_clk_mux_ck",
3632         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3633 };
3634
3635 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
3636         {
3637                 .pa_start       = 0x4a002000,
3638                 .pa_end         = 0x4a0027ff,
3639                 .flags          = ADDR_TYPE_RT
3640         },
3641         { }
3642 };
3643
3644 /* l4_cfg -> ctrl_module_core */
3645 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
3646         .master         = &omap44xx_l4_cfg_hwmod,
3647         .slave          = &omap44xx_ctrl_module_core_hwmod,
3648         .clk            = "l4_div_ck",
3649         .addr           = omap44xx_ctrl_module_core_addrs,
3650         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3651 };
3652
3653 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
3654         {
3655                 .pa_start       = 0x4a100000,
3656                 .pa_end         = 0x4a1007ff,
3657                 .flags          = ADDR_TYPE_RT
3658         },
3659         { }
3660 };
3661
3662 /* l4_cfg -> ctrl_module_pad_core */
3663 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
3664         .master         = &omap44xx_l4_cfg_hwmod,
3665         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
3666         .clk            = "l4_div_ck",
3667         .addr           = omap44xx_ctrl_module_pad_core_addrs,
3668         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3669 };
3670
3671 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
3672         {
3673                 .pa_start       = 0x4a30c000,
3674                 .pa_end         = 0x4a30c7ff,
3675                 .flags          = ADDR_TYPE_RT
3676         },
3677         { }
3678 };
3679
3680 /* l4_wkup -> ctrl_module_wkup */
3681 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
3682         .master         = &omap44xx_l4_wkup_hwmod,
3683         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
3684         .clk            = "l4_wkup_clk_mux_ck",
3685         .addr           = omap44xx_ctrl_module_wkup_addrs,
3686         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3687 };
3688
3689 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
3690         {
3691                 .pa_start       = 0x4a31e000,
3692                 .pa_end         = 0x4a31e7ff,
3693                 .flags          = ADDR_TYPE_RT
3694         },
3695         { }
3696 };
3697
3698 /* l4_wkup -> ctrl_module_pad_wkup */
3699 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
3700         .master         = &omap44xx_l4_wkup_hwmod,
3701         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
3702         .clk            = "l4_wkup_clk_mux_ck",
3703         .addr           = omap44xx_ctrl_module_pad_wkup_addrs,
3704         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3705 };
3706
3707 /* l3_instr -> debugss */
3708 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
3709         .master         = &omap44xx_l3_instr_hwmod,
3710         .slave          = &omap44xx_debugss_hwmod,
3711         .clk            = "l3_div_ck",
3712         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3713 };
3714
3715 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
3716         {
3717                 .pa_start       = 0x4a056000,
3718                 .pa_end         = 0x4a056fff,
3719                 .flags          = ADDR_TYPE_RT
3720         },
3721         { }
3722 };
3723
3724 /* l4_cfg -> dma_system */
3725 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
3726         .master         = &omap44xx_l4_cfg_hwmod,
3727         .slave          = &omap44xx_dma_system_hwmod,
3728         .clk            = "l4_div_ck",
3729         .addr           = omap44xx_dma_system_addrs,
3730         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3731 };
3732
3733 /* l4_abe -> dmic */
3734 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
3735         .master         = &omap44xx_l4_abe_hwmod,
3736         .slave          = &omap44xx_dmic_hwmod,
3737         .clk            = "ocp_abe_iclk",
3738         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3739 };
3740
3741 /* dsp -> iva */
3742 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
3743         .master         = &omap44xx_dsp_hwmod,
3744         .slave          = &omap44xx_iva_hwmod,
3745         .clk            = "dpll_iva_m5x2_ck",
3746         .user           = OCP_USER_DSP,
3747 };
3748
3749 /* dsp -> sl2if */
3750 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
3751         .master         = &omap44xx_dsp_hwmod,
3752         .slave          = &omap44xx_sl2if_hwmod,
3753         .clk            = "dpll_iva_m5x2_ck",
3754         .user           = OCP_USER_DSP,
3755 };
3756
3757 /* l4_cfg -> dsp */
3758 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
3759         .master         = &omap44xx_l4_cfg_hwmod,
3760         .slave          = &omap44xx_dsp_hwmod,
3761         .clk            = "l4_div_ck",
3762         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3763 };
3764
3765 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
3766         {
3767                 .pa_start       = 0x58000000,
3768                 .pa_end         = 0x5800007f,
3769                 .flags          = ADDR_TYPE_RT
3770         },
3771         { }
3772 };
3773
3774 /* l3_main_2 -> dss */
3775 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
3776         .master         = &omap44xx_l3_main_2_hwmod,
3777         .slave          = &omap44xx_dss_hwmod,
3778         .clk            = "l3_div_ck",
3779         .addr           = omap44xx_dss_dma_addrs,
3780         .user           = OCP_USER_SDMA,
3781 };
3782
3783 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
3784         {
3785                 .pa_start       = 0x48040000,
3786                 .pa_end         = 0x4804007f,
3787                 .flags          = ADDR_TYPE_RT
3788         },
3789         { }
3790 };
3791
3792 /* l4_per -> dss */
3793 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
3794         .master         = &omap44xx_l4_per_hwmod,
3795         .slave          = &omap44xx_dss_hwmod,
3796         .clk            = "l4_div_ck",
3797         .addr           = omap44xx_dss_addrs,
3798         .user           = OCP_USER_MPU,
3799 };
3800
3801 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
3802         {
3803                 .pa_start       = 0x58001000,
3804                 .pa_end         = 0x58001fff,
3805                 .flags          = ADDR_TYPE_RT
3806         },
3807         { }
3808 };
3809
3810 /* l3_main_2 -> dss_dispc */
3811 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
3812         .master         = &omap44xx_l3_main_2_hwmod,
3813         .slave          = &omap44xx_dss_dispc_hwmod,
3814         .clk            = "l3_div_ck",
3815         .addr           = omap44xx_dss_dispc_dma_addrs,
3816         .user           = OCP_USER_SDMA,
3817 };
3818
3819 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
3820         {
3821                 .pa_start       = 0x48041000,
3822                 .pa_end         = 0x48041fff,
3823                 .flags          = ADDR_TYPE_RT
3824         },
3825         { }
3826 };
3827
3828 /* l4_per -> dss_dispc */
3829 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
3830         .master         = &omap44xx_l4_per_hwmod,
3831         .slave          = &omap44xx_dss_dispc_hwmod,
3832         .clk            = "l4_div_ck",
3833         .addr           = omap44xx_dss_dispc_addrs,
3834         .user           = OCP_USER_MPU,
3835 };
3836
3837 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
3838         {
3839                 .pa_start       = 0x58004000,
3840                 .pa_end         = 0x580041ff,
3841                 .flags          = ADDR_TYPE_RT
3842         },
3843         { }
3844 };
3845
3846 /* l3_main_2 -> dss_dsi1 */
3847 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
3848         .master         = &omap44xx_l3_main_2_hwmod,
3849         .slave          = &omap44xx_dss_dsi1_hwmod,
3850         .clk            = "l3_div_ck",
3851         .addr           = omap44xx_dss_dsi1_dma_addrs,
3852         .user           = OCP_USER_SDMA,
3853 };
3854
3855 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
3856         {
3857                 .pa_start       = 0x48044000,
3858                 .pa_end         = 0x480441ff,
3859                 .flags          = ADDR_TYPE_RT
3860         },
3861         { }
3862 };
3863
3864 /* l4_per -> dss_dsi1 */
3865 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
3866         .master         = &omap44xx_l4_per_hwmod,
3867         .slave          = &omap44xx_dss_dsi1_hwmod,
3868         .clk            = "l4_div_ck",
3869         .addr           = omap44xx_dss_dsi1_addrs,
3870         .user           = OCP_USER_MPU,
3871 };
3872
3873 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
3874         {
3875                 .pa_start       = 0x58005000,
3876                 .pa_end         = 0x580051ff,
3877                 .flags          = ADDR_TYPE_RT
3878         },
3879         { }
3880 };
3881
3882 /* l3_main_2 -> dss_dsi2 */
3883 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
3884         .master         = &omap44xx_l3_main_2_hwmod,
3885         .slave          = &omap44xx_dss_dsi2_hwmod,
3886         .clk            = "l3_div_ck",
3887         .addr           = omap44xx_dss_dsi2_dma_addrs,
3888         .user           = OCP_USER_SDMA,
3889 };
3890
3891 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
3892         {
3893                 .pa_start       = 0x48045000,
3894                 .pa_end         = 0x480451ff,
3895                 .flags          = ADDR_TYPE_RT
3896         },
3897         { }
3898 };
3899
3900 /* l4_per -> dss_dsi2 */
3901 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
3902         .master         = &omap44xx_l4_per_hwmod,
3903         .slave          = &omap44xx_dss_dsi2_hwmod,
3904         .clk            = "l4_div_ck",
3905         .addr           = omap44xx_dss_dsi2_addrs,
3906         .user           = OCP_USER_MPU,
3907 };
3908
3909 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
3910         {
3911                 .pa_start       = 0x58006000,
3912                 .pa_end         = 0x58006fff,
3913                 .flags          = ADDR_TYPE_RT
3914         },
3915         { }
3916 };
3917
3918 /* l3_main_2 -> dss_hdmi */
3919 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
3920         .master         = &omap44xx_l3_main_2_hwmod,
3921         .slave          = &omap44xx_dss_hdmi_hwmod,
3922         .clk            = "l3_div_ck",
3923         .addr           = omap44xx_dss_hdmi_dma_addrs,
3924         .user           = OCP_USER_SDMA,
3925 };
3926
3927 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
3928         {
3929                 .pa_start       = 0x48046000,
3930                 .pa_end         = 0x48046fff,
3931                 .flags          = ADDR_TYPE_RT
3932         },
3933         { }
3934 };
3935
3936 /* l4_per -> dss_hdmi */
3937 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
3938         .master         = &omap44xx_l4_per_hwmod,
3939         .slave          = &omap44xx_dss_hdmi_hwmod,
3940         .clk            = "l4_div_ck",
3941         .addr           = omap44xx_dss_hdmi_addrs,
3942         .user           = OCP_USER_MPU,
3943 };
3944
3945 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
3946         {
3947                 .pa_start       = 0x58002000,
3948                 .pa_end         = 0x580020ff,
3949                 .flags          = ADDR_TYPE_RT
3950         },
3951         { }
3952 };
3953
3954 /* l3_main_2 -> dss_rfbi */
3955 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
3956         .master         = &omap44xx_l3_main_2_hwmod,
3957         .slave          = &omap44xx_dss_rfbi_hwmod,
3958         .clk            = "l3_div_ck",
3959         .addr           = omap44xx_dss_rfbi_dma_addrs,
3960         .user           = OCP_USER_SDMA,
3961 };
3962
3963 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
3964         {
3965                 .pa_start       = 0x48042000,
3966                 .pa_end         = 0x480420ff,
3967                 .flags          = ADDR_TYPE_RT
3968         },
3969         { }
3970 };
3971
3972 /* l4_per -> dss_rfbi */
3973 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
3974         .master         = &omap44xx_l4_per_hwmod,
3975         .slave          = &omap44xx_dss_rfbi_hwmod,
3976         .clk            = "l4_div_ck",
3977         .addr           = omap44xx_dss_rfbi_addrs,
3978         .user           = OCP_USER_MPU,
3979 };
3980
3981 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
3982         {
3983                 .pa_start       = 0x58003000,
3984                 .pa_end         = 0x580030ff,
3985                 .flags          = ADDR_TYPE_RT
3986         },
3987         { }
3988 };
3989
3990 /* l3_main_2 -> dss_venc */
3991 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
3992         .master         = &omap44xx_l3_main_2_hwmod,
3993         .slave          = &omap44xx_dss_venc_hwmod,
3994         .clk            = "l3_div_ck",
3995         .addr           = omap44xx_dss_venc_dma_addrs,
3996         .user           = OCP_USER_SDMA,
3997 };
3998
3999 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
4000         {
4001                 .pa_start       = 0x48043000,
4002                 .pa_end         = 0x480430ff,
4003                 .flags          = ADDR_TYPE_RT
4004         },
4005         { }
4006 };
4007
4008 /* l4_per -> dss_venc */
4009 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
4010         .master         = &omap44xx_l4_per_hwmod,
4011         .slave          = &omap44xx_dss_venc_hwmod,
4012         .clk            = "l4_div_ck",
4013         .addr           = omap44xx_dss_venc_addrs,
4014         .user           = OCP_USER_MPU,
4015 };
4016
4017 /* l3_main_2 -> sham */
4018 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sha0 = {
4019         .master         = &omap44xx_l3_main_2_hwmod,
4020         .slave          = &omap44xx_sha0_hwmod,
4021         .clk            = "l3_div_ck",
4022         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4023 };
4024
4025 /* l4_per -> elm */
4026 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4027         .master         = &omap44xx_l4_per_hwmod,
4028         .slave          = &omap44xx_elm_hwmod,
4029         .clk            = "l4_div_ck",
4030         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4031 };
4032
4033 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4034         {
4035                 .pa_start       = 0x4a10a000,
4036                 .pa_end         = 0x4a10a1ff,
4037                 .flags          = ADDR_TYPE_RT
4038         },
4039         { }
4040 };
4041
4042 /* l4_cfg -> fdif */
4043 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4044         .master         = &omap44xx_l4_cfg_hwmod,
4045         .slave          = &omap44xx_fdif_hwmod,
4046         .clk            = "l4_div_ck",
4047         .addr           = omap44xx_fdif_addrs,
4048         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4049 };
4050
4051 /* l4_wkup -> gpio1 */
4052 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4053         .master         = &omap44xx_l4_wkup_hwmod,
4054         .slave          = &omap44xx_gpio1_hwmod,
4055         .clk            = "l4_wkup_clk_mux_ck",
4056         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4057 };
4058
4059 /* l4_per -> gpio2 */
4060 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4061         .master         = &omap44xx_l4_per_hwmod,
4062         .slave          = &omap44xx_gpio2_hwmod,
4063         .clk            = "l4_div_ck",
4064         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4065 };
4066
4067 /* l4_per -> gpio3 */
4068 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4069         .master         = &omap44xx_l4_per_hwmod,
4070         .slave          = &omap44xx_gpio3_hwmod,
4071         .clk            = "l4_div_ck",
4072         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4073 };
4074
4075 /* l4_per -> gpio4 */
4076 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4077         .master         = &omap44xx_l4_per_hwmod,
4078         .slave          = &omap44xx_gpio4_hwmod,
4079         .clk            = "l4_div_ck",
4080         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4081 };
4082
4083 /* l4_per -> gpio5 */
4084 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4085         .master         = &omap44xx_l4_per_hwmod,
4086         .slave          = &omap44xx_gpio5_hwmod,
4087         .clk            = "l4_div_ck",
4088         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4089 };
4090
4091 /* l4_per -> gpio6 */
4092 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4093         .master         = &omap44xx_l4_per_hwmod,
4094         .slave          = &omap44xx_gpio6_hwmod,
4095         .clk            = "l4_div_ck",
4096         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4097 };
4098
4099 /* l3_main_2 -> gpmc */
4100 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4101         .master         = &omap44xx_l3_main_2_hwmod,
4102         .slave          = &omap44xx_gpmc_hwmod,
4103         .clk            = "l3_div_ck",
4104         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4105 };
4106
4107 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4108         {
4109                 .pa_start       = 0x56000000,
4110                 .pa_end         = 0x5600ffff,
4111                 .flags          = ADDR_TYPE_RT
4112         },
4113         { }
4114 };
4115
4116 /* l3_main_2 -> gpu */
4117 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4118         .master         = &omap44xx_l3_main_2_hwmod,
4119         .slave          = &omap44xx_gpu_hwmod,
4120         .clk            = "l3_div_ck",
4121         .addr           = omap44xx_gpu_addrs,
4122         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4123 };
4124
4125 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4126         {
4127                 .pa_start       = 0x480b2000,
4128                 .pa_end         = 0x480b201f,
4129                 .flags          = ADDR_TYPE_RT
4130         },
4131         { }
4132 };
4133
4134 /* l4_per -> hdq1w */
4135 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4136         .master         = &omap44xx_l4_per_hwmod,
4137         .slave          = &omap44xx_hdq1w_hwmod,
4138         .clk            = "l4_div_ck",
4139         .addr           = omap44xx_hdq1w_addrs,
4140         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4141 };
4142
4143 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4144         {
4145                 .pa_start       = 0x4a058000,
4146                 .pa_end         = 0x4a05bfff,
4147                 .flags          = ADDR_TYPE_RT
4148         },
4149         { }
4150 };
4151
4152 /* l4_cfg -> hsi */
4153 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4154         .master         = &omap44xx_l4_cfg_hwmod,
4155         .slave          = &omap44xx_hsi_hwmod,
4156         .clk            = "l4_div_ck",
4157         .addr           = omap44xx_hsi_addrs,
4158         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4159 };
4160
4161 /* l4_per -> i2c1 */
4162 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4163         .master         = &omap44xx_l4_per_hwmod,
4164         .slave          = &omap44xx_i2c1_hwmod,
4165         .clk            = "l4_div_ck",
4166         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4167 };
4168
4169 /* l4_per -> i2c2 */
4170 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
4171         .master         = &omap44xx_l4_per_hwmod,
4172         .slave          = &omap44xx_i2c2_hwmod,
4173         .clk            = "l4_div_ck",
4174         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4175 };
4176
4177 /* l4_per -> i2c3 */
4178 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
4179         .master         = &omap44xx_l4_per_hwmod,
4180         .slave          = &omap44xx_i2c3_hwmod,
4181         .clk            = "l4_div_ck",
4182         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4183 };
4184
4185 /* l4_per -> i2c4 */
4186 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
4187         .master         = &omap44xx_l4_per_hwmod,
4188         .slave          = &omap44xx_i2c4_hwmod,
4189         .clk            = "l4_div_ck",
4190         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4191 };
4192
4193 /* l3_main_2 -> ipu */
4194 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
4195         .master         = &omap44xx_l3_main_2_hwmod,
4196         .slave          = &omap44xx_ipu_hwmod,
4197         .clk            = "l3_div_ck",
4198         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4199 };
4200
4201 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
4202         {
4203                 .pa_start       = 0x52000000,
4204                 .pa_end         = 0x520000ff,
4205                 .flags          = ADDR_TYPE_RT
4206         },
4207         { }
4208 };
4209
4210 /* l3_main_2 -> iss */
4211 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
4212         .master         = &omap44xx_l3_main_2_hwmod,
4213         .slave          = &omap44xx_iss_hwmod,
4214         .clk            = "l3_div_ck",
4215         .addr           = omap44xx_iss_addrs,
4216         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4217 };
4218
4219 /* iva -> sl2if */
4220 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
4221         .master         = &omap44xx_iva_hwmod,
4222         .slave          = &omap44xx_sl2if_hwmod,
4223         .clk            = "dpll_iva_m5x2_ck",
4224         .user           = OCP_USER_IVA,
4225 };
4226
4227 /* l3_main_2 -> iva */
4228 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
4229         .master         = &omap44xx_l3_main_2_hwmod,
4230         .slave          = &omap44xx_iva_hwmod,
4231         .clk            = "l3_div_ck",
4232         .user           = OCP_USER_MPU,
4233 };
4234
4235 /* l4_wkup -> kbd */
4236 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
4237         .master         = &omap44xx_l4_wkup_hwmod,
4238         .slave          = &omap44xx_kbd_hwmod,
4239         .clk            = "l4_wkup_clk_mux_ck",
4240         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4241 };
4242
4243 /* l4_cfg -> mailbox */
4244 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
4245         .master         = &omap44xx_l4_cfg_hwmod,
4246         .slave          = &omap44xx_mailbox_hwmod,
4247         .clk            = "l4_div_ck",
4248         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4249 };
4250
4251 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
4252         {
4253                 .pa_start       = 0x40128000,
4254                 .pa_end         = 0x401283ff,
4255                 .flags          = ADDR_TYPE_RT
4256         },
4257         { }
4258 };
4259
4260 /* l4_abe -> mcasp */
4261 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
4262         .master         = &omap44xx_l4_abe_hwmod,
4263         .slave          = &omap44xx_mcasp_hwmod,
4264         .clk            = "ocp_abe_iclk",
4265         .addr           = omap44xx_mcasp_addrs,
4266         .user           = OCP_USER_MPU,
4267 };
4268
4269 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
4270         {
4271                 .pa_start       = 0x49028000,
4272                 .pa_end         = 0x490283ff,
4273                 .flags          = ADDR_TYPE_RT
4274         },
4275         { }
4276 };
4277
4278 /* l4_abe -> mcasp (dma) */
4279 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
4280         .master         = &omap44xx_l4_abe_hwmod,
4281         .slave          = &omap44xx_mcasp_hwmod,
4282         .clk            = "ocp_abe_iclk",
4283         .addr           = omap44xx_mcasp_dma_addrs,
4284         .user           = OCP_USER_SDMA,
4285 };
4286
4287 /* l4_abe -> mcbsp1 */
4288 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
4289         .master         = &omap44xx_l4_abe_hwmod,
4290         .slave          = &omap44xx_mcbsp1_hwmod,
4291         .clk            = "ocp_abe_iclk",
4292         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4293 };
4294
4295 /* l4_abe -> mcbsp2 */
4296 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
4297         .master         = &omap44xx_l4_abe_hwmod,
4298         .slave          = &omap44xx_mcbsp2_hwmod,
4299         .clk            = "ocp_abe_iclk",
4300         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4301 };
4302
4303 /* l4_abe -> mcbsp3 */
4304 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
4305         .master         = &omap44xx_l4_abe_hwmod,
4306         .slave          = &omap44xx_mcbsp3_hwmod,
4307         .clk            = "ocp_abe_iclk",
4308         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4309 };
4310
4311 /* l4_per -> mcbsp4 */
4312 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
4313         .master         = &omap44xx_l4_per_hwmod,
4314         .slave          = &omap44xx_mcbsp4_hwmod,
4315         .clk            = "l4_div_ck",
4316         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4317 };
4318
4319 /* l4_abe -> mcpdm */
4320 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
4321         .master         = &omap44xx_l4_abe_hwmod,
4322         .slave          = &omap44xx_mcpdm_hwmod,
4323         .clk            = "ocp_abe_iclk",
4324         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4325 };
4326
4327 /* l4_per -> mcspi1 */
4328 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
4329         .master         = &omap44xx_l4_per_hwmod,
4330         .slave          = &omap44xx_mcspi1_hwmod,
4331         .clk            = "l4_div_ck",
4332         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4333 };
4334
4335 /* l4_per -> mcspi2 */
4336 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
4337         .master         = &omap44xx_l4_per_hwmod,
4338         .slave          = &omap44xx_mcspi2_hwmod,
4339         .clk            = "l4_div_ck",
4340         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4341 };
4342
4343 /* l4_per -> mcspi3 */
4344 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
4345         .master         = &omap44xx_l4_per_hwmod,
4346         .slave          = &omap44xx_mcspi3_hwmod,
4347         .clk            = "l4_div_ck",
4348         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4349 };
4350
4351 /* l4_per -> mcspi4 */
4352 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
4353         .master         = &omap44xx_l4_per_hwmod,
4354         .slave          = &omap44xx_mcspi4_hwmod,
4355         .clk            = "l4_div_ck",
4356         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4357 };
4358
4359 /* l4_per -> mmc1 */
4360 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
4361         .master         = &omap44xx_l4_per_hwmod,
4362         .slave          = &omap44xx_mmc1_hwmod,
4363         .clk            = "l4_div_ck",
4364         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4365 };
4366
4367 /* l4_per -> mmc2 */
4368 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
4369         .master         = &omap44xx_l4_per_hwmod,
4370         .slave          = &omap44xx_mmc2_hwmod,
4371         .clk            = "l4_div_ck",
4372         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4373 };
4374
4375 /* l4_per -> mmc3 */
4376 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
4377         .master         = &omap44xx_l4_per_hwmod,
4378         .slave          = &omap44xx_mmc3_hwmod,
4379         .clk            = "l4_div_ck",
4380         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4381 };
4382
4383 /* l4_per -> mmc4 */
4384 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
4385         .master         = &omap44xx_l4_per_hwmod,
4386         .slave          = &omap44xx_mmc4_hwmod,
4387         .clk            = "l4_div_ck",
4388         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4389 };
4390
4391 /* l4_per -> mmc5 */
4392 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
4393         .master         = &omap44xx_l4_per_hwmod,
4394         .slave          = &omap44xx_mmc5_hwmod,
4395         .clk            = "l4_div_ck",
4396         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4397 };
4398
4399 /* l3_main_2 -> ocmc_ram */
4400 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
4401         .master         = &omap44xx_l3_main_2_hwmod,
4402         .slave          = &omap44xx_ocmc_ram_hwmod,
4403         .clk            = "l3_div_ck",
4404         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4405 };
4406
4407 /* l4_cfg -> ocp2scp_usb_phy */
4408 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
4409         .master         = &omap44xx_l4_cfg_hwmod,
4410         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
4411         .clk            = "l4_div_ck",
4412         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4413 };
4414
4415 /* mpu_private -> prcm_mpu */
4416 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
4417         .master         = &omap44xx_mpu_private_hwmod,
4418         .slave          = &omap44xx_prcm_mpu_hwmod,
4419         .clk            = "l3_div_ck",
4420         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4421 };
4422
4423 /* l4_wkup -> cm_core_aon */
4424 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
4425         .master         = &omap44xx_l4_wkup_hwmod,
4426         .slave          = &omap44xx_cm_core_aon_hwmod,
4427         .clk            = "l4_wkup_clk_mux_ck",
4428         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4429 };
4430
4431 /* l4_cfg -> cm_core */
4432 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
4433         .master         = &omap44xx_l4_cfg_hwmod,
4434         .slave          = &omap44xx_cm_core_hwmod,
4435         .clk            = "l4_div_ck",
4436         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4437 };
4438
4439 /* l4_wkup -> prm */
4440 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
4441         .master         = &omap44xx_l4_wkup_hwmod,
4442         .slave          = &omap44xx_prm_hwmod,
4443         .clk            = "l4_wkup_clk_mux_ck",
4444         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4445 };
4446
4447 /* l4_wkup -> scrm */
4448 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
4449         .master         = &omap44xx_l4_wkup_hwmod,
4450         .slave          = &omap44xx_scrm_hwmod,
4451         .clk            = "l4_wkup_clk_mux_ck",
4452         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4453 };
4454
4455 /* l3_main_2 -> sl2if */
4456 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
4457         .master         = &omap44xx_l3_main_2_hwmod,
4458         .slave          = &omap44xx_sl2if_hwmod,
4459         .clk            = "l3_div_ck",
4460         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4461 };
4462
4463 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
4464         {
4465                 .pa_start       = 0x4012c000,
4466                 .pa_end         = 0x4012c3ff,
4467                 .flags          = ADDR_TYPE_RT
4468         },
4469         { }
4470 };
4471
4472 /* l4_abe -> slimbus1 */
4473 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
4474         .master         = &omap44xx_l4_abe_hwmod,
4475         .slave          = &omap44xx_slimbus1_hwmod,
4476         .clk            = "ocp_abe_iclk",
4477         .addr           = omap44xx_slimbus1_addrs,
4478         .user           = OCP_USER_MPU,
4479 };
4480
4481 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
4482         {
4483                 .pa_start       = 0x4902c000,
4484                 .pa_end         = 0x4902c3ff,
4485                 .flags          = ADDR_TYPE_RT
4486         },
4487         { }
4488 };
4489
4490 /* l4_abe -> slimbus1 (dma) */
4491 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
4492         .master         = &omap44xx_l4_abe_hwmod,
4493         .slave          = &omap44xx_slimbus1_hwmod,
4494         .clk            = "ocp_abe_iclk",
4495         .addr           = omap44xx_slimbus1_dma_addrs,
4496         .user           = OCP_USER_SDMA,
4497 };
4498
4499 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
4500         {
4501                 .pa_start       = 0x48076000,
4502                 .pa_end         = 0x480763ff,
4503                 .flags          = ADDR_TYPE_RT
4504         },
4505         { }
4506 };
4507
4508 /* l4_per -> slimbus2 */
4509 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
4510         .master         = &omap44xx_l4_per_hwmod,
4511         .slave          = &omap44xx_slimbus2_hwmod,
4512         .clk            = "l4_div_ck",
4513         .addr           = omap44xx_slimbus2_addrs,
4514         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4515 };
4516
4517 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
4518         {
4519                 .pa_start       = 0x4a0dd000,
4520                 .pa_end         = 0x4a0dd03f,
4521                 .flags          = ADDR_TYPE_RT
4522         },
4523         { }
4524 };
4525
4526 /* l4_cfg -> smartreflex_core */
4527 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
4528         .master         = &omap44xx_l4_cfg_hwmod,
4529         .slave          = &omap44xx_smartreflex_core_hwmod,
4530         .clk            = "l4_div_ck",
4531         .addr           = omap44xx_smartreflex_core_addrs,
4532         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4533 };
4534
4535 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
4536         {
4537                 .pa_start       = 0x4a0db000,
4538                 .pa_end         = 0x4a0db03f,
4539                 .flags          = ADDR_TYPE_RT
4540         },
4541         { }
4542 };
4543
4544 /* l4_cfg -> smartreflex_iva */
4545 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
4546         .master         = &omap44xx_l4_cfg_hwmod,
4547         .slave          = &omap44xx_smartreflex_iva_hwmod,
4548         .clk            = "l4_div_ck",
4549         .addr           = omap44xx_smartreflex_iva_addrs,
4550         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4551 };
4552
4553 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
4554         {
4555                 .pa_start       = 0x4a0d9000,
4556                 .pa_end         = 0x4a0d903f,
4557                 .flags          = ADDR_TYPE_RT
4558         },
4559         { }
4560 };
4561
4562 /* l4_cfg -> smartreflex_mpu */
4563 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
4564         .master         = &omap44xx_l4_cfg_hwmod,
4565         .slave          = &omap44xx_smartreflex_mpu_hwmod,
4566         .clk            = "l4_div_ck",
4567         .addr           = omap44xx_smartreflex_mpu_addrs,
4568         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4569 };
4570
4571 /* l4_cfg -> spinlock */
4572 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
4573         .master         = &omap44xx_l4_cfg_hwmod,
4574         .slave          = &omap44xx_spinlock_hwmod,
4575         .clk            = "l4_div_ck",
4576         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4577 };
4578
4579 /* l4_wkup -> timer1 */
4580 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4581         .master         = &omap44xx_l4_wkup_hwmod,
4582         .slave          = &omap44xx_timer1_hwmod,
4583         .clk            = "l4_wkup_clk_mux_ck",
4584         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4585 };
4586
4587 /* l4_per -> timer2 */
4588 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4589         .master         = &omap44xx_l4_per_hwmod,
4590         .slave          = &omap44xx_timer2_hwmod,
4591         .clk            = "l4_div_ck",
4592         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4593 };
4594
4595 /* l4_per -> timer3 */
4596 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4597         .master         = &omap44xx_l4_per_hwmod,
4598         .slave          = &omap44xx_timer3_hwmod,
4599         .clk            = "l4_div_ck",
4600         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4601 };
4602
4603 /* l4_per -> timer4 */
4604 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4605         .master         = &omap44xx_l4_per_hwmod,
4606         .slave          = &omap44xx_timer4_hwmod,
4607         .clk            = "l4_div_ck",
4608         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4609 };
4610
4611 /* l4_abe -> timer5 */
4612 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4613         .master         = &omap44xx_l4_abe_hwmod,
4614         .slave          = &omap44xx_timer5_hwmod,
4615         .clk            = "ocp_abe_iclk",
4616         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4617 };
4618
4619 /* l4_abe -> timer6 */
4620 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4621         .master         = &omap44xx_l4_abe_hwmod,
4622         .slave          = &omap44xx_timer6_hwmod,
4623         .clk            = "ocp_abe_iclk",
4624         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4625 };
4626
4627 /* l4_abe -> timer7 */
4628 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4629         .master         = &omap44xx_l4_abe_hwmod,
4630         .slave          = &omap44xx_timer7_hwmod,
4631         .clk            = "ocp_abe_iclk",
4632         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4633 };
4634
4635 /* l4_abe -> timer8 */
4636 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4637         .master         = &omap44xx_l4_abe_hwmod,
4638         .slave          = &omap44xx_timer8_hwmod,
4639         .clk            = "ocp_abe_iclk",
4640         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4641 };
4642
4643 /* l4_per -> timer9 */
4644 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4645         .master         = &omap44xx_l4_per_hwmod,
4646         .slave          = &omap44xx_timer9_hwmod,
4647         .clk            = "l4_div_ck",
4648         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4649 };
4650
4651 /* l4_per -> timer10 */
4652 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4653         .master         = &omap44xx_l4_per_hwmod,
4654         .slave          = &omap44xx_timer10_hwmod,
4655         .clk            = "l4_div_ck",
4656         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4657 };
4658
4659 /* l4_per -> timer11 */
4660 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4661         .master         = &omap44xx_l4_per_hwmod,
4662         .slave          = &omap44xx_timer11_hwmod,
4663         .clk            = "l4_div_ck",
4664         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4665 };
4666
4667 /* l4_per -> uart1 */
4668 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4669         .master         = &omap44xx_l4_per_hwmod,
4670         .slave          = &omap44xx_uart1_hwmod,
4671         .clk            = "l4_div_ck",
4672         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4673 };
4674
4675 /* l4_per -> uart2 */
4676 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4677         .master         = &omap44xx_l4_per_hwmod,
4678         .slave          = &omap44xx_uart2_hwmod,
4679         .clk            = "l4_div_ck",
4680         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4681 };
4682
4683 /* l4_per -> uart3 */
4684 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4685         .master         = &omap44xx_l4_per_hwmod,
4686         .slave          = &omap44xx_uart3_hwmod,
4687         .clk            = "l4_div_ck",
4688         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4689 };
4690
4691 /* l4_per -> uart4 */
4692 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
4693         .master         = &omap44xx_l4_per_hwmod,
4694         .slave          = &omap44xx_uart4_hwmod,
4695         .clk            = "l4_div_ck",
4696         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4697 };
4698
4699 /* l4_cfg -> usb_host_fs */
4700 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
4701         .master         = &omap44xx_l4_cfg_hwmod,
4702         .slave          = &omap44xx_usb_host_fs_hwmod,
4703         .clk            = "l4_div_ck",
4704         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4705 };
4706
4707 /* l4_cfg -> usb_host_hs */
4708 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
4709         .master         = &omap44xx_l4_cfg_hwmod,
4710         .slave          = &omap44xx_usb_host_hs_hwmod,
4711         .clk            = "l4_div_ck",
4712         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4713 };
4714
4715 /* l4_cfg -> usb_otg_hs */
4716 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4717         .master         = &omap44xx_l4_cfg_hwmod,
4718         .slave          = &omap44xx_usb_otg_hs_hwmod,
4719         .clk            = "l4_div_ck",
4720         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4721 };
4722
4723 /* l4_cfg -> usb_tll_hs */
4724 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
4725         .master         = &omap44xx_l4_cfg_hwmod,
4726         .slave          = &omap44xx_usb_tll_hs_hwmod,
4727         .clk            = "l4_div_ck",
4728         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4729 };
4730
4731 /* l4_wkup -> wd_timer2 */
4732 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
4733         .master         = &omap44xx_l4_wkup_hwmod,
4734         .slave          = &omap44xx_wd_timer2_hwmod,
4735         .clk            = "l4_wkup_clk_mux_ck",
4736         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4737 };
4738
4739 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
4740         {
4741                 .pa_start       = 0x40130000,
4742                 .pa_end         = 0x4013007f,
4743                 .flags          = ADDR_TYPE_RT
4744         },
4745         { }
4746 };
4747
4748 /* l4_abe -> wd_timer3 */
4749 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
4750         .master         = &omap44xx_l4_abe_hwmod,
4751         .slave          = &omap44xx_wd_timer3_hwmod,
4752         .clk            = "ocp_abe_iclk",
4753         .addr           = omap44xx_wd_timer3_addrs,
4754         .user           = OCP_USER_MPU,
4755 };
4756
4757 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
4758         {
4759                 .pa_start       = 0x49030000,
4760                 .pa_end         = 0x4903007f,
4761                 .flags          = ADDR_TYPE_RT
4762         },
4763         { }
4764 };
4765
4766 /* l4_abe -> wd_timer3 (dma) */
4767 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
4768         .master         = &omap44xx_l4_abe_hwmod,
4769         .slave          = &omap44xx_wd_timer3_hwmod,
4770         .clk            = "ocp_abe_iclk",
4771         .addr           = omap44xx_wd_timer3_dma_addrs,
4772         .user           = OCP_USER_SDMA,
4773 };
4774
4775 /* mpu -> emif1 */
4776 static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
4777         .master         = &omap44xx_mpu_hwmod,
4778         .slave          = &omap44xx_emif1_hwmod,
4779         .clk            = "l3_div_ck",
4780         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4781 };
4782
4783 /* mpu -> emif2 */
4784 static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
4785         .master         = &omap44xx_mpu_hwmod,
4786         .slave          = &omap44xx_emif2_hwmod,
4787         .clk            = "l3_div_ck",
4788         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4789 };
4790
4791 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
4792         &omap44xx_l3_main_1__dmm,
4793         &omap44xx_mpu__dmm,
4794         &omap44xx_iva__l3_instr,
4795         &omap44xx_l3_main_3__l3_instr,
4796         &omap44xx_ocp_wp_noc__l3_instr,
4797         &omap44xx_dsp__l3_main_1,
4798         &omap44xx_dss__l3_main_1,
4799         &omap44xx_l3_main_2__l3_main_1,
4800         &omap44xx_l4_cfg__l3_main_1,
4801         &omap44xx_mmc1__l3_main_1,
4802         &omap44xx_mmc2__l3_main_1,
4803         &omap44xx_mpu__l3_main_1,
4804         &omap44xx_debugss__l3_main_2,
4805         &omap44xx_dma_system__l3_main_2,
4806         &omap44xx_fdif__l3_main_2,
4807         &omap44xx_gpu__l3_main_2,
4808         &omap44xx_hsi__l3_main_2,
4809         &omap44xx_ipu__l3_main_2,
4810         &omap44xx_iss__l3_main_2,
4811         &omap44xx_iva__l3_main_2,
4812         &omap44xx_l3_main_1__l3_main_2,
4813         &omap44xx_l4_cfg__l3_main_2,
4814         /* &omap44xx_usb_host_fs__l3_main_2, */
4815         &omap44xx_usb_host_hs__l3_main_2,
4816         &omap44xx_usb_otg_hs__l3_main_2,
4817         &omap44xx_l3_main_1__l3_main_3,
4818         &omap44xx_l3_main_2__l3_main_3,
4819         &omap44xx_l4_cfg__l3_main_3,
4820         &omap44xx_aess__l4_abe,
4821         &omap44xx_dsp__l4_abe,
4822         &omap44xx_l3_main_1__l4_abe,
4823         &omap44xx_mpu__l4_abe,
4824         &omap44xx_l3_main_1__l4_cfg,
4825         &omap44xx_l3_main_2__l4_per,
4826         &omap44xx_l4_cfg__l4_wkup,
4827         &omap44xx_mpu__mpu_private,
4828         &omap44xx_l4_cfg__ocp_wp_noc,
4829         &omap44xx_l4_abe__aess,
4830         &omap44xx_l4_abe__aess_dma,
4831         &omap44xx_l3_main_2__c2c,
4832         &omap44xx_l4_wkup__counter_32k,
4833         &omap44xx_l4_cfg__ctrl_module_core,
4834         &omap44xx_l4_cfg__ctrl_module_pad_core,
4835         &omap44xx_l4_wkup__ctrl_module_wkup,
4836         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
4837         &omap44xx_l3_instr__debugss,
4838         &omap44xx_l4_cfg__dma_system,
4839         &omap44xx_l4_abe__dmic,
4840         &omap44xx_dsp__iva,
4841         /* &omap44xx_dsp__sl2if, */
4842         &omap44xx_l4_cfg__dsp,
4843         &omap44xx_l3_main_2__dss,
4844         &omap44xx_l4_per__dss,
4845         &omap44xx_l3_main_2__dss_dispc,
4846         &omap44xx_l4_per__dss_dispc,
4847         &omap44xx_l3_main_2__dss_dsi1,
4848         &omap44xx_l4_per__dss_dsi1,
4849         &omap44xx_l3_main_2__dss_dsi2,
4850         &omap44xx_l4_per__dss_dsi2,
4851         &omap44xx_l3_main_2__dss_hdmi,
4852         &omap44xx_l4_per__dss_hdmi,
4853         &omap44xx_l3_main_2__dss_rfbi,
4854         &omap44xx_l4_per__dss_rfbi,
4855         &omap44xx_l3_main_2__dss_venc,
4856         &omap44xx_l4_per__dss_venc,
4857         &omap44xx_l4_per__elm,
4858         &omap44xx_l4_cfg__fdif,
4859         &omap44xx_l4_wkup__gpio1,
4860         &omap44xx_l4_per__gpio2,
4861         &omap44xx_l4_per__gpio3,
4862         &omap44xx_l4_per__gpio4,
4863         &omap44xx_l4_per__gpio5,
4864         &omap44xx_l4_per__gpio6,
4865         &omap44xx_l3_main_2__gpmc,
4866         &omap44xx_l3_main_2__gpu,
4867         &omap44xx_l4_per__hdq1w,
4868         &omap44xx_l4_cfg__hsi,
4869         &omap44xx_l4_per__i2c1,
4870         &omap44xx_l4_per__i2c2,
4871         &omap44xx_l4_per__i2c3,
4872         &omap44xx_l4_per__i2c4,
4873         &omap44xx_l3_main_2__ipu,
4874         &omap44xx_l3_main_2__iss,
4875         /* &omap44xx_iva__sl2if, */
4876         &omap44xx_l3_main_2__iva,
4877         &omap44xx_l4_wkup__kbd,
4878         &omap44xx_l4_cfg__mailbox,
4879         &omap44xx_l4_abe__mcasp,
4880         &omap44xx_l4_abe__mcasp_dma,
4881         &omap44xx_l4_abe__mcbsp1,
4882         &omap44xx_l4_abe__mcbsp2,
4883         &omap44xx_l4_abe__mcbsp3,
4884         &omap44xx_l4_per__mcbsp4,
4885         &omap44xx_l4_abe__mcpdm,
4886         &omap44xx_l4_per__mcspi1,
4887         &omap44xx_l4_per__mcspi2,
4888         &omap44xx_l4_per__mcspi3,
4889         &omap44xx_l4_per__mcspi4,
4890         &omap44xx_l4_per__mmc1,
4891         &omap44xx_l4_per__mmc2,
4892         &omap44xx_l4_per__mmc3,
4893         &omap44xx_l4_per__mmc4,
4894         &omap44xx_l4_per__mmc5,
4895         &omap44xx_l3_main_2__mmu_ipu,
4896         &omap44xx_l4_cfg__mmu_dsp,
4897         &omap44xx_l3_main_2__ocmc_ram,
4898         &omap44xx_l4_cfg__ocp2scp_usb_phy,
4899         &omap44xx_mpu_private__prcm_mpu,
4900         &omap44xx_l4_wkup__cm_core_aon,
4901         &omap44xx_l4_cfg__cm_core,
4902         &omap44xx_l4_wkup__prm,
4903         &omap44xx_l4_wkup__scrm,
4904         /* &omap44xx_l3_main_2__sl2if, */
4905         &omap44xx_l4_abe__slimbus1,
4906         &omap44xx_l4_abe__slimbus1_dma,
4907         &omap44xx_l4_per__slimbus2,
4908         &omap44xx_l4_cfg__smartreflex_core,
4909         &omap44xx_l4_cfg__smartreflex_iva,
4910         &omap44xx_l4_cfg__smartreflex_mpu,
4911         &omap44xx_l4_cfg__spinlock,
4912         &omap44xx_l4_wkup__timer1,
4913         &omap44xx_l4_per__timer2,
4914         &omap44xx_l4_per__timer3,
4915         &omap44xx_l4_per__timer4,
4916         &omap44xx_l4_abe__timer5,
4917         &omap44xx_l4_abe__timer6,
4918         &omap44xx_l4_abe__timer7,
4919         &omap44xx_l4_abe__timer8,
4920         &omap44xx_l4_per__timer9,
4921         &omap44xx_l4_per__timer10,
4922         &omap44xx_l4_per__timer11,
4923         &omap44xx_l4_per__uart1,
4924         &omap44xx_l4_per__uart2,
4925         &omap44xx_l4_per__uart3,
4926         &omap44xx_l4_per__uart4,
4927         /* &omap44xx_l4_cfg__usb_host_fs, */
4928         &omap44xx_l4_cfg__usb_host_hs,
4929         &omap44xx_l4_cfg__usb_otg_hs,
4930         &omap44xx_l4_cfg__usb_tll_hs,
4931         &omap44xx_l4_wkup__wd_timer2,
4932         &omap44xx_l4_abe__wd_timer3,
4933         &omap44xx_l4_abe__wd_timer3_dma,
4934         &omap44xx_mpu__emif1,
4935         &omap44xx_mpu__emif2,
4936         &omap44xx_l3_main_2__aes1,
4937         &omap44xx_l3_main_2__aes2,
4938         &omap44xx_l3_main_2__des,
4939         &omap44xx_l3_main_2__sha0,
4940         NULL,
4941 };
4942
4943 int __init omap44xx_hwmod_init(void)
4944 {
4945         omap_hwmod_init();
4946         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
4947 }
4948