arch/arm/mach-omap2/omap_hwmod_43xx_data.c

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated
   3  *
   4  * Hwmod present only in AM43x and those that differ other than register
   5  * offsets as compared to AM335x.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include "omap_hwmod.h"
  18 #include "omap_hwmod_33xx_43xx_common_data.h"
  19 #include "prcm43xx.h"
  20 #include "omap_hwmod_common_data.h"
  21 #include "hdq1w.h"
  22
  23
  24 /* IP blocks */
  25 static struct omap_hwmod am43xx_emif_hwmod = {
  26         .name           = "emif",
  27         .class          = &am33xx_emif_hwmod_class,
  28         .clkdm_name     = "emif_clkdm",
  29         .flags          = HWMOD_INIT_NO_IDLE,
  30         .main_clk       = "dpll_ddr_m2_ck",
  31         .prcm           = {
  32                 .omap4  = {
  33                         .clkctrl_offs   = AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET,
  34                         .modulemode     = MODULEMODE_SWCTRL,
  35                 },
  36         },
  37 };
  38
  39 static struct omap_hwmod am43xx_l4_hs_hwmod = {
  40         .name           = "l4_hs",
  41         .class          = &am33xx_l4_hwmod_class,
  42         .clkdm_name     = "l3_clkdm",
  43         .flags          = HWMOD_INIT_NO_IDLE,
  44         .main_clk       = "l4hs_gclk",
  45         .prcm           = {
  46                 .omap4  = {
  47                         .clkctrl_offs   = AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET,
  48                         .modulemode     = MODULEMODE_SWCTRL,
  49                 },
  50         },
  51 };
  52
  53 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
  54         { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
  55 };
  56
  57 static struct omap_hwmod am43xx_wkup_m3_hwmod = {
  58         .name           = "wkup_m3",
  59         .class          = &am33xx_wkup_m3_hwmod_class,
  60         .clkdm_name     = "l4_wkup_aon_clkdm",
  61         /* Keep hardreset asserted */
  62         .flags          = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
  63         .main_clk       = "sys_clkin_ck",
  64         .prcm           = {
  65                 .omap4  = {
  66                         .clkctrl_offs   = AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
  67                         .rstctrl_offs   = AM43XX_RM_WKUP_RSTCTRL_OFFSET,
  68                         .rstst_offs     = AM43XX_RM_WKUP_RSTST_OFFSET,
  69                         .modulemode     = MODULEMODE_SWCTRL,
  70                 },
  71         },
  72         .rst_lines      = am33xx_wkup_m3_resets,
  73         .rst_lines_cnt  = ARRAY_SIZE(am33xx_wkup_m3_resets),
  74 };
  75
  76 static struct omap_hwmod am43xx_control_hwmod = {
  77         .name           = "control",
  78         .class          = &am33xx_control_hwmod_class,
  79         .clkdm_name     = "l4_wkup_clkdm",
  80         .flags          = HWMOD_INIT_NO_IDLE,
  81         .main_clk       = "sys_clkin_ck",
  82         .prcm           = {
  83                 .omap4  = {
  84                         .clkctrl_offs   = AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
  85                         .modulemode     = MODULEMODE_SWCTRL,
  86                 },
  87         },
  88 };
  89
  90 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
  91         { .role = "dbclk", .clk = "gpio0_dbclk" },
  92 };
  93
  94 static struct omap_hwmod am43xx_gpio0_hwmod = {
  95         .name           = "gpio1",
  96         .class          = &am33xx_gpio_hwmod_class,
  97         .clkdm_name     = "l4_wkup_clkdm",
  98         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  99         .main_clk       = "sys_clkin_ck",
 100         .prcm           = {
 101                 .omap4  = {
 102                         .clkctrl_offs   = AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
 103                         .modulemode     = MODULEMODE_SWCTRL,
 104                 },
 105         },
 106         .opt_clks       = gpio0_opt_clks,
 107         .opt_clks_cnt   = ARRAY_SIZE(gpio0_opt_clks),
 108 };
 109
 110 static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = {
 111         .rev_offs       = 0x0,
 112         .sysc_offs      = 0x4,
 113         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 114         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 115         .sysc_fields    = &omap_hwmod_sysc_type1,
 116 };
 117
 118 static struct omap_hwmod_class am43xx_synctimer_hwmod_class = {
 119         .name   = "synctimer",
 120         .sysc   = &am43xx_synctimer_sysc,
 121 };
 122
 123 static struct omap_hwmod am43xx_synctimer_hwmod = {
 124         .name           = "counter_32k",
 125         .class          = &am43xx_synctimer_hwmod_class,
 126         .clkdm_name     = "l4_wkup_aon_clkdm",
 127         .flags          = HWMOD_SWSUP_SIDLE,
 128         .main_clk       = "synctimer_32kclk",
 129         .prcm = {
 130                 .omap4 = {
 131                         .clkctrl_offs = AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 132                         .modulemode   = MODULEMODE_SWCTRL,
 133                 },
 134         },
 135 };
 136
 137 static struct omap_hwmod am43xx_timer8_hwmod = {
 138         .name           = "timer8",
 139         .class          = &am33xx_timer_hwmod_class,
 140         .clkdm_name     = "l4ls_clkdm",
 141         .main_clk       = "timer8_fck",
 142         .prcm           = {
 143                 .omap4  = {
 144                         .clkctrl_offs   = AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET,
 145                         .modulemode     = MODULEMODE_SWCTRL,
 146                 },
 147         },
 148 };
 149
 150 static struct omap_hwmod am43xx_timer9_hwmod = {
 151         .name           = "timer9",
 152         .class          = &am33xx_timer_hwmod_class,
 153         .clkdm_name     = "l4ls_clkdm",
 154         .main_clk       = "timer9_fck",
 155         .prcm           = {
 156                 .omap4  = {
 157                         .clkctrl_offs   = AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET,
 158                         .modulemode     = MODULEMODE_SWCTRL,
 159                 },
 160         },
 161 };
 162
 163 static struct omap_hwmod am43xx_timer10_hwmod = {
 164         .name           = "timer10",
 165         .class          = &am33xx_timer_hwmod_class,
 166         .clkdm_name     = "l4ls_clkdm",
 167         .main_clk       = "timer10_fck",
 168         .prcm           = {
 169                 .omap4  = {
 170                         .clkctrl_offs   = AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET,
 171                         .modulemode     = MODULEMODE_SWCTRL,
 172                 },
 173         },
 174 };
 175
 176 static struct omap_hwmod am43xx_timer11_hwmod = {
 177         .name           = "timer11",
 178         .class          = &am33xx_timer_hwmod_class,
 179         .clkdm_name     = "l4ls_clkdm",
 180         .main_clk       = "timer11_fck",
 181         .prcm           = {
 182                 .omap4  = {
 183                         .clkctrl_offs   = AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET,
 184                         .modulemode     = MODULEMODE_SWCTRL,
 185                 },
 186         },
 187 };
 188
 189 static struct omap_hwmod am43xx_epwmss3_hwmod = {
 190         .name           = "epwmss3",
 191         .class          = &am33xx_epwmss_hwmod_class,
 192         .clkdm_name     = "l4ls_clkdm",
 193         .main_clk       = "l4ls_gclk",
 194         .prcm           = {
 195                 .omap4  = {
 196                         .clkctrl_offs = AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET,
 197                         .modulemode   = MODULEMODE_SWCTRL,
 198                 },
 199         },
 200 };
 201
 202 static struct omap_hwmod am43xx_epwmss4_hwmod = {
 203         .name           = "epwmss4",
 204         .class          = &am33xx_epwmss_hwmod_class,
 205         .clkdm_name     = "l4ls_clkdm",
 206         .main_clk       = "l4ls_gclk",
 207         .prcm           = {
 208                 .omap4  = {
 209                         .clkctrl_offs = AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET,
 210                         .modulemode   = MODULEMODE_SWCTRL,
 211                 },
 212         },
 213 };
 214
 215 static struct omap_hwmod am43xx_epwmss5_hwmod = {
 216         .name           = "epwmss5",
 217         .class          = &am33xx_epwmss_hwmod_class,
 218         .clkdm_name     = "l4ls_clkdm",
 219         .main_clk       = "l4ls_gclk",
 220         .prcm           = {
 221                 .omap4  = {
 222                         .clkctrl_offs = AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET,
 223                         .modulemode   = MODULEMODE_SWCTRL,
 224                 },
 225         },
 226 };
 227
 228 static struct omap_hwmod am43xx_spi2_hwmod = {
 229         .name           = "spi2",
 230         .class          = &am33xx_spi_hwmod_class,
 231         .clkdm_name     = "l4ls_clkdm",
 232         .main_clk       = "dpll_per_m2_div4_ck",
 233         .prcm           = {
 234                 .omap4  = {
 235                         .clkctrl_offs = AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET,
 236                         .modulemode   = MODULEMODE_SWCTRL,
 237                 },
 238         },
 239 };
 240
 241 static struct omap_hwmod am43xx_spi3_hwmod = {
 242         .name           = "spi3",
 243         .class          = &am33xx_spi_hwmod_class,
 244         .clkdm_name     = "l4ls_clkdm",
 245         .main_clk       = "dpll_per_m2_div4_ck",
 246         .prcm           = {
 247                 .omap4  = {
 248                         .clkctrl_offs = AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET,
 249                         .modulemode   = MODULEMODE_SWCTRL,
 250                 },
 251         },
 252 };
 253
 254 static struct omap_hwmod am43xx_spi4_hwmod = {
 255         .name           = "spi4",
 256         .class          = &am33xx_spi_hwmod_class,
 257         .clkdm_name     = "l4ls_clkdm",
 258         .main_clk       = "dpll_per_m2_div4_ck",
 259         .prcm           = {
 260                 .omap4  = {
 261                         .clkctrl_offs = AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET,
 262                         .modulemode   = MODULEMODE_SWCTRL,
 263                 },
 264         },
 265 };
 266
 267 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 268         { .role = "dbclk", .clk = "gpio4_dbclk" },
 269 };
 270
 271 static struct omap_hwmod am43xx_gpio4_hwmod = {
 272         .name           = "gpio5",
 273         .class          = &am33xx_gpio_hwmod_class,
 274         .clkdm_name     = "l4ls_clkdm",
 275         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 276         .main_clk       = "l4ls_gclk",
 277         .prcm           = {
 278                 .omap4  = {
 279                         .clkctrl_offs = AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET,
 280                         .modulemode   = MODULEMODE_SWCTRL,
 281                 },
 282         },
 283         .opt_clks       = gpio4_opt_clks,
 284         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 285 };
 286
 287 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 288         { .role = "dbclk", .clk = "gpio5_dbclk" },
 289 };
 290
 291 static struct omap_hwmod am43xx_gpio5_hwmod = {
 292         .name           = "gpio6",
 293         .class          = &am33xx_gpio_hwmod_class,
 294         .clkdm_name     = "l4ls_clkdm",
 295         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 296         .main_clk       = "l4ls_gclk",
 297         .prcm           = {
 298                 .omap4  = {
 299                         .clkctrl_offs = AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET,
 300                         .modulemode   = MODULEMODE_SWCTRL,
 301                 },
 302         },
 303         .opt_clks       = gpio5_opt_clks,
 304         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
 305 };
 306
 307 static struct omap_hwmod_class am43xx_ocp2scp_hwmod_class = {
 308         .name   = "ocp2scp",
 309 };
 310
 311 static struct omap_hwmod am43xx_ocp2scp0_hwmod = {
 312         .name           = "ocp2scp0",
 313         .class          = &am43xx_ocp2scp_hwmod_class,
 314         .clkdm_name     = "l4ls_clkdm",
 315         .main_clk       = "l4ls_gclk",
 316         .prcm = {
 317                 .omap4 = {
 318                         .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET,
 319                         .modulemode   = MODULEMODE_SWCTRL,
 320                 },
 321         },
 322 };
 323
 324 static struct omap_hwmod am43xx_ocp2scp1_hwmod = {
 325         .name           = "ocp2scp1",
 326         .class          = &am43xx_ocp2scp_hwmod_class,
 327         .clkdm_name     = "l4ls_clkdm",
 328         .main_clk       = "l4ls_gclk",
 329         .prcm = {
 330                 .omap4 = {
 331                         .clkctrl_offs   = AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET,
 332                         .modulemode     = MODULEMODE_SWCTRL,
 333                 },
 334         },
 335 };
 336
 337 static struct omap_hwmod_class_sysconfig am43xx_usb_otg_ss_sysc = {
 338         .rev_offs       = 0x0000,
 339         .sysc_offs      = 0x0010,
 340         .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
 341                                 SYSC_HAS_SIDLEMODE),
 342         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 343                                 SIDLE_SMART_WKUP | MSTANDBY_FORCE |
 344                                 MSTANDBY_NO | MSTANDBY_SMART |
 345                                 MSTANDBY_SMART_WKUP),
 346         .sysc_fields    = &omap_hwmod_sysc_type2,
 347 };
 348
 349 static struct omap_hwmod_class am43xx_usb_otg_ss_hwmod_class = {
 350         .name   = "usb_otg_ss",
 351         .sysc   = &am43xx_usb_otg_ss_sysc,
 352 };
 353
 354 static struct omap_hwmod am43xx_usb_otg_ss0_hwmod = {
 355         .name           = "usb_otg_ss0",
 356         .class          = &am43xx_usb_otg_ss_hwmod_class,
 357         .clkdm_name     = "l3s_clkdm",
 358         .main_clk       = "l3s_gclk",
 359         .prcm = {
 360                 .omap4 = {
 361                         .clkctrl_offs   = AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET,
 362                         .modulemode     = MODULEMODE_SWCTRL,
 363                 },
 364         },
 365 };
 366
 367 static struct omap_hwmod am43xx_usb_otg_ss1_hwmod = {
 368         .name           = "usb_otg_ss1",
 369         .class          = &am43xx_usb_otg_ss_hwmod_class,
 370         .clkdm_name     = "l3s_clkdm",
 371         .main_clk       = "l3s_gclk",
 372         .prcm = {
 373                 .omap4 = {
 374                         .clkctrl_offs   = AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET,
 375                         .modulemode     = MODULEMODE_SWCTRL,
 376                 },
 377         },
 378 };
 379
 380 static struct omap_hwmod_class_sysconfig am43xx_qspi_sysc = {
 381         .rev_offs       = 0,
 382         .sysc_offs      = 0x0010,
 383         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 384         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 385                                 SIDLE_SMART_WKUP),
 386         .sysc_fields    = &omap_hwmod_sysc_type2,
 387 };
 388
 389 static struct omap_hwmod_class am43xx_qspi_hwmod_class = {
 390         .name   = "qspi",
 391         .sysc   = &am43xx_qspi_sysc,
 392 };
 393
 394 static struct omap_hwmod am43xx_qspi_hwmod = {
 395         .name           = "qspi",
 396         .class          = &am43xx_qspi_hwmod_class,
 397         .clkdm_name     = "l3s_clkdm",
 398         .main_clk       = "l3s_gclk",
 399         .prcm = {
 400                 .omap4 = {
 401                         .clkctrl_offs = AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET,
 402                         .modulemode   = MODULEMODE_SWCTRL,
 403                 },
 404         },
 405 };
 406
 407 /*
 408  * 'adc/tsc' class
 409  * TouchScreen Controller (Analog-To-Digital Converter)
 410  */
 411 static struct omap_hwmod_class_sysconfig am43xx_adc_tsc_sysc = {
 412         .rev_offs       = 0x00,
 413         .sysc_offs      = 0x10,
 414         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 415         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 416                           SIDLE_SMART_WKUP),
 417         .sysc_fields    = &omap_hwmod_sysc_type2,
 418 };
 419
 420 static struct omap_hwmod_class am43xx_adc_tsc_hwmod_class = {
 421         .name           = "adc_tsc",
 422         .sysc           = &am43xx_adc_tsc_sysc,
 423 };
 424
 425 static struct omap_hwmod am43xx_adc_tsc_hwmod = {
 426         .name           = "adc_tsc",
 427         .class          = &am43xx_adc_tsc_hwmod_class,
 428         .clkdm_name     = "l3s_tsc_clkdm",
 429         .main_clk       = "adc_tsc_fck",
 430         .prcm           = {
 431                 .omap4  = {
 432                         .clkctrl_offs   = AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
 433                         .modulemode     = MODULEMODE_SWCTRL,
 434                 },
 435         },
 436 };
 437
 438 static struct omap_hwmod_class_sysconfig am43xx_des_sysc = {
 439         .rev_offs       = 0x30,
 440         .sysc_offs      = 0x34,
 441         .syss_offs      = 0x38,
 442         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 443 };
 444
 445 static struct omap_hwmod_class am43xx_des_hwmod_class = {
 446         .name           = "des",
 447         .sysc           = &am43xx_des_sysc,
 448 };
 449
 450 static struct omap_hwmod am43xx_des_hwmod = {
 451         .name           = "des",
 452         .class          = &am43xx_des_hwmod_class,
 453         .clkdm_name     = "l3_clkdm",
 454         .main_clk       = "l3_gclk",
 455         .prcm           = {
 456                 .omap4  = {
 457                         .clkctrl_offs   = AM43XX_CM_PER_DES_CLKCTRL_OFFSET,
 458                         .modulemode     = MODULEMODE_SWCTRL,
 459                 },
 460         },
 461 };
 462
 463 /* dss */
 464
 465 static struct omap_hwmod am43xx_dss_core_hwmod = {
 466         .name           = "dss_core",
 467         .class          = &omap2_dss_hwmod_class,
 468         .clkdm_name     = "dss_clkdm",
 469         .main_clk       = "disp_clk",
 470         .prcm = {
 471                 .omap4 = {
 472                         .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
 473                         .modulemode   = MODULEMODE_SWCTRL,
 474                 },
 475         },
 476 };
 477
 478 /* dispc */
 479
 480 static struct omap_dss_dispc_dev_attr am43xx_dss_dispc_dev_attr = {
 481         .manager_count          = 1,
 482         .has_framedonetv_irq    = 0
 483 };
 484
 485 static struct omap_hwmod_class_sysconfig am43xx_dispc_sysc = {
 486         .rev_offs       = 0x0000,
 487         .sysc_offs      = 0x0010,
 488         .syss_offs      = 0x0014,
 489         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
 490                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 491                            SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_MIDLEMODE),
 492         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 493                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 494         .sysc_fields    = &omap_hwmod_sysc_type1,
 495 };
 496
 497 static struct omap_hwmod_class am43xx_dispc_hwmod_class = {
 498         .name   = "dispc",
 499         .sysc   = &am43xx_dispc_sysc,
 500 };
 501
 502 static struct omap_hwmod am43xx_dss_dispc_hwmod = {
 503         .name           = "dss_dispc",
 504         .class          = &am43xx_dispc_hwmod_class,
 505         .clkdm_name     = "dss_clkdm",
 506         .main_clk       = "disp_clk",
 507         .prcm = {
 508                 .omap4 = {
 509                         .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
 510                 },
 511         },
 512         .dev_attr       = &am43xx_dss_dispc_dev_attr,
 513         .parent_hwmod   = &am43xx_dss_core_hwmod,
 514 };
 515
 516 /* rfbi */
 517
 518 static struct omap_hwmod am43xx_dss_rfbi_hwmod = {
 519         .name           = "dss_rfbi",
 520         .class          = &omap2_rfbi_hwmod_class,
 521         .clkdm_name     = "dss_clkdm",
 522         .main_clk       = "disp_clk",
 523         .prcm = {
 524                 .omap4 = {
 525                         .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
 526                 },
 527         },
 528         .parent_hwmod   = &am43xx_dss_core_hwmod,
 529 };
 530
 531 /* HDQ1W */
 532 static struct omap_hwmod_class_sysconfig am43xx_hdq1w_sysc = {
 533         .rev_offs       = 0x0000,
 534         .sysc_offs      = 0x0014,
 535         .syss_offs      = 0x0018,
 536         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 537         .sysc_fields    = &omap_hwmod_sysc_type1,
 538 };
 539
 540 static struct omap_hwmod_class am43xx_hdq1w_hwmod_class = {
 541         .name   = "hdq1w",
 542         .sysc   = &am43xx_hdq1w_sysc,
 543         .reset  = &omap_hdq1w_reset,
 544 };
 545
 546 static struct omap_hwmod am43xx_hdq1w_hwmod = {
 547         .name           = "hdq1w",
 548         .class          = &am43xx_hdq1w_hwmod_class,
 549         .clkdm_name     = "l4ls_clkdm",
 550         .prcm = {
 551                 .omap4 = {
 552                         .clkctrl_offs = AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET,
 553                         .modulemode   = MODULEMODE_SWCTRL,
 554                 },
 555         },
 556 };
 557
 558 static struct omap_hwmod_class_sysconfig am43xx_vpfe_sysc = {
 559         .rev_offs       = 0x0,
 560         .sysc_offs      = 0x104,
 561         .sysc_flags     = SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE,
 562         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 563                                 MSTANDBY_FORCE | MSTANDBY_SMART | MSTANDBY_NO),
 564         .sysc_fields    = &omap_hwmod_sysc_type2,
 565 };
 566
 567 static struct omap_hwmod_class am43xx_vpfe_hwmod_class = {
 568         .name           = "vpfe",
 569         .sysc           = &am43xx_vpfe_sysc,
 570 };
 571
 572 static struct omap_hwmod am43xx_vpfe0_hwmod = {
 573         .name           = "vpfe0",
 574         .class          = &am43xx_vpfe_hwmod_class,
 575         .clkdm_name     = "l3s_clkdm",
 576         .prcm           = {
 577                 .omap4  = {
 578                         .modulemode     = MODULEMODE_SWCTRL,
 579                         .clkctrl_offs   = AM43XX_CM_PER_VPFE0_CLKCTRL_OFFSET,
 580                 },
 581         },
 582 };
 583
 584 static struct omap_hwmod am43xx_vpfe1_hwmod = {
 585         .name           = "vpfe1",
 586         .class          = &am43xx_vpfe_hwmod_class,
 587         .clkdm_name     = "l3s_clkdm",
 588         .prcm           = {
 589                 .omap4  = {
 590                         .modulemode     = MODULEMODE_SWCTRL,
 591                         .clkctrl_offs   = AM43XX_CM_PER_VPFE1_CLKCTRL_OFFSET,
 592                 },
 593         },
 594 };
 595
 596 /* Interfaces */
 597 static struct omap_hwmod_ocp_if am43xx_l3_main__emif = {
 598         .master         = &am33xx_l3_main_hwmod,
 599         .slave          = &am43xx_emif_hwmod,
 600         .clk            = "dpll_core_m4_ck",
 601         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 602 };
 603
 604 static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
 605         .master         = &am33xx_l3_main_hwmod,
 606         .slave          = &am43xx_l4_hs_hwmod,
 607         .clk            = "l3s_gclk",
 608         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 609 };
 610
 611 static struct omap_hwmod_ocp_if am43xx_wkup_m3__l4_wkup = {
 612         .master         = &am43xx_wkup_m3_hwmod,
 613         .slave          = &am33xx_l4_wkup_hwmod,
 614         .clk            = "sys_clkin_ck",
 615         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 616 };
 617
 618 static struct omap_hwmod_ocp_if am43xx_l4_wkup__wkup_m3 = {
 619         .master         = &am33xx_l4_wkup_hwmod,
 620         .slave          = &am43xx_wkup_m3_hwmod,
 621         .clk            = "sys_clkin_ck",
 622         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 623 };
 624
 625 static struct omap_hwmod_ocp_if am43xx_l3_main__pruss = {
 626         .master         = &am33xx_l3_main_hwmod,
 627         .slave          = &am33xx_pruss_hwmod,
 628         .clk            = "dpll_core_m4_ck",
 629         .user           = OCP_USER_MPU,
 630 };
 631
 632 static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex0 = {
 633         .master         = &am33xx_l4_wkup_hwmod,
 634         .slave          = &am33xx_smartreflex0_hwmod,
 635         .clk            = "sys_clkin_ck",
 636         .user           = OCP_USER_MPU,
 637 };
 638
 639 static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex1 = {
 640         .master         = &am33xx_l4_wkup_hwmod,
 641         .slave          = &am33xx_smartreflex1_hwmod,
 642         .clk            = "sys_clkin_ck",
 643         .user           = OCP_USER_MPU,
 644 };
 645
 646 static struct omap_hwmod_ocp_if am43xx_l4_wkup__control = {
 647         .master         = &am33xx_l4_wkup_hwmod,
 648         .slave          = &am43xx_control_hwmod,
 649         .clk            = "sys_clkin_ck",
 650         .user           = OCP_USER_MPU,
 651 };
 652
 653 static struct omap_hwmod_ocp_if am43xx_l4_wkup__i2c1 = {
 654         .master         = &am33xx_l4_wkup_hwmod,
 655         .slave          = &am33xx_i2c1_hwmod,
 656         .clk            = "sys_clkin_ck",
 657         .user           = OCP_USER_MPU,
 658 };
 659
 660 static struct omap_hwmod_ocp_if am43xx_l4_wkup__gpio0 = {
 661         .master         = &am33xx_l4_wkup_hwmod,
 662         .slave          = &am43xx_gpio0_hwmod,
 663         .clk            = "sys_clkin_ck",
 664         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 665 };
 666
 667 static struct omap_hwmod_ocp_if am43xx_l4_wkup__adc_tsc = {
 668         .master         = &am33xx_l4_wkup_hwmod,
 669         .slave          = &am43xx_adc_tsc_hwmod,
 670         .clk            = "dpll_core_m4_div2_ck",
 671         .user           = OCP_USER_MPU,
 672 };
 673
 674 static struct omap_hwmod_ocp_if am43xx_l4_hs__cpgmac0 = {
 675         .master         = &am43xx_l4_hs_hwmod,
 676         .slave          = &am33xx_cpgmac0_hwmod,
 677         .clk            = "cpsw_125mhz_gclk",
 678         .user           = OCP_USER_MPU,
 679 };
 680
 681 static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = {
 682         .master         = &am33xx_l4_wkup_hwmod,
 683         .slave          = &am33xx_timer1_hwmod,
 684         .clk            = "sys_clkin_ck",
 685         .user           = OCP_USER_MPU,
 686 };
 687
 688 static struct omap_hwmod_ocp_if am43xx_l4_wkup__uart1 = {
 689         .master         = &am33xx_l4_wkup_hwmod,
 690         .slave          = &am33xx_uart1_hwmod,
 691         .clk            = "sys_clkin_ck",
 692         .user           = OCP_USER_MPU,
 693 };
 694
 695 static struct omap_hwmod_ocp_if am43xx_l4_wkup__wd_timer1 = {
 696         .master         = &am33xx_l4_wkup_hwmod,
 697         .slave          = &am33xx_wd_timer1_hwmod,
 698         .clk            = "sys_clkin_ck",
 699         .user           = OCP_USER_MPU,
 700 };
 701
 702 static struct omap_hwmod_ocp_if am33xx_l4_wkup__synctimer = {
 703         .master         = &am33xx_l4_wkup_hwmod,
 704         .slave          = &am43xx_synctimer_hwmod,
 705         .clk            = "sys_clkin_ck",
 706         .user           = OCP_USER_MPU,
 707 };
 708
 709 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer8 = {
 710         .master         = &am33xx_l4_ls_hwmod,
 711         .slave          = &am43xx_timer8_hwmod,
 712         .clk            = "l4ls_gclk",
 713         .user           = OCP_USER_MPU,
 714 };
 715
 716 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer9 = {
 717         .master         = &am33xx_l4_ls_hwmod,
 718         .slave          = &am43xx_timer9_hwmod,
 719         .clk            = "l4ls_gclk",
 720         .user           = OCP_USER_MPU,
 721 };
 722
 723 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer10 = {
 724         .master         = &am33xx_l4_ls_hwmod,
 725         .slave          = &am43xx_timer10_hwmod,
 726         .clk            = "l4ls_gclk",
 727         .user           = OCP_USER_MPU,
 728 };
 729
 730 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer11 = {
 731         .master         = &am33xx_l4_ls_hwmod,
 732         .slave          = &am43xx_timer11_hwmod,
 733         .clk            = "l4ls_gclk",
 734         .user           = OCP_USER_MPU,
 735 };
 736
 737 static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss3 = {
 738         .master         = &am33xx_l4_ls_hwmod,
 739         .slave          = &am43xx_epwmss3_hwmod,
 740         .clk            = "l4ls_gclk",
 741         .user           = OCP_USER_MPU,
 742 };
 743
 744 static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = {
 745         .master         = &am33xx_l4_ls_hwmod,
 746         .slave          = &am43xx_epwmss4_hwmod,
 747         .clk            = "l4ls_gclk",
 748         .user           = OCP_USER_MPU,
 749 };
 750
 751 static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = {
 752         .master         = &am33xx_l4_ls_hwmod,
 753         .slave          = &am43xx_epwmss5_hwmod,
 754         .clk            = "l4ls_gclk",
 755         .user           = OCP_USER_MPU,
 756 };
 757
 758 static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi2 = {
 759         .master         = &am33xx_l4_ls_hwmod,
 760         .slave          = &am43xx_spi2_hwmod,
 761         .clk            = "l4ls_gclk",
 762         .user           = OCP_USER_MPU,
 763 };
 764
 765 static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi3 = {
 766         .master         = &am33xx_l4_ls_hwmod,
 767         .slave          = &am43xx_spi3_hwmod,
 768         .clk            = "l4ls_gclk",
 769         .user           = OCP_USER_MPU,
 770 };
 771
 772 static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi4 = {
 773         .master         = &am33xx_l4_ls_hwmod,
 774         .slave          = &am43xx_spi4_hwmod,
 775         .clk            = "l4ls_gclk",
 776         .user           = OCP_USER_MPU,
 777 };
 778
 779 static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio4 = {
 780         .master         = &am33xx_l4_ls_hwmod,
 781         .slave          = &am43xx_gpio4_hwmod,
 782         .clk            = "l4ls_gclk",
 783         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 784 };
 785
 786 static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio5 = {
 787         .master         = &am33xx_l4_ls_hwmod,
 788         .slave          = &am43xx_gpio5_hwmod,
 789         .clk            = "l4ls_gclk",
 790         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 791 };
 792
 793 static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp0 = {
 794         .master         = &am33xx_l4_ls_hwmod,
 795         .slave          = &am43xx_ocp2scp0_hwmod,
 796         .clk            = "l4ls_gclk",
 797         .user           = OCP_USER_MPU,
 798 };
 799
 800 static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp1 = {
 801         .master         = &am33xx_l4_ls_hwmod,
 802         .slave          = &am43xx_ocp2scp1_hwmod,
 803         .clk            = "l4ls_gclk",
 804         .user           = OCP_USER_MPU,
 805 };
 806
 807 static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss0 = {
 808         .master         = &am33xx_l3_s_hwmod,
 809         .slave          = &am43xx_usb_otg_ss0_hwmod,
 810         .clk            = "l3s_gclk",
 811         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 812 };
 813
 814 static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss1 = {
 815         .master         = &am33xx_l3_s_hwmod,
 816         .slave          = &am43xx_usb_otg_ss1_hwmod,
 817         .clk            = "l3s_gclk",
 818         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 819 };
 820
 821 static struct omap_hwmod_ocp_if am43xx_l3_s__qspi = {
 822         .master         = &am33xx_l3_s_hwmod,
 823         .slave          = &am43xx_qspi_hwmod,
 824         .clk            = "l3s_gclk",
 825         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 826 };
 827
 828 static struct omap_hwmod_ocp_if am43xx_dss__l3_main = {
 829         .master         = &am43xx_dss_core_hwmod,
 830         .slave          = &am33xx_l3_main_hwmod,
 831         .clk            = "l3_gclk",
 832         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 833 };
 834
 835 static struct omap_hwmod_ocp_if am43xx_l4_ls__dss = {
 836         .master         = &am33xx_l4_ls_hwmod,
 837         .slave          = &am43xx_dss_core_hwmod,
 838         .clk            = "l4ls_gclk",
 839         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 840 };
 841
 842 static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_dispc = {
 843         .master         = &am33xx_l4_ls_hwmod,
 844         .slave          = &am43xx_dss_dispc_hwmod,
 845         .clk            = "l4ls_gclk",
 846         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 847 };
 848
 849 static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_rfbi = {
 850         .master         = &am33xx_l4_ls_hwmod,
 851         .slave          = &am43xx_dss_rfbi_hwmod,
 852         .clk            = "l4ls_gclk",
 853         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 854 };
 855
 856 static struct omap_hwmod_ocp_if am43xx_l4_ls__hdq1w = {
 857         .master         = &am33xx_l4_ls_hwmod,
 858         .slave          = &am43xx_hdq1w_hwmod,
 859         .clk            = "l4ls_gclk",
 860         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 861 };
 862
 863 static struct omap_hwmod_ocp_if am43xx_l3__vpfe0 = {
 864         .master         = &am43xx_vpfe0_hwmod,
 865         .slave          = &am33xx_l3_main_hwmod,
 866         .clk            = "l3_gclk",
 867         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 868 };
 869
 870 static struct omap_hwmod_ocp_if am43xx_l3__vpfe1 = {
 871         .master         = &am43xx_vpfe1_hwmod,
 872         .slave          = &am33xx_l3_main_hwmod,
 873         .clk            = "l3_gclk",
 874         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 875 };
 876
 877 static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe0 = {
 878         .master         = &am33xx_l4_ls_hwmod,
 879         .slave          = &am43xx_vpfe0_hwmod,
 880         .clk            = "l4ls_gclk",
 881         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 882 };
 883
 884 static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe1 = {
 885         .master         = &am33xx_l4_ls_hwmod,
 886         .slave          = &am43xx_vpfe1_hwmod,
 887         .clk            = "l4ls_gclk",
 888         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 889 };
 890
 891 static struct omap_hwmod_ocp_if am43xx_l3_main__des = {
 892         .master         = &am33xx_l3_main_hwmod,
 893         .slave          = &am43xx_des_hwmod,
 894         .clk            = "l3_gclk",
 895         .user           = OCP_USER_MPU,
 896 };
 897
 898 static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
 899         &am33xx_l4_wkup__synctimer,
 900         &am43xx_l4_ls__timer8,
 901         &am43xx_l4_ls__timer9,
 902         &am43xx_l4_ls__timer10,
 903         &am43xx_l4_ls__timer11,
 904         &am43xx_l4_ls__epwmss3,
 905         &am43xx_l4_ls__epwmss4,
 906         &am43xx_l4_ls__epwmss5,
 907         &am43xx_l4_ls__mcspi2,
 908         &am43xx_l4_ls__mcspi3,
 909         &am43xx_l4_ls__mcspi4,
 910         &am43xx_l4_ls__gpio4,
 911         &am43xx_l4_ls__gpio5,
 912         &am43xx_l3_main__pruss,
 913         &am33xx_mpu__l3_main,
 914         &am33xx_mpu__prcm,
 915         &am33xx_l3_s__l4_ls,
 916         &am33xx_l3_s__l4_wkup,
 917         &am43xx_l3_main__l4_hs,
 918         &am33xx_l3_main__l3_s,
 919         &am33xx_l3_main__l3_instr,
 920         &am33xx_l3_main__gfx,
 921         &am33xx_l3_s__l3_main,
 922         &am43xx_l3_main__emif,
 923         &am33xx_pruss__l3_main,
 924         &am43xx_wkup_m3__l4_wkup,
 925         &am33xx_gfx__l3_main,
 926         &am43xx_l4_wkup__wkup_m3,
 927         &am43xx_l4_wkup__control,
 928         &am43xx_l4_wkup__smartreflex0,
 929         &am43xx_l4_wkup__smartreflex1,
 930         &am43xx_l4_wkup__uart1,
 931         &am43xx_l4_wkup__timer1,
 932         &am43xx_l4_wkup__i2c1,
 933         &am43xx_l4_wkup__gpio0,
 934         &am43xx_l4_wkup__wd_timer1,
 935         &am43xx_l4_wkup__adc_tsc,
 936         &am43xx_l3_s__qspi,
 937         &am33xx_l4_per__dcan0,
 938         &am33xx_l4_per__dcan1,
 939         &am33xx_l4_per__gpio1,
 940         &am33xx_l4_per__gpio2,
 941         &am33xx_l4_per__gpio3,
 942         &am33xx_l4_per__i2c2,
 943         &am33xx_l4_per__i2c3,
 944         &am33xx_l4_per__mailbox,
 945         &am33xx_l4_per__rng,
 946         &am33xx_l4_ls__mcasp0,
 947         &am33xx_l4_ls__mcasp1,
 948         &am33xx_l4_ls__mmc0,
 949         &am33xx_l4_ls__mmc1,
 950         &am33xx_l3_s__mmc2,
 951         &am33xx_l4_ls__timer2,
 952         &am33xx_l4_ls__timer3,
 953         &am33xx_l4_ls__timer4,
 954         &am33xx_l4_ls__timer5,
 955         &am33xx_l4_ls__timer6,
 956         &am33xx_l4_ls__timer7,
 957         &am33xx_l3_main__tpcc,
 958         &am33xx_l4_ls__uart2,
 959         &am33xx_l4_ls__uart3,
 960         &am33xx_l4_ls__uart4,
 961         &am33xx_l4_ls__uart5,
 962         &am33xx_l4_ls__uart6,
 963         &am33xx_l4_ls__spinlock,
 964         &am33xx_l4_ls__elm,
 965         &am33xx_l4_ls__epwmss0,
 966         &am33xx_l4_ls__epwmss1,
 967         &am33xx_l4_ls__epwmss2,
 968         &am33xx_l3_s__gpmc,
 969         &am33xx_l4_ls__mcspi0,
 970         &am33xx_l4_ls__mcspi1,
 971         &am33xx_l3_main__tptc0,
 972         &am33xx_l3_main__tptc1,
 973         &am33xx_l3_main__tptc2,
 974         &am33xx_l3_main__ocmc,
 975         &am43xx_l4_hs__cpgmac0,
 976         &am33xx_cpgmac0__mdio,
 977         &am33xx_l3_main__sha0,
 978         &am33xx_l3_main__aes0,
 979         &am43xx_l3_main__des,
 980         &am43xx_l4_ls__ocp2scp0,
 981         &am43xx_l4_ls__ocp2scp1,
 982         &am43xx_l3_s__usbotgss0,
 983         &am43xx_l3_s__usbotgss1,
 984         &am43xx_dss__l3_main,
 985         &am43xx_l4_ls__dss,
 986         &am43xx_l4_ls__dss_dispc,
 987         &am43xx_l4_ls__dss_rfbi,
 988         &am43xx_l4_ls__hdq1w,
 989         &am43xx_l3__vpfe0,
 990         &am43xx_l3__vpfe1,
 991         &am43xx_l4_ls__vpfe0,
 992         &am43xx_l4_ls__vpfe1,
 993         NULL,
 994 };
 995
 996 static struct omap_hwmod_ocp_if *am43xx_rtc_hwmod_ocp_ifs[] __initdata = {
 997         &am33xx_l4_wkup__rtc,
 998         NULL,
 999 };
1000
1001 int __init am43xx_hwmod_init(void)
1002 {
1003         int ret;
1004
1005         omap_hwmod_am43xx_reg();
1006         omap_hwmod_init();
1007         ret = omap_hwmod_register_links(am43xx_hwmod_ocp_ifs);
1008
1009         if (!ret && of_machine_is_compatible("ti,am4372"))
1010                 ret = omap_hwmod_register_links(am43xx_rtc_hwmod_ocp_ifs);
1011
1012         return ret;
1013 }