arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * The data in this file should be completely autogeneratable from
  12  * the TI hardware database or other technical documentation.
  13  *
  14  * XXX these should be marked initdata for multi-OMAP kernels
  15  */
  16 #include <plat/omap_hwmod.h>
  17 #include <mach/irqs.h>
  18 #include <plat/cpu.h>
  19 #include <plat/dma.h>
  20 #include <plat/serial.h>
  21 #include <plat/l3_3xxx.h>
  22 #include <plat/l4_3xxx.h>
  23 #include <plat/i2c.h>
  24 #include <plat/gpio.h>
  25 #include <plat/mmc.h>
  26 #include <plat/mcbsp.h>
  27 #include <plat/mcspi.h>
  28 #include <plat/dmtimer.h>
  29
  30 #include "omap_hwmod_common_data.h"
  31
  32 #include "prm-regbits-34xx.h"
  33 #include "cm-regbits-34xx.h"
  34 #include "wd_timer.h"
  35 #include <mach/am35xx.h>
  36
  37 /*
  38  * OMAP3xxx hardware module integration data
  39  *
  40  * ALl of the data in this section should be autogeneratable from the
  41  * TI hardware database or other technical documentation.  Data that
  42  * is driver-specific or driver-kernel integration-specific belongs
  43  * elsewhere.
  44  */
  45
  46 static struct omap_hwmod omap3xxx_mpu_hwmod;
  47 static struct omap_hwmod omap3xxx_iva_hwmod;
  48 static struct omap_hwmod omap3xxx_l3_main_hwmod;
  49 static struct omap_hwmod omap3xxx_l4_core_hwmod;
  50 static struct omap_hwmod omap3xxx_l4_per_hwmod;
  51 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
  52 static struct omap_hwmod omap3430es1_dss_core_hwmod;
  53 static struct omap_hwmod omap3xxx_dss_core_hwmod;
  54 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
  55 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
  56 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
  57 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
  58 static struct omap_hwmod omap3xxx_i2c1_hwmod;
  59 static struct omap_hwmod omap3xxx_i2c2_hwmod;
  60 static struct omap_hwmod omap3xxx_i2c3_hwmod;
  61 static struct omap_hwmod omap3xxx_gpio1_hwmod;
  62 static struct omap_hwmod omap3xxx_gpio2_hwmod;
  63 static struct omap_hwmod omap3xxx_gpio3_hwmod;
  64 static struct omap_hwmod omap3xxx_gpio4_hwmod;
  65 static struct omap_hwmod omap3xxx_gpio5_hwmod;
  66 static struct omap_hwmod omap3xxx_gpio6_hwmod;
  67 static struct omap_hwmod omap34xx_sr1_hwmod;
  68 static struct omap_hwmod omap34xx_sr2_hwmod;
  69 static struct omap_hwmod omap34xx_mcspi1;
  70 static struct omap_hwmod omap34xx_mcspi2;
  71 static struct omap_hwmod omap34xx_mcspi3;
  72 static struct omap_hwmod omap34xx_mcspi4;
  73 static struct omap_hwmod omap3xxx_mmc1_hwmod;
  74 static struct omap_hwmod omap3xxx_mmc2_hwmod;
  75 static struct omap_hwmod omap3xxx_mmc3_hwmod;
  76 static struct omap_hwmod am35xx_usbhsotg_hwmod;
  77
  78 static struct omap_hwmod omap3xxx_dma_system_hwmod;
  79
  80 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
  81 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
  82 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
  83 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
  84 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
  85 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
  86 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
  87
  88 /* L3 -> L4_CORE interface */
  89 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
  90         .master = &omap3xxx_l3_main_hwmod,
  91         .slave  = &omap3xxx_l4_core_hwmod,
  92         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  93 };
  94
  95 /* L3 -> L4_PER interface */
  96 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
  97         .master = &omap3xxx_l3_main_hwmod,
  98         .slave  = &omap3xxx_l4_per_hwmod,
  99         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 100 };
 101
 102 /* L3 taret configuration and error log registers */
 103 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
 104         { .irq = INT_34XX_L3_DBG_IRQ },
 105         { .irq = INT_34XX_L3_APP_IRQ },
 106         { .irq = -1 }
 107 };
 108
 109 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
 110         {
 111                 .pa_start       = 0x68000000,
 112                 .pa_end         = 0x6800ffff,
 113                 .flags          = ADDR_TYPE_RT,
 114         },
 115         { }
 116 };
 117
 118 /* MPU -> L3 interface */
 119 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
 120         .master   = &omap3xxx_mpu_hwmod,
 121         .slave    = &omap3xxx_l3_main_hwmod,
 122         .addr     = omap3xxx_l3_main_addrs,
 123         .user   = OCP_USER_MPU,
 124 };
 125
 126 /* Slave interfaces on the L3 interconnect */
 127 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
 128         &omap3xxx_mpu__l3_main,
 129 };
 130
 131 /* DSS -> l3 */
 132 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
 133         .master         = &omap3xxx_dss_core_hwmod,
 134         .slave          = &omap3xxx_l3_main_hwmod,
 135         .fw = {
 136                 .omap2 = {
 137                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
 138                         .flags  = OMAP_FIREWALL_L3,
 139                 }
 140         },
 141         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 142 };
 143
 144 /* Master interfaces on the L3 interconnect */
 145 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
 146         &omap3xxx_l3_main__l4_core,
 147         &omap3xxx_l3_main__l4_per,
 148 };
 149
 150 /* L3 */
 151 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
 152         .name           = "l3_main",
 153         .class          = &l3_hwmod_class,
 154         .mpu_irqs       = omap3xxx_l3_main_irqs,
 155         .masters        = omap3xxx_l3_main_masters,
 156         .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_main_masters),
 157         .slaves         = omap3xxx_l3_main_slaves,
 158         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l3_main_slaves),
 159         .flags          = HWMOD_NO_IDLEST,
 160 };
 161
 162 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
 163 static struct omap_hwmod omap3xxx_uart1_hwmod;
 164 static struct omap_hwmod omap3xxx_uart2_hwmod;
 165 static struct omap_hwmod omap3xxx_uart3_hwmod;
 166 static struct omap_hwmod omap3xxx_uart4_hwmod;
 167 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
 168
 169 /* l3_core -> usbhsotg interface */
 170 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
 171         .master         = &omap3xxx_usbhsotg_hwmod,
 172         .slave          = &omap3xxx_l3_main_hwmod,
 173         .clk            = "core_l3_ick",
 174         .user           = OCP_USER_MPU,
 175 };
 176
 177 /* l3_core -> am35xx_usbhsotg interface */
 178 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
 179         .master         = &am35xx_usbhsotg_hwmod,
 180         .slave          = &omap3xxx_l3_main_hwmod,
 181         .clk            = "core_l3_ick",
 182         .user           = OCP_USER_MPU,
 183 };
 184 /* L4_CORE -> L4_WKUP interface */
 185 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
 186         .master = &omap3xxx_l4_core_hwmod,
 187         .slave  = &omap3xxx_l4_wkup_hwmod,
 188         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 189 };
 190
 191 /* L4 CORE -> MMC1 interface */
 192 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
 193         .master         = &omap3xxx_l4_core_hwmod,
 194         .slave          = &omap3xxx_mmc1_hwmod,
 195         .clk            = "mmchs1_ick",
 196         .addr           = omap2430_mmc1_addr_space,
 197         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 198         .flags          = OMAP_FIREWALL_L4
 199 };
 200
 201 /* L4 CORE -> MMC2 interface */
 202 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
 203         .master         = &omap3xxx_l4_core_hwmod,
 204         .slave          = &omap3xxx_mmc2_hwmod,
 205         .clk            = "mmchs2_ick",
 206         .addr           = omap2430_mmc2_addr_space,
 207         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 208         .flags          = OMAP_FIREWALL_L4
 209 };
 210
 211 /* L4 CORE -> MMC3 interface */
 212 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
 213         {
 214                 .pa_start       = 0x480ad000,
 215                 .pa_end         = 0x480ad1ff,
 216                 .flags          = ADDR_TYPE_RT,
 217         },
 218         { }
 219 };
 220
 221 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
 222         .master         = &omap3xxx_l4_core_hwmod,
 223         .slave          = &omap3xxx_mmc3_hwmod,
 224         .clk            = "mmchs3_ick",
 225         .addr           = omap3xxx_mmc3_addr_space,
 226         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 227         .flags          = OMAP_FIREWALL_L4
 228 };
 229
 230 /* L4 CORE -> UART1 interface */
 231 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
 232         {
 233                 .pa_start       = OMAP3_UART1_BASE,
 234                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
 235                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 236         },
 237         { }
 238 };
 239
 240 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
 241         .master         = &omap3xxx_l4_core_hwmod,
 242         .slave          = &omap3xxx_uart1_hwmod,
 243         .clk            = "uart1_ick",
 244         .addr           = omap3xxx_uart1_addr_space,
 245         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 246 };
 247
 248 /* L4 CORE -> UART2 interface */
 249 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
 250         {
 251                 .pa_start       = OMAP3_UART2_BASE,
 252                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
 253                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 254         },
 255         { }
 256 };
 257
 258 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
 259         .master         = &omap3xxx_l4_core_hwmod,
 260         .slave          = &omap3xxx_uart2_hwmod,
 261         .clk            = "uart2_ick",
 262         .addr           = omap3xxx_uart2_addr_space,
 263         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 264 };
 265
 266 /* L4 PER -> UART3 interface */
 267 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
 268         {
 269                 .pa_start       = OMAP3_UART3_BASE,
 270                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
 271                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 272         },
 273         { }
 274 };
 275
 276 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
 277         .master         = &omap3xxx_l4_per_hwmod,
 278         .slave          = &omap3xxx_uart3_hwmod,
 279         .clk            = "uart3_ick",
 280         .addr           = omap3xxx_uart3_addr_space,
 281         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 282 };
 283
 284 /* L4 PER -> UART4 interface */
 285 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
 286         {
 287                 .pa_start       = OMAP3_UART4_BASE,
 288                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
 289                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 290         },
 291         { }
 292 };
 293
 294 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
 295         .master         = &omap3xxx_l4_per_hwmod,
 296         .slave          = &omap3xxx_uart4_hwmod,
 297         .clk            = "uart4_ick",
 298         .addr           = omap3xxx_uart4_addr_space,
 299         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 300 };
 301
 302 /* L4 CORE -> I2C1 interface */
 303 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
 304         .master         = &omap3xxx_l4_core_hwmod,
 305         .slave          = &omap3xxx_i2c1_hwmod,
 306         .clk            = "i2c1_ick",
 307         .addr           = omap2_i2c1_addr_space,
 308         .fw = {
 309                 .omap2 = {
 310                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
 311                         .l4_prot_group = 7,
 312                         .flags  = OMAP_FIREWALL_L4,
 313                 }
 314         },
 315         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 316 };
 317
 318 /* L4 CORE -> I2C2 interface */
 319 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
 320         .master         = &omap3xxx_l4_core_hwmod,
 321         .slave          = &omap3xxx_i2c2_hwmod,
 322         .clk            = "i2c2_ick",
 323         .addr           = omap2_i2c2_addr_space,
 324         .fw = {
 325                 .omap2 = {
 326                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
 327                         .l4_prot_group = 7,
 328                         .flags = OMAP_FIREWALL_L4,
 329                 }
 330         },
 331         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 332 };
 333
 334 /* L4 CORE -> I2C3 interface */
 335 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
 336         {
 337                 .pa_start       = 0x48060000,
 338                 .pa_end         = 0x48060000 + SZ_128 - 1,
 339                 .flags          = ADDR_TYPE_RT,
 340         },
 341         { }
 342 };
 343
 344 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
 345         .master         = &omap3xxx_l4_core_hwmod,
 346         .slave          = &omap3xxx_i2c3_hwmod,
 347         .clk            = "i2c3_ick",
 348         .addr           = omap3xxx_i2c3_addr_space,
 349         .fw = {
 350                 .omap2 = {
 351                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
 352                         .l4_prot_group = 7,
 353                         .flags = OMAP_FIREWALL_L4,
 354                 }
 355         },
 356         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 357 };
 358
 359 /* L4 CORE -> SR1 interface */
 360 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
 361         {
 362                 .pa_start       = OMAP34XX_SR1_BASE,
 363                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
 364                 .flags          = ADDR_TYPE_RT,
 365         },
 366         { }
 367 };
 368
 369 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
 370         .master         = &omap3xxx_l4_core_hwmod,
 371         .slave          = &omap34xx_sr1_hwmod,
 372         .clk            = "sr_l4_ick",
 373         .addr           = omap3_sr1_addr_space,
 374         .user           = OCP_USER_MPU,
 375 };
 376
 377 /* L4 CORE -> SR1 interface */
 378 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
 379         {
 380                 .pa_start       = OMAP34XX_SR2_BASE,
 381                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
 382                 .flags          = ADDR_TYPE_RT,
 383         },
 384         { }
 385 };
 386
 387 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
 388         .master         = &omap3xxx_l4_core_hwmod,
 389         .slave          = &omap34xx_sr2_hwmod,
 390         .clk            = "sr_l4_ick",
 391         .addr           = omap3_sr2_addr_space,
 392         .user           = OCP_USER_MPU,
 393 };
 394
 395 /*
 396 * usbhsotg interface data
 397 */
 398
 399 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
 400         {
 401                 .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
 402                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
 403                 .flags          = ADDR_TYPE_RT
 404         },
 405         { }
 406 };
 407
 408 /* l4_core -> usbhsotg  */
 409 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
 410         .master         = &omap3xxx_l4_core_hwmod,
 411         .slave          = &omap3xxx_usbhsotg_hwmod,
 412         .clk            = "l4_ick",
 413         .addr           = omap3xxx_usbhsotg_addrs,
 414         .user           = OCP_USER_MPU,
 415 };
 416
 417 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
 418         &omap3xxx_usbhsotg__l3,
 419 };
 420
 421 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
 422         &omap3xxx_l4_core__usbhsotg,
 423 };
 424
 425 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
 426         {
 427                 .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
 428                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
 429                 .flags          = ADDR_TYPE_RT
 430         },
 431         { }
 432 };
 433
 434 /* l4_core -> usbhsotg  */
 435 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
 436         .master         = &omap3xxx_l4_core_hwmod,
 437         .slave          = &am35xx_usbhsotg_hwmod,
 438         .clk            = "l4_ick",
 439         .addr           = am35xx_usbhsotg_addrs,
 440         .user           = OCP_USER_MPU,
 441 };
 442
 443 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
 444         &am35xx_usbhsotg__l3,
 445 };
 446
 447 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
 448         &am35xx_l4_core__usbhsotg,
 449 };
 450 /* Slave interfaces on the L4_CORE interconnect */
 451 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
 452         &omap3xxx_l3_main__l4_core,
 453 };
 454
 455 /* L4 CORE */
 456 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
 457         .name           = "l4_core",
 458         .class          = &l4_hwmod_class,
 459         .slaves         = omap3xxx_l4_core_slaves,
 460         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_core_slaves),
 461         .flags          = HWMOD_NO_IDLEST,
 462 };
 463
 464 /* Slave interfaces on the L4_PER interconnect */
 465 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
 466         &omap3xxx_l3_main__l4_per,
 467 };
 468
 469 /* L4 PER */
 470 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
 471         .name           = "l4_per",
 472         .class          = &l4_hwmod_class,
 473         .slaves         = omap3xxx_l4_per_slaves,
 474         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_per_slaves),
 475         .flags          = HWMOD_NO_IDLEST,
 476 };
 477
 478 /* Slave interfaces on the L4_WKUP interconnect */
 479 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
 480         &omap3xxx_l4_core__l4_wkup,
 481 };
 482
 483 /* L4 WKUP */
 484 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
 485         .name           = "l4_wkup",
 486         .class          = &l4_hwmod_class,
 487         .slaves         = omap3xxx_l4_wkup_slaves,
 488         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
 489         .flags          = HWMOD_NO_IDLEST,
 490 };
 491
 492 /* Master interfaces on the MPU device */
 493 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
 494         &omap3xxx_mpu__l3_main,
 495 };
 496
 497 /* MPU */
 498 static struct omap_hwmod omap3xxx_mpu_hwmod = {
 499         .name           = "mpu",
 500         .class          = &mpu_hwmod_class,
 501         .main_clk       = "arm_fck",
 502         .masters        = omap3xxx_mpu_masters,
 503         .masters_cnt    = ARRAY_SIZE(omap3xxx_mpu_masters),
 504 };
 505
 506 /*
 507  * IVA2_2 interface data
 508  */
 509
 510 /* IVA2 <- L3 interface */
 511 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
 512         .master         = &omap3xxx_l3_main_hwmod,
 513         .slave          = &omap3xxx_iva_hwmod,
 514         .clk            = "iva2_ck",
 515         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 516 };
 517
 518 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
 519         &omap3xxx_l3__iva,
 520 };
 521
 522 /*
 523  * IVA2 (IVA2)
 524  */
 525
 526 static struct omap_hwmod omap3xxx_iva_hwmod = {
 527         .name           = "iva",
 528         .class          = &iva_hwmod_class,
 529         .masters        = omap3xxx_iva_masters,
 530         .masters_cnt    = ARRAY_SIZE(omap3xxx_iva_masters),
 531 };
 532
 533 /* timer class */
 534 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
 535         .rev_offs       = 0x0000,
 536         .sysc_offs      = 0x0010,
 537         .syss_offs      = 0x0014,
 538         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 539                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 540                                 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
 541         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 542         .sysc_fields    = &omap_hwmod_sysc_type1,
 543 };
 544
 545 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
 546         .name = "timer",
 547         .sysc = &omap3xxx_timer_1ms_sysc,
 548         .rev = OMAP_TIMER_IP_VERSION_1,
 549 };
 550
 551 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 552         .rev_offs       = 0x0000,
 553         .sysc_offs      = 0x0010,
 554         .syss_offs      = 0x0014,
 555         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
 556                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 557         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 558         .sysc_fields    = &omap_hwmod_sysc_type1,
 559 };
 560
 561 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 562         .name = "timer",
 563         .sysc = &omap3xxx_timer_sysc,
 564         .rev =  OMAP_TIMER_IP_VERSION_1,
 565 };
 566
 567 /* secure timers dev attribute */
 568 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
 569         .timer_capability       = OMAP_TIMER_SECURE,
 570 };
 571
 572 /* always-on timers dev attribute */
 573 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 574         .timer_capability       = OMAP_TIMER_ALWON,
 575 };
 576
 577 /* pwm timers dev attribute */
 578 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 579         .timer_capability       = OMAP_TIMER_HAS_PWM,
 580 };
 581
 582 /* timer1 */
 583 static struct omap_hwmod omap3xxx_timer1_hwmod;
 584
 585 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
 586         {
 587                 .pa_start       = 0x48318000,
 588                 .pa_end         = 0x48318000 + SZ_1K - 1,
 589                 .flags          = ADDR_TYPE_RT
 590         },
 591         { }
 592 };
 593
 594 /* l4_wkup -> timer1 */
 595 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
 596         .master         = &omap3xxx_l4_wkup_hwmod,
 597         .slave          = &omap3xxx_timer1_hwmod,
 598         .clk            = "gpt1_ick",
 599         .addr           = omap3xxx_timer1_addrs,
 600         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 601 };
 602
 603 /* timer1 slave port */
 604 static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
 605         &omap3xxx_l4_wkup__timer1,
 606 };
 607
 608 /* timer1 hwmod */
 609 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 610         .name           = "timer1",
 611         .mpu_irqs       = omap2_timer1_mpu_irqs,
 612         .main_clk       = "gpt1_fck",
 613         .prcm           = {
 614                 .omap2 = {
 615                         .prcm_reg_id = 1,
 616                         .module_bit = OMAP3430_EN_GPT1_SHIFT,
 617                         .module_offs = WKUP_MOD,
 618                         .idlest_reg_id = 1,
 619                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 620                 },
 621         },
 622         .dev_attr       = &capability_alwon_dev_attr,
 623         .slaves         = omap3xxx_timer1_slaves,
 624         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer1_slaves),
 625         .class          = &omap3xxx_timer_1ms_hwmod_class,
 626 };
 627
 628 /* timer2 */
 629 static struct omap_hwmod omap3xxx_timer2_hwmod;
 630
 631 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
 632         {
 633                 .pa_start       = 0x49032000,
 634                 .pa_end         = 0x49032000 + SZ_1K - 1,
 635                 .flags          = ADDR_TYPE_RT
 636         },
 637         { }
 638 };
 639
 640 /* l4_per -> timer2 */
 641 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
 642         .master         = &omap3xxx_l4_per_hwmod,
 643         .slave          = &omap3xxx_timer2_hwmod,
 644         .clk            = "gpt2_ick",
 645         .addr           = omap3xxx_timer2_addrs,
 646         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 647 };
 648
 649 /* timer2 slave port */
 650 static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
 651         &omap3xxx_l4_per__timer2,
 652 };
 653
 654 /* timer2 hwmod */
 655 static struct omap_hwmod omap3xxx_timer2_hwmod = {
 656         .name           = "timer2",
 657         .mpu_irqs       = omap2_timer2_mpu_irqs,
 658         .main_clk       = "gpt2_fck",
 659         .prcm           = {
 660                 .omap2 = {
 661                         .prcm_reg_id = 1,
 662                         .module_bit = OMAP3430_EN_GPT2_SHIFT,
 663                         .module_offs = OMAP3430_PER_MOD,
 664                         .idlest_reg_id = 1,
 665                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 666                 },
 667         },
 668         .dev_attr       = &capability_alwon_dev_attr,
 669         .slaves         = omap3xxx_timer2_slaves,
 670         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer2_slaves),
 671         .class          = &omap3xxx_timer_1ms_hwmod_class,
 672 };
 673
 674 /* timer3 */
 675 static struct omap_hwmod omap3xxx_timer3_hwmod;
 676
 677 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
 678         {
 679                 .pa_start       = 0x49034000,
 680                 .pa_end         = 0x49034000 + SZ_1K - 1,
 681                 .flags          = ADDR_TYPE_RT
 682         },
 683         { }
 684 };
 685
 686 /* l4_per -> timer3 */
 687 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
 688         .master         = &omap3xxx_l4_per_hwmod,
 689         .slave          = &omap3xxx_timer3_hwmod,
 690         .clk            = "gpt3_ick",
 691         .addr           = omap3xxx_timer3_addrs,
 692         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 693 };
 694
 695 /* timer3 slave port */
 696 static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
 697         &omap3xxx_l4_per__timer3,
 698 };
 699
 700 /* timer3 hwmod */
 701 static struct omap_hwmod omap3xxx_timer3_hwmod = {
 702         .name           = "timer3",
 703         .mpu_irqs       = omap2_timer3_mpu_irqs,
 704         .main_clk       = "gpt3_fck",
 705         .prcm           = {
 706                 .omap2 = {
 707                         .prcm_reg_id = 1,
 708                         .module_bit = OMAP3430_EN_GPT3_SHIFT,
 709                         .module_offs = OMAP3430_PER_MOD,
 710                         .idlest_reg_id = 1,
 711                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 712                 },
 713         },
 714         .dev_attr       = &capability_alwon_dev_attr,
 715         .slaves         = omap3xxx_timer3_slaves,
 716         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer3_slaves),
 717         .class          = &omap3xxx_timer_hwmod_class,
 718 };
 719
 720 /* timer4 */
 721 static struct omap_hwmod omap3xxx_timer4_hwmod;
 722
 723 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
 724         {
 725                 .pa_start       = 0x49036000,
 726                 .pa_end         = 0x49036000 + SZ_1K - 1,
 727                 .flags          = ADDR_TYPE_RT
 728         },
 729         { }
 730 };
 731
 732 /* l4_per -> timer4 */
 733 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
 734         .master         = &omap3xxx_l4_per_hwmod,
 735         .slave          = &omap3xxx_timer4_hwmod,
 736         .clk            = "gpt4_ick",
 737         .addr           = omap3xxx_timer4_addrs,
 738         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 739 };
 740
 741 /* timer4 slave port */
 742 static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
 743         &omap3xxx_l4_per__timer4,
 744 };
 745
 746 /* timer4 hwmod */
 747 static struct omap_hwmod omap3xxx_timer4_hwmod = {
 748         .name           = "timer4",
 749         .mpu_irqs       = omap2_timer4_mpu_irqs,
 750         .main_clk       = "gpt4_fck",
 751         .prcm           = {
 752                 .omap2 = {
 753                         .prcm_reg_id = 1,
 754                         .module_bit = OMAP3430_EN_GPT4_SHIFT,
 755                         .module_offs = OMAP3430_PER_MOD,
 756                         .idlest_reg_id = 1,
 757                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 758                 },
 759         },
 760         .dev_attr       = &capability_alwon_dev_attr,
 761         .slaves         = omap3xxx_timer4_slaves,
 762         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer4_slaves),
 763         .class          = &omap3xxx_timer_hwmod_class,
 764 };
 765
 766 /* timer5 */
 767 static struct omap_hwmod omap3xxx_timer5_hwmod;
 768
 769 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
 770         {
 771                 .pa_start       = 0x49038000,
 772                 .pa_end         = 0x49038000 + SZ_1K - 1,
 773                 .flags          = ADDR_TYPE_RT
 774         },
 775         { }
 776 };
 777
 778 /* l4_per -> timer5 */
 779 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
 780         .master         = &omap3xxx_l4_per_hwmod,
 781         .slave          = &omap3xxx_timer5_hwmod,
 782         .clk            = "gpt5_ick",
 783         .addr           = omap3xxx_timer5_addrs,
 784         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 785 };
 786
 787 /* timer5 slave port */
 788 static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
 789         &omap3xxx_l4_per__timer5,
 790 };
 791
 792 /* timer5 hwmod */
 793 static struct omap_hwmod omap3xxx_timer5_hwmod = {
 794         .name           = "timer5",
 795         .mpu_irqs       = omap2_timer5_mpu_irqs,
 796         .main_clk       = "gpt5_fck",
 797         .prcm           = {
 798                 .omap2 = {
 799                         .prcm_reg_id = 1,
 800                         .module_bit = OMAP3430_EN_GPT5_SHIFT,
 801                         .module_offs = OMAP3430_PER_MOD,
 802                         .idlest_reg_id = 1,
 803                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 804                 },
 805         },
 806         .dev_attr       = &capability_alwon_dev_attr,
 807         .slaves         = omap3xxx_timer5_slaves,
 808         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer5_slaves),
 809         .class          = &omap3xxx_timer_hwmod_class,
 810 };
 811
 812 /* timer6 */
 813 static struct omap_hwmod omap3xxx_timer6_hwmod;
 814
 815 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
 816         {
 817                 .pa_start       = 0x4903A000,
 818                 .pa_end         = 0x4903A000 + SZ_1K - 1,
 819                 .flags          = ADDR_TYPE_RT
 820         },
 821         { }
 822 };
 823
 824 /* l4_per -> timer6 */
 825 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
 826         .master         = &omap3xxx_l4_per_hwmod,
 827         .slave          = &omap3xxx_timer6_hwmod,
 828         .clk            = "gpt6_ick",
 829         .addr           = omap3xxx_timer6_addrs,
 830         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 831 };
 832
 833 /* timer6 slave port */
 834 static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
 835         &omap3xxx_l4_per__timer6,
 836 };
 837
 838 /* timer6 hwmod */
 839 static struct omap_hwmod omap3xxx_timer6_hwmod = {
 840         .name           = "timer6",
 841         .mpu_irqs       = omap2_timer6_mpu_irqs,
 842         .main_clk       = "gpt6_fck",
 843         .prcm           = {
 844                 .omap2 = {
 845                         .prcm_reg_id = 1,
 846                         .module_bit = OMAP3430_EN_GPT6_SHIFT,
 847                         .module_offs = OMAP3430_PER_MOD,
 848                         .idlest_reg_id = 1,
 849                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 850                 },
 851         },
 852         .dev_attr       = &capability_alwon_dev_attr,
 853         .slaves         = omap3xxx_timer6_slaves,
 854         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer6_slaves),
 855         .class          = &omap3xxx_timer_hwmod_class,
 856 };
 857
 858 /* timer7 */
 859 static struct omap_hwmod omap3xxx_timer7_hwmod;
 860
 861 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
 862         {
 863                 .pa_start       = 0x4903C000,
 864                 .pa_end         = 0x4903C000 + SZ_1K - 1,
 865                 .flags          = ADDR_TYPE_RT
 866         },
 867         { }
 868 };
 869
 870 /* l4_per -> timer7 */
 871 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
 872         .master         = &omap3xxx_l4_per_hwmod,
 873         .slave          = &omap3xxx_timer7_hwmod,
 874         .clk            = "gpt7_ick",
 875         .addr           = omap3xxx_timer7_addrs,
 876         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 877 };
 878
 879 /* timer7 slave port */
 880 static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
 881         &omap3xxx_l4_per__timer7,
 882 };
 883
 884 /* timer7 hwmod */
 885 static struct omap_hwmod omap3xxx_timer7_hwmod = {
 886         .name           = "timer7",
 887         .mpu_irqs       = omap2_timer7_mpu_irqs,
 888         .main_clk       = "gpt7_fck",
 889         .prcm           = {
 890                 .omap2 = {
 891                         .prcm_reg_id = 1,
 892                         .module_bit = OMAP3430_EN_GPT7_SHIFT,
 893                         .module_offs = OMAP3430_PER_MOD,
 894                         .idlest_reg_id = 1,
 895                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 896                 },
 897         },
 898         .dev_attr       = &capability_alwon_dev_attr,
 899         .slaves         = omap3xxx_timer7_slaves,
 900         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer7_slaves),
 901         .class          = &omap3xxx_timer_hwmod_class,
 902 };
 903
 904 /* timer8 */
 905 static struct omap_hwmod omap3xxx_timer8_hwmod;
 906
 907 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
 908         {
 909                 .pa_start       = 0x4903E000,
 910                 .pa_end         = 0x4903E000 + SZ_1K - 1,
 911                 .flags          = ADDR_TYPE_RT
 912         },
 913         { }
 914 };
 915
 916 /* l4_per -> timer8 */
 917 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
 918         .master         = &omap3xxx_l4_per_hwmod,
 919         .slave          = &omap3xxx_timer8_hwmod,
 920         .clk            = "gpt8_ick",
 921         .addr           = omap3xxx_timer8_addrs,
 922         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 923 };
 924
 925 /* timer8 slave port */
 926 static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
 927         &omap3xxx_l4_per__timer8,
 928 };
 929
 930 /* timer8 hwmod */
 931 static struct omap_hwmod omap3xxx_timer8_hwmod = {
 932         .name           = "timer8",
 933         .mpu_irqs       = omap2_timer8_mpu_irqs,
 934         .main_clk       = "gpt8_fck",
 935         .prcm           = {
 936                 .omap2 = {
 937                         .prcm_reg_id = 1,
 938                         .module_bit = OMAP3430_EN_GPT8_SHIFT,
 939                         .module_offs = OMAP3430_PER_MOD,
 940                         .idlest_reg_id = 1,
 941                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 942                 },
 943         },
 944         .dev_attr       = &capability_pwm_dev_attr,
 945         .slaves         = omap3xxx_timer8_slaves,
 946         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer8_slaves),
 947         .class          = &omap3xxx_timer_hwmod_class,
 948 };
 949
 950 /* timer9 */
 951 static struct omap_hwmod omap3xxx_timer9_hwmod;
 952
 953 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
 954         {
 955                 .pa_start       = 0x49040000,
 956                 .pa_end         = 0x49040000 + SZ_1K - 1,
 957                 .flags          = ADDR_TYPE_RT
 958         },
 959         { }
 960 };
 961
 962 /* l4_per -> timer9 */
 963 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
 964         .master         = &omap3xxx_l4_per_hwmod,
 965         .slave          = &omap3xxx_timer9_hwmod,
 966         .clk            = "gpt9_ick",
 967         .addr           = omap3xxx_timer9_addrs,
 968         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 969 };
 970
 971 /* timer9 slave port */
 972 static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
 973         &omap3xxx_l4_per__timer9,
 974 };
 975
 976 /* timer9 hwmod */
 977 static struct omap_hwmod omap3xxx_timer9_hwmod = {
 978         .name           = "timer9",
 979         .mpu_irqs       = omap2_timer9_mpu_irqs,
 980         .main_clk       = "gpt9_fck",
 981         .prcm           = {
 982                 .omap2 = {
 983                         .prcm_reg_id = 1,
 984                         .module_bit = OMAP3430_EN_GPT9_SHIFT,
 985                         .module_offs = OMAP3430_PER_MOD,
 986                         .idlest_reg_id = 1,
 987                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
 988                 },
 989         },
 990         .dev_attr       = &capability_pwm_dev_attr,
 991         .slaves         = omap3xxx_timer9_slaves,
 992         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer9_slaves),
 993         .class          = &omap3xxx_timer_hwmod_class,
 994 };
 995
 996 /* timer10 */
 997 static struct omap_hwmod omap3xxx_timer10_hwmod;
 998
 999 /* l4_core -> timer10 */
1000 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1001         .master         = &omap3xxx_l4_core_hwmod,
1002         .slave          = &omap3xxx_timer10_hwmod,
1003         .clk            = "gpt10_ick",
1004         .addr           = omap2_timer10_addrs,
1005         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1006 };
1007
1008 /* timer10 slave port */
1009 static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1010         &omap3xxx_l4_core__timer10,
1011 };
1012
1013 /* timer10 hwmod */
1014 static struct omap_hwmod omap3xxx_timer10_hwmod = {
1015         .name           = "timer10",
1016         .mpu_irqs       = omap2_timer10_mpu_irqs,
1017         .main_clk       = "gpt10_fck",
1018         .prcm           = {
1019                 .omap2 = {
1020                         .prcm_reg_id = 1,
1021                         .module_bit = OMAP3430_EN_GPT10_SHIFT,
1022                         .module_offs = CORE_MOD,
1023                         .idlest_reg_id = 1,
1024                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1025                 },
1026         },
1027         .dev_attr       = &capability_pwm_dev_attr,
1028         .slaves         = omap3xxx_timer10_slaves,
1029         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer10_slaves),
1030         .class          = &omap3xxx_timer_1ms_hwmod_class,
1031 };
1032
1033 /* timer11 */
1034 static struct omap_hwmod omap3xxx_timer11_hwmod;
1035
1036 /* l4_core -> timer11 */
1037 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1038         .master         = &omap3xxx_l4_core_hwmod,
1039         .slave          = &omap3xxx_timer11_hwmod,
1040         .clk            = "gpt11_ick",
1041         .addr           = omap2_timer11_addrs,
1042         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1043 };
1044
1045 /* timer11 slave port */
1046 static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1047         &omap3xxx_l4_core__timer11,
1048 };
1049
1050 /* timer11 hwmod */
1051 static struct omap_hwmod omap3xxx_timer11_hwmod = {
1052         .name           = "timer11",
1053         .mpu_irqs       = omap2_timer11_mpu_irqs,
1054         .main_clk       = "gpt11_fck",
1055         .prcm           = {
1056                 .omap2 = {
1057                         .prcm_reg_id = 1,
1058                         .module_bit = OMAP3430_EN_GPT11_SHIFT,
1059                         .module_offs = CORE_MOD,
1060                         .idlest_reg_id = 1,
1061                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1062                 },
1063         },
1064         .dev_attr       = &capability_pwm_dev_attr,
1065         .slaves         = omap3xxx_timer11_slaves,
1066         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer11_slaves),
1067         .class          = &omap3xxx_timer_hwmod_class,
1068 };
1069
1070 /* timer12*/
1071 static struct omap_hwmod omap3xxx_timer12_hwmod;
1072 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1073         { .irq = 95, },
1074         { .irq = -1 }
1075 };
1076
1077 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1078         {
1079                 .pa_start       = 0x48304000,
1080                 .pa_end         = 0x48304000 + SZ_1K - 1,
1081                 .flags          = ADDR_TYPE_RT
1082         },
1083         { }
1084 };
1085
1086 /* l4_core -> timer12 */
1087 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1088         .master         = &omap3xxx_l4_core_hwmod,
1089         .slave          = &omap3xxx_timer12_hwmod,
1090         .clk            = "gpt12_ick",
1091         .addr           = omap3xxx_timer12_addrs,
1092         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1093 };
1094
1095 /* timer12 slave port */
1096 static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1097         &omap3xxx_l4_core__timer12,
1098 };
1099
1100 /* timer12 hwmod */
1101 static struct omap_hwmod omap3xxx_timer12_hwmod = {
1102         .name           = "timer12",
1103         .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
1104         .main_clk       = "gpt12_fck",
1105         .prcm           = {
1106                 .omap2 = {
1107                         .prcm_reg_id = 1,
1108                         .module_bit = OMAP3430_EN_GPT12_SHIFT,
1109                         .module_offs = WKUP_MOD,
1110                         .idlest_reg_id = 1,
1111                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1112                 },
1113         },
1114         .dev_attr       = &capability_secure_dev_attr,
1115         .slaves         = omap3xxx_timer12_slaves,
1116         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer12_slaves),
1117         .class          = &omap3xxx_timer_hwmod_class,
1118 };
1119
1120 /* l4_wkup -> wd_timer2 */
1121 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1122         {
1123                 .pa_start       = 0x48314000,
1124                 .pa_end         = 0x4831407f,
1125                 .flags          = ADDR_TYPE_RT
1126         },
1127         { }
1128 };
1129
1130 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1131         .master         = &omap3xxx_l4_wkup_hwmod,
1132         .slave          = &omap3xxx_wd_timer2_hwmod,
1133         .clk            = "wdt2_ick",
1134         .addr           = omap3xxx_wd_timer2_addrs,
1135         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1136 };
1137
1138 /*
1139  * 'wd_timer' class
1140  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1141  * overflow condition
1142  */
1143
1144 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
1145         .rev_offs       = 0x0000,
1146         .sysc_offs      = 0x0010,
1147         .syss_offs      = 0x0014,
1148         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
1149                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1150                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1151                            SYSS_HAS_RESET_STATUS),
1152         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1153         .sysc_fields    = &omap_hwmod_sysc_type1,
1154 };
1155
1156 /* I2C common */
1157 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1158         .rev_offs       = 0x00,
1159         .sysc_offs      = 0x20,
1160         .syss_offs      = 0x10,
1161         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1162                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1163                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1164         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1165         .sysc_fields    = &omap_hwmod_sysc_type1,
1166 };
1167
1168 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1169         .name           = "wd_timer",
1170         .sysc           = &omap3xxx_wd_timer_sysc,
1171         .pre_shutdown   = &omap2_wd_timer_disable
1172 };
1173
1174 /* wd_timer2 */
1175 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1176         &omap3xxx_l4_wkup__wd_timer2,
1177 };
1178
1179 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1180         .name           = "wd_timer2",
1181         .class          = &omap3xxx_wd_timer_hwmod_class,
1182         .main_clk       = "wdt2_fck",
1183         .prcm           = {
1184                 .omap2 = {
1185                         .prcm_reg_id = 1,
1186                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
1187                         .module_offs = WKUP_MOD,
1188                         .idlest_reg_id = 1,
1189                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1190                 },
1191         },
1192         .slaves         = omap3xxx_wd_timer2_slaves,
1193         .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1194         /*
1195          * XXX: Use software supervised mode, HW supervised smartidle seems to
1196          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1197          */
1198         .flags          = HWMOD_SWSUP_SIDLE,
1199 };
1200
1201 /* UART1 */
1202
1203 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1204         &omap3_l4_core__uart1,
1205 };
1206
1207 static struct omap_hwmod omap3xxx_uart1_hwmod = {
1208         .name           = "uart1",
1209         .mpu_irqs       = omap2_uart1_mpu_irqs,
1210         .sdma_reqs      = omap2_uart1_sdma_reqs,
1211         .main_clk       = "uart1_fck",
1212         .prcm           = {
1213                 .omap2 = {
1214                         .module_offs = CORE_MOD,
1215                         .prcm_reg_id = 1,
1216                         .module_bit = OMAP3430_EN_UART1_SHIFT,
1217                         .idlest_reg_id = 1,
1218                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1219                 },
1220         },
1221         .slaves         = omap3xxx_uart1_slaves,
1222         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
1223         .class          = &omap2_uart_class,
1224 };
1225
1226 /* UART2 */
1227
1228 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1229         &omap3_l4_core__uart2,
1230 };
1231
1232 static struct omap_hwmod omap3xxx_uart2_hwmod = {
1233         .name           = "uart2",
1234         .mpu_irqs       = omap2_uart2_mpu_irqs,
1235         .sdma_reqs      = omap2_uart2_sdma_reqs,
1236         .main_clk       = "uart2_fck",
1237         .prcm           = {
1238                 .omap2 = {
1239                         .module_offs = CORE_MOD,
1240                         .prcm_reg_id = 1,
1241                         .module_bit = OMAP3430_EN_UART2_SHIFT,
1242                         .idlest_reg_id = 1,
1243                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1244                 },
1245         },
1246         .slaves         = omap3xxx_uart2_slaves,
1247         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
1248         .class          = &omap2_uart_class,
1249 };
1250
1251 /* UART3 */
1252
1253 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1254         &omap3_l4_per__uart3,
1255 };
1256
1257 static struct omap_hwmod omap3xxx_uart3_hwmod = {
1258         .name           = "uart3",
1259         .mpu_irqs       = omap2_uart3_mpu_irqs,
1260         .sdma_reqs      = omap2_uart3_sdma_reqs,
1261         .main_clk       = "uart3_fck",
1262         .prcm           = {
1263                 .omap2 = {
1264                         .module_offs = OMAP3430_PER_MOD,
1265                         .prcm_reg_id = 1,
1266                         .module_bit = OMAP3430_EN_UART3_SHIFT,
1267                         .idlest_reg_id = 1,
1268                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1269                 },
1270         },
1271         .slaves         = omap3xxx_uart3_slaves,
1272         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
1273         .class          = &omap2_uart_class,
1274 };
1275
1276 /* UART4 */
1277
1278 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1279         { .irq = INT_36XX_UART4_IRQ, },
1280         { .irq = -1 }
1281 };
1282
1283 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1284         { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1285         { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1286         { .dma_req = -1 }
1287 };
1288
1289 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1290         &omap3_l4_per__uart4,
1291 };
1292
1293 static struct omap_hwmod omap3xxx_uart4_hwmod = {
1294         .name           = "uart4",
1295         .mpu_irqs       = uart4_mpu_irqs,
1296         .sdma_reqs      = uart4_sdma_reqs,
1297         .main_clk       = "uart4_fck",
1298         .prcm           = {
1299                 .omap2 = {
1300                         .module_offs = OMAP3430_PER_MOD,
1301                         .prcm_reg_id = 1,
1302                         .module_bit = OMAP3630_EN_UART4_SHIFT,
1303                         .idlest_reg_id = 1,
1304                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1305                 },
1306         },
1307         .slaves         = omap3xxx_uart4_slaves,
1308         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
1309         .class          = &omap2_uart_class,
1310 };
1311
1312 static struct omap_hwmod_class i2c_class = {
1313         .name   = "i2c",
1314         .sysc   = &i2c_sysc,
1315         .rev    = OMAP_I2C_IP_VERSION_1,
1316         .reset  = &omap_i2c_reset,
1317 };
1318
1319 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1320         { .name = "dispc", .dma_req = 5 },
1321         { .name = "dsi1", .dma_req = 74 },
1322         { .dma_req = -1 }
1323 };
1324
1325 /* dss */
1326 /* dss master ports */
1327 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1328         &omap3xxx_dss__l3,
1329 };
1330
1331 /* l4_core -> dss */
1332 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1333         .master         = &omap3xxx_l4_core_hwmod,
1334         .slave          = &omap3430es1_dss_core_hwmod,
1335         .clk            = "dss_ick",
1336         .addr           = omap2_dss_addrs,
1337         .fw = {
1338                 .omap2 = {
1339                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1340                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1341                         .flags  = OMAP_FIREWALL_L4,
1342                 }
1343         },
1344         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1345 };
1346
1347 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1348         .master         = &omap3xxx_l4_core_hwmod,
1349         .slave          = &omap3xxx_dss_core_hwmod,
1350         .clk            = "dss_ick",
1351         .addr           = omap2_dss_addrs,
1352         .fw = {
1353                 .omap2 = {
1354                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1355                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1356                         .flags  = OMAP_FIREWALL_L4,
1357                 }
1358         },
1359         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1360 };
1361
1362 /* dss slave ports */
1363 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1364         &omap3430es1_l4_core__dss,
1365 };
1366
1367 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1368         &omap3xxx_l4_core__dss,
1369 };
1370
1371 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1372         /*
1373          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
1374          * driver does not use these clocks.
1375          */
1376         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1377         { .role = "tv_clk", .clk = "dss_tv_fck" },
1378         /* required only on OMAP3430 */
1379         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1380 };
1381
1382 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1383         .name           = "dss_core",
1384         .class          = &omap2_dss_hwmod_class,
1385         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1386         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1387         .prcm           = {
1388                 .omap2 = {
1389                         .prcm_reg_id = 1,
1390                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1391                         .module_offs = OMAP3430_DSS_MOD,
1392                         .idlest_reg_id = 1,
1393                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
1394                 },
1395         },
1396         .opt_clks       = dss_opt_clks,
1397         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1398         .slaves         = omap3430es1_dss_slaves,
1399         .slaves_cnt     = ARRAY_SIZE(omap3430es1_dss_slaves),
1400         .masters        = omap3xxx_dss_masters,
1401         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1402         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1403 };
1404
1405 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1406         .name           = "dss_core",
1407         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1408         .class          = &omap2_dss_hwmod_class,
1409         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1410         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1411         .prcm           = {
1412                 .omap2 = {
1413                         .prcm_reg_id = 1,
1414                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1415                         .module_offs = OMAP3430_DSS_MOD,
1416                         .idlest_reg_id = 1,
1417                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
1418                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
1419                 },
1420         },
1421         .opt_clks       = dss_opt_clks,
1422         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1423         .slaves         = omap3xxx_dss_slaves,
1424         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_slaves),
1425         .masters        = omap3xxx_dss_masters,
1426         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1427 };
1428
1429 /* l4_core -> dss_dispc */
1430 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1431         .master         = &omap3xxx_l4_core_hwmod,
1432         .slave          = &omap3xxx_dss_dispc_hwmod,
1433         .clk            = "dss_ick",
1434         .addr           = omap2_dss_dispc_addrs,
1435         .fw = {
1436                 .omap2 = {
1437                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1438                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1439                         .flags  = OMAP_FIREWALL_L4,
1440                 }
1441         },
1442         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1443 };
1444
1445 /* dss_dispc slave ports */
1446 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1447         &omap3xxx_l4_core__dss_dispc,
1448 };
1449
1450 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1451         .name           = "dss_dispc",
1452         .class          = &omap2_dispc_hwmod_class,
1453         .mpu_irqs       = omap2_dispc_irqs,
1454         .main_clk       = "dss1_alwon_fck",
1455         .prcm           = {
1456                 .omap2 = {
1457                         .prcm_reg_id = 1,
1458                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1459                         .module_offs = OMAP3430_DSS_MOD,
1460                 },
1461         },
1462         .slaves         = omap3xxx_dss_dispc_slaves,
1463         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1464         .flags          = HWMOD_NO_IDLEST,
1465         .dev_attr       = &omap2_3_dss_dispc_dev_attr
1466 };
1467
1468 /*
1469  * 'dsi' class
1470  * display serial interface controller
1471  */
1472
1473 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1474         .name = "dsi",
1475 };
1476
1477 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1478         { .irq = 25 },
1479         { .irq = -1 }
1480 };
1481
1482 /* dss_dsi1 */
1483 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1484         {
1485                 .pa_start       = 0x4804FC00,
1486                 .pa_end         = 0x4804FFFF,
1487                 .flags          = ADDR_TYPE_RT
1488         },
1489         { }
1490 };
1491
1492 /* l4_core -> dss_dsi1 */
1493 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1494         .master         = &omap3xxx_l4_core_hwmod,
1495         .slave          = &omap3xxx_dss_dsi1_hwmod,
1496         .clk            = "dss_ick",
1497         .addr           = omap3xxx_dss_dsi1_addrs,
1498         .fw = {
1499                 .omap2 = {
1500                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1501                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1502                         .flags  = OMAP_FIREWALL_L4,
1503                 }
1504         },
1505         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1506 };
1507
1508 /* dss_dsi1 slave ports */
1509 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1510         &omap3xxx_l4_core__dss_dsi1,
1511 };
1512
1513 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1514         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1515 };
1516
1517 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1518         .name           = "dss_dsi1",
1519         .class          = &omap3xxx_dsi_hwmod_class,
1520         .mpu_irqs       = omap3xxx_dsi1_irqs,
1521         .main_clk       = "dss1_alwon_fck",
1522         .prcm           = {
1523                 .omap2 = {
1524                         .prcm_reg_id = 1,
1525                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1526                         .module_offs = OMAP3430_DSS_MOD,
1527                 },
1528         },
1529         .opt_clks       = dss_dsi1_opt_clks,
1530         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
1531         .slaves         = omap3xxx_dss_dsi1_slaves,
1532         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1533         .flags          = HWMOD_NO_IDLEST,
1534 };
1535
1536 /* l4_core -> dss_rfbi */
1537 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1538         .master         = &omap3xxx_l4_core_hwmod,
1539         .slave          = &omap3xxx_dss_rfbi_hwmod,
1540         .clk            = "dss_ick",
1541         .addr           = omap2_dss_rfbi_addrs,
1542         .fw = {
1543                 .omap2 = {
1544                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1545                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1546                         .flags  = OMAP_FIREWALL_L4,
1547                 }
1548         },
1549         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1550 };
1551
1552 /* dss_rfbi slave ports */
1553 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1554         &omap3xxx_l4_core__dss_rfbi,
1555 };
1556
1557 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1558         { .role = "ick", .clk = "dss_ick" },
1559 };
1560
1561 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1562         .name           = "dss_rfbi",
1563         .class          = &omap2_rfbi_hwmod_class,
1564         .main_clk       = "dss1_alwon_fck",
1565         .prcm           = {
1566                 .omap2 = {
1567                         .prcm_reg_id = 1,
1568                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1569                         .module_offs = OMAP3430_DSS_MOD,
1570                 },
1571         },
1572         .opt_clks       = dss_rfbi_opt_clks,
1573         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
1574         .slaves         = omap3xxx_dss_rfbi_slaves,
1575         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1576         .flags          = HWMOD_NO_IDLEST,
1577 };
1578
1579 /* l4_core -> dss_venc */
1580 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1581         .master         = &omap3xxx_l4_core_hwmod,
1582         .slave          = &omap3xxx_dss_venc_hwmod,
1583         .clk            = "dss_ick",
1584         .addr           = omap2_dss_venc_addrs,
1585         .fw = {
1586                 .omap2 = {
1587                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1588                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1589                         .flags  = OMAP_FIREWALL_L4,
1590                 }
1591         },
1592         .flags          = OCPIF_SWSUP_IDLE,
1593         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1594 };
1595
1596 /* dss_venc slave ports */
1597 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1598         &omap3xxx_l4_core__dss_venc,
1599 };
1600
1601 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
1602         /* required only on OMAP3430 */
1603         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1604 };
1605
1606 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1607         .name           = "dss_venc",
1608         .class          = &omap2_venc_hwmod_class,
1609         .main_clk       = "dss_tv_fck",
1610         .prcm           = {
1611                 .omap2 = {
1612                         .prcm_reg_id = 1,
1613                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1614                         .module_offs = OMAP3430_DSS_MOD,
1615                 },
1616         },
1617         .opt_clks       = dss_venc_opt_clks,
1618         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
1619         .slaves         = omap3xxx_dss_venc_slaves,
1620         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1621         .flags          = HWMOD_NO_IDLEST,
1622 };
1623
1624 /* I2C1 */
1625
1626 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1627         .fifo_depth     = 8, /* bytes */
1628         .flags          = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1629                           OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1630                           OMAP_I2C_FLAG_BUS_SHIFT_2,
1631 };
1632
1633 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1634         &omap3_l4_core__i2c1,
1635 };
1636
1637 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1638         .name           = "i2c1",
1639         .flags          = HWMOD_16BIT_REG,
1640         .mpu_irqs       = omap2_i2c1_mpu_irqs,
1641         .sdma_reqs      = omap2_i2c1_sdma_reqs,
1642         .main_clk       = "i2c1_fck",
1643         .prcm           = {
1644                 .omap2 = {
1645                         .module_offs = CORE_MOD,
1646                         .prcm_reg_id = 1,
1647                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
1648                         .idlest_reg_id = 1,
1649                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1650                 },
1651         },
1652         .slaves         = omap3xxx_i2c1_slaves,
1653         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1654         .class          = &i2c_class,
1655         .dev_attr       = &i2c1_dev_attr,
1656 };
1657
1658 /* I2C2 */
1659
1660 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1661         .fifo_depth     = 8, /* bytes */
1662         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1663                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1664                  OMAP_I2C_FLAG_BUS_SHIFT_2,
1665 };
1666
1667 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1668         &omap3_l4_core__i2c2,
1669 };
1670
1671 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1672         .name           = "i2c2",
1673         .flags          = HWMOD_16BIT_REG,
1674         .mpu_irqs       = omap2_i2c2_mpu_irqs,
1675         .sdma_reqs      = omap2_i2c2_sdma_reqs,
1676         .main_clk       = "i2c2_fck",
1677         .prcm           = {
1678                 .omap2 = {
1679                         .module_offs = CORE_MOD,
1680                         .prcm_reg_id = 1,
1681                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
1682                         .idlest_reg_id = 1,
1683                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1684                 },
1685         },
1686         .slaves         = omap3xxx_i2c2_slaves,
1687         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1688         .class          = &i2c_class,
1689         .dev_attr       = &i2c2_dev_attr,
1690 };
1691
1692 /* I2C3 */
1693
1694 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1695         .fifo_depth     = 64, /* bytes */
1696         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1697                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1698                  OMAP_I2C_FLAG_BUS_SHIFT_2,
1699 };
1700
1701 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1702         { .irq = INT_34XX_I2C3_IRQ, },
1703         { .irq = -1 }
1704 };
1705
1706 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1707         { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1708         { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1709         { .dma_req = -1 }
1710 };
1711
1712 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1713         &omap3_l4_core__i2c3,
1714 };
1715
1716 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1717         .name           = "i2c3",
1718         .flags          = HWMOD_16BIT_REG,
1719         .mpu_irqs       = i2c3_mpu_irqs,
1720         .sdma_reqs      = i2c3_sdma_reqs,
1721         .main_clk       = "i2c3_fck",
1722         .prcm           = {
1723                 .omap2 = {
1724                         .module_offs = CORE_MOD,
1725                         .prcm_reg_id = 1,
1726                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
1727                         .idlest_reg_id = 1,
1728                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1729                 },
1730         },
1731         .slaves         = omap3xxx_i2c3_slaves,
1732         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1733         .class          = &i2c_class,
1734         .dev_attr       = &i2c3_dev_attr,
1735 };
1736
1737 /* l4_wkup -> gpio1 */
1738 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1739         {
1740                 .pa_start       = 0x48310000,
1741                 .pa_end         = 0x483101ff,
1742                 .flags          = ADDR_TYPE_RT
1743         },
1744         { }
1745 };
1746
1747 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1748         .master         = &omap3xxx_l4_wkup_hwmod,
1749         .slave          = &omap3xxx_gpio1_hwmod,
1750         .addr           = omap3xxx_gpio1_addrs,
1751         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1752 };
1753
1754 /* l4_per -> gpio2 */
1755 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1756         {
1757                 .pa_start       = 0x49050000,
1758                 .pa_end         = 0x490501ff,
1759                 .flags          = ADDR_TYPE_RT
1760         },
1761         { }
1762 };
1763
1764 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1765         .master         = &omap3xxx_l4_per_hwmod,
1766         .slave          = &omap3xxx_gpio2_hwmod,
1767         .addr           = omap3xxx_gpio2_addrs,
1768         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1769 };
1770
1771 /* l4_per -> gpio3 */
1772 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1773         {
1774                 .pa_start       = 0x49052000,
1775                 .pa_end         = 0x490521ff,
1776                 .flags          = ADDR_TYPE_RT
1777         },
1778         { }
1779 };
1780
1781 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1782         .master         = &omap3xxx_l4_per_hwmod,
1783         .slave          = &omap3xxx_gpio3_hwmod,
1784         .addr           = omap3xxx_gpio3_addrs,
1785         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1786 };
1787
1788 /* l4_per -> gpio4 */
1789 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1790         {
1791                 .pa_start       = 0x49054000,
1792                 .pa_end         = 0x490541ff,
1793                 .flags          = ADDR_TYPE_RT
1794         },
1795         { }
1796 };
1797
1798 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1799         .master         = &omap3xxx_l4_per_hwmod,
1800         .slave          = &omap3xxx_gpio4_hwmod,
1801         .addr           = omap3xxx_gpio4_addrs,
1802         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1803 };
1804
1805 /* l4_per -> gpio5 */
1806 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
1807         {
1808                 .pa_start       = 0x49056000,
1809                 .pa_end         = 0x490561ff,
1810                 .flags          = ADDR_TYPE_RT
1811         },
1812         { }
1813 };
1814
1815 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1816         .master         = &omap3xxx_l4_per_hwmod,
1817         .slave          = &omap3xxx_gpio5_hwmod,
1818         .addr           = omap3xxx_gpio5_addrs,
1819         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1820 };
1821
1822 /* l4_per -> gpio6 */
1823 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
1824         {
1825                 .pa_start       = 0x49058000,
1826                 .pa_end         = 0x490581ff,
1827                 .flags          = ADDR_TYPE_RT
1828         },
1829         { }
1830 };
1831
1832 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
1833         .master         = &omap3xxx_l4_per_hwmod,
1834         .slave          = &omap3xxx_gpio6_hwmod,
1835         .addr           = omap3xxx_gpio6_addrs,
1836         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1837 };
1838
1839 /*
1840  * 'gpio' class
1841  * general purpose io module
1842  */
1843
1844 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
1845         .rev_offs       = 0x0000,
1846         .sysc_offs      = 0x0010,
1847         .syss_offs      = 0x0014,
1848         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1849                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1850                            SYSS_HAS_RESET_STATUS),
1851         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1852         .sysc_fields    = &omap_hwmod_sysc_type1,
1853 };
1854
1855 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
1856         .name = "gpio",
1857         .sysc = &omap3xxx_gpio_sysc,
1858         .rev = 1,
1859 };
1860
1861 /* gpio_dev_attr*/
1862 static struct omap_gpio_dev_attr gpio_dev_attr = {
1863         .bank_width = 32,
1864         .dbck_flag = true,
1865 };
1866
1867 /* gpio1 */
1868 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1869         { .role = "dbclk", .clk = "gpio1_dbck", },
1870 };
1871
1872 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
1873         &omap3xxx_l4_wkup__gpio1,
1874 };
1875
1876 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
1877         .name           = "gpio1",
1878         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1879         .mpu_irqs       = omap2_gpio1_irqs,
1880         .main_clk       = "gpio1_ick",
1881         .opt_clks       = gpio1_opt_clks,
1882         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1883         .prcm           = {
1884                 .omap2 = {
1885                         .prcm_reg_id = 1,
1886                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
1887                         .module_offs = WKUP_MOD,
1888                         .idlest_reg_id = 1,
1889                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
1890                 },
1891         },
1892         .slaves         = omap3xxx_gpio1_slaves,
1893         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio1_slaves),
1894         .class          = &omap3xxx_gpio_hwmod_class,
1895         .dev_attr       = &gpio_dev_attr,
1896 };
1897
1898 /* gpio2 */
1899 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1900         { .role = "dbclk", .clk = "gpio2_dbck", },
1901 };
1902
1903 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
1904         &omap3xxx_l4_per__gpio2,
1905 };
1906
1907 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
1908         .name           = "gpio2",
1909         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1910         .mpu_irqs       = omap2_gpio2_irqs,
1911         .main_clk       = "gpio2_ick",
1912         .opt_clks       = gpio2_opt_clks,
1913         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1914         .prcm           = {
1915                 .omap2 = {
1916                         .prcm_reg_id = 1,
1917                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
1918                         .module_offs = OMAP3430_PER_MOD,
1919                         .idlest_reg_id = 1,
1920                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
1921                 },
1922         },
1923         .slaves         = omap3xxx_gpio2_slaves,
1924         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio2_slaves),
1925         .class          = &omap3xxx_gpio_hwmod_class,
1926         .dev_attr       = &gpio_dev_attr,
1927 };
1928
1929 /* gpio3 */
1930 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1931         { .role = "dbclk", .clk = "gpio3_dbck", },
1932 };
1933
1934 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
1935         &omap3xxx_l4_per__gpio3,
1936 };
1937
1938 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
1939         .name           = "gpio3",
1940         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1941         .mpu_irqs       = omap2_gpio3_irqs,
1942         .main_clk       = "gpio3_ick",
1943         .opt_clks       = gpio3_opt_clks,
1944         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1945         .prcm           = {
1946                 .omap2 = {
1947                         .prcm_reg_id = 1,
1948                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
1949                         .module_offs = OMAP3430_PER_MOD,
1950                         .idlest_reg_id = 1,
1951                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
1952                 },
1953         },
1954         .slaves         = omap3xxx_gpio3_slaves,
1955         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio3_slaves),
1956         .class          = &omap3xxx_gpio_hwmod_class,
1957         .dev_attr       = &gpio_dev_attr,
1958 };
1959
1960 /* gpio4 */
1961 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1962         { .role = "dbclk", .clk = "gpio4_dbck", },
1963 };
1964
1965 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
1966         &omap3xxx_l4_per__gpio4,
1967 };
1968
1969 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
1970         .name           = "gpio4",
1971         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1972         .mpu_irqs       = omap2_gpio4_irqs,
1973         .main_clk       = "gpio4_ick",
1974         .opt_clks       = gpio4_opt_clks,
1975         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1976         .prcm           = {
1977                 .omap2 = {
1978                         .prcm_reg_id = 1,
1979                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
1980                         .module_offs = OMAP3430_PER_MOD,
1981                         .idlest_reg_id = 1,
1982                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
1983                 },
1984         },
1985         .slaves         = omap3xxx_gpio4_slaves,
1986         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio4_slaves),
1987         .class          = &omap3xxx_gpio_hwmod_class,
1988         .dev_attr       = &gpio_dev_attr,
1989 };
1990
1991 /* gpio5 */
1992 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1993         { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
1994         { .irq = -1 }
1995 };
1996
1997 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1998         { .role = "dbclk", .clk = "gpio5_dbck", },
1999 };
2000
2001 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
2002         &omap3xxx_l4_per__gpio5,
2003 };
2004
2005 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2006         .name           = "gpio5",
2007         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2008         .mpu_irqs       = omap3xxx_gpio5_irqs,
2009         .main_clk       = "gpio5_ick",
2010         .opt_clks       = gpio5_opt_clks,
2011         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
2012         .prcm           = {
2013                 .omap2 = {
2014                         .prcm_reg_id = 1,
2015                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
2016                         .module_offs = OMAP3430_PER_MOD,
2017                         .idlest_reg_id = 1,
2018                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
2019                 },
2020         },
2021         .slaves         = omap3xxx_gpio5_slaves,
2022         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2023         .class          = &omap3xxx_gpio_hwmod_class,
2024         .dev_attr       = &gpio_dev_attr,
2025 };
2026
2027 /* gpio6 */
2028 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2029         { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2030         { .irq = -1 }
2031 };
2032
2033 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2034         { .role = "dbclk", .clk = "gpio6_dbck", },
2035 };
2036
2037 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2038         &omap3xxx_l4_per__gpio6,
2039 };
2040
2041 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2042         .name           = "gpio6",
2043         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2044         .mpu_irqs       = omap3xxx_gpio6_irqs,
2045         .main_clk       = "gpio6_ick",
2046         .opt_clks       = gpio6_opt_clks,
2047         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
2048         .prcm           = {
2049                 .omap2 = {
2050                         .prcm_reg_id = 1,
2051                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
2052                         .module_offs = OMAP3430_PER_MOD,
2053                         .idlest_reg_id = 1,
2054                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2055                 },
2056         },
2057         .slaves         = omap3xxx_gpio6_slaves,
2058         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2059         .class          = &omap3xxx_gpio_hwmod_class,
2060         .dev_attr       = &gpio_dev_attr,
2061 };
2062
2063 /* dma_system -> L3 */
2064 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2065         .master         = &omap3xxx_dma_system_hwmod,
2066         .slave          = &omap3xxx_l3_main_hwmod,
2067         .clk            = "core_l3_ick",
2068         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2069 };
2070
2071 /* dma attributes */
2072 static struct omap_dma_dev_attr dma_dev_attr = {
2073         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
2074                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
2075         .lch_count = 32,
2076 };
2077
2078 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
2079         .rev_offs       = 0x0000,
2080         .sysc_offs      = 0x002c,
2081         .syss_offs      = 0x0028,
2082         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2083                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
2084                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
2085                            SYSS_HAS_RESET_STATUS),
2086         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2087                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2088         .sysc_fields    = &omap_hwmod_sysc_type1,
2089 };
2090
2091 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2092         .name = "dma",
2093         .sysc = &omap3xxx_dma_sysc,
2094 };
2095
2096 /* dma_system */
2097 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2098         {
2099                 .pa_start       = 0x48056000,
2100                 .pa_end         = 0x48056fff,
2101                 .flags          = ADDR_TYPE_RT
2102         },
2103         { }
2104 };
2105
2106 /* dma_system master ports */
2107 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2108         &omap3xxx_dma_system__l3,
2109 };
2110
2111 /* l4_cfg -> dma_system */
2112 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2113         .master         = &omap3xxx_l4_core_hwmod,
2114         .slave          = &omap3xxx_dma_system_hwmod,
2115         .clk            = "core_l4_ick",
2116         .addr           = omap3xxx_dma_system_addrs,
2117         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2118 };
2119
2120 /* dma_system slave ports */
2121 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2122         &omap3xxx_l4_core__dma_system,
2123 };
2124
2125 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2126         .name           = "dma",
2127         .class          = &omap3xxx_dma_hwmod_class,
2128         .mpu_irqs       = omap2_dma_system_irqs,
2129         .main_clk       = "core_l3_ick",
2130         .prcm = {
2131                 .omap2 = {
2132                         .module_offs            = CORE_MOD,
2133                         .prcm_reg_id            = 1,
2134                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
2135                         .idlest_reg_id          = 1,
2136                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
2137                 },
2138         },
2139         .slaves         = omap3xxx_dma_system_slaves,
2140         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2141         .masters        = omap3xxx_dma_system_masters,
2142         .masters_cnt    = ARRAY_SIZE(omap3xxx_dma_system_masters),
2143         .dev_attr       = &dma_dev_attr,
2144         .flags          = HWMOD_NO_IDLEST,
2145 };
2146
2147 /*
2148  * 'mcbsp' class
2149  * multi channel buffered serial port controller
2150  */
2151
2152 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2153         .sysc_offs      = 0x008c,
2154         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2155                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2156         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2157         .sysc_fields    = &omap_hwmod_sysc_type1,
2158         .clockact       = 0x2,
2159 };
2160
2161 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2162         .name = "mcbsp",
2163         .sysc = &omap3xxx_mcbsp_sysc,
2164         .rev  = MCBSP_CONFIG_TYPE3,
2165 };
2166
2167 /* mcbsp1 */
2168 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2169         { .name = "irq", .irq = 16 },
2170         { .name = "tx", .irq = 59 },
2171         { .name = "rx", .irq = 60 },
2172         { .irq = -1 }
2173 };
2174
2175 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2176         {
2177                 .name           = "mpu",
2178                 .pa_start       = 0x48074000,
2179                 .pa_end         = 0x480740ff,
2180                 .flags          = ADDR_TYPE_RT
2181         },
2182         { }
2183 };
2184
2185 /* l4_core -> mcbsp1 */
2186 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2187         .master         = &omap3xxx_l4_core_hwmod,
2188         .slave          = &omap3xxx_mcbsp1_hwmod,
2189         .clk            = "mcbsp1_ick",
2190         .addr           = omap3xxx_mcbsp1_addrs,
2191         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2192 };
2193
2194 /* mcbsp1 slave ports */
2195 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2196         &omap3xxx_l4_core__mcbsp1,
2197 };
2198
2199 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2200         .name           = "mcbsp1",
2201         .class          = &omap3xxx_mcbsp_hwmod_class,
2202         .mpu_irqs       = omap3xxx_mcbsp1_irqs,
2203         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
2204         .main_clk       = "mcbsp1_fck",
2205         .prcm           = {
2206                 .omap2 = {
2207                         .prcm_reg_id = 1,
2208                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2209                         .module_offs = CORE_MOD,
2210                         .idlest_reg_id = 1,
2211                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2212                 },
2213         },
2214         .slaves         = omap3xxx_mcbsp1_slaves,
2215         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2216 };
2217
2218 /* mcbsp2 */
2219 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2220         { .name = "irq", .irq = 17 },
2221         { .name = "tx", .irq = 62 },
2222         { .name = "rx", .irq = 63 },
2223         { .irq = -1 }
2224 };
2225
2226 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2227         {
2228                 .name           = "mpu",
2229                 .pa_start       = 0x49022000,
2230                 .pa_end         = 0x490220ff,
2231                 .flags          = ADDR_TYPE_RT
2232         },
2233         { }
2234 };
2235
2236 /* l4_per -> mcbsp2 */
2237 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2238         .master         = &omap3xxx_l4_per_hwmod,
2239         .slave          = &omap3xxx_mcbsp2_hwmod,
2240         .clk            = "mcbsp2_ick",
2241         .addr           = omap3xxx_mcbsp2_addrs,
2242         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2243 };
2244
2245 /* mcbsp2 slave ports */
2246 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2247         &omap3xxx_l4_per__mcbsp2,
2248 };
2249
2250 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2251         .sidetone       = "mcbsp2_sidetone",
2252 };
2253
2254 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2255         .name           = "mcbsp2",
2256         .class          = &omap3xxx_mcbsp_hwmod_class,
2257         .mpu_irqs       = omap3xxx_mcbsp2_irqs,
2258         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
2259         .main_clk       = "mcbsp2_fck",
2260         .prcm           = {
2261                 .omap2 = {
2262                         .prcm_reg_id = 1,
2263                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2264                         .module_offs = OMAP3430_PER_MOD,
2265                         .idlest_reg_id = 1,
2266                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2267                 },
2268         },
2269         .slaves         = omap3xxx_mcbsp2_slaves,
2270         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2271         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
2272 };
2273
2274 /* mcbsp3 */
2275 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2276         { .name = "irq", .irq = 22 },
2277         { .name = "tx", .irq = 89 },
2278         { .name = "rx", .irq = 90 },
2279         { .irq = -1 }
2280 };
2281
2282 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2283         {
2284                 .name           = "mpu",
2285                 .pa_start       = 0x49024000,
2286                 .pa_end         = 0x490240ff,
2287                 .flags          = ADDR_TYPE_RT
2288         },
2289         { }
2290 };
2291
2292 /* l4_per -> mcbsp3 */
2293 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2294         .master         = &omap3xxx_l4_per_hwmod,
2295         .slave          = &omap3xxx_mcbsp3_hwmod,
2296         .clk            = "mcbsp3_ick",
2297         .addr           = omap3xxx_mcbsp3_addrs,
2298         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2299 };
2300
2301 /* mcbsp3 slave ports */
2302 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2303         &omap3xxx_l4_per__mcbsp3,
2304 };
2305
2306 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2307         .sidetone       = "mcbsp3_sidetone",
2308 };
2309
2310 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2311         .name           = "mcbsp3",
2312         .class          = &omap3xxx_mcbsp_hwmod_class,
2313         .mpu_irqs       = omap3xxx_mcbsp3_irqs,
2314         .sdma_reqs      = omap2_mcbsp3_sdma_reqs,
2315         .main_clk       = "mcbsp3_fck",
2316         .prcm           = {
2317                 .omap2 = {
2318                         .prcm_reg_id = 1,
2319                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2320                         .module_offs = OMAP3430_PER_MOD,
2321                         .idlest_reg_id = 1,
2322                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2323                 },
2324         },
2325         .slaves         = omap3xxx_mcbsp3_slaves,
2326         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2327         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
2328 };
2329
2330 /* mcbsp4 */
2331 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2332         { .name = "irq", .irq = 23 },
2333         { .name = "tx", .irq = 54 },
2334         { .name = "rx", .irq = 55 },
2335         { .irq = -1 }
2336 };
2337
2338 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2339         { .name = "rx", .dma_req = 20 },
2340         { .name = "tx", .dma_req = 19 },
2341         { .dma_req = -1 }
2342 };
2343
2344 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2345         {
2346                 .name           = "mpu",
2347                 .pa_start       = 0x49026000,
2348                 .pa_end         = 0x490260ff,
2349                 .flags          = ADDR_TYPE_RT
2350         },
2351         { }
2352 };
2353
2354 /* l4_per -> mcbsp4 */
2355 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2356         .master         = &omap3xxx_l4_per_hwmod,
2357         .slave          = &omap3xxx_mcbsp4_hwmod,
2358         .clk            = "mcbsp4_ick",
2359         .addr           = omap3xxx_mcbsp4_addrs,
2360         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2361 };
2362
2363 /* mcbsp4 slave ports */
2364 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2365         &omap3xxx_l4_per__mcbsp4,
2366 };
2367
2368 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2369         .name           = "mcbsp4",
2370         .class          = &omap3xxx_mcbsp_hwmod_class,
2371         .mpu_irqs       = omap3xxx_mcbsp4_irqs,
2372         .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
2373         .main_clk       = "mcbsp4_fck",
2374         .prcm           = {
2375                 .omap2 = {
2376                         .prcm_reg_id = 1,
2377                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2378                         .module_offs = OMAP3430_PER_MOD,
2379                         .idlest_reg_id = 1,
2380                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2381                 },
2382         },
2383         .slaves         = omap3xxx_mcbsp4_slaves,
2384         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2385 };
2386
2387 /* mcbsp5 */
2388 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2389         { .name = "irq", .irq = 27 },
2390         { .name = "tx", .irq = 81 },
2391         { .name = "rx", .irq = 82 },
2392         { .irq = -1 }
2393 };
2394
2395 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2396         { .name = "rx", .dma_req = 22 },
2397         { .name = "tx", .dma_req = 21 },
2398         { .dma_req = -1 }
2399 };
2400
2401 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2402         {
2403                 .name           = "mpu",
2404                 .pa_start       = 0x48096000,
2405                 .pa_end         = 0x480960ff,
2406                 .flags          = ADDR_TYPE_RT
2407         },
2408         { }
2409 };
2410
2411 /* l4_core -> mcbsp5 */
2412 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2413         .master         = &omap3xxx_l4_core_hwmod,
2414         .slave          = &omap3xxx_mcbsp5_hwmod,
2415         .clk            = "mcbsp5_ick",
2416         .addr           = omap3xxx_mcbsp5_addrs,
2417         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2418 };
2419
2420 /* mcbsp5 slave ports */
2421 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2422         &omap3xxx_l4_core__mcbsp5,
2423 };
2424
2425 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2426         .name           = "mcbsp5",
2427         .class          = &omap3xxx_mcbsp_hwmod_class,
2428         .mpu_irqs       = omap3xxx_mcbsp5_irqs,
2429         .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
2430         .main_clk       = "mcbsp5_fck",
2431         .prcm           = {
2432                 .omap2 = {
2433                         .prcm_reg_id = 1,
2434                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2435                         .module_offs = CORE_MOD,
2436                         .idlest_reg_id = 1,
2437                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2438                 },
2439         },
2440         .slaves         = omap3xxx_mcbsp5_slaves,
2441         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2442 };
2443 /* 'mcbsp sidetone' class */
2444
2445 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2446         .sysc_offs      = 0x0010,
2447         .sysc_flags     = SYSC_HAS_AUTOIDLE,
2448         .sysc_fields    = &omap_hwmod_sysc_type1,
2449 };
2450
2451 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2452         .name = "mcbsp_sidetone",
2453         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2454 };
2455
2456 /* mcbsp2_sidetone */
2457 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2458         { .name = "irq", .irq = 4 },
2459         { .irq = -1 }
2460 };
2461
2462 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2463         {
2464                 .name           = "sidetone",
2465                 .pa_start       = 0x49028000,
2466                 .pa_end         = 0x490280ff,
2467                 .flags          = ADDR_TYPE_RT
2468         },
2469         { }
2470 };
2471
2472 /* l4_per -> mcbsp2_sidetone */
2473 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2474         .master         = &omap3xxx_l4_per_hwmod,
2475         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
2476         .clk            = "mcbsp2_ick",
2477         .addr           = omap3xxx_mcbsp2_sidetone_addrs,
2478         .user           = OCP_USER_MPU,
2479 };
2480
2481 /* mcbsp2_sidetone slave ports */
2482 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2483         &omap3xxx_l4_per__mcbsp2_sidetone,
2484 };
2485
2486 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2487         .name           = "mcbsp2_sidetone",
2488         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2489         .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
2490         .main_clk       = "mcbsp2_fck",
2491         .prcm           = {
2492                 .omap2 = {
2493                         .prcm_reg_id = 1,
2494                          .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2495                         .module_offs = OMAP3430_PER_MOD,
2496                         .idlest_reg_id = 1,
2497                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2498                 },
2499         },
2500         .slaves         = omap3xxx_mcbsp2_sidetone_slaves,
2501         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2502 };
2503
2504 /* mcbsp3_sidetone */
2505 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2506         { .name = "irq", .irq = 5 },
2507         { .irq = -1 }
2508 };
2509
2510 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2511         {
2512                 .name           = "sidetone",
2513                 .pa_start       = 0x4902A000,
2514                 .pa_end         = 0x4902A0ff,
2515                 .flags          = ADDR_TYPE_RT
2516         },
2517         { }
2518 };
2519
2520 /* l4_per -> mcbsp3_sidetone */
2521 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2522         .master         = &omap3xxx_l4_per_hwmod,
2523         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
2524         .clk            = "mcbsp3_ick",
2525         .addr           = omap3xxx_mcbsp3_sidetone_addrs,
2526         .user           = OCP_USER_MPU,
2527 };
2528
2529 /* mcbsp3_sidetone slave ports */
2530 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2531         &omap3xxx_l4_per__mcbsp3_sidetone,
2532 };
2533
2534 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2535         .name           = "mcbsp3_sidetone",
2536         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2537         .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
2538         .main_clk       = "mcbsp3_fck",
2539         .prcm           = {
2540                 .omap2 = {
2541                         .prcm_reg_id = 1,
2542                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2543                         .module_offs = OMAP3430_PER_MOD,
2544                         .idlest_reg_id = 1,
2545                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2546                 },
2547         },
2548         .slaves         = omap3xxx_mcbsp3_sidetone_slaves,
2549         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2550 };
2551
2552
2553 /* SR common */
2554 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2555         .clkact_shift   = 20,
2556 };
2557
2558 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2559         .sysc_offs      = 0x24,
2560         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2561         .clockact       = CLOCKACT_TEST_ICLK,
2562         .sysc_fields    = &omap34xx_sr_sysc_fields,
2563 };
2564
2565 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2566         .name = "smartreflex",
2567         .sysc = &omap34xx_sr_sysc,
2568         .rev  = 1,
2569 };
2570
2571 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2572         .sidle_shift    = 24,
2573         .enwkup_shift   = 26
2574 };
2575
2576 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2577         .sysc_offs      = 0x38,
2578         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2579         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2580                         SYSC_NO_CACHE),
2581         .sysc_fields    = &omap36xx_sr_sysc_fields,
2582 };
2583
2584 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2585         .name = "smartreflex",
2586         .sysc = &omap36xx_sr_sysc,
2587         .rev  = 2,
2588 };
2589
2590 /* SR1 */
2591 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
2592         &omap3_l4_core__sr1,
2593 };
2594
2595 static struct omap_hwmod omap34xx_sr1_hwmod = {
2596         .name           = "sr1_hwmod",
2597         .class          = &omap34xx_smartreflex_hwmod_class,
2598         .main_clk       = "sr1_fck",
2599         .vdd_name       = "mpu_iva",
2600         .prcm           = {
2601                 .omap2 = {
2602                         .prcm_reg_id = 1,
2603                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2604                         .module_offs = WKUP_MOD,
2605                         .idlest_reg_id = 1,
2606                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2607                 },
2608         },
2609         .slaves         = omap3_sr1_slaves,
2610         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
2611         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2612 };
2613
2614 static struct omap_hwmod omap36xx_sr1_hwmod = {
2615         .name           = "sr1_hwmod",
2616         .class          = &omap36xx_smartreflex_hwmod_class,
2617         .main_clk       = "sr1_fck",
2618         .vdd_name       = "mpu_iva",
2619         .prcm           = {
2620                 .omap2 = {
2621                         .prcm_reg_id = 1,
2622                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2623                         .module_offs = WKUP_MOD,
2624                         .idlest_reg_id = 1,
2625                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2626                 },
2627         },
2628         .slaves         = omap3_sr1_slaves,
2629         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
2630 };
2631
2632 /* SR2 */
2633 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
2634         &omap3_l4_core__sr2,
2635 };
2636
2637 static struct omap_hwmod omap34xx_sr2_hwmod = {
2638         .name           = "sr2_hwmod",
2639         .class          = &omap34xx_smartreflex_hwmod_class,
2640         .main_clk       = "sr2_fck",
2641         .vdd_name       = "core",
2642         .prcm           = {
2643                 .omap2 = {
2644                         .prcm_reg_id = 1,
2645                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2646                         .module_offs = WKUP_MOD,
2647                         .idlest_reg_id = 1,
2648                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2649                 },
2650         },
2651         .slaves         = omap3_sr2_slaves,
2652         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
2653         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2654 };
2655
2656 static struct omap_hwmod omap36xx_sr2_hwmod = {
2657         .name           = "sr2_hwmod",
2658         .class          = &omap36xx_smartreflex_hwmod_class,
2659         .main_clk       = "sr2_fck",
2660         .vdd_name       = "core",
2661         .prcm           = {
2662                 .omap2 = {
2663                         .prcm_reg_id = 1,
2664                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2665                         .module_offs = WKUP_MOD,
2666                         .idlest_reg_id = 1,
2667                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2668                 },
2669         },
2670         .slaves         = omap3_sr2_slaves,
2671         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
2672 };
2673
2674 /*
2675  * 'mailbox' class
2676  * mailbox module allowing communication between the on-chip processors
2677  * using a queued mailbox-interrupt mechanism.
2678  */
2679
2680 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
2681         .rev_offs       = 0x000,
2682         .sysc_offs      = 0x010,
2683         .syss_offs      = 0x014,
2684         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2685                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2686         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2687         .sysc_fields    = &omap_hwmod_sysc_type1,
2688 };
2689
2690 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
2691         .name = "mailbox",
2692         .sysc = &omap3xxx_mailbox_sysc,
2693 };
2694
2695 static struct omap_hwmod omap3xxx_mailbox_hwmod;
2696 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
2697         { .irq = 26 },
2698         { .irq = -1 }
2699 };
2700
2701 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2702         {
2703                 .pa_start       = 0x48094000,
2704                 .pa_end         = 0x480941ff,
2705                 .flags          = ADDR_TYPE_RT,
2706         },
2707         { }
2708 };
2709
2710 /* l4_core -> mailbox */
2711 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2712         .master         = &omap3xxx_l4_core_hwmod,
2713         .slave          = &omap3xxx_mailbox_hwmod,
2714         .addr           = omap3xxx_mailbox_addrs,
2715         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2716 };
2717
2718 /* mailbox slave ports */
2719 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
2720         &omap3xxx_l4_core__mailbox,
2721 };
2722
2723 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2724         .name           = "mailbox",
2725         .class          = &omap3xxx_mailbox_hwmod_class,
2726         .mpu_irqs       = omap3xxx_mailbox_irqs,
2727         .main_clk       = "mailboxes_ick",
2728         .prcm           = {
2729                 .omap2 = {
2730                         .prcm_reg_id = 1,
2731                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2732                         .module_offs = CORE_MOD,
2733                         .idlest_reg_id = 1,
2734                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2735                 },
2736         },
2737         .slaves         = omap3xxx_mailbox_slaves,
2738         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mailbox_slaves),
2739 };
2740
2741 /* l4 core -> mcspi1 interface */
2742 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2743         .master         = &omap3xxx_l4_core_hwmod,
2744         .slave          = &omap34xx_mcspi1,
2745         .clk            = "mcspi1_ick",
2746         .addr           = omap2_mcspi1_addr_space,
2747         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2748 };
2749
2750 /* l4 core -> mcspi2 interface */
2751 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2752         .master         = &omap3xxx_l4_core_hwmod,
2753         .slave          = &omap34xx_mcspi2,
2754         .clk            = "mcspi2_ick",
2755         .addr           = omap2_mcspi2_addr_space,
2756         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2757 };
2758
2759 /* l4 core -> mcspi3 interface */
2760 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2761         .master         = &omap3xxx_l4_core_hwmod,
2762         .slave          = &omap34xx_mcspi3,
2763         .clk            = "mcspi3_ick",
2764         .addr           = omap2430_mcspi3_addr_space,
2765         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2766 };
2767
2768 /* l4 core -> mcspi4 interface */
2769 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
2770         {
2771                 .pa_start       = 0x480ba000,
2772                 .pa_end         = 0x480ba0ff,
2773                 .flags          = ADDR_TYPE_RT,
2774         },
2775         { }
2776 };
2777
2778 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2779         .master         = &omap3xxx_l4_core_hwmod,
2780         .slave          = &omap34xx_mcspi4,
2781         .clk            = "mcspi4_ick",
2782         .addr           = omap34xx_mcspi4_addr_space,
2783         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2784 };
2785
2786 /*
2787  * 'mcspi' class
2788  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2789  * bus
2790  */
2791
2792 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
2793         .rev_offs       = 0x0000,
2794         .sysc_offs      = 0x0010,
2795         .syss_offs      = 0x0014,
2796         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2797                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2798                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2799         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2800         .sysc_fields    = &omap_hwmod_sysc_type1,
2801 };
2802
2803 static struct omap_hwmod_class omap34xx_mcspi_class = {
2804         .name = "mcspi",
2805         .sysc = &omap34xx_mcspi_sysc,
2806         .rev = OMAP3_MCSPI_REV,
2807 };
2808
2809 /* mcspi1 */
2810 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
2811         &omap34xx_l4_core__mcspi1,
2812 };
2813
2814 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2815         .num_chipselect = 4,
2816 };
2817
2818 static struct omap_hwmod omap34xx_mcspi1 = {
2819         .name           = "mcspi1",
2820         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
2821         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
2822         .main_clk       = "mcspi1_fck",
2823         .prcm           = {
2824                 .omap2 = {
2825                         .module_offs = CORE_MOD,
2826                         .prcm_reg_id = 1,
2827                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
2828                         .idlest_reg_id = 1,
2829                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
2830                 },
2831         },
2832         .slaves         = omap34xx_mcspi1_slaves,
2833         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi1_slaves),
2834         .class          = &omap34xx_mcspi_class,
2835         .dev_attr       = &omap_mcspi1_dev_attr,
2836 };
2837
2838 /* mcspi2 */
2839 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
2840         &omap34xx_l4_core__mcspi2,
2841 };
2842
2843 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2844         .num_chipselect = 2,
2845 };
2846
2847 static struct omap_hwmod omap34xx_mcspi2 = {
2848         .name           = "mcspi2",
2849         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
2850         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
2851         .main_clk       = "mcspi2_fck",
2852         .prcm           = {
2853                 .omap2 = {
2854                         .module_offs = CORE_MOD,
2855                         .prcm_reg_id = 1,
2856                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
2857                         .idlest_reg_id = 1,
2858                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
2859                 },
2860         },
2861         .slaves         = omap34xx_mcspi2_slaves,
2862         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi2_slaves),
2863         .class          = &omap34xx_mcspi_class,
2864         .dev_attr       = &omap_mcspi2_dev_attr,
2865 };
2866
2867 /* mcspi3 */
2868 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
2869         { .name = "irq", .irq = 91 }, /* 91 */
2870         { .irq = -1 }
2871 };
2872
2873 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
2874         { .name = "tx0", .dma_req = 15 },
2875         { .name = "rx0", .dma_req = 16 },
2876         { .name = "tx1", .dma_req = 23 },
2877         { .name = "rx1", .dma_req = 24 },
2878         { .dma_req = -1 }
2879 };
2880
2881 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
2882         &omap34xx_l4_core__mcspi3,
2883 };
2884
2885 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2886         .num_chipselect = 2,
2887 };
2888
2889 static struct omap_hwmod omap34xx_mcspi3 = {
2890         .name           = "mcspi3",
2891         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
2892         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
2893         .main_clk       = "mcspi3_fck",
2894         .prcm           = {
2895                 .omap2 = {
2896                         .module_offs = CORE_MOD,
2897                         .prcm_reg_id = 1,
2898                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
2899                         .idlest_reg_id = 1,
2900                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
2901                 },
2902         },
2903         .slaves         = omap34xx_mcspi3_slaves,
2904         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi3_slaves),
2905         .class          = &omap34xx_mcspi_class,
2906         .dev_attr       = &omap_mcspi3_dev_attr,
2907 };
2908
2909 /* SPI4 */
2910 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
2911         { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
2912         { .irq = -1 }
2913 };
2914
2915 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
2916         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
2917         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
2918         { .dma_req = -1 }
2919 };
2920
2921 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
2922         &omap34xx_l4_core__mcspi4,
2923 };
2924
2925 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
2926         .num_chipselect = 1,
2927 };
2928
2929 static struct omap_hwmod omap34xx_mcspi4 = {
2930         .name           = "mcspi4",
2931         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
2932         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
2933         .main_clk       = "mcspi4_fck",
2934         .prcm           = {
2935                 .omap2 = {
2936                         .module_offs = CORE_MOD,
2937                         .prcm_reg_id = 1,
2938                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
2939                         .idlest_reg_id = 1,
2940                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
2941                 },
2942         },
2943         .slaves         = omap34xx_mcspi4_slaves,
2944         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi4_slaves),
2945         .class          = &omap34xx_mcspi_class,
2946         .dev_attr       = &omap_mcspi4_dev_attr,
2947 };
2948
2949 /*
2950  * usbhsotg
2951  */
2952 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
2953         .rev_offs       = 0x0400,
2954         .sysc_offs      = 0x0404,
2955         .syss_offs      = 0x0408,
2956         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
2957                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2958                           SYSC_HAS_AUTOIDLE),
2959         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2960                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2961         .sysc_fields    = &omap_hwmod_sysc_type1,
2962 };
2963
2964 static struct omap_hwmod_class usbotg_class = {
2965         .name = "usbotg",
2966         .sysc = &omap3xxx_usbhsotg_sysc,
2967 };
2968 /* usb_otg_hs */
2969 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
2970
2971         { .name = "mc", .irq = 92 },
2972         { .name = "dma", .irq = 93 },
2973         { .irq = -1 }
2974 };
2975
2976 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
2977         .name           = "usb_otg_hs",
2978         .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
2979         .main_clk       = "hsotgusb_ick",
2980         .prcm           = {
2981                 .omap2 = {
2982                         .prcm_reg_id = 1,
2983                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
2984                         .module_offs = CORE_MOD,
2985                         .idlest_reg_id = 1,
2986                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
2987                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
2988                 },
2989         },
2990         .masters        = omap3xxx_usbhsotg_masters,
2991         .masters_cnt    = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
2992         .slaves         = omap3xxx_usbhsotg_slaves,
2993         .slaves_cnt     = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
2994         .class          = &usbotg_class,
2995
2996         /*
2997          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
2998          * broken when autoidle is enabled
2999          * workaround is to disable the autoidle bit at module level.
3000          */
3001         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
3002                                 | HWMOD_SWSUP_MSTANDBY,
3003 };
3004
3005 /* usb_otg_hs */
3006 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
3007
3008         { .name = "mc", .irq = 71 },
3009         { .irq = -1 }
3010 };
3011
3012 static struct omap_hwmod_class am35xx_usbotg_class = {
3013         .name = "am35xx_usbotg",
3014         .sysc = NULL,
3015 };
3016
3017 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3018         .name           = "am35x_otg_hs",
3019         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
3020         .main_clk       = NULL,
3021         .prcm = {
3022                 .omap2 = {
3023                 },
3024         },
3025         .masters        = am35xx_usbhsotg_masters,
3026         .masters_cnt    = ARRAY_SIZE(am35xx_usbhsotg_masters),
3027         .slaves         = am35xx_usbhsotg_slaves,
3028         .slaves_cnt     = ARRAY_SIZE(am35xx_usbhsotg_slaves),
3029         .class          = &am35xx_usbotg_class,
3030 };
3031
3032 /* MMC/SD/SDIO common */
3033
3034 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3035         .rev_offs       = 0x1fc,
3036         .sysc_offs      = 0x10,
3037         .syss_offs      = 0x14,
3038         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3039                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3040                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3041         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3042         .sysc_fields    = &omap_hwmod_sysc_type1,
3043 };
3044
3045 static struct omap_hwmod_class omap34xx_mmc_class = {
3046         .name = "mmc",
3047         .sysc = &omap34xx_mmc_sysc,
3048 };
3049
3050 /* MMC/SD/SDIO1 */
3051
3052 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3053         { .irq = 83, },
3054         { .irq = -1 }
3055 };
3056
3057 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3058         { .name = "tx", .dma_req = 61, },
3059         { .name = "rx", .dma_req = 62, },
3060         { .dma_req = -1 }
3061 };
3062
3063 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3064         { .role = "dbck", .clk = "omap_32k_fck", },
3065 };
3066
3067 static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3068         &omap3xxx_l4_core__mmc1,
3069 };
3070
3071 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3072         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3073 };
3074
3075 static struct omap_hwmod omap3xxx_mmc1_hwmod = {
3076         .name           = "mmc1",
3077         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
3078         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
3079         .opt_clks       = omap34xx_mmc1_opt_clks,
3080         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3081         .main_clk       = "mmchs1_fck",
3082         .prcm           = {
3083                 .omap2 = {
3084                         .module_offs = CORE_MOD,
3085                         .prcm_reg_id = 1,
3086                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
3087                         .idlest_reg_id = 1,
3088                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3089                 },
3090         },
3091         .dev_attr       = &mmc1_dev_attr,
3092         .slaves         = omap3xxx_mmc1_slaves,
3093         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3094         .class          = &omap34xx_mmc_class,
3095 };
3096
3097 /* MMC/SD/SDIO2 */
3098
3099 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3100         { .irq = INT_24XX_MMC2_IRQ, },
3101         { .irq = -1 }
3102 };
3103
3104 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3105         { .name = "tx", .dma_req = 47, },
3106         { .name = "rx", .dma_req = 48, },
3107         { .dma_req = -1 }
3108 };
3109
3110 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3111         { .role = "dbck", .clk = "omap_32k_fck", },
3112 };
3113
3114 static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3115         &omap3xxx_l4_core__mmc2,
3116 };
3117
3118 static struct omap_hwmod omap3xxx_mmc2_hwmod = {
3119         .name           = "mmc2",
3120         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
3121         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
3122         .opt_clks       = omap34xx_mmc2_opt_clks,
3123         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3124         .main_clk       = "mmchs2_fck",
3125         .prcm           = {
3126                 .omap2 = {
3127                         .module_offs = CORE_MOD,
3128                         .prcm_reg_id = 1,
3129                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
3130                         .idlest_reg_id = 1,
3131                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3132                 },
3133         },
3134         .slaves         = omap3xxx_mmc2_slaves,
3135         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3136         .class          = &omap34xx_mmc_class,
3137 };
3138
3139 /* MMC/SD/SDIO3 */
3140
3141 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3142         { .irq = 94, },
3143         { .irq = -1 }
3144 };
3145
3146 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3147         { .name = "tx", .dma_req = 77, },
3148         { .name = "rx", .dma_req = 78, },
3149         { .dma_req = -1 }
3150 };
3151
3152 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3153         { .role = "dbck", .clk = "omap_32k_fck", },
3154 };
3155
3156 static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3157         &omap3xxx_l4_core__mmc3,
3158 };
3159
3160 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3161         .name           = "mmc3",
3162         .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
3163         .sdma_reqs      = omap34xx_mmc3_sdma_reqs,
3164         .opt_clks       = omap34xx_mmc3_opt_clks,
3165         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3166         .main_clk       = "mmchs3_fck",
3167         .prcm           = {
3168                 .omap2 = {
3169                         .prcm_reg_id = 1,
3170                         .module_bit = OMAP3430_EN_MMC3_SHIFT,
3171                         .idlest_reg_id = 1,
3172                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3173                 },
3174         },
3175         .slaves         = omap3xxx_mmc3_slaves,
3176         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3177         .class          = &omap34xx_mmc_class,
3178 };
3179
3180 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3181         &omap3xxx_l3_main_hwmod,
3182         &omap3xxx_l4_core_hwmod,
3183         &omap3xxx_l4_per_hwmod,
3184         &omap3xxx_l4_wkup_hwmod,
3185         &omap3xxx_mmc1_hwmod,
3186         &omap3xxx_mmc2_hwmod,
3187         &omap3xxx_mmc3_hwmod,
3188         &omap3xxx_mpu_hwmod,
3189
3190         &omap3xxx_timer1_hwmod,
3191         &omap3xxx_timer2_hwmod,
3192         &omap3xxx_timer3_hwmod,
3193         &omap3xxx_timer4_hwmod,
3194         &omap3xxx_timer5_hwmod,
3195         &omap3xxx_timer6_hwmod,
3196         &omap3xxx_timer7_hwmod,
3197         &omap3xxx_timer8_hwmod,
3198         &omap3xxx_timer9_hwmod,
3199         &omap3xxx_timer10_hwmod,
3200         &omap3xxx_timer11_hwmod,
3201         &omap3xxx_timer12_hwmod,
3202
3203         &omap3xxx_wd_timer2_hwmod,
3204         &omap3xxx_uart1_hwmod,
3205         &omap3xxx_uart2_hwmod,
3206         &omap3xxx_uart3_hwmod,
3207         /* dss class */
3208         &omap3xxx_dss_dispc_hwmod,
3209         &omap3xxx_dss_dsi1_hwmod,
3210         &omap3xxx_dss_rfbi_hwmod,
3211         &omap3xxx_dss_venc_hwmod,
3212
3213         /* i2c class */
3214         &omap3xxx_i2c1_hwmod,
3215         &omap3xxx_i2c2_hwmod,
3216         &omap3xxx_i2c3_hwmod,
3217
3218         /* gpio class */
3219         &omap3xxx_gpio1_hwmod,
3220         &omap3xxx_gpio2_hwmod,
3221         &omap3xxx_gpio3_hwmod,
3222         &omap3xxx_gpio4_hwmod,
3223         &omap3xxx_gpio5_hwmod,
3224         &omap3xxx_gpio6_hwmod,
3225
3226         /* dma_system class*/
3227         &omap3xxx_dma_system_hwmod,
3228
3229         /* mcbsp class */
3230         &omap3xxx_mcbsp1_hwmod,
3231         &omap3xxx_mcbsp2_hwmod,
3232         &omap3xxx_mcbsp3_hwmod,
3233         &omap3xxx_mcbsp4_hwmod,
3234         &omap3xxx_mcbsp5_hwmod,
3235         &omap3xxx_mcbsp2_sidetone_hwmod,
3236         &omap3xxx_mcbsp3_sidetone_hwmod,
3237
3238
3239         /* mcspi class */
3240         &omap34xx_mcspi1,
3241         &omap34xx_mcspi2,
3242         &omap34xx_mcspi3,
3243         &omap34xx_mcspi4,
3244
3245         NULL,
3246 };
3247
3248 /* 3430ES1-only hwmods */
3249 static __initdata struct omap_hwmod *omap3430es1_hwmods[] = {
3250         &omap3430es1_dss_core_hwmod,
3251         NULL
3252 };
3253
3254 /* 3430ES2+-only hwmods */
3255 static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = {
3256         &omap3xxx_dss_core_hwmod,
3257         &omap3xxx_usbhsotg_hwmod,
3258         NULL
3259 };
3260
3261 /* 34xx-only hwmods (all ES revisions) */
3262 static __initdata struct omap_hwmod *omap34xx_hwmods[] = {
3263         &omap3xxx_iva_hwmod,
3264         &omap34xx_sr1_hwmod,
3265         &omap34xx_sr2_hwmod,
3266         &omap3xxx_mailbox_hwmod,
3267         NULL
3268 };
3269
3270 /* 36xx-only hwmods (all ES revisions) */
3271 static __initdata struct omap_hwmod *omap36xx_hwmods[] = {
3272         &omap3xxx_iva_hwmod,
3273         &omap3xxx_uart4_hwmod,
3274         &omap3xxx_dss_core_hwmod,
3275         &omap36xx_sr1_hwmod,
3276         &omap36xx_sr2_hwmod,
3277         &omap3xxx_usbhsotg_hwmod,
3278         &omap3xxx_mailbox_hwmod,
3279         NULL
3280 };
3281
3282 static __initdata struct omap_hwmod *am35xx_hwmods[] = {
3283         &omap3xxx_dss_core_hwmod, /* XXX ??? */
3284         &am35xx_usbhsotg_hwmod,
3285         NULL
3286 };
3287
3288 int __init omap3xxx_hwmod_init(void)
3289 {
3290         int r;
3291         struct omap_hwmod **h = NULL;
3292         unsigned int rev;
3293
3294         /* Register hwmods common to all OMAP3 */
3295         r = omap_hwmod_register(omap3xxx_hwmods);
3296         if (r < 0)
3297                 return r;
3298
3299         rev = omap_rev();
3300
3301         /*
3302          * Register hwmods common to individual OMAP3 families, all
3303          * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3304          * All possible revisions should be included in this conditional.
3305          */
3306         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3307             rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3308             rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3309                 h = omap34xx_hwmods;
3310         } else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) {
3311                 h = am35xx_hwmods;
3312         } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3313                    rev == OMAP3630_REV_ES1_2) {
3314                 h = omap36xx_hwmods;
3315         } else {
3316                 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3317                 return -EINVAL;
3318         };
3319
3320         r = omap_hwmod_register(h);
3321         if (r < 0)
3322                 return r;
3323
3324         /*
3325          * Register hwmods specific to certain ES levels of a
3326          * particular family of silicon (e.g., 34xx ES1.0)
3327          */
3328         h = NULL;
3329         if (rev == OMAP3430_REV_ES1_0) {
3330                 h = omap3430es1_hwmods;
3331         } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3332                    rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3333                    rev == OMAP3430_REV_ES3_1_2) {
3334                 h = omap3430es2plus_hwmods;
3335         };
3336
3337         if (h)
3338                 r = omap_hwmod_register(h);
3339
3340         return r;
3341 }