arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  * Paul Walmsley
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * The data in this file should be completely autogeneratable from
  13  * the TI hardware database or other technical documentation.
  14  *
  15  * XXX these should be marked initdata for multi-OMAP kernels
  16  */
  17
  18 #include <linux/i2c-omap.h>
  19 #include <linux/power/smartreflex.h>
  20 #include <linux/platform_data/gpio-omap.h>
  21 #include <linux/platform_data/hsmmc-omap.h>
  22
  23 #include <linux/omap-dma.h>
  24 #include "l3_3xxx.h"
  25 #include "l4_3xxx.h"
  26 #include <linux/platform_data/asoc-ti-mcbsp.h>
  27 #include <linux/platform_data/spi-omap2-mcspi.h>
  28 #include <plat/dmtimer.h>
  29
  30 #include "soc.h"
  31 #include "omap_hwmod.h"
  32 #include "omap_hwmod_common_data.h"
  33 #include "prm-regbits-34xx.h"
  34 #include "cm-regbits-34xx.h"
  35
  36 #include "i2c.h"
  37 #include "wd_timer.h"
  38 #include "serial.h"
  39
  40 /*
  41  * OMAP3xxx hardware module integration data
  42  *
  43  * All of the data in this section should be autogeneratable from the
  44  * TI hardware database or other technical documentation.  Data that
  45  * is driver-specific or driver-kernel integration-specific belongs
  46  * elsewhere.
  47  */
  48
  49 #define AM35XX_IPSS_USBOTGSS_BASE      0x5C040000
  50
  51 /*
  52  * IP blocks
  53  */
  54
  55 /* L3 */
  56
  57 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
  58         .name           = "l3_main",
  59         .class          = &l3_hwmod_class,
  60         .flags          = HWMOD_NO_IDLEST,
  61 };
  62
  63 /* L4 CORE */
  64 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
  65         .name           = "l4_core",
  66         .class          = &l4_hwmod_class,
  67         .flags          = HWMOD_NO_IDLEST,
  68 };
  69
  70 /* L4 PER */
  71 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
  72         .name           = "l4_per",
  73         .class          = &l4_hwmod_class,
  74         .flags          = HWMOD_NO_IDLEST,
  75 };
  76
  77 /* L4 WKUP */
  78 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
  79         .name           = "l4_wkup",
  80         .class          = &l4_hwmod_class,
  81         .flags          = HWMOD_NO_IDLEST,
  82 };
  83
  84 /* L4 SEC */
  85 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
  86         .name           = "l4_sec",
  87         .class          = &l4_hwmod_class,
  88         .flags          = HWMOD_NO_IDLEST,
  89 };
  90
  91 /* MPU */
  92
  93 static struct omap_hwmod omap3xxx_mpu_hwmod = {
  94         .name           = "mpu",
  95         .class          = &mpu_hwmod_class,
  96         .main_clk       = "arm_fck",
  97 };
  98
  99 /* IVA2 (IVA2) */
 100 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
 101         { .name = "logic", .rst_shift = 0, .st_shift = 8 },
 102         { .name = "seq0", .rst_shift = 1, .st_shift = 9 },
 103         { .name = "seq1", .rst_shift = 2, .st_shift = 10 },
 104 };
 105
 106 static struct omap_hwmod omap3xxx_iva_hwmod = {
 107         .name           = "iva",
 108         .class          = &iva_hwmod_class,
 109         .clkdm_name     = "iva2_clkdm",
 110         .rst_lines      = omap3xxx_iva_resets,
 111         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_iva_resets),
 112         .main_clk       = "iva2_ck",
 113         .prcm = {
 114                 .omap2 = {
 115                         .module_offs = OMAP3430_IVA2_MOD,
 116                         .prcm_reg_id = 1,
 117                         .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
 118                         .idlest_reg_id = 1,
 119                         .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
 120                 },
 121         },
 122 };
 123
 124 /*
 125  * 'debugss' class
 126  * debug and emulation sub system
 127  */
 128
 129 static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = {
 130         .name   = "debugss",
 131 };
 132
 133 /* debugss */
 134 static struct omap_hwmod omap3xxx_debugss_hwmod = {
 135         .name           = "debugss",
 136         .class          = &omap3xxx_debugss_hwmod_class,
 137         .clkdm_name     = "emu_clkdm",
 138         .main_clk       = "emu_src_ck",
 139         .flags          = HWMOD_NO_IDLEST,
 140 };
 141
 142 /* timer class */
 143 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 144         .rev_offs       = 0x0000,
 145         .sysc_offs      = 0x0010,
 146         .syss_offs      = 0x0014,
 147         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 148                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 149                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
 150                            SYSS_HAS_RESET_STATUS),
 151         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 152         .sysc_fields    = &omap_hwmod_sysc_type1,
 153 };
 154
 155 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 156         .name = "timer",
 157         .sysc = &omap3xxx_timer_sysc,
 158 };
 159
 160 /* secure timers dev attribute */
 161 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
 162         .timer_capability       = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
 163 };
 164
 165 /* always-on timers dev attribute */
 166 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 167         .timer_capability       = OMAP_TIMER_ALWON,
 168 };
 169
 170 /* pwm timers dev attribute */
 171 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 172         .timer_capability       = OMAP_TIMER_HAS_PWM,
 173 };
 174
 175 /* timers with DSP interrupt dev attribute */
 176 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
 177         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
 178 };
 179
 180 /* pwm timers with DSP interrupt dev attribute */
 181 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
 182         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
 183 };
 184
 185 /* timer1 */
 186 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 187         .name           = "timer1",
 188         .main_clk       = "gpt1_fck",
 189         .prcm           = {
 190                 .omap2 = {
 191                         .prcm_reg_id = 1,
 192                         .module_bit = OMAP3430_EN_GPT1_SHIFT,
 193                         .module_offs = WKUP_MOD,
 194                         .idlest_reg_id = 1,
 195                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 196                 },
 197         },
 198         .dev_attr       = &capability_alwon_dev_attr,
 199         .class          = &omap3xxx_timer_hwmod_class,
 200         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 201 };
 202
 203 /* timer2 */
 204 static struct omap_hwmod omap3xxx_timer2_hwmod = {
 205         .name           = "timer2",
 206         .main_clk       = "gpt2_fck",
 207         .prcm           = {
 208                 .omap2 = {
 209                         .prcm_reg_id = 1,
 210                         .module_bit = OMAP3430_EN_GPT2_SHIFT,
 211                         .module_offs = OMAP3430_PER_MOD,
 212                         .idlest_reg_id = 1,
 213                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 214                 },
 215         },
 216         .class          = &omap3xxx_timer_hwmod_class,
 217         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 218 };
 219
 220 /* timer3 */
 221 static struct omap_hwmod omap3xxx_timer3_hwmod = {
 222         .name           = "timer3",
 223         .main_clk       = "gpt3_fck",
 224         .prcm           = {
 225                 .omap2 = {
 226                         .prcm_reg_id = 1,
 227                         .module_bit = OMAP3430_EN_GPT3_SHIFT,
 228                         .module_offs = OMAP3430_PER_MOD,
 229                         .idlest_reg_id = 1,
 230                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 231                 },
 232         },
 233         .class          = &omap3xxx_timer_hwmod_class,
 234         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 235 };
 236
 237 /* timer4 */
 238 static struct omap_hwmod omap3xxx_timer4_hwmod = {
 239         .name           = "timer4",
 240         .main_clk       = "gpt4_fck",
 241         .prcm           = {
 242                 .omap2 = {
 243                         .prcm_reg_id = 1,
 244                         .module_bit = OMAP3430_EN_GPT4_SHIFT,
 245                         .module_offs = OMAP3430_PER_MOD,
 246                         .idlest_reg_id = 1,
 247                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 248                 },
 249         },
 250         .class          = &omap3xxx_timer_hwmod_class,
 251         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 252 };
 253
 254 /* timer5 */
 255 static struct omap_hwmod omap3xxx_timer5_hwmod = {
 256         .name           = "timer5",
 257         .main_clk       = "gpt5_fck",
 258         .prcm           = {
 259                 .omap2 = {
 260                         .prcm_reg_id = 1,
 261                         .module_bit = OMAP3430_EN_GPT5_SHIFT,
 262                         .module_offs = OMAP3430_PER_MOD,
 263                         .idlest_reg_id = 1,
 264                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 265                 },
 266         },
 267         .dev_attr       = &capability_dsp_dev_attr,
 268         .class          = &omap3xxx_timer_hwmod_class,
 269         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 270 };
 271
 272 /* timer6 */
 273 static struct omap_hwmod omap3xxx_timer6_hwmod = {
 274         .name           = "timer6",
 275         .main_clk       = "gpt6_fck",
 276         .prcm           = {
 277                 .omap2 = {
 278                         .prcm_reg_id = 1,
 279                         .module_bit = OMAP3430_EN_GPT6_SHIFT,
 280                         .module_offs = OMAP3430_PER_MOD,
 281                         .idlest_reg_id = 1,
 282                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 283                 },
 284         },
 285         .dev_attr       = &capability_dsp_dev_attr,
 286         .class          = &omap3xxx_timer_hwmod_class,
 287         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 288 };
 289
 290 /* timer7 */
 291 static struct omap_hwmod omap3xxx_timer7_hwmod = {
 292         .name           = "timer7",
 293         .main_clk       = "gpt7_fck",
 294         .prcm           = {
 295                 .omap2 = {
 296                         .prcm_reg_id = 1,
 297                         .module_bit = OMAP3430_EN_GPT7_SHIFT,
 298                         .module_offs = OMAP3430_PER_MOD,
 299                         .idlest_reg_id = 1,
 300                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 301                 },
 302         },
 303         .dev_attr       = &capability_dsp_dev_attr,
 304         .class          = &omap3xxx_timer_hwmod_class,
 305         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 306 };
 307
 308 /* timer8 */
 309 static struct omap_hwmod omap3xxx_timer8_hwmod = {
 310         .name           = "timer8",
 311         .main_clk       = "gpt8_fck",
 312         .prcm           = {
 313                 .omap2 = {
 314                         .prcm_reg_id = 1,
 315                         .module_bit = OMAP3430_EN_GPT8_SHIFT,
 316                         .module_offs = OMAP3430_PER_MOD,
 317                         .idlest_reg_id = 1,
 318                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 319                 },
 320         },
 321         .dev_attr       = &capability_dsp_pwm_dev_attr,
 322         .class          = &omap3xxx_timer_hwmod_class,
 323         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 324 };
 325
 326 /* timer9 */
 327 static struct omap_hwmod omap3xxx_timer9_hwmod = {
 328         .name           = "timer9",
 329         .main_clk       = "gpt9_fck",
 330         .prcm           = {
 331                 .omap2 = {
 332                         .prcm_reg_id = 1,
 333                         .module_bit = OMAP3430_EN_GPT9_SHIFT,
 334                         .module_offs = OMAP3430_PER_MOD,
 335                         .idlest_reg_id = 1,
 336                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
 337                 },
 338         },
 339         .dev_attr       = &capability_pwm_dev_attr,
 340         .class          = &omap3xxx_timer_hwmod_class,
 341         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 342 };
 343
 344 /* timer10 */
 345 static struct omap_hwmod omap3xxx_timer10_hwmod = {
 346         .name           = "timer10",
 347         .main_clk       = "gpt10_fck",
 348         .prcm           = {
 349                 .omap2 = {
 350                         .prcm_reg_id = 1,
 351                         .module_bit = OMAP3430_EN_GPT10_SHIFT,
 352                         .module_offs = CORE_MOD,
 353                         .idlest_reg_id = 1,
 354                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
 355                 },
 356         },
 357         .dev_attr       = &capability_pwm_dev_attr,
 358         .class          = &omap3xxx_timer_hwmod_class,
 359         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 360 };
 361
 362 /* timer11 */
 363 static struct omap_hwmod omap3xxx_timer11_hwmod = {
 364         .name           = "timer11",
 365         .main_clk       = "gpt11_fck",
 366         .prcm           = {
 367                 .omap2 = {
 368                         .prcm_reg_id = 1,
 369                         .module_bit = OMAP3430_EN_GPT11_SHIFT,
 370                         .module_offs = CORE_MOD,
 371                         .idlest_reg_id = 1,
 372                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
 373                 },
 374         },
 375         .dev_attr       = &capability_pwm_dev_attr,
 376         .class          = &omap3xxx_timer_hwmod_class,
 377         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 378 };
 379
 380 /* timer12 */
 381
 382 static struct omap_hwmod omap3xxx_timer12_hwmod = {
 383         .name           = "timer12",
 384         .main_clk       = "gpt12_fck",
 385         .prcm           = {
 386                 .omap2 = {
 387                         .prcm_reg_id = 1,
 388                         .module_bit = OMAP3430_EN_GPT12_SHIFT,
 389                         .module_offs = WKUP_MOD,
 390                         .idlest_reg_id = 1,
 391                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
 392                 },
 393         },
 394         .dev_attr       = &capability_secure_dev_attr,
 395         .class          = &omap3xxx_timer_hwmod_class,
 396         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 397 };
 398
 399 /*
 400  * 'wd_timer' class
 401  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 402  * overflow condition
 403  */
 404
 405 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
 406         .rev_offs       = 0x0000,
 407         .sysc_offs      = 0x0010,
 408         .syss_offs      = 0x0014,
 409         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
 410                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 411                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 412                            SYSS_HAS_RESET_STATUS),
 413         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 414         .sysc_fields    = &omap_hwmod_sysc_type1,
 415 };
 416
 417 /* I2C common */
 418 static struct omap_hwmod_class_sysconfig i2c_sysc = {
 419         .rev_offs       = 0x00,
 420         .sysc_offs      = 0x20,
 421         .syss_offs      = 0x10,
 422         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 423                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 424                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 425         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 426         .sysc_fields    = &omap_hwmod_sysc_type1,
 427 };
 428
 429 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
 430         .name           = "wd_timer",
 431         .sysc           = &omap3xxx_wd_timer_sysc,
 432         .pre_shutdown   = &omap2_wd_timer_disable,
 433         .reset          = &omap2_wd_timer_reset,
 434 };
 435
 436 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
 437         .name           = "wd_timer2",
 438         .class          = &omap3xxx_wd_timer_hwmod_class,
 439         .main_clk       = "wdt2_fck",
 440         .prcm           = {
 441                 .omap2 = {
 442                         .prcm_reg_id = 1,
 443                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
 444                         .module_offs = WKUP_MOD,
 445                         .idlest_reg_id = 1,
 446                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
 447                 },
 448         },
 449         /*
 450          * XXX: Use software supervised mode, HW supervised smartidle seems to
 451          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
 452          */
 453         .flags          = HWMOD_SWSUP_SIDLE,
 454 };
 455
 456 /* UART1 */
 457 static struct omap_hwmod omap3xxx_uart1_hwmod = {
 458         .name           = "uart1",
 459         .main_clk       = "uart1_fck",
 460         .flags          = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE,
 461         .prcm           = {
 462                 .omap2 = {
 463                         .module_offs = CORE_MOD,
 464                         .prcm_reg_id = 1,
 465                         .module_bit = OMAP3430_EN_UART1_SHIFT,
 466                         .idlest_reg_id = 1,
 467                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
 468                 },
 469         },
 470         .class          = &omap2_uart_class,
 471 };
 472
 473 /* UART2 */
 474 static struct omap_hwmod omap3xxx_uart2_hwmod = {
 475         .name           = "uart2",
 476         .main_clk       = "uart2_fck",
 477         .flags          = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE,
 478         .prcm           = {
 479                 .omap2 = {
 480                         .module_offs = CORE_MOD,
 481                         .prcm_reg_id = 1,
 482                         .module_bit = OMAP3430_EN_UART2_SHIFT,
 483                         .idlest_reg_id = 1,
 484                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
 485                 },
 486         },
 487         .class          = &omap2_uart_class,
 488 };
 489
 490 /* UART3 */
 491 static struct omap_hwmod omap3xxx_uart3_hwmod = {
 492         .name           = "uart3",
 493         .main_clk       = "uart3_fck",
 494         .flags          = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS |
 495                                 HWMOD_SWSUP_SIDLE,
 496         .prcm           = {
 497                 .omap2 = {
 498                         .module_offs = OMAP3430_PER_MOD,
 499                         .prcm_reg_id = 1,
 500                         .module_bit = OMAP3430_EN_UART3_SHIFT,
 501                         .idlest_reg_id = 1,
 502                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
 503                 },
 504         },
 505         .class          = &omap2_uart_class,
 506 };
 507
 508 /* UART4 */
 509
 510
 511 static struct omap_hwmod omap36xx_uart4_hwmod = {
 512         .name           = "uart4",
 513         .main_clk       = "uart4_fck",
 514         .flags          = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE,
 515         .prcm           = {
 516                 .omap2 = {
 517                         .module_offs = OMAP3430_PER_MOD,
 518                         .prcm_reg_id = 1,
 519                         .module_bit = OMAP3630_EN_UART4_SHIFT,
 520                         .idlest_reg_id = 1,
 521                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
 522                 },
 523         },
 524         .class          = &omap2_uart_class,
 525 };
 526
 527
 528
 529 /*
 530  * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
 531  * uart2_fck being enabled.  So we add uart1_fck as an optional clock,
 532  * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET.  This really
 533  * should not be needed.  The functional clock structure of the AM35xx
 534  * UART4 is extremely unclear and opaque; it is unclear what the role
 535  * of uart1/2_fck is for the UART4.  Any clarification from either
 536  * empirical testing or the AM3505/3517 hardware designers would be
 537  * most welcome.
 538  */
 539 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
 540         { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
 541 };
 542
 543 static struct omap_hwmod am35xx_uart4_hwmod = {
 544         .name           = "uart4",
 545         .main_clk       = "uart4_fck",
 546         .prcm           = {
 547                 .omap2 = {
 548                         .module_offs = CORE_MOD,
 549                         .prcm_reg_id = 1,
 550                         .module_bit = AM35XX_EN_UART4_SHIFT,
 551                         .idlest_reg_id = 1,
 552                         .idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
 553                 },
 554         },
 555         .opt_clks       = am35xx_uart4_opt_clks,
 556         .opt_clks_cnt   = ARRAY_SIZE(am35xx_uart4_opt_clks),
 557         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 558         .class          = &omap2_uart_class,
 559 };
 560
 561 static struct omap_hwmod_class i2c_class = {
 562         .name   = "i2c",
 563         .sysc   = &i2c_sysc,
 564         .rev    = OMAP_I2C_IP_VERSION_1,
 565         .reset  = &omap_i2c_reset,
 566 };
 567
 568 /* dss */
 569 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 570         /*
 571          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
 572          * driver does not use these clocks.
 573          */
 574         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 575         { .role = "tv_clk", .clk = "dss_tv_fck" },
 576         /* required only on OMAP3430 */
 577         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 578 };
 579
 580 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
 581         .name           = "dss_core",
 582         .class          = &omap2_dss_hwmod_class,
 583         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 584         .prcm           = {
 585                 .omap2 = {
 586                         .prcm_reg_id = 1,
 587                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 588                         .module_offs = OMAP3430_DSS_MOD,
 589                         .idlest_reg_id = 1,
 590                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
 591                 },
 592         },
 593         .opt_clks       = dss_opt_clks,
 594         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 595         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 596 };
 597
 598 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
 599         .name           = "dss_core",
 600         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 601         .class          = &omap2_dss_hwmod_class,
 602         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 603         .prcm           = {
 604                 .omap2 = {
 605                         .prcm_reg_id = 1,
 606                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 607                         .module_offs = OMAP3430_DSS_MOD,
 608                         .idlest_reg_id = 1,
 609                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
 610                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
 611                 },
 612         },
 613         .opt_clks       = dss_opt_clks,
 614         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 615 };
 616
 617 /*
 618  * 'dispc' class
 619  * display controller
 620  */
 621
 622 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
 623         .rev_offs       = 0x0000,
 624         .sysc_offs      = 0x0010,
 625         .syss_offs      = 0x0014,
 626         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 627                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 628                            SYSC_HAS_ENAWAKEUP),
 629         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 630                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 631         .sysc_fields    = &omap_hwmod_sysc_type1,
 632 };
 633
 634 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
 635         .name   = "dispc",
 636         .sysc   = &omap3_dispc_sysc,
 637 };
 638
 639 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
 640         .name           = "dss_dispc",
 641         .class          = &omap3_dispc_hwmod_class,
 642         .main_clk       = "dss1_alwon_fck",
 643         .prcm           = {
 644                 .omap2 = {
 645                         .prcm_reg_id = 1,
 646                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 647                         .module_offs = OMAP3430_DSS_MOD,
 648                 },
 649         },
 650         .flags          = HWMOD_NO_IDLEST,
 651         .dev_attr       = &omap2_3_dss_dispc_dev_attr,
 652 };
 653
 654 /*
 655  * 'dsi' class
 656  * display serial interface controller
 657  */
 658
 659 static struct omap_hwmod_class_sysconfig omap3xxx_dsi_sysc = {
 660         .rev_offs       = 0x0000,
 661         .sysc_offs      = 0x0010,
 662         .syss_offs      = 0x0014,
 663         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 664                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 665                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 666         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 667         .sysc_fields    = &omap_hwmod_sysc_type1,
 668 };
 669
 670 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
 671         .name = "dsi",
 672         .sysc   = &omap3xxx_dsi_sysc,
 673 };
 674
 675 /* dss_dsi1 */
 676 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 677         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 678 };
 679
 680 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
 681         .name           = "dss_dsi1",
 682         .class          = &omap3xxx_dsi_hwmod_class,
 683         .main_clk       = "dss1_alwon_fck",
 684         .prcm           = {
 685                 .omap2 = {
 686                         .prcm_reg_id = 1,
 687                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 688                         .module_offs = OMAP3430_DSS_MOD,
 689                 },
 690         },
 691         .opt_clks       = dss_dsi1_opt_clks,
 692         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 693         .flags          = HWMOD_NO_IDLEST,
 694 };
 695
 696 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 697         { .role = "ick", .clk = "dss_ick" },
 698 };
 699
 700 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
 701         .name           = "dss_rfbi",
 702         .class          = &omap2_rfbi_hwmod_class,
 703         .main_clk       = "dss1_alwon_fck",
 704         .prcm           = {
 705                 .omap2 = {
 706                         .prcm_reg_id = 1,
 707                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 708                         .module_offs = OMAP3430_DSS_MOD,
 709                 },
 710         },
 711         .opt_clks       = dss_rfbi_opt_clks,
 712         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 713         .flags          = HWMOD_NO_IDLEST,
 714 };
 715
 716 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
 717         /* required only on OMAP3430 */
 718         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 719 };
 720
 721 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
 722         .name           = "dss_venc",
 723         .class          = &omap2_venc_hwmod_class,
 724         .main_clk       = "dss_tv_fck",
 725         .prcm           = {
 726                 .omap2 = {
 727                         .prcm_reg_id = 1,
 728                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 729                         .module_offs = OMAP3430_DSS_MOD,
 730                 },
 731         },
 732         .opt_clks       = dss_venc_opt_clks,
 733         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
 734         .flags          = HWMOD_NO_IDLEST,
 735 };
 736
 737 /* I2C1 */
 738 static struct omap_i2c_dev_attr i2c1_dev_attr = {
 739         .fifo_depth     = 8, /* bytes */
 740         .flags          = OMAP_I2C_FLAG_BUS_SHIFT_2,
 741 };
 742
 743 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
 744         .name           = "i2c1",
 745         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 746         .main_clk       = "i2c1_fck",
 747         .prcm           = {
 748                 .omap2 = {
 749                         .module_offs = CORE_MOD,
 750                         .prcm_reg_id = 1,
 751                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
 752                         .idlest_reg_id = 1,
 753                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
 754                 },
 755         },
 756         .class          = &i2c_class,
 757         .dev_attr       = &i2c1_dev_attr,
 758 };
 759
 760 /* I2C2 */
 761 static struct omap_i2c_dev_attr i2c2_dev_attr = {
 762         .fifo_depth     = 8, /* bytes */
 763         .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
 764 };
 765
 766 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
 767         .name           = "i2c2",
 768         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 769         .main_clk       = "i2c2_fck",
 770         .prcm           = {
 771                 .omap2 = {
 772                         .module_offs = CORE_MOD,
 773                         .prcm_reg_id = 1,
 774                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
 775                         .idlest_reg_id = 1,
 776                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
 777                 },
 778         },
 779         .class          = &i2c_class,
 780         .dev_attr       = &i2c2_dev_attr,
 781 };
 782
 783 /* I2C3 */
 784 static struct omap_i2c_dev_attr i2c3_dev_attr = {
 785         .fifo_depth     = 64, /* bytes */
 786         .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
 787 };
 788
 789
 790
 791 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
 792         .name           = "i2c3",
 793         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 794         .main_clk       = "i2c3_fck",
 795         .prcm           = {
 796                 .omap2 = {
 797                         .module_offs = CORE_MOD,
 798                         .prcm_reg_id = 1,
 799                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
 800                         .idlest_reg_id = 1,
 801                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
 802                 },
 803         },
 804         .class          = &i2c_class,
 805         .dev_attr       = &i2c3_dev_attr,
 806 };
 807
 808 /*
 809  * 'gpio' class
 810  * general purpose io module
 811  */
 812
 813 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
 814         .rev_offs       = 0x0000,
 815         .sysc_offs      = 0x0010,
 816         .syss_offs      = 0x0014,
 817         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 818                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 819                            SYSS_HAS_RESET_STATUS),
 820         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 821         .sysc_fields    = &omap_hwmod_sysc_type1,
 822 };
 823
 824 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
 825         .name = "gpio",
 826         .sysc = &omap3xxx_gpio_sysc,
 827         .rev = 1,
 828 };
 829
 830 /* gpio_dev_attr */
 831 static struct omap_gpio_dev_attr gpio_dev_attr = {
 832         .bank_width = 32,
 833         .dbck_flag = true,
 834 };
 835
 836 /* gpio1 */
 837 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 838         { .role = "dbclk", .clk = "gpio1_dbck", },
 839 };
 840
 841 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
 842         .name           = "gpio1",
 843         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 844         .main_clk       = "gpio1_ick",
 845         .opt_clks       = gpio1_opt_clks,
 846         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 847         .prcm           = {
 848                 .omap2 = {
 849                         .prcm_reg_id = 1,
 850                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
 851                         .module_offs = WKUP_MOD,
 852                         .idlest_reg_id = 1,
 853                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
 854                 },
 855         },
 856         .class          = &omap3xxx_gpio_hwmod_class,
 857         .dev_attr       = &gpio_dev_attr,
 858 };
 859
 860 /* gpio2 */
 861 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 862         { .role = "dbclk", .clk = "gpio2_dbck", },
 863 };
 864
 865 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
 866         .name           = "gpio2",
 867         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 868         .main_clk       = "gpio2_ick",
 869         .opt_clks       = gpio2_opt_clks,
 870         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 871         .prcm           = {
 872                 .omap2 = {
 873                         .prcm_reg_id = 1,
 874                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
 875                         .module_offs = OMAP3430_PER_MOD,
 876                         .idlest_reg_id = 1,
 877                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
 878                 },
 879         },
 880         .class          = &omap3xxx_gpio_hwmod_class,
 881         .dev_attr       = &gpio_dev_attr,
 882 };
 883
 884 /* gpio3 */
 885 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 886         { .role = "dbclk", .clk = "gpio3_dbck", },
 887 };
 888
 889 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
 890         .name           = "gpio3",
 891         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 892         .main_clk       = "gpio3_ick",
 893         .opt_clks       = gpio3_opt_clks,
 894         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 895         .prcm           = {
 896                 .omap2 = {
 897                         .prcm_reg_id = 1,
 898                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
 899                         .module_offs = OMAP3430_PER_MOD,
 900                         .idlest_reg_id = 1,
 901                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
 902                 },
 903         },
 904         .class          = &omap3xxx_gpio_hwmod_class,
 905         .dev_attr       = &gpio_dev_attr,
 906 };
 907
 908 /* gpio4 */
 909 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 910         { .role = "dbclk", .clk = "gpio4_dbck", },
 911 };
 912
 913 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
 914         .name           = "gpio4",
 915         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 916         .main_clk       = "gpio4_ick",
 917         .opt_clks       = gpio4_opt_clks,
 918         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 919         .prcm           = {
 920                 .omap2 = {
 921                         .prcm_reg_id = 1,
 922                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
 923                         .module_offs = OMAP3430_PER_MOD,
 924                         .idlest_reg_id = 1,
 925                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
 926                 },
 927         },
 928         .class          = &omap3xxx_gpio_hwmod_class,
 929         .dev_attr       = &gpio_dev_attr,
 930 };
 931
 932 /* gpio5 */
 933
 934 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 935         { .role = "dbclk", .clk = "gpio5_dbck", },
 936 };
 937
 938 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
 939         .name           = "gpio5",
 940         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 941         .main_clk       = "gpio5_ick",
 942         .opt_clks       = gpio5_opt_clks,
 943         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
 944         .prcm           = {
 945                 .omap2 = {
 946                         .prcm_reg_id = 1,
 947                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
 948                         .module_offs = OMAP3430_PER_MOD,
 949                         .idlest_reg_id = 1,
 950                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
 951                 },
 952         },
 953         .class          = &omap3xxx_gpio_hwmod_class,
 954         .dev_attr       = &gpio_dev_attr,
 955 };
 956
 957 /* gpio6 */
 958
 959 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
 960         { .role = "dbclk", .clk = "gpio6_dbck", },
 961 };
 962
 963 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
 964         .name           = "gpio6",
 965         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 966         .main_clk       = "gpio6_ick",
 967         .opt_clks       = gpio6_opt_clks,
 968         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
 969         .prcm           = {
 970                 .omap2 = {
 971                         .prcm_reg_id = 1,
 972                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
 973                         .module_offs = OMAP3430_PER_MOD,
 974                         .idlest_reg_id = 1,
 975                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
 976                 },
 977         },
 978         .class          = &omap3xxx_gpio_hwmod_class,
 979         .dev_attr       = &gpio_dev_attr,
 980 };
 981
 982 /* dma attributes */
 983 static struct omap_dma_dev_attr dma_dev_attr = {
 984         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 985                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 986         .lch_count = 32,
 987 };
 988
 989 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
 990         .rev_offs       = 0x0000,
 991         .sysc_offs      = 0x002c,
 992         .syss_offs      = 0x0028,
 993         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 994                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 995                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
 996                            SYSS_HAS_RESET_STATUS),
 997         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 998                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 999         .sysc_fields    = &omap_hwmod_sysc_type1,
1000 };
1001
1002 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1003         .name = "dma",
1004         .sysc = &omap3xxx_dma_sysc,
1005 };
1006
1007 /* dma_system */
1008 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1009         .name           = "dma",
1010         .class          = &omap3xxx_dma_hwmod_class,
1011         .main_clk       = "core_l3_ick",
1012         .prcm = {
1013                 .omap2 = {
1014                         .module_offs            = CORE_MOD,
1015                         .prcm_reg_id            = 1,
1016                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
1017                         .idlest_reg_id          = 1,
1018                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
1019                 },
1020         },
1021         .dev_attr       = &dma_dev_attr,
1022         .flags          = HWMOD_NO_IDLEST,
1023 };
1024
1025 /*
1026  * 'mcbsp' class
1027  * multi channel buffered serial port controller
1028  */
1029
1030 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1031         .sysc_offs      = 0x008c,
1032         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1033                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1034         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1035         .sysc_fields    = &omap_hwmod_sysc_type1,
1036 };
1037
1038 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1039         .name = "mcbsp",
1040         .sysc = &omap3xxx_mcbsp_sysc,
1041         .rev  = MCBSP_CONFIG_TYPE3,
1042 };
1043
1044 /* McBSP functional clock mapping */
1045 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
1046         { .role = "pad_fck", .clk = "mcbsp_clks" },
1047         { .role = "prcm_fck", .clk = "core_96m_fck" },
1048 };
1049
1050 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
1051         { .role = "pad_fck", .clk = "mcbsp_clks" },
1052         { .role = "prcm_fck", .clk = "per_96m_fck" },
1053 };
1054
1055 /* mcbsp1 */
1056
1057 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1058         .name           = "mcbsp1",
1059         .class          = &omap3xxx_mcbsp_hwmod_class,
1060         .main_clk       = "mcbsp1_fck",
1061         .prcm           = {
1062                 .omap2 = {
1063                         .prcm_reg_id = 1,
1064                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1065                         .module_offs = CORE_MOD,
1066                         .idlest_reg_id = 1,
1067                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1068                 },
1069         },
1070         .opt_clks       = mcbsp15_opt_clks,
1071         .opt_clks_cnt   = ARRAY_SIZE(mcbsp15_opt_clks),
1072 };
1073
1074 /* mcbsp2 */
1075
1076 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1077         .sidetone       = "mcbsp2_sidetone",
1078 };
1079
1080 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1081         .name           = "mcbsp2",
1082         .class          = &omap3xxx_mcbsp_hwmod_class,
1083         .main_clk       = "mcbsp2_fck",
1084         .prcm           = {
1085                 .omap2 = {
1086                         .prcm_reg_id = 1,
1087                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1088                         .module_offs = OMAP3430_PER_MOD,
1089                         .idlest_reg_id = 1,
1090                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1091                 },
1092         },
1093         .opt_clks       = mcbsp234_opt_clks,
1094         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1095         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
1096 };
1097
1098 /* mcbsp3 */
1099
1100 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1101         .sidetone       = "mcbsp3_sidetone",
1102 };
1103
1104 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1105         .name           = "mcbsp3",
1106         .class          = &omap3xxx_mcbsp_hwmod_class,
1107         .main_clk       = "mcbsp3_fck",
1108         .prcm           = {
1109                 .omap2 = {
1110                         .prcm_reg_id = 1,
1111                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1112                         .module_offs = OMAP3430_PER_MOD,
1113                         .idlest_reg_id = 1,
1114                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1115                 },
1116         },
1117         .opt_clks       = mcbsp234_opt_clks,
1118         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1119         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
1120 };
1121
1122 /* mcbsp4 */
1123
1124
1125 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1126         .name           = "mcbsp4",
1127         .class          = &omap3xxx_mcbsp_hwmod_class,
1128         .main_clk       = "mcbsp4_fck",
1129         .prcm           = {
1130                 .omap2 = {
1131                         .prcm_reg_id = 1,
1132                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1133                         .module_offs = OMAP3430_PER_MOD,
1134                         .idlest_reg_id = 1,
1135                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1136                 },
1137         },
1138         .opt_clks       = mcbsp234_opt_clks,
1139         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1140 };
1141
1142 /* mcbsp5 */
1143
1144
1145 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1146         .name           = "mcbsp5",
1147         .class          = &omap3xxx_mcbsp_hwmod_class,
1148         .main_clk       = "mcbsp5_fck",
1149         .prcm           = {
1150                 .omap2 = {
1151                         .prcm_reg_id = 1,
1152                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
1153                         .module_offs = CORE_MOD,
1154                         .idlest_reg_id = 1,
1155                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1156                 },
1157         },
1158         .opt_clks       = mcbsp15_opt_clks,
1159         .opt_clks_cnt   = ARRAY_SIZE(mcbsp15_opt_clks),
1160 };
1161
1162 /* 'mcbsp sidetone' class */
1163 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
1164         .sysc_offs      = 0x0010,
1165         .sysc_flags     = SYSC_HAS_AUTOIDLE,
1166         .sysc_fields    = &omap_hwmod_sysc_type1,
1167 };
1168
1169 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1170         .name = "mcbsp_sidetone",
1171         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
1172 };
1173
1174 /* mcbsp2_sidetone */
1175
1176 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1177         .name           = "mcbsp2_sidetone",
1178         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
1179         .main_clk       = "mcbsp2_ick",
1180         .flags          = HWMOD_NO_IDLEST,
1181 };
1182
1183 /* mcbsp3_sidetone */
1184
1185 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1186         .name           = "mcbsp3_sidetone",
1187         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
1188         .main_clk       = "mcbsp3_ick",
1189         .flags          = HWMOD_NO_IDLEST,
1190 };
1191
1192 /* SR common */
1193 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1194         .clkact_shift   = 20,
1195 };
1196
1197 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1198         .sysc_offs      = 0x24,
1199         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1200         .sysc_fields    = &omap34xx_sr_sysc_fields,
1201 };
1202
1203 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1204         .name = "smartreflex",
1205         .sysc = &omap34xx_sr_sysc,
1206         .rev  = 1,
1207 };
1208
1209 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1210         .sidle_shift    = 24,
1211         .enwkup_shift   = 26,
1212 };
1213
1214 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1215         .sysc_offs      = 0x38,
1216         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1217         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1218                         SYSC_NO_CACHE),
1219         .sysc_fields    = &omap36xx_sr_sysc_fields,
1220 };
1221
1222 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1223         .name = "smartreflex",
1224         .sysc = &omap36xx_sr_sysc,
1225         .rev  = 2,
1226 };
1227
1228 /* SR1 */
1229 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1230         .sensor_voltdm_name   = "mpu_iva",
1231 };
1232
1233
1234 static struct omap_hwmod omap34xx_sr1_hwmod = {
1235         .name           = "smartreflex_mpu_iva",
1236         .class          = &omap34xx_smartreflex_hwmod_class,
1237         .main_clk       = "sr1_fck",
1238         .prcm           = {
1239                 .omap2 = {
1240                         .prcm_reg_id = 1,
1241                         .module_bit = OMAP3430_EN_SR1_SHIFT,
1242                         .module_offs = WKUP_MOD,
1243                         .idlest_reg_id = 1,
1244                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1245                 },
1246         },
1247         .dev_attr       = &sr1_dev_attr,
1248         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1249 };
1250
1251 static struct omap_hwmod omap36xx_sr1_hwmod = {
1252         .name           = "smartreflex_mpu_iva",
1253         .class          = &omap36xx_smartreflex_hwmod_class,
1254         .main_clk       = "sr1_fck",
1255         .prcm           = {
1256                 .omap2 = {
1257                         .prcm_reg_id = 1,
1258                         .module_bit = OMAP3430_EN_SR1_SHIFT,
1259                         .module_offs = WKUP_MOD,
1260                         .idlest_reg_id = 1,
1261                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1262                 },
1263         },
1264         .dev_attr       = &sr1_dev_attr,
1265 };
1266
1267 /* SR2 */
1268 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1269         .sensor_voltdm_name     = "core",
1270 };
1271
1272
1273 static struct omap_hwmod omap34xx_sr2_hwmod = {
1274         .name           = "smartreflex_core",
1275         .class          = &omap34xx_smartreflex_hwmod_class,
1276         .main_clk       = "sr2_fck",
1277         .prcm           = {
1278                 .omap2 = {
1279                         .prcm_reg_id = 1,
1280                         .module_bit = OMAP3430_EN_SR2_SHIFT,
1281                         .module_offs = WKUP_MOD,
1282                         .idlest_reg_id = 1,
1283                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1284                 },
1285         },
1286         .dev_attr       = &sr2_dev_attr,
1287         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1288 };
1289
1290 static struct omap_hwmod omap36xx_sr2_hwmod = {
1291         .name           = "smartreflex_core",
1292         .class          = &omap36xx_smartreflex_hwmod_class,
1293         .main_clk       = "sr2_fck",
1294         .prcm           = {
1295                 .omap2 = {
1296                         .prcm_reg_id = 1,
1297                         .module_bit = OMAP3430_EN_SR2_SHIFT,
1298                         .module_offs = WKUP_MOD,
1299                         .idlest_reg_id = 1,
1300                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1301                 },
1302         },
1303         .dev_attr       = &sr2_dev_attr,
1304 };
1305
1306 /*
1307  * 'mailbox' class
1308  * mailbox module allowing communication between the on-chip processors
1309  * using a queued mailbox-interrupt mechanism.
1310  */
1311
1312 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1313         .rev_offs       = 0x000,
1314         .sysc_offs      = 0x010,
1315         .syss_offs      = 0x014,
1316         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1317                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1318         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1319         .sysc_fields    = &omap_hwmod_sysc_type1,
1320 };
1321
1322 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1323         .name = "mailbox",
1324         .sysc = &omap3xxx_mailbox_sysc,
1325 };
1326
1327 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1328         .name           = "mailbox",
1329         .class          = &omap3xxx_mailbox_hwmod_class,
1330         .main_clk       = "mailboxes_ick",
1331         .prcm           = {
1332                 .omap2 = {
1333                         .prcm_reg_id = 1,
1334                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1335                         .module_offs = CORE_MOD,
1336                         .idlest_reg_id = 1,
1337                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1338                 },
1339         },
1340 };
1341
1342 /*
1343  * 'mcspi' class
1344  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1345  * bus
1346  */
1347
1348 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1349         .rev_offs       = 0x0000,
1350         .sysc_offs      = 0x0010,
1351         .syss_offs      = 0x0014,
1352         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1353                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1354                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1355         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1356         .sysc_fields    = &omap_hwmod_sysc_type1,
1357 };
1358
1359 static struct omap_hwmod_class omap34xx_mcspi_class = {
1360         .name = "mcspi",
1361         .sysc = &omap34xx_mcspi_sysc,
1362         .rev = OMAP3_MCSPI_REV,
1363 };
1364
1365 /* mcspi1 */
1366 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1367         .num_chipselect = 4,
1368 };
1369
1370 static struct omap_hwmod omap34xx_mcspi1 = {
1371         .name           = "mcspi1",
1372         .main_clk       = "mcspi1_fck",
1373         .prcm           = {
1374                 .omap2 = {
1375                         .module_offs = CORE_MOD,
1376                         .prcm_reg_id = 1,
1377                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1378                         .idlest_reg_id = 1,
1379                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1380                 },
1381         },
1382         .class          = &omap34xx_mcspi_class,
1383         .dev_attr       = &omap_mcspi1_dev_attr,
1384 };
1385
1386 /* mcspi2 */
1387 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1388         .num_chipselect = 2,
1389 };
1390
1391 static struct omap_hwmod omap34xx_mcspi2 = {
1392         .name           = "mcspi2",
1393         .main_clk       = "mcspi2_fck",
1394         .prcm           = {
1395                 .omap2 = {
1396                         .module_offs = CORE_MOD,
1397                         .prcm_reg_id = 1,
1398                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1399                         .idlest_reg_id = 1,
1400                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1401                 },
1402         },
1403         .class          = &omap34xx_mcspi_class,
1404         .dev_attr       = &omap_mcspi2_dev_attr,
1405 };
1406
1407 /* mcspi3 */
1408
1409
1410 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1411         .num_chipselect = 2,
1412 };
1413
1414 static struct omap_hwmod omap34xx_mcspi3 = {
1415         .name           = "mcspi3",
1416         .main_clk       = "mcspi3_fck",
1417         .prcm           = {
1418                 .omap2 = {
1419                         .module_offs = CORE_MOD,
1420                         .prcm_reg_id = 1,
1421                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1422                         .idlest_reg_id = 1,
1423                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1424                 },
1425         },
1426         .class          = &omap34xx_mcspi_class,
1427         .dev_attr       = &omap_mcspi3_dev_attr,
1428 };
1429
1430 /* mcspi4 */
1431
1432
1433 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1434         .num_chipselect = 1,
1435 };
1436
1437 static struct omap_hwmod omap34xx_mcspi4 = {
1438         .name           = "mcspi4",
1439         .main_clk       = "mcspi4_fck",
1440         .prcm           = {
1441                 .omap2 = {
1442                         .module_offs = CORE_MOD,
1443                         .prcm_reg_id = 1,
1444                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1445                         .idlest_reg_id = 1,
1446                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1447                 },
1448         },
1449         .class          = &omap34xx_mcspi_class,
1450         .dev_attr       = &omap_mcspi4_dev_attr,
1451 };
1452
1453 /* usbhsotg */
1454 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1455         .rev_offs       = 0x0400,
1456         .sysc_offs      = 0x0404,
1457         .syss_offs      = 0x0408,
1458         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1459                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1460                           SYSC_HAS_AUTOIDLE),
1461         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1462                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1463         .sysc_fields    = &omap_hwmod_sysc_type1,
1464 };
1465
1466 static struct omap_hwmod_class usbotg_class = {
1467         .name = "usbotg",
1468         .sysc = &omap3xxx_usbhsotg_sysc,
1469 };
1470
1471 /* usb_otg_hs */
1472
1473 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1474         .name           = "usb_otg_hs",
1475         .main_clk       = "hsotgusb_ick",
1476         .prcm           = {
1477                 .omap2 = {
1478                         .prcm_reg_id = 1,
1479                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1480                         .module_offs = CORE_MOD,
1481                         .idlest_reg_id = 1,
1482                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1483                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT,
1484                 },
1485         },
1486         .class          = &usbotg_class,
1487
1488         /*
1489          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
1490          * broken when autoidle is enabled
1491          * workaround is to disable the autoidle bit at module level.
1492          *
1493          * Enabling the device in any other MIDLEMODE setting but force-idle
1494          * causes core_pwrdm not enter idle states at least on OMAP3630.
1495          * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
1496          * signal when MIDLEMODE is set to force-idle.
1497          */
1498         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE |
1499                           HWMOD_FORCE_MSTANDBY | HWMOD_RECONFIG_IO_CHAIN,
1500 };
1501
1502 /* usb_otg_hs */
1503
1504 static struct omap_hwmod_class am35xx_usbotg_class = {
1505         .name = "am35xx_usbotg",
1506 };
1507
1508 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1509         .name           = "am35x_otg_hs",
1510         .main_clk       = "hsotgusb_fck",
1511         .class          = &am35xx_usbotg_class,
1512         .flags          = HWMOD_NO_IDLEST,
1513 };
1514
1515 /* MMC/SD/SDIO common */
1516 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1517         .rev_offs       = 0x1fc,
1518         .sysc_offs      = 0x10,
1519         .syss_offs      = 0x14,
1520         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1521                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1522                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1523         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1524         .sysc_fields    = &omap_hwmod_sysc_type1,
1525 };
1526
1527 static struct omap_hwmod_class omap34xx_mmc_class = {
1528         .name = "mmc",
1529         .sysc = &omap34xx_mmc_sysc,
1530 };
1531
1532 /* MMC/SD/SDIO1 */
1533
1534
1535
1536 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1537         { .role = "dbck", .clk = "omap_32k_fck", },
1538 };
1539
1540 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1541         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1542 };
1543
1544 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1545 static struct omap_hsmmc_dev_attr mmc1_pre_es3_dev_attr = {
1546         .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1547                   OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1548 };
1549
1550 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1551         .name           = "mmc1",
1552         .opt_clks       = omap34xx_mmc1_opt_clks,
1553         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1554         .main_clk       = "mmchs1_fck",
1555         .prcm           = {
1556                 .omap2 = {
1557                         .module_offs = CORE_MOD,
1558                         .prcm_reg_id = 1,
1559                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
1560                         .idlest_reg_id = 1,
1561                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1562                 },
1563         },
1564         .dev_attr       = &mmc1_pre_es3_dev_attr,
1565         .class          = &omap34xx_mmc_class,
1566 };
1567
1568 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1569         .name           = "mmc1",
1570         .opt_clks       = omap34xx_mmc1_opt_clks,
1571         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1572         .main_clk       = "mmchs1_fck",
1573         .prcm           = {
1574                 .omap2 = {
1575                         .module_offs = CORE_MOD,
1576                         .prcm_reg_id = 1,
1577                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
1578                         .idlest_reg_id = 1,
1579                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1580                 },
1581         },
1582         .dev_attr       = &mmc1_dev_attr,
1583         .class          = &omap34xx_mmc_class,
1584 };
1585
1586 /* MMC/SD/SDIO2 */
1587
1588
1589
1590 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1591         { .role = "dbck", .clk = "omap_32k_fck", },
1592 };
1593
1594 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1595 static struct omap_hsmmc_dev_attr mmc2_pre_es3_dev_attr = {
1596         .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1597 };
1598
1599 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1600         .name           = "mmc2",
1601         .opt_clks       = omap34xx_mmc2_opt_clks,
1602         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1603         .main_clk       = "mmchs2_fck",
1604         .prcm           = {
1605                 .omap2 = {
1606                         .module_offs = CORE_MOD,
1607                         .prcm_reg_id = 1,
1608                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
1609                         .idlest_reg_id = 1,
1610                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1611                 },
1612         },
1613         .dev_attr       = &mmc2_pre_es3_dev_attr,
1614         .class          = &omap34xx_mmc_class,
1615 };
1616
1617 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1618         .name           = "mmc2",
1619         .opt_clks       = omap34xx_mmc2_opt_clks,
1620         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1621         .main_clk       = "mmchs2_fck",
1622         .prcm           = {
1623                 .omap2 = {
1624                         .module_offs = CORE_MOD,
1625                         .prcm_reg_id = 1,
1626                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
1627                         .idlest_reg_id = 1,
1628                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1629                 },
1630         },
1631         .class          = &omap34xx_mmc_class,
1632 };
1633
1634 /* MMC/SD/SDIO3 */
1635
1636
1637
1638 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1639         { .role = "dbck", .clk = "omap_32k_fck", },
1640 };
1641
1642 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1643         .name           = "mmc3",
1644         .opt_clks       = omap34xx_mmc3_opt_clks,
1645         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1646         .main_clk       = "mmchs3_fck",
1647         .prcm           = {
1648                 .omap2 = {
1649                         .module_offs = CORE_MOD,
1650                         .prcm_reg_id = 1,
1651                         .module_bit = OMAP3430_EN_MMC3_SHIFT,
1652                         .idlest_reg_id = 1,
1653                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1654                 },
1655         },
1656         .class          = &omap34xx_mmc_class,
1657 };
1658
1659 /*
1660  * 'usb_host_hs' class
1661  * high-speed multi-port usb host controller
1662  */
1663
1664 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1665         .rev_offs       = 0x0000,
1666         .sysc_offs      = 0x0010,
1667         .syss_offs      = 0x0014,
1668         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1669                            SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1670                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1671                            SYSS_HAS_RESET_STATUS),
1672         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1673                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1674         .sysc_fields    = &omap_hwmod_sysc_type1,
1675 };
1676
1677 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1678         .name = "usb_host_hs",
1679         .sysc = &omap3xxx_usb_host_hs_sysc,
1680 };
1681
1682
1683 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1684         .name           = "usb_host_hs",
1685         .class          = &omap3xxx_usb_host_hs_hwmod_class,
1686         .clkdm_name     = "usbhost_clkdm",
1687         .main_clk       = "usbhost_48m_fck",
1688         .prcm = {
1689                 .omap2 = {
1690                         .module_offs = OMAP3430ES2_USBHOST_MOD,
1691                         .prcm_reg_id = 1,
1692                         .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
1693                         .idlest_reg_id = 1,
1694                         .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1695                         .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
1696                 },
1697         },
1698
1699         /*
1700          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1701          * id: i660
1702          *
1703          * Description:
1704          * In the following configuration :
1705          * - USBHOST module is set to smart-idle mode
1706          * - PRCM asserts idle_req to the USBHOST module ( This typically
1707          *   happens when the system is going to a low power mode : all ports
1708          *   have been suspended, the master part of the USBHOST module has
1709          *   entered the standby state, and SW has cut the functional clocks)
1710          * - an USBHOST interrupt occurs before the module is able to answer
1711          *   idle_ack, typically a remote wakeup IRQ.
1712          * Then the USB HOST module will enter a deadlock situation where it
1713          * is no more accessible nor functional.
1714          *
1715          * Workaround:
1716          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1717          */
1718
1719         /*
1720          * Errata: USB host EHCI may stall when entering smart-standby mode
1721          * Id: i571
1722          *
1723          * Description:
1724          * When the USBHOST module is set to smart-standby mode, and when it is
1725          * ready to enter the standby state (i.e. all ports are suspended and
1726          * all attached devices are in suspend mode), then it can wrongly assert
1727          * the Mstandby signal too early while there are still some residual OCP
1728          * transactions ongoing. If this condition occurs, the internal state
1729          * machine may go to an undefined state and the USB link may be stuck
1730          * upon the next resume.
1731          *
1732          * Workaround:
1733          * Don't use smart standby; use only force standby,
1734          * hence HWMOD_SWSUP_MSTANDBY
1735          */
1736
1737         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1738 };
1739
1740 /*
1741  * 'usb_tll_hs' class
1742  * usb_tll_hs module is the adapter on the usb_host_hs ports
1743  */
1744 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
1745         .rev_offs       = 0x0000,
1746         .sysc_offs      = 0x0010,
1747         .syss_offs      = 0x0014,
1748         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1749                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1750                            SYSC_HAS_AUTOIDLE),
1751         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1752         .sysc_fields    = &omap_hwmod_sysc_type1,
1753 };
1754
1755 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
1756         .name = "usb_tll_hs",
1757         .sysc = &omap3xxx_usb_tll_hs_sysc,
1758 };
1759
1760
1761 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
1762         .name           = "usb_tll_hs",
1763         .class          = &omap3xxx_usb_tll_hs_hwmod_class,
1764         .clkdm_name     = "core_l4_clkdm",
1765         .main_clk       = "usbtll_fck",
1766         .prcm = {
1767                 .omap2 = {
1768                         .module_offs = CORE_MOD,
1769                         .prcm_reg_id = 3,
1770                         .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1771                         .idlest_reg_id = 3,
1772                         .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
1773                 },
1774         },
1775 };
1776
1777 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
1778         .name           = "hdq1w",
1779         .main_clk       = "hdq_fck",
1780         .prcm           = {
1781                 .omap2 = {
1782                         .module_offs = CORE_MOD,
1783                         .prcm_reg_id = 1,
1784                         .module_bit = OMAP3430_EN_HDQ_SHIFT,
1785                         .idlest_reg_id = 1,
1786                         .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
1787                 },
1788         },
1789         .class          = &omap2_hdq1w_class,
1790 };
1791
1792 /* SAD2D */
1793 static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
1794         { .name = "rst_modem_pwron_sw", .rst_shift = 0 },
1795         { .name = "rst_modem_sw", .rst_shift = 1 },
1796 };
1797
1798 static struct omap_hwmod_class omap3xxx_sad2d_class = {
1799         .name                   = "sad2d",
1800 };
1801
1802 static struct omap_hwmod omap3xxx_sad2d_hwmod = {
1803         .name           = "sad2d",
1804         .rst_lines      = omap3xxx_sad2d_resets,
1805         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_sad2d_resets),
1806         .main_clk       = "sad2d_ick",
1807         .prcm           = {
1808                 .omap2 = {
1809                         .module_offs = CORE_MOD,
1810                         .prcm_reg_id = 1,
1811                         .module_bit = OMAP3430_EN_SAD2D_SHIFT,
1812                         .idlest_reg_id = 1,
1813                         .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
1814                 },
1815         },
1816         .class          = &omap3xxx_sad2d_class,
1817 };
1818
1819 /*
1820  * '32K sync counter' class
1821  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
1822  */
1823 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
1824         .rev_offs       = 0x0000,
1825         .sysc_offs      = 0x0004,
1826         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1827         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
1828         .sysc_fields    = &omap_hwmod_sysc_type1,
1829 };
1830
1831 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
1832         .name   = "counter",
1833         .sysc   = &omap3xxx_counter_sysc,
1834 };
1835
1836 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
1837         .name           = "counter_32k",
1838         .class          = &omap3xxx_counter_hwmod_class,
1839         .clkdm_name     = "wkup_clkdm",
1840         .flags          = HWMOD_SWSUP_SIDLE,
1841         .main_clk       = "wkup_32k_fck",
1842         .prcm           = {
1843                 .omap2  = {
1844                         .module_offs = WKUP_MOD,
1845                         .prcm_reg_id = 1,
1846                         .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
1847                         .idlest_reg_id = 1,
1848                         .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
1849                 },
1850         },
1851 };
1852
1853 /*
1854  * 'gpmc' class
1855  * general purpose memory controller
1856  */
1857
1858 static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
1859         .rev_offs       = 0x0000,
1860         .sysc_offs      = 0x0010,
1861         .syss_offs      = 0x0014,
1862         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1863                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1864         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1865         .sysc_fields    = &omap_hwmod_sysc_type1,
1866 };
1867
1868 static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
1869         .name   = "gpmc",
1870         .sysc   = &omap3xxx_gpmc_sysc,
1871 };
1872
1873 static struct omap_hwmod omap3xxx_gpmc_hwmod = {
1874         .name           = "gpmc",
1875         .class          = &omap3xxx_gpmc_hwmod_class,
1876         .clkdm_name     = "core_l3_clkdm",
1877         .main_clk       = "gpmc_fck",
1878         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
1879         .flags          = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
1880 };
1881
1882 /*
1883  * interfaces
1884  */
1885
1886 /* L3 -> L4_CORE interface */
1887 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
1888         .master = &omap3xxx_l3_main_hwmod,
1889         .slave  = &omap3xxx_l4_core_hwmod,
1890         .user   = OCP_USER_MPU | OCP_USER_SDMA,
1891 };
1892
1893 /* L3 -> L4_PER interface */
1894 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
1895         .master = &omap3xxx_l3_main_hwmod,
1896         .slave  = &omap3xxx_l4_per_hwmod,
1897         .user   = OCP_USER_MPU | OCP_USER_SDMA,
1898 };
1899
1900
1901 /* MPU -> L3 interface */
1902 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
1903         .master   = &omap3xxx_mpu_hwmod,
1904         .slave    = &omap3xxx_l3_main_hwmod,
1905         .user   = OCP_USER_MPU,
1906 };
1907
1908
1909 /* l3 -> debugss */
1910 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
1911         .master         = &omap3xxx_l3_main_hwmod,
1912         .slave          = &omap3xxx_debugss_hwmod,
1913         .user           = OCP_USER_MPU,
1914 };
1915
1916 /* DSS -> l3 */
1917 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
1918         .master         = &omap3430es1_dss_core_hwmod,
1919         .slave          = &omap3xxx_l3_main_hwmod,
1920         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1921 };
1922
1923 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
1924         .master         = &omap3xxx_dss_core_hwmod,
1925         .slave          = &omap3xxx_l3_main_hwmod,
1926         .fw = {
1927                 .omap2 = {
1928                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
1929                         .flags  = OMAP_FIREWALL_L3,
1930                 },
1931         },
1932         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1933 };
1934
1935 /* l3_core -> usbhsotg interface */
1936 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
1937         .master         = &omap3xxx_usbhsotg_hwmod,
1938         .slave          = &omap3xxx_l3_main_hwmod,
1939         .clk            = "core_l3_ick",
1940         .user           = OCP_USER_MPU,
1941 };
1942
1943 /* l3_core -> am35xx_usbhsotg interface */
1944 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
1945         .master         = &am35xx_usbhsotg_hwmod,
1946         .slave          = &omap3xxx_l3_main_hwmod,
1947         .clk            = "hsotgusb_ick",
1948         .user           = OCP_USER_MPU,
1949 };
1950
1951 /* l3_core -> sad2d interface */
1952 static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
1953         .master         = &omap3xxx_sad2d_hwmod,
1954         .slave          = &omap3xxx_l3_main_hwmod,
1955         .clk            = "core_l3_ick",
1956         .user           = OCP_USER_MPU,
1957 };
1958
1959 /* L4_CORE -> L4_WKUP interface */
1960 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
1961         .master = &omap3xxx_l4_core_hwmod,
1962         .slave  = &omap3xxx_l4_wkup_hwmod,
1963         .user   = OCP_USER_MPU | OCP_USER_SDMA,
1964 };
1965
1966 /* L4 CORE -> MMC1 interface */
1967 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
1968         .master         = &omap3xxx_l4_core_hwmod,
1969         .slave          = &omap3xxx_pre_es3_mmc1_hwmod,
1970         .clk            = "mmchs1_ick",
1971         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1972         .flags          = OMAP_FIREWALL_L4,
1973 };
1974
1975 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
1976         .master         = &omap3xxx_l4_core_hwmod,
1977         .slave          = &omap3xxx_es3plus_mmc1_hwmod,
1978         .clk            = "mmchs1_ick",
1979         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1980         .flags          = OMAP_FIREWALL_L4,
1981 };
1982
1983 /* L4 CORE -> MMC2 interface */
1984 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
1985         .master         = &omap3xxx_l4_core_hwmod,
1986         .slave          = &omap3xxx_pre_es3_mmc2_hwmod,
1987         .clk            = "mmchs2_ick",
1988         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1989         .flags          = OMAP_FIREWALL_L4,
1990 };
1991
1992 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
1993         .master         = &omap3xxx_l4_core_hwmod,
1994         .slave          = &omap3xxx_es3plus_mmc2_hwmod,
1995         .clk            = "mmchs2_ick",
1996         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1997         .flags          = OMAP_FIREWALL_L4,
1998 };
1999
2000 /* L4 CORE -> MMC3 interface */
2001
2002 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2003         .master         = &omap3xxx_l4_core_hwmod,
2004         .slave          = &omap3xxx_mmc3_hwmod,
2005         .clk            = "mmchs3_ick",
2006         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2007         .flags          = OMAP_FIREWALL_L4,
2008 };
2009
2010 /* L4 CORE -> UART1 interface */
2011
2012 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2013         .master         = &omap3xxx_l4_core_hwmod,
2014         .slave          = &omap3xxx_uart1_hwmod,
2015         .clk            = "uart1_ick",
2016         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2017 };
2018
2019 /* L4 CORE -> UART2 interface */
2020
2021 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2022         .master         = &omap3xxx_l4_core_hwmod,
2023         .slave          = &omap3xxx_uart2_hwmod,
2024         .clk            = "uart2_ick",
2025         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2026 };
2027
2028 /* L4 PER -> UART3 interface */
2029
2030 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2031         .master         = &omap3xxx_l4_per_hwmod,
2032         .slave          = &omap3xxx_uart3_hwmod,
2033         .clk            = "uart3_ick",
2034         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2035 };
2036
2037 /* L4 PER -> UART4 interface */
2038
2039 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2040         .master         = &omap3xxx_l4_per_hwmod,
2041         .slave          = &omap36xx_uart4_hwmod,
2042         .clk            = "uart4_ick",
2043         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2044 };
2045
2046 /* AM35xx: L4 CORE -> UART4 interface */
2047
2048 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2049         .master         = &omap3xxx_l4_core_hwmod,
2050         .slave          = &am35xx_uart4_hwmod,
2051         .clk            = "uart4_ick",
2052         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2053 };
2054
2055 /* L4 CORE -> I2C1 interface */
2056 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2057         .master         = &omap3xxx_l4_core_hwmod,
2058         .slave          = &omap3xxx_i2c1_hwmod,
2059         .clk            = "i2c1_ick",
2060         .fw = {
2061                 .omap2 = {
2062                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
2063                         .l4_prot_group = 7,
2064                         .flags  = OMAP_FIREWALL_L4,
2065                 },
2066         },
2067         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2068 };
2069
2070 /* L4 CORE -> I2C2 interface */
2071 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2072         .master         = &omap3xxx_l4_core_hwmod,
2073         .slave          = &omap3xxx_i2c2_hwmod,
2074         .clk            = "i2c2_ick",
2075         .fw = {
2076                 .omap2 = {
2077                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
2078                         .l4_prot_group = 7,
2079                         .flags = OMAP_FIREWALL_L4,
2080                 },
2081         },
2082         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2083 };
2084
2085 /* L4 CORE -> I2C3 interface */
2086
2087 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2088         .master         = &omap3xxx_l4_core_hwmod,
2089         .slave          = &omap3xxx_i2c3_hwmod,
2090         .clk            = "i2c3_ick",
2091         .fw = {
2092                 .omap2 = {
2093                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
2094                         .l4_prot_group = 7,
2095                         .flags = OMAP_FIREWALL_L4,
2096                 },
2097         },
2098         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2099 };
2100
2101 /* L4 CORE -> SR1 interface */
2102 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2103         .master         = &omap3xxx_l4_core_hwmod,
2104         .slave          = &omap34xx_sr1_hwmod,
2105         .clk            = "sr_l4_ick",
2106         .user           = OCP_USER_MPU,
2107 };
2108
2109 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2110         .master         = &omap3xxx_l4_core_hwmod,
2111         .slave          = &omap36xx_sr1_hwmod,
2112         .clk            = "sr_l4_ick",
2113         .user           = OCP_USER_MPU,
2114 };
2115
2116 /* L4 CORE -> SR2 interface */
2117
2118 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2119         .master         = &omap3xxx_l4_core_hwmod,
2120         .slave          = &omap34xx_sr2_hwmod,
2121         .clk            = "sr_l4_ick",
2122         .user           = OCP_USER_MPU,
2123 };
2124
2125 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2126         .master         = &omap3xxx_l4_core_hwmod,
2127         .slave          = &omap36xx_sr2_hwmod,
2128         .clk            = "sr_l4_ick",
2129         .user           = OCP_USER_MPU,
2130 };
2131
2132
2133 /* l4_core -> usbhsotg  */
2134 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2135         .master         = &omap3xxx_l4_core_hwmod,
2136         .slave          = &omap3xxx_usbhsotg_hwmod,
2137         .clk            = "l4_ick",
2138         .user           = OCP_USER_MPU,
2139 };
2140
2141
2142 /* l4_core -> usbhsotg  */
2143 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2144         .master         = &omap3xxx_l4_core_hwmod,
2145         .slave          = &am35xx_usbhsotg_hwmod,
2146         .clk            = "hsotgusb_ick",
2147         .user           = OCP_USER_MPU,
2148 };
2149
2150 /* L4_WKUP -> L4_SEC interface */
2151 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2152         .master = &omap3xxx_l4_wkup_hwmod,
2153         .slave  = &omap3xxx_l4_sec_hwmod,
2154         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2155 };
2156
2157 /* IVA2 <- L3 interface */
2158 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2159         .master         = &omap3xxx_l3_main_hwmod,
2160         .slave          = &omap3xxx_iva_hwmod,
2161         .clk            = "core_l3_ick",
2162         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2163 };
2164
2165
2166 /* l4_wkup -> timer1 */
2167 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2168         .master         = &omap3xxx_l4_wkup_hwmod,
2169         .slave          = &omap3xxx_timer1_hwmod,
2170         .clk            = "gpt1_ick",
2171         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2172 };
2173
2174
2175 /* l4_per -> timer2 */
2176 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2177         .master         = &omap3xxx_l4_per_hwmod,
2178         .slave          = &omap3xxx_timer2_hwmod,
2179         .clk            = "gpt2_ick",
2180         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2181 };
2182
2183
2184 /* l4_per -> timer3 */
2185 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2186         .master         = &omap3xxx_l4_per_hwmod,
2187         .slave          = &omap3xxx_timer3_hwmod,
2188         .clk            = "gpt3_ick",
2189         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2190 };
2191
2192
2193 /* l4_per -> timer4 */
2194 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2195         .master         = &omap3xxx_l4_per_hwmod,
2196         .slave          = &omap3xxx_timer4_hwmod,
2197         .clk            = "gpt4_ick",
2198         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2199 };
2200
2201
2202 /* l4_per -> timer5 */
2203 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2204         .master         = &omap3xxx_l4_per_hwmod,
2205         .slave          = &omap3xxx_timer5_hwmod,
2206         .clk            = "gpt5_ick",
2207         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2208 };
2209
2210
2211 /* l4_per -> timer6 */
2212 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2213         .master         = &omap3xxx_l4_per_hwmod,
2214         .slave          = &omap3xxx_timer6_hwmod,
2215         .clk            = "gpt6_ick",
2216         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2217 };
2218
2219
2220 /* l4_per -> timer7 */
2221 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2222         .master         = &omap3xxx_l4_per_hwmod,
2223         .slave          = &omap3xxx_timer7_hwmod,
2224         .clk            = "gpt7_ick",
2225         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2226 };
2227
2228
2229 /* l4_per -> timer8 */
2230 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2231         .master         = &omap3xxx_l4_per_hwmod,
2232         .slave          = &omap3xxx_timer8_hwmod,
2233         .clk            = "gpt8_ick",
2234         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2235 };
2236
2237
2238 /* l4_per -> timer9 */
2239 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2240         .master         = &omap3xxx_l4_per_hwmod,
2241         .slave          = &omap3xxx_timer9_hwmod,
2242         .clk            = "gpt9_ick",
2243         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2244 };
2245
2246 /* l4_core -> timer10 */
2247 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2248         .master         = &omap3xxx_l4_core_hwmod,
2249         .slave          = &omap3xxx_timer10_hwmod,
2250         .clk            = "gpt10_ick",
2251         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2252 };
2253
2254 /* l4_core -> timer11 */
2255 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2256         .master         = &omap3xxx_l4_core_hwmod,
2257         .slave          = &omap3xxx_timer11_hwmod,
2258         .clk            = "gpt11_ick",
2259         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2260 };
2261
2262
2263 /* l4_core -> timer12 */
2264 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2265         .master         = &omap3xxx_l4_sec_hwmod,
2266         .slave          = &omap3xxx_timer12_hwmod,
2267         .clk            = "gpt12_ick",
2268         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2269 };
2270
2271 /* l4_wkup -> wd_timer2 */
2272
2273 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2274         .master         = &omap3xxx_l4_wkup_hwmod,
2275         .slave          = &omap3xxx_wd_timer2_hwmod,
2276         .clk            = "wdt2_ick",
2277         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2278 };
2279
2280 /* l4_core -> dss */
2281 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2282         .master         = &omap3xxx_l4_core_hwmod,
2283         .slave          = &omap3430es1_dss_core_hwmod,
2284         .clk            = "dss_ick",
2285         .fw = {
2286                 .omap2 = {
2287                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2288                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2289                         .flags  = OMAP_FIREWALL_L4,
2290                 },
2291         },
2292         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2293 };
2294
2295 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2296         .master         = &omap3xxx_l4_core_hwmod,
2297         .slave          = &omap3xxx_dss_core_hwmod,
2298         .clk            = "dss_ick",
2299         .fw = {
2300                 .omap2 = {
2301                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2302                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2303                         .flags  = OMAP_FIREWALL_L4,
2304                 },
2305         },
2306         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2307 };
2308
2309 /* l4_core -> dss_dispc */
2310 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2311         .master         = &omap3xxx_l4_core_hwmod,
2312         .slave          = &omap3xxx_dss_dispc_hwmod,
2313         .clk            = "dss_ick",
2314         .fw = {
2315                 .omap2 = {
2316                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2317                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2318                         .flags  = OMAP_FIREWALL_L4,
2319                 },
2320         },
2321         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2322 };
2323
2324 /* l4_core -> dss_dsi1 */
2325 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2326         .master         = &omap3xxx_l4_core_hwmod,
2327         .slave          = &omap3xxx_dss_dsi1_hwmod,
2328         .clk            = "dss_ick",
2329         .fw = {
2330                 .omap2 = {
2331                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2332                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2333                         .flags  = OMAP_FIREWALL_L4,
2334                 },
2335         },
2336         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2337 };
2338
2339 /* l4_core -> dss_rfbi */
2340 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2341         .master         = &omap3xxx_l4_core_hwmod,
2342         .slave          = &omap3xxx_dss_rfbi_hwmod,
2343         .clk            = "dss_ick",
2344         .fw = {
2345                 .omap2 = {
2346                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2347                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2348                         .flags  = OMAP_FIREWALL_L4,
2349                 },
2350         },
2351         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2352 };
2353
2354 /* l4_core -> dss_venc */
2355 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2356         .master         = &omap3xxx_l4_core_hwmod,
2357         .slave          = &omap3xxx_dss_venc_hwmod,
2358         .clk            = "dss_ick",
2359         .fw = {
2360                 .omap2 = {
2361                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2362                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2363                         .flags  = OMAP_FIREWALL_L4,
2364                 },
2365         },
2366         .flags          = OCPIF_SWSUP_IDLE,
2367         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2368 };
2369
2370 /* l4_wkup -> gpio1 */
2371
2372 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2373         .master         = &omap3xxx_l4_wkup_hwmod,
2374         .slave          = &omap3xxx_gpio1_hwmod,
2375         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2376 };
2377
2378 /* l4_per -> gpio2 */
2379
2380 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2381         .master         = &omap3xxx_l4_per_hwmod,
2382         .slave          = &omap3xxx_gpio2_hwmod,
2383         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2384 };
2385
2386 /* l4_per -> gpio3 */
2387
2388 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2389         .master         = &omap3xxx_l4_per_hwmod,
2390         .slave          = &omap3xxx_gpio3_hwmod,
2391         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2392 };
2393
2394 /*
2395  * 'mmu' class
2396  * The memory management unit performs virtual to physical address translation
2397  * for its requestors.
2398  */
2399
2400 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2401         .rev_offs       = 0x000,
2402         .sysc_offs      = 0x010,
2403         .syss_offs      = 0x014,
2404         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2405                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2406         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2407         .sysc_fields    = &omap_hwmod_sysc_type1,
2408 };
2409
2410 static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
2411         .name = "mmu",
2412         .sysc = &mmu_sysc,
2413 };
2414
2415 /* mmu isp */
2416 static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
2417
2418 /* l4_core -> mmu isp */
2419 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
2420         .master         = &omap3xxx_l4_core_hwmod,
2421         .slave          = &omap3xxx_mmu_isp_hwmod,
2422         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2423 };
2424
2425 static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
2426         .name           = "mmu_isp",
2427         .class          = &omap3xxx_mmu_hwmod_class,
2428         .main_clk       = "cam_ick",
2429         .flags          = HWMOD_NO_IDLEST,
2430 };
2431
2432 /* mmu iva */
2433
2434 static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
2435
2436 static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
2437         { .name = "mmu", .rst_shift = 1, .st_shift = 9 },
2438 };
2439
2440 /* l3_main -> iva mmu */
2441 static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
2442         .master         = &omap3xxx_l3_main_hwmod,
2443         .slave          = &omap3xxx_mmu_iva_hwmod,
2444         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2445 };
2446
2447 static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
2448         .name           = "mmu_iva",
2449         .class          = &omap3xxx_mmu_hwmod_class,
2450         .clkdm_name     = "iva2_clkdm",
2451         .rst_lines      = omap3xxx_mmu_iva_resets,
2452         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_mmu_iva_resets),
2453         .main_clk       = "iva2_ck",
2454         .prcm = {
2455                 .omap2 = {
2456                         .module_offs = OMAP3430_IVA2_MOD,
2457                         .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
2458                         .idlest_reg_id = 1,
2459                         .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
2460                 },
2461         },
2462         .flags          = HWMOD_NO_IDLEST,
2463 };
2464
2465 /* l4_per -> gpio4 */
2466
2467 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
2468         .master         = &omap3xxx_l4_per_hwmod,
2469         .slave          = &omap3xxx_gpio4_hwmod,
2470         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2471 };
2472
2473 /* l4_per -> gpio5 */
2474
2475 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2476         .master         = &omap3xxx_l4_per_hwmod,
2477         .slave          = &omap3xxx_gpio5_hwmod,
2478         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2479 };
2480
2481 /* l4_per -> gpio6 */
2482
2483 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2484         .master         = &omap3xxx_l4_per_hwmod,
2485         .slave          = &omap3xxx_gpio6_hwmod,
2486         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2487 };
2488
2489 /* dma_system -> L3 */
2490 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2491         .master         = &omap3xxx_dma_system_hwmod,
2492         .slave          = &omap3xxx_l3_main_hwmod,
2493         .clk            = "core_l3_ick",
2494         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2495 };
2496
2497 /* l4_cfg -> dma_system */
2498 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2499         .master         = &omap3xxx_l4_core_hwmod,
2500         .slave          = &omap3xxx_dma_system_hwmod,
2501         .clk            = "core_l4_ick",
2502         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2503 };
2504
2505
2506 /* l4_core -> mcbsp1 */
2507 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2508         .master         = &omap3xxx_l4_core_hwmod,
2509         .slave          = &omap3xxx_mcbsp1_hwmod,
2510         .clk            = "mcbsp1_ick",
2511         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2512 };
2513
2514
2515 /* l4_per -> mcbsp2 */
2516 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2517         .master         = &omap3xxx_l4_per_hwmod,
2518         .slave          = &omap3xxx_mcbsp2_hwmod,
2519         .clk            = "mcbsp2_ick",
2520         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2521 };
2522
2523
2524 /* l4_per -> mcbsp3 */
2525 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2526         .master         = &omap3xxx_l4_per_hwmod,
2527         .slave          = &omap3xxx_mcbsp3_hwmod,
2528         .clk            = "mcbsp3_ick",
2529         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2530 };
2531
2532
2533 /* l4_per -> mcbsp4 */
2534 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2535         .master         = &omap3xxx_l4_per_hwmod,
2536         .slave          = &omap3xxx_mcbsp4_hwmod,
2537         .clk            = "mcbsp4_ick",
2538         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2539 };
2540
2541
2542 /* l4_core -> mcbsp5 */
2543 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2544         .master         = &omap3xxx_l4_core_hwmod,
2545         .slave          = &omap3xxx_mcbsp5_hwmod,
2546         .clk            = "mcbsp5_ick",
2547         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2548 };
2549
2550
2551 /* l4_per -> mcbsp2_sidetone */
2552 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2553         .master         = &omap3xxx_l4_per_hwmod,
2554         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
2555         .clk            = "mcbsp2_ick",
2556         .user           = OCP_USER_MPU,
2557 };
2558
2559
2560 /* l4_per -> mcbsp3_sidetone */
2561 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2562         .master         = &omap3xxx_l4_per_hwmod,
2563         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
2564         .clk            = "mcbsp3_ick",
2565         .user           = OCP_USER_MPU,
2566 };
2567
2568 /* l4_core -> mailbox */
2569 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2570         .master         = &omap3xxx_l4_core_hwmod,
2571         .slave          = &omap3xxx_mailbox_hwmod,
2572         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2573 };
2574
2575 /* l4 core -> mcspi1 interface */
2576 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2577         .master         = &omap3xxx_l4_core_hwmod,
2578         .slave          = &omap34xx_mcspi1,
2579         .clk            = "mcspi1_ick",
2580         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2581 };
2582
2583 /* l4 core -> mcspi2 interface */
2584 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2585         .master         = &omap3xxx_l4_core_hwmod,
2586         .slave          = &omap34xx_mcspi2,
2587         .clk            = "mcspi2_ick",
2588         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2589 };
2590
2591 /* l4 core -> mcspi3 interface */
2592 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2593         .master         = &omap3xxx_l4_core_hwmod,
2594         .slave          = &omap34xx_mcspi3,
2595         .clk            = "mcspi3_ick",
2596         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2597 };
2598
2599 /* l4 core -> mcspi4 interface */
2600
2601 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2602         .master         = &omap3xxx_l4_core_hwmod,
2603         .slave          = &omap34xx_mcspi4,
2604         .clk            = "mcspi4_ick",
2605         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2606 };
2607
2608 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
2609         .master         = &omap3xxx_usb_host_hs_hwmod,
2610         .slave          = &omap3xxx_l3_main_hwmod,
2611         .clk            = "core_l3_ick",
2612         .user           = OCP_USER_MPU,
2613 };
2614
2615
2616 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
2617         .master         = &omap3xxx_l4_core_hwmod,
2618         .slave          = &omap3xxx_usb_host_hs_hwmod,
2619         .clk            = "usbhost_ick",
2620         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2621 };
2622
2623
2624 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
2625         .master         = &omap3xxx_l4_core_hwmod,
2626         .slave          = &omap3xxx_usb_tll_hs_hwmod,
2627         .clk            = "usbtll_ick",
2628         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2629 };
2630
2631 /* l4_core -> hdq1w interface */
2632 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
2633         .master         = &omap3xxx_l4_core_hwmod,
2634         .slave          = &omap3xxx_hdq1w_hwmod,
2635         .clk            = "hdq_ick",
2636         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2637         .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
2638 };
2639
2640 /* l4_wkup -> 32ksync_counter */
2641
2642
2643 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
2644         .master         = &omap3xxx_l4_wkup_hwmod,
2645         .slave          = &omap3xxx_counter_32k_hwmod,
2646         .clk            = "omap_32ksync_ick",
2647         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2648 };
2649
2650 /* am35xx has Davinci MDIO & EMAC */
2651 static struct omap_hwmod_class am35xx_mdio_class = {
2652         .name = "davinci_mdio",
2653 };
2654
2655 static struct omap_hwmod am35xx_mdio_hwmod = {
2656         .name           = "davinci_mdio",
2657         .class          = &am35xx_mdio_class,
2658         .flags          = HWMOD_NO_IDLEST,
2659 };
2660
2661 /*
2662  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
2663  * but this will probably require some additional hwmod core support,
2664  * so is left as a future to-do item.
2665  */
2666 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
2667         .master         = &am35xx_mdio_hwmod,
2668         .slave          = &omap3xxx_l3_main_hwmod,
2669         .clk            = "emac_fck",
2670         .user           = OCP_USER_MPU,
2671 };
2672
2673 /* l4_core -> davinci mdio  */
2674 /*
2675  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
2676  * but this will probably require some additional hwmod core support,
2677  * so is left as a future to-do item.
2678  */
2679 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
2680         .master         = &omap3xxx_l4_core_hwmod,
2681         .slave          = &am35xx_mdio_hwmod,
2682         .clk            = "emac_fck",
2683         .user           = OCP_USER_MPU,
2684 };
2685
2686 static struct omap_hwmod_class am35xx_emac_class = {
2687         .name = "davinci_emac",
2688 };
2689
2690 static struct omap_hwmod am35xx_emac_hwmod = {
2691         .name           = "davinci_emac",
2692         .class          = &am35xx_emac_class,
2693         /*
2694          * According to Mark Greer, the MPU will not return from WFI
2695          * when the EMAC signals an interrupt.
2696          * http://www.spinics.net/lists/arm-kernel/msg174734.html
2697          */
2698         .flags          = (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI),
2699 };
2700
2701 /* l3_core -> davinci emac interface */
2702 /*
2703  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
2704  * but this will probably require some additional hwmod core support,
2705  * so is left as a future to-do item.
2706  */
2707 static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
2708         .master         = &am35xx_emac_hwmod,
2709         .slave          = &omap3xxx_l3_main_hwmod,
2710         .clk            = "emac_ick",
2711         .user           = OCP_USER_MPU,
2712 };
2713
2714 /* l4_core -> davinci emac  */
2715 /*
2716  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
2717  * but this will probably require some additional hwmod core support,
2718  * so is left as a future to-do item.
2719  */
2720 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
2721         .master         = &omap3xxx_l4_core_hwmod,
2722         .slave          = &am35xx_emac_hwmod,
2723         .clk            = "emac_ick",
2724         .user           = OCP_USER_MPU,
2725 };
2726
2727 static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
2728         .master         = &omap3xxx_l3_main_hwmod,
2729         .slave          = &omap3xxx_gpmc_hwmod,
2730         .clk            = "core_l3_ick",
2731         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2732 };
2733
2734 /* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */
2735 static struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = {
2736         .sidle_shift    = 4,
2737         .srst_shift     = 1,
2738         .autoidle_shift = 0,
2739 };
2740
2741 static struct omap_hwmod_class_sysconfig omap3_sham_sysc = {
2742         .rev_offs       = 0x5c,
2743         .sysc_offs      = 0x60,
2744         .syss_offs      = 0x64,
2745         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2746                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2747         .sysc_fields    = &omap3_sham_sysc_fields,
2748 };
2749
2750 static struct omap_hwmod_class omap3xxx_sham_class = {
2751         .name   = "sham",
2752         .sysc   = &omap3_sham_sysc,
2753 };
2754
2755
2756
2757 static struct omap_hwmod omap3xxx_sham_hwmod = {
2758         .name           = "sham",
2759         .main_clk       = "sha12_ick",
2760         .prcm           = {
2761                 .omap2 = {
2762                         .module_offs = CORE_MOD,
2763                         .prcm_reg_id = 1,
2764                         .module_bit = OMAP3430_EN_SHA12_SHIFT,
2765                         .idlest_reg_id = 1,
2766                         .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT,
2767                 },
2768         },
2769         .class          = &omap3xxx_sham_class,
2770 };
2771
2772
2773 static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
2774         .master         = &omap3xxx_l4_core_hwmod,
2775         .slave          = &omap3xxx_sham_hwmod,
2776         .clk            = "sha12_ick",
2777         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2778 };
2779
2780 /* l4_core -> AES */
2781 static struct omap_hwmod_sysc_fields omap3xxx_aes_sysc_fields = {
2782         .sidle_shift    = 6,
2783         .srst_shift     = 1,
2784         .autoidle_shift = 0,
2785 };
2786
2787 static struct omap_hwmod_class_sysconfig omap3_aes_sysc = {
2788         .rev_offs       = 0x44,
2789         .sysc_offs      = 0x48,
2790         .syss_offs      = 0x4c,
2791         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2792                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2793         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2794         .sysc_fields    = &omap3xxx_aes_sysc_fields,
2795 };
2796
2797 static struct omap_hwmod_class omap3xxx_aes_class = {
2798         .name   = "aes",
2799         .sysc   = &omap3_aes_sysc,
2800 };
2801
2802
2803 static struct omap_hwmod omap3xxx_aes_hwmod = {
2804         .name           = "aes",
2805         .main_clk       = "aes2_ick",
2806         .prcm           = {
2807                 .omap2 = {
2808                         .module_offs = CORE_MOD,
2809                         .prcm_reg_id = 1,
2810                         .module_bit = OMAP3430_EN_AES2_SHIFT,
2811                         .idlest_reg_id = 1,
2812                         .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT,
2813                 },
2814         },
2815         .class          = &omap3xxx_aes_class,
2816 };
2817
2818
2819 static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
2820         .master         = &omap3xxx_l4_core_hwmod,
2821         .slave          = &omap3xxx_aes_hwmod,
2822         .clk            = "aes2_ick",
2823         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2824 };
2825
2826 /*
2827  * 'ssi' class
2828  * synchronous serial interface (multichannel and full-duplex serial if)
2829  */
2830
2831 static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = {
2832         .rev_offs       = 0x0000,
2833         .sysc_offs      = 0x0010,
2834         .syss_offs      = 0x0014,
2835         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_MIDLEMODE |
2836                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2837         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2838         .sysc_fields    = &omap_hwmod_sysc_type1,
2839 };
2840
2841 static struct omap_hwmod_class omap3xxx_ssi_hwmod_class = {
2842         .name   = "ssi",
2843         .sysc   = &omap34xx_ssi_sysc,
2844 };
2845
2846 static struct omap_hwmod omap3xxx_ssi_hwmod = {
2847         .name           = "ssi",
2848         .class          = &omap3xxx_ssi_hwmod_class,
2849         .clkdm_name     = "core_l4_clkdm",
2850         .main_clk       = "ssi_ssr_fck",
2851         .prcm           = {
2852                 .omap2 = {
2853                         .prcm_reg_id            = 1,
2854                         .module_bit             = OMAP3430_EN_SSI_SHIFT,
2855                         .module_offs            = CORE_MOD,
2856                         .idlest_reg_id          = 1,
2857                         .idlest_idle_bit        = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
2858                 },
2859         },
2860 };
2861
2862 /* L4 CORE -> SSI */
2863 static struct omap_hwmod_ocp_if omap3xxx_l4_core__ssi = {
2864         .master         = &omap3xxx_l4_core_hwmod,
2865         .slave          = &omap3xxx_ssi_hwmod,
2866         .clk            = "ssi_ick",
2867         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2868 };
2869
2870 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
2871         &omap3xxx_l3_main__l4_core,
2872         &omap3xxx_l3_main__l4_per,
2873         &omap3xxx_mpu__l3_main,
2874         &omap3xxx_l3_main__l4_debugss,
2875         &omap3xxx_l4_core__l4_wkup,
2876         &omap3xxx_l4_core__mmc3,
2877         &omap3_l4_core__uart1,
2878         &omap3_l4_core__uart2,
2879         &omap3_l4_per__uart3,
2880         &omap3_l4_core__i2c1,
2881         &omap3_l4_core__i2c2,
2882         &omap3_l4_core__i2c3,
2883         &omap3xxx_l4_wkup__l4_sec,
2884         &omap3xxx_l4_wkup__timer1,
2885         &omap3xxx_l4_per__timer2,
2886         &omap3xxx_l4_per__timer3,
2887         &omap3xxx_l4_per__timer4,
2888         &omap3xxx_l4_per__timer5,
2889         &omap3xxx_l4_per__timer6,
2890         &omap3xxx_l4_per__timer7,
2891         &omap3xxx_l4_per__timer8,
2892         &omap3xxx_l4_per__timer9,
2893         &omap3xxx_l4_core__timer10,
2894         &omap3xxx_l4_core__timer11,
2895         &omap3xxx_l4_wkup__wd_timer2,
2896         &omap3xxx_l4_wkup__gpio1,
2897         &omap3xxx_l4_per__gpio2,
2898         &omap3xxx_l4_per__gpio3,
2899         &omap3xxx_l4_per__gpio4,
2900         &omap3xxx_l4_per__gpio5,
2901         &omap3xxx_l4_per__gpio6,
2902         &omap3xxx_dma_system__l3,
2903         &omap3xxx_l4_core__dma_system,
2904         &omap3xxx_l4_core__mcbsp1,
2905         &omap3xxx_l4_per__mcbsp2,
2906         &omap3xxx_l4_per__mcbsp3,
2907         &omap3xxx_l4_per__mcbsp4,
2908         &omap3xxx_l4_core__mcbsp5,
2909         &omap3xxx_l4_per__mcbsp2_sidetone,
2910         &omap3xxx_l4_per__mcbsp3_sidetone,
2911         &omap34xx_l4_core__mcspi1,
2912         &omap34xx_l4_core__mcspi2,
2913         &omap34xx_l4_core__mcspi3,
2914         &omap34xx_l4_core__mcspi4,
2915         &omap3xxx_l4_wkup__counter_32k,
2916         &omap3xxx_l3_main__gpmc,
2917         NULL,
2918 };
2919
2920 /* GP-only hwmod links */
2921 static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
2922         &omap3xxx_l4_sec__timer12,
2923         NULL,
2924 };
2925
2926 static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
2927         &omap3xxx_l4_sec__timer12,
2928         NULL,
2929 };
2930
2931 static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
2932         &omap3xxx_l4_sec__timer12,
2933         NULL,
2934 };
2935
2936 /* crypto hwmod links */
2937 static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = {
2938         &omap3xxx_l4_core__sham,
2939         NULL,
2940 };
2941
2942 static struct omap_hwmod_ocp_if *omap34xx_aes_hwmod_ocp_ifs[] __initdata = {
2943         &omap3xxx_l4_core__aes,
2944         NULL,
2945 };
2946
2947 static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = {
2948         &omap3xxx_l4_core__sham,
2949         NULL
2950 };
2951
2952 static struct omap_hwmod_ocp_if *omap36xx_aes_hwmod_ocp_ifs[] __initdata = {
2953         &omap3xxx_l4_core__aes,
2954         NULL
2955 };
2956
2957 /*
2958  * Apparently the SHA/MD5 and AES accelerator IP blocks are
2959  * only present on some AM35xx chips, and no one knows which
2960  * ones.  See
2961  * http://www.spinics.net/lists/arm-kernel/msg215466.html So
2962  * if you need these IP blocks on an AM35xx, try uncommenting
2963  * the following lines.
2964  */
2965 static struct omap_hwmod_ocp_if *am35xx_sham_hwmod_ocp_ifs[] __initdata = {
2966         /* &omap3xxx_l4_core__sham, */
2967         NULL
2968 };
2969
2970 static struct omap_hwmod_ocp_if *am35xx_aes_hwmod_ocp_ifs[] __initdata = {
2971         /* &omap3xxx_l4_core__aes, */
2972         NULL,
2973 };
2974
2975 /* 3430ES1-only hwmod links */
2976 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
2977         &omap3430es1_dss__l3,
2978         &omap3430es1_l4_core__dss,
2979         NULL,
2980 };
2981
2982 /* 3430ES2+-only hwmod links */
2983 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
2984         &omap3xxx_dss__l3,
2985         &omap3xxx_l4_core__dss,
2986         &omap3xxx_usbhsotg__l3,
2987         &omap3xxx_l4_core__usbhsotg,
2988         &omap3xxx_usb_host_hs__l3_main_2,
2989         &omap3xxx_l4_core__usb_host_hs,
2990         &omap3xxx_l4_core__usb_tll_hs,
2991         NULL,
2992 };
2993
2994 /* <= 3430ES3-only hwmod links */
2995 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
2996         &omap3xxx_l4_core__pre_es3_mmc1,
2997         &omap3xxx_l4_core__pre_es3_mmc2,
2998         NULL,
2999 };
3000
3001 /* 3430ES3+-only hwmod links */
3002 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3003         &omap3xxx_l4_core__es3plus_mmc1,
3004         &omap3xxx_l4_core__es3plus_mmc2,
3005         NULL,
3006 };
3007
3008 /* 34xx-only hwmod links (all ES revisions) */
3009 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3010         &omap3xxx_l3__iva,
3011         &omap34xx_l4_core__sr1,
3012         &omap34xx_l4_core__sr2,
3013         &omap3xxx_l4_core__mailbox,
3014         &omap3xxx_l4_core__hdq1w,
3015         &omap3xxx_sad2d__l3,
3016         &omap3xxx_l4_core__mmu_isp,
3017         &omap3xxx_l3_main__mmu_iva,
3018         &omap3xxx_l4_core__ssi,
3019         NULL,
3020 };
3021
3022 /* 36xx-only hwmod links (all ES revisions) */
3023 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3024         &omap3xxx_l3__iva,
3025         &omap36xx_l4_per__uart4,
3026         &omap3xxx_dss__l3,
3027         &omap3xxx_l4_core__dss,
3028         &omap36xx_l4_core__sr1,
3029         &omap36xx_l4_core__sr2,
3030         &omap3xxx_usbhsotg__l3,
3031         &omap3xxx_l4_core__usbhsotg,
3032         &omap3xxx_l4_core__mailbox,
3033         &omap3xxx_usb_host_hs__l3_main_2,
3034         &omap3xxx_l4_core__usb_host_hs,
3035         &omap3xxx_l4_core__usb_tll_hs,
3036         &omap3xxx_l4_core__es3plus_mmc1,
3037         &omap3xxx_l4_core__es3plus_mmc2,
3038         &omap3xxx_l4_core__hdq1w,
3039         &omap3xxx_sad2d__l3,
3040         &omap3xxx_l4_core__mmu_isp,
3041         &omap3xxx_l3_main__mmu_iva,
3042         &omap3xxx_l4_core__ssi,
3043         NULL,
3044 };
3045
3046 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3047         &omap3xxx_dss__l3,
3048         &omap3xxx_l4_core__dss,
3049         &am35xx_usbhsotg__l3,
3050         &am35xx_l4_core__usbhsotg,
3051         &am35xx_l4_core__uart4,
3052         &omap3xxx_usb_host_hs__l3_main_2,
3053         &omap3xxx_l4_core__usb_host_hs,
3054         &omap3xxx_l4_core__usb_tll_hs,
3055         &omap3xxx_l4_core__es3plus_mmc1,
3056         &omap3xxx_l4_core__es3plus_mmc2,
3057         &omap3xxx_l4_core__hdq1w,
3058         &am35xx_mdio__l3,
3059         &am35xx_l4_core__mdio,
3060         &am35xx_emac__l3,
3061         &am35xx_l4_core__emac,
3062         NULL,
3063 };
3064
3065 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3066         &omap3xxx_l4_core__dss_dispc,
3067         &omap3xxx_l4_core__dss_dsi1,
3068         &omap3xxx_l4_core__dss_rfbi,
3069         &omap3xxx_l4_core__dss_venc,
3070         NULL,
3071 };
3072
3073 /**
3074  * omap3xxx_hwmod_is_hs_ip_block_usable - is a security IP block accessible?
3075  * @bus: struct device_node * for the top-level OMAP DT data
3076  * @dev_name: device name used in the DT file
3077  *
3078  * Determine whether a "secure" IP block @dev_name is usable by Linux.
3079  * There doesn't appear to be a 100% reliable way to determine this,
3080  * so we rely on heuristics.  If @bus is null, meaning there's no DT
3081  * data, then we only assume the IP block is accessible if the OMAP is
3082  * fused as a 'general-purpose' SoC.  If however DT data is present,
3083  * test to see if the IP block is described in the DT data and set to
3084  * 'status = "okay"'.  If so then we assume the ODM has configured the
3085  * OMAP firewalls to allow access to the IP block.
3086  *
3087  * Return: 0 if device named @dev_name is not likely to be accessible,
3088  * or 1 if it is likely to be accessible.
3089  */
3090 static bool __init omap3xxx_hwmod_is_hs_ip_block_usable(struct device_node *bus,
3091                                                         const char *dev_name)
3092 {
3093         struct device_node *node;
3094         bool available;
3095
3096         if (!bus)
3097                 return omap_type() == OMAP2_DEVICE_TYPE_GP;
3098
3099         node = of_get_child_by_name(bus, dev_name);
3100         available = of_device_is_available(node);
3101         of_node_put(node);
3102
3103         return available;
3104 }
3105
3106 int __init omap3xxx_hwmod_init(void)
3107 {
3108         int r;
3109         struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL, **h_sham = NULL;
3110         struct omap_hwmod_ocp_if **h_aes = NULL;
3111         struct device_node *bus;
3112         unsigned int rev;
3113
3114         omap_hwmod_init();
3115
3116         /* Register hwmod links common to all OMAP3 */
3117         r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3118         if (r < 0)
3119                 return r;
3120
3121         rev = omap_rev();
3122
3123         /*
3124          * Register hwmod links common to individual OMAP3 families, all
3125          * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3126          * All possible revisions should be included in this conditional.
3127          */
3128         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3129             rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3130             rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3131                 h = omap34xx_hwmod_ocp_ifs;
3132                 h_gp = omap34xx_gp_hwmod_ocp_ifs;
3133                 h_sham = omap34xx_sham_hwmod_ocp_ifs;
3134                 h_aes = omap34xx_aes_hwmod_ocp_ifs;
3135         } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
3136                 h = am35xx_hwmod_ocp_ifs;
3137                 h_gp = am35xx_gp_hwmod_ocp_ifs;
3138                 h_sham = am35xx_sham_hwmod_ocp_ifs;
3139                 h_aes = am35xx_aes_hwmod_ocp_ifs;
3140         } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3141                    rev == OMAP3630_REV_ES1_2) {
3142                 h = omap36xx_hwmod_ocp_ifs;
3143                 h_gp = omap36xx_gp_hwmod_ocp_ifs;
3144                 h_sham = omap36xx_sham_hwmod_ocp_ifs;
3145                 h_aes = omap36xx_aes_hwmod_ocp_ifs;
3146         } else {
3147                 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3148                 return -EINVAL;
3149         }
3150
3151         r = omap_hwmod_register_links(h);
3152         if (r < 0)
3153                 return r;
3154
3155         /* Register GP-only hwmod links. */
3156         if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) {
3157                 r = omap_hwmod_register_links(h_gp);
3158                 if (r < 0)
3159                         return r;
3160         }
3161
3162         /*
3163          * Register crypto hwmod links only if they are not disabled in DT.
3164          * If DT information is missing, enable them only for GP devices.
3165          */
3166
3167         bus = of_find_node_by_name(NULL, "ocp");
3168
3169         if (h_sham && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "sham")) {
3170                 r = omap_hwmod_register_links(h_sham);
3171                 if (r < 0)
3172                         goto put_node;
3173         }
3174
3175         if (h_aes && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "aes")) {
3176                 r = omap_hwmod_register_links(h_aes);
3177                 if (r < 0)
3178                         goto put_node;
3179         }
3180         of_node_put(bus);
3181
3182         /*
3183          * Register hwmod links specific to certain ES levels of a
3184          * particular family of silicon (e.g., 34xx ES1.0)
3185          */
3186         h = NULL;
3187         if (rev == OMAP3430_REV_ES1_0) {
3188                 h = omap3430es1_hwmod_ocp_ifs;
3189         } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3190                    rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3191                    rev == OMAP3430_REV_ES3_1_2) {
3192                 h = omap3430es2plus_hwmod_ocp_ifs;
3193         }
3194
3195         if (h) {
3196                 r = omap_hwmod_register_links(h);
3197                 if (r < 0)
3198                         return r;
3199         }
3200
3201         h = NULL;
3202         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3203             rev == OMAP3430_REV_ES2_1) {
3204                 h = omap3430_pre_es3_hwmod_ocp_ifs;
3205         } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3206                    rev == OMAP3430_REV_ES3_1_2) {
3207                 h = omap3430_es3plus_hwmod_ocp_ifs;
3208         }
3209
3210         if (h)
3211                 r = omap_hwmod_register_links(h);
3212         if (r < 0)
3213                 return r;
3214
3215         /*
3216          * DSS code presumes that dss_core hwmod is handled first,
3217          * _before_ any other DSS related hwmods so register common
3218          * DSS hwmod links last to ensure that dss_core is already
3219          * registered.  Otherwise some change things may happen, for
3220          * ex. if dispc is handled before dss_core and DSS is enabled
3221          * in bootloader DISPC will be reset with outputs enabled
3222          * which sometimes leads to unrecoverable L3 error.  XXX The
3223          * long-term fix to this is to ensure hwmods are set up in
3224          * dependency order in the hwmod core code.
3225          */
3226         r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
3227
3228         return r;
3229
3230 put_node:
3231         of_node_put(bus);
3232         return r;
3233 }