arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  * Paul Walmsley
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * The data in this file should be completely autogeneratable from
  13  * the TI hardware database or other technical documentation.
  14  *
  15  * XXX these should be marked initdata for multi-OMAP kernels
  16  */
  17
  18 #include <linux/i2c-omap.h>
  19 #include <linux/power/smartreflex.h>
  20 #include <linux/platform_data/gpio-omap.h>
  21 #include <linux/platform_data/hsmmc-omap.h>
  22
  23 #include <linux/omap-dma.h>
  24 #include "l3_3xxx.h"
  25 #include "l4_3xxx.h"
  26 #include <linux/platform_data/asoc-ti-mcbsp.h>
  27 #include <linux/platform_data/spi-omap2-mcspi.h>
  28 #include <plat/dmtimer.h>
  29
  30 #include "soc.h"
  31 #include "omap_hwmod.h"
  32 #include "omap_hwmod_common_data.h"
  33 #include "prm-regbits-34xx.h"
  34 #include "cm-regbits-34xx.h"
  35
  36 #include "i2c.h"
  37 #include "wd_timer.h"
  38 #include "serial.h"
  39
  40 /*
  41  * OMAP3xxx hardware module integration data
  42  *
  43  * All of the data in this section should be autogeneratable from the
  44  * TI hardware database or other technical documentation.  Data that
  45  * is driver-specific or driver-kernel integration-specific belongs
  46  * elsewhere.
  47  */
  48
  49 #define AM35XX_IPSS_USBOTGSS_BASE      0x5C040000
  50
  51 /*
  52  * IP blocks
  53  */
  54
  55 /* L3 */
  56
  57 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
  58         .name           = "l3_main",
  59         .class          = &l3_hwmod_class,
  60         .flags          = HWMOD_NO_IDLEST,
  61 };
  62
  63 /* L4 CORE */
  64 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
  65         .name           = "l4_core",
  66         .class          = &l4_hwmod_class,
  67         .flags          = HWMOD_NO_IDLEST,
  68 };
  69
  70 /* L4 PER */
  71 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
  72         .name           = "l4_per",
  73         .class          = &l4_hwmod_class,
  74         .flags          = HWMOD_NO_IDLEST,
  75 };
  76
  77 /* L4 WKUP */
  78 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
  79         .name           = "l4_wkup",
  80         .class          = &l4_hwmod_class,
  81         .flags          = HWMOD_NO_IDLEST,
  82 };
  83
  84 /* L4 SEC */
  85 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
  86         .name           = "l4_sec",
  87         .class          = &l4_hwmod_class,
  88         .flags          = HWMOD_NO_IDLEST,
  89 };
  90
  91 /* MPU */
  92
  93 static struct omap_hwmod omap3xxx_mpu_hwmod = {
  94         .name           = "mpu",
  95         .class          = &mpu_hwmod_class,
  96         .main_clk       = "arm_fck",
  97 };
  98
  99 /* IVA2 (IVA2) */
 100 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
 101         { .name = "logic", .rst_shift = 0, .st_shift = 8 },
 102         { .name = "seq0", .rst_shift = 1, .st_shift = 9 },
 103         { .name = "seq1", .rst_shift = 2, .st_shift = 10 },
 104 };
 105
 106 static struct omap_hwmod omap3xxx_iva_hwmod = {
 107         .name           = "iva",
 108         .class          = &iva_hwmod_class,
 109         .clkdm_name     = "iva2_clkdm",
 110         .rst_lines      = omap3xxx_iva_resets,
 111         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_iva_resets),
 112         .main_clk       = "iva2_ck",
 113         .prcm = {
 114                 .omap2 = {
 115                         .module_offs = OMAP3430_IVA2_MOD,
 116                         .idlest_reg_id = 1,
 117                         .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
 118                 },
 119         },
 120 };
 121
 122 /*
 123  * 'debugss' class
 124  * debug and emulation sub system
 125  */
 126
 127 static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = {
 128         .name   = "debugss",
 129 };
 130
 131 /* debugss */
 132 static struct omap_hwmod omap3xxx_debugss_hwmod = {
 133         .name           = "debugss",
 134         .class          = &omap3xxx_debugss_hwmod_class,
 135         .clkdm_name     = "emu_clkdm",
 136         .main_clk       = "emu_src_ck",
 137         .flags          = HWMOD_NO_IDLEST,
 138 };
 139
 140 /* timer class */
 141 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 142         .rev_offs       = 0x0000,
 143         .sysc_offs      = 0x0010,
 144         .syss_offs      = 0x0014,
 145         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 146                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 147                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
 148                            SYSS_HAS_RESET_STATUS),
 149         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 150         .sysc_fields    = &omap_hwmod_sysc_type1,
 151 };
 152
 153 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 154         .name = "timer",
 155         .sysc = &omap3xxx_timer_sysc,
 156 };
 157
 158 /* secure timers dev attribute */
 159 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
 160         .timer_capability       = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
 161 };
 162
 163 /* always-on timers dev attribute */
 164 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 165         .timer_capability       = OMAP_TIMER_ALWON,
 166 };
 167
 168 /* pwm timers dev attribute */
 169 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 170         .timer_capability       = OMAP_TIMER_HAS_PWM,
 171 };
 172
 173 /* timers with DSP interrupt dev attribute */
 174 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
 175         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
 176 };
 177
 178 /* pwm timers with DSP interrupt dev attribute */
 179 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
 180         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
 181 };
 182
 183 /* timer1 */
 184 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 185         .name           = "timer1",
 186         .main_clk       = "gpt1_fck",
 187         .prcm           = {
 188                 .omap2 = {
 189                         .module_offs = WKUP_MOD,
 190                         .idlest_reg_id = 1,
 191                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 192                 },
 193         },
 194         .dev_attr       = &capability_alwon_dev_attr,
 195         .class          = &omap3xxx_timer_hwmod_class,
 196         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 197 };
 198
 199 /* timer2 */
 200 static struct omap_hwmod omap3xxx_timer2_hwmod = {
 201         .name           = "timer2",
 202         .main_clk       = "gpt2_fck",
 203         .prcm           = {
 204                 .omap2 = {
 205                         .module_offs = OMAP3430_PER_MOD,
 206                         .idlest_reg_id = 1,
 207                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 208                 },
 209         },
 210         .class          = &omap3xxx_timer_hwmod_class,
 211         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 212 };
 213
 214 /* timer3 */
 215 static struct omap_hwmod omap3xxx_timer3_hwmod = {
 216         .name           = "timer3",
 217         .main_clk       = "gpt3_fck",
 218         .prcm           = {
 219                 .omap2 = {
 220                         .module_offs = OMAP3430_PER_MOD,
 221                         .idlest_reg_id = 1,
 222                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 223                 },
 224         },
 225         .class          = &omap3xxx_timer_hwmod_class,
 226         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 227 };
 228
 229 /* timer4 */
 230 static struct omap_hwmod omap3xxx_timer4_hwmod = {
 231         .name           = "timer4",
 232         .main_clk       = "gpt4_fck",
 233         .prcm           = {
 234                 .omap2 = {
 235                         .module_offs = OMAP3430_PER_MOD,
 236                         .idlest_reg_id = 1,
 237                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 238                 },
 239         },
 240         .class          = &omap3xxx_timer_hwmod_class,
 241         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 242 };
 243
 244 /* timer5 */
 245 static struct omap_hwmod omap3xxx_timer5_hwmod = {
 246         .name           = "timer5",
 247         .main_clk       = "gpt5_fck",
 248         .prcm           = {
 249                 .omap2 = {
 250                         .module_offs = OMAP3430_PER_MOD,
 251                         .idlest_reg_id = 1,
 252                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 253                 },
 254         },
 255         .dev_attr       = &capability_dsp_dev_attr,
 256         .class          = &omap3xxx_timer_hwmod_class,
 257         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 258 };
 259
 260 /* timer6 */
 261 static struct omap_hwmod omap3xxx_timer6_hwmod = {
 262         .name           = "timer6",
 263         .main_clk       = "gpt6_fck",
 264         .prcm           = {
 265                 .omap2 = {
 266                         .module_offs = OMAP3430_PER_MOD,
 267                         .idlest_reg_id = 1,
 268                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 269                 },
 270         },
 271         .dev_attr       = &capability_dsp_dev_attr,
 272         .class          = &omap3xxx_timer_hwmod_class,
 273         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 274 };
 275
 276 /* timer7 */
 277 static struct omap_hwmod omap3xxx_timer7_hwmod = {
 278         .name           = "timer7",
 279         .main_clk       = "gpt7_fck",
 280         .prcm           = {
 281                 .omap2 = {
 282                         .module_offs = OMAP3430_PER_MOD,
 283                         .idlest_reg_id = 1,
 284                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 285                 },
 286         },
 287         .dev_attr       = &capability_dsp_dev_attr,
 288         .class          = &omap3xxx_timer_hwmod_class,
 289         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 290 };
 291
 292 /* timer8 */
 293 static struct omap_hwmod omap3xxx_timer8_hwmod = {
 294         .name           = "timer8",
 295         .main_clk       = "gpt8_fck",
 296         .prcm           = {
 297                 .omap2 = {
 298                         .module_offs = OMAP3430_PER_MOD,
 299                         .idlest_reg_id = 1,
 300                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 301                 },
 302         },
 303         .dev_attr       = &capability_dsp_pwm_dev_attr,
 304         .class          = &omap3xxx_timer_hwmod_class,
 305         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 306 };
 307
 308 /* timer9 */
 309 static struct omap_hwmod omap3xxx_timer9_hwmod = {
 310         .name           = "timer9",
 311         .main_clk       = "gpt9_fck",
 312         .prcm           = {
 313                 .omap2 = {
 314                         .module_offs = OMAP3430_PER_MOD,
 315                         .idlest_reg_id = 1,
 316                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
 317                 },
 318         },
 319         .dev_attr       = &capability_pwm_dev_attr,
 320         .class          = &omap3xxx_timer_hwmod_class,
 321         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 322 };
 323
 324 /* timer10 */
 325 static struct omap_hwmod omap3xxx_timer10_hwmod = {
 326         .name           = "timer10",
 327         .main_clk       = "gpt10_fck",
 328         .prcm           = {
 329                 .omap2 = {
 330                         .module_offs = CORE_MOD,
 331                         .idlest_reg_id = 1,
 332                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
 333                 },
 334         },
 335         .dev_attr       = &capability_pwm_dev_attr,
 336         .class          = &omap3xxx_timer_hwmod_class,
 337         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 338 };
 339
 340 /* timer11 */
 341 static struct omap_hwmod omap3xxx_timer11_hwmod = {
 342         .name           = "timer11",
 343         .main_clk       = "gpt11_fck",
 344         .prcm           = {
 345                 .omap2 = {
 346                         .module_offs = CORE_MOD,
 347                         .idlest_reg_id = 1,
 348                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
 349                 },
 350         },
 351         .dev_attr       = &capability_pwm_dev_attr,
 352         .class          = &omap3xxx_timer_hwmod_class,
 353         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 354 };
 355
 356 /* timer12 */
 357
 358 static struct omap_hwmod omap3xxx_timer12_hwmod = {
 359         .name           = "timer12",
 360         .main_clk       = "gpt12_fck",
 361         .prcm           = {
 362                 .omap2 = {
 363                         .module_offs = WKUP_MOD,
 364                         .idlest_reg_id = 1,
 365                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
 366                 },
 367         },
 368         .dev_attr       = &capability_secure_dev_attr,
 369         .class          = &omap3xxx_timer_hwmod_class,
 370         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 371 };
 372
 373 /*
 374  * 'wd_timer' class
 375  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 376  * overflow condition
 377  */
 378
 379 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
 380         .rev_offs       = 0x0000,
 381         .sysc_offs      = 0x0010,
 382         .syss_offs      = 0x0014,
 383         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
 384                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 385                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 386                            SYSS_HAS_RESET_STATUS),
 387         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 388         .sysc_fields    = &omap_hwmod_sysc_type1,
 389 };
 390
 391 /* I2C common */
 392 static struct omap_hwmod_class_sysconfig i2c_sysc = {
 393         .rev_offs       = 0x00,
 394         .sysc_offs      = 0x20,
 395         .syss_offs      = 0x10,
 396         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 397                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 398                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 399         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 400         .sysc_fields    = &omap_hwmod_sysc_type1,
 401 };
 402
 403 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
 404         .name           = "wd_timer",
 405         .sysc           = &omap3xxx_wd_timer_sysc,
 406         .pre_shutdown   = &omap2_wd_timer_disable,
 407         .reset          = &omap2_wd_timer_reset,
 408 };
 409
 410 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
 411         .name           = "wd_timer2",
 412         .class          = &omap3xxx_wd_timer_hwmod_class,
 413         .main_clk       = "wdt2_fck",
 414         .prcm           = {
 415                 .omap2 = {
 416                         .module_offs = WKUP_MOD,
 417                         .idlest_reg_id = 1,
 418                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
 419                 },
 420         },
 421         /*
 422          * XXX: Use software supervised mode, HW supervised smartidle seems to
 423          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
 424          */
 425         .flags          = HWMOD_SWSUP_SIDLE,
 426 };
 427
 428 /* UART1 */
 429 static struct omap_hwmod omap3xxx_uart1_hwmod = {
 430         .name           = "uart1",
 431         .main_clk       = "uart1_fck",
 432         .flags          = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE,
 433         .prcm           = {
 434                 .omap2 = {
 435                         .module_offs = CORE_MOD,
 436                         .idlest_reg_id = 1,
 437                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
 438                 },
 439         },
 440         .class          = &omap2_uart_class,
 441 };
 442
 443 /* UART2 */
 444 static struct omap_hwmod omap3xxx_uart2_hwmod = {
 445         .name           = "uart2",
 446         .main_clk       = "uart2_fck",
 447         .flags          = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE,
 448         .prcm           = {
 449                 .omap2 = {
 450                         .module_offs = CORE_MOD,
 451                         .idlest_reg_id = 1,
 452                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
 453                 },
 454         },
 455         .class          = &omap2_uart_class,
 456 };
 457
 458 /* UART3 */
 459 static struct omap_hwmod omap3xxx_uart3_hwmod = {
 460         .name           = "uart3",
 461         .main_clk       = "uart3_fck",
 462         .flags          = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS |
 463                                 HWMOD_SWSUP_SIDLE,
 464         .prcm           = {
 465                 .omap2 = {
 466                         .module_offs = OMAP3430_PER_MOD,
 467                         .idlest_reg_id = 1,
 468                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
 469                 },
 470         },
 471         .class          = &omap2_uart_class,
 472 };
 473
 474 /* UART4 */
 475
 476
 477 static struct omap_hwmod omap36xx_uart4_hwmod = {
 478         .name           = "uart4",
 479         .main_clk       = "uart4_fck",
 480         .flags          = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE,
 481         .prcm           = {
 482                 .omap2 = {
 483                         .module_offs = OMAP3430_PER_MOD,
 484                         .idlest_reg_id = 1,
 485                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
 486                 },
 487         },
 488         .class          = &omap2_uart_class,
 489 };
 490
 491
 492
 493 /*
 494  * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
 495  * uart2_fck being enabled.  So we add uart1_fck as an optional clock,
 496  * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET.  This really
 497  * should not be needed.  The functional clock structure of the AM35xx
 498  * UART4 is extremely unclear and opaque; it is unclear what the role
 499  * of uart1/2_fck is for the UART4.  Any clarification from either
 500  * empirical testing or the AM3505/3517 hardware designers would be
 501  * most welcome.
 502  */
 503 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
 504         { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
 505 };
 506
 507 static struct omap_hwmod am35xx_uart4_hwmod = {
 508         .name           = "uart4",
 509         .main_clk       = "uart4_fck",
 510         .prcm           = {
 511                 .omap2 = {
 512                         .module_offs = CORE_MOD,
 513                         .idlest_reg_id = 1,
 514                         .idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
 515                 },
 516         },
 517         .opt_clks       = am35xx_uart4_opt_clks,
 518         .opt_clks_cnt   = ARRAY_SIZE(am35xx_uart4_opt_clks),
 519         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 520         .class          = &omap2_uart_class,
 521 };
 522
 523 static struct omap_hwmod_class i2c_class = {
 524         .name   = "i2c",
 525         .sysc   = &i2c_sysc,
 526         .rev    = OMAP_I2C_IP_VERSION_1,
 527         .reset  = &omap_i2c_reset,
 528 };
 529
 530 /* dss */
 531 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 532         /*
 533          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
 534          * driver does not use these clocks.
 535          */
 536         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 537         { .role = "tv_clk", .clk = "dss_tv_fck" },
 538         /* required only on OMAP3430 */
 539         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 540 };
 541
 542 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
 543         .name           = "dss_core",
 544         .class          = &omap2_dss_hwmod_class,
 545         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 546         .prcm           = {
 547                 .omap2 = {
 548                         .module_offs = OMAP3430_DSS_MOD,
 549                         .idlest_reg_id = 1,
 550                 },
 551         },
 552         .opt_clks       = dss_opt_clks,
 553         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 554         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 555 };
 556
 557 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
 558         .name           = "dss_core",
 559         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 560         .class          = &omap2_dss_hwmod_class,
 561         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 562         .prcm           = {
 563                 .omap2 = {
 564                         .module_offs = OMAP3430_DSS_MOD,
 565                         .idlest_reg_id = 1,
 566                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
 567                 },
 568         },
 569         .opt_clks       = dss_opt_clks,
 570         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 571 };
 572
 573 /*
 574  * 'dispc' class
 575  * display controller
 576  */
 577
 578 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
 579         .rev_offs       = 0x0000,
 580         .sysc_offs      = 0x0010,
 581         .syss_offs      = 0x0014,
 582         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 583                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 584                            SYSC_HAS_ENAWAKEUP),
 585         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 586                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 587         .sysc_fields    = &omap_hwmod_sysc_type1,
 588 };
 589
 590 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
 591         .name   = "dispc",
 592         .sysc   = &omap3_dispc_sysc,
 593 };
 594
 595 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
 596         .name           = "dss_dispc",
 597         .class          = &omap3_dispc_hwmod_class,
 598         .main_clk       = "dss1_alwon_fck",
 599         .prcm           = {
 600                 .omap2 = {
 601                         .module_offs = OMAP3430_DSS_MOD,
 602                 },
 603         },
 604         .flags          = HWMOD_NO_IDLEST,
 605         .dev_attr       = &omap2_3_dss_dispc_dev_attr,
 606 };
 607
 608 /*
 609  * 'dsi' class
 610  * display serial interface controller
 611  */
 612
 613 static struct omap_hwmod_class_sysconfig omap3xxx_dsi_sysc = {
 614         .rev_offs       = 0x0000,
 615         .sysc_offs      = 0x0010,
 616         .syss_offs      = 0x0014,
 617         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 618                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 619                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 620         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 621         .sysc_fields    = &omap_hwmod_sysc_type1,
 622 };
 623
 624 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
 625         .name = "dsi",
 626         .sysc   = &omap3xxx_dsi_sysc,
 627 };
 628
 629 /* dss_dsi1 */
 630 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 631         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 632 };
 633
 634 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
 635         .name           = "dss_dsi1",
 636         .class          = &omap3xxx_dsi_hwmod_class,
 637         .main_clk       = "dss1_alwon_fck",
 638         .prcm           = {
 639                 .omap2 = {
 640                         .module_offs = OMAP3430_DSS_MOD,
 641                 },
 642         },
 643         .opt_clks       = dss_dsi1_opt_clks,
 644         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 645         .flags          = HWMOD_NO_IDLEST,
 646 };
 647
 648 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 649         { .role = "ick", .clk = "dss_ick" },
 650 };
 651
 652 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
 653         .name           = "dss_rfbi",
 654         .class          = &omap2_rfbi_hwmod_class,
 655         .main_clk       = "dss1_alwon_fck",
 656         .prcm           = {
 657                 .omap2 = {
 658                         .module_offs = OMAP3430_DSS_MOD,
 659                 },
 660         },
 661         .opt_clks       = dss_rfbi_opt_clks,
 662         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 663         .flags          = HWMOD_NO_IDLEST,
 664 };
 665
 666 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
 667         /* required only on OMAP3430 */
 668         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 669 };
 670
 671 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
 672         .name           = "dss_venc",
 673         .class          = &omap2_venc_hwmod_class,
 674         .main_clk       = "dss_tv_fck",
 675         .prcm           = {
 676                 .omap2 = {
 677                         .module_offs = OMAP3430_DSS_MOD,
 678                 },
 679         },
 680         .opt_clks       = dss_venc_opt_clks,
 681         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
 682         .flags          = HWMOD_NO_IDLEST,
 683 };
 684
 685 /* I2C1 */
 686 static struct omap_i2c_dev_attr i2c1_dev_attr = {
 687         .fifo_depth     = 8, /* bytes */
 688         .flags          = OMAP_I2C_FLAG_BUS_SHIFT_2,
 689 };
 690
 691 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
 692         .name           = "i2c1",
 693         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 694         .main_clk       = "i2c1_fck",
 695         .prcm           = {
 696                 .omap2 = {
 697                         .module_offs = CORE_MOD,
 698                         .idlest_reg_id = 1,
 699                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
 700                 },
 701         },
 702         .class          = &i2c_class,
 703         .dev_attr       = &i2c1_dev_attr,
 704 };
 705
 706 /* I2C2 */
 707 static struct omap_i2c_dev_attr i2c2_dev_attr = {
 708         .fifo_depth     = 8, /* bytes */
 709         .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
 710 };
 711
 712 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
 713         .name           = "i2c2",
 714         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 715         .main_clk       = "i2c2_fck",
 716         .prcm           = {
 717                 .omap2 = {
 718                         .module_offs = CORE_MOD,
 719                         .idlest_reg_id = 1,
 720                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
 721                 },
 722         },
 723         .class          = &i2c_class,
 724         .dev_attr       = &i2c2_dev_attr,
 725 };
 726
 727 /* I2C3 */
 728 static struct omap_i2c_dev_attr i2c3_dev_attr = {
 729         .fifo_depth     = 64, /* bytes */
 730         .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
 731 };
 732
 733
 734
 735 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
 736         .name           = "i2c3",
 737         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 738         .main_clk       = "i2c3_fck",
 739         .prcm           = {
 740                 .omap2 = {
 741                         .module_offs = CORE_MOD,
 742                         .idlest_reg_id = 1,
 743                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
 744                 },
 745         },
 746         .class          = &i2c_class,
 747         .dev_attr       = &i2c3_dev_attr,
 748 };
 749
 750 /*
 751  * 'gpio' class
 752  * general purpose io module
 753  */
 754
 755 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
 756         .rev_offs       = 0x0000,
 757         .sysc_offs      = 0x0010,
 758         .syss_offs      = 0x0014,
 759         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 760                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 761                            SYSS_HAS_RESET_STATUS),
 762         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 763         .sysc_fields    = &omap_hwmod_sysc_type1,
 764 };
 765
 766 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
 767         .name = "gpio",
 768         .sysc = &omap3xxx_gpio_sysc,
 769         .rev = 1,
 770 };
 771
 772 /* gpio_dev_attr */
 773 static struct omap_gpio_dev_attr gpio_dev_attr = {
 774         .bank_width = 32,
 775         .dbck_flag = true,
 776 };
 777
 778 /* gpio1 */
 779 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 780         { .role = "dbclk", .clk = "gpio1_dbck", },
 781 };
 782
 783 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
 784         .name           = "gpio1",
 785         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 786         .main_clk       = "gpio1_ick",
 787         .opt_clks       = gpio1_opt_clks,
 788         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 789         .prcm           = {
 790                 .omap2 = {
 791                         .module_offs = WKUP_MOD,
 792                         .idlest_reg_id = 1,
 793                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
 794                 },
 795         },
 796         .class          = &omap3xxx_gpio_hwmod_class,
 797         .dev_attr       = &gpio_dev_attr,
 798 };
 799
 800 /* gpio2 */
 801 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 802         { .role = "dbclk", .clk = "gpio2_dbck", },
 803 };
 804
 805 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
 806         .name           = "gpio2",
 807         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 808         .main_clk       = "gpio2_ick",
 809         .opt_clks       = gpio2_opt_clks,
 810         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 811         .prcm           = {
 812                 .omap2 = {
 813                         .module_offs = OMAP3430_PER_MOD,
 814                         .idlest_reg_id = 1,
 815                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
 816                 },
 817         },
 818         .class          = &omap3xxx_gpio_hwmod_class,
 819         .dev_attr       = &gpio_dev_attr,
 820 };
 821
 822 /* gpio3 */
 823 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 824         { .role = "dbclk", .clk = "gpio3_dbck", },
 825 };
 826
 827 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
 828         .name           = "gpio3",
 829         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 830         .main_clk       = "gpio3_ick",
 831         .opt_clks       = gpio3_opt_clks,
 832         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 833         .prcm           = {
 834                 .omap2 = {
 835                         .module_offs = OMAP3430_PER_MOD,
 836                         .idlest_reg_id = 1,
 837                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
 838                 },
 839         },
 840         .class          = &omap3xxx_gpio_hwmod_class,
 841         .dev_attr       = &gpio_dev_attr,
 842 };
 843
 844 /* gpio4 */
 845 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 846         { .role = "dbclk", .clk = "gpio4_dbck", },
 847 };
 848
 849 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
 850         .name           = "gpio4",
 851         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 852         .main_clk       = "gpio4_ick",
 853         .opt_clks       = gpio4_opt_clks,
 854         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 855         .prcm           = {
 856                 .omap2 = {
 857                         .module_offs = OMAP3430_PER_MOD,
 858                         .idlest_reg_id = 1,
 859                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
 860                 },
 861         },
 862         .class          = &omap3xxx_gpio_hwmod_class,
 863         .dev_attr       = &gpio_dev_attr,
 864 };
 865
 866 /* gpio5 */
 867
 868 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 869         { .role = "dbclk", .clk = "gpio5_dbck", },
 870 };
 871
 872 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
 873         .name           = "gpio5",
 874         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 875         .main_clk       = "gpio5_ick",
 876         .opt_clks       = gpio5_opt_clks,
 877         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
 878         .prcm           = {
 879                 .omap2 = {
 880                         .module_offs = OMAP3430_PER_MOD,
 881                         .idlest_reg_id = 1,
 882                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
 883                 },
 884         },
 885         .class          = &omap3xxx_gpio_hwmod_class,
 886         .dev_attr       = &gpio_dev_attr,
 887 };
 888
 889 /* gpio6 */
 890
 891 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
 892         { .role = "dbclk", .clk = "gpio6_dbck", },
 893 };
 894
 895 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
 896         .name           = "gpio6",
 897         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 898         .main_clk       = "gpio6_ick",
 899         .opt_clks       = gpio6_opt_clks,
 900         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
 901         .prcm           = {
 902                 .omap2 = {
 903                         .module_offs = OMAP3430_PER_MOD,
 904                         .idlest_reg_id = 1,
 905                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
 906                 },
 907         },
 908         .class          = &omap3xxx_gpio_hwmod_class,
 909         .dev_attr       = &gpio_dev_attr,
 910 };
 911
 912 /* dma attributes */
 913 static struct omap_dma_dev_attr dma_dev_attr = {
 914         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 915                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 916         .lch_count = 32,
 917 };
 918
 919 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
 920         .rev_offs       = 0x0000,
 921         .sysc_offs      = 0x002c,
 922         .syss_offs      = 0x0028,
 923         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 924                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 925                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
 926                            SYSS_HAS_RESET_STATUS),
 927         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 928                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 929         .sysc_fields    = &omap_hwmod_sysc_type1,
 930 };
 931
 932 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
 933         .name = "dma",
 934         .sysc = &omap3xxx_dma_sysc,
 935 };
 936
 937 /* dma_system */
 938 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
 939         .name           = "dma",
 940         .class          = &omap3xxx_dma_hwmod_class,
 941         .main_clk       = "core_l3_ick",
 942         .prcm = {
 943                 .omap2 = {
 944                         .module_offs            = CORE_MOD,
 945                         .idlest_reg_id          = 1,
 946                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
 947                 },
 948         },
 949         .dev_attr       = &dma_dev_attr,
 950         .flags          = HWMOD_NO_IDLEST,
 951 };
 952
 953 /*
 954  * 'mcbsp' class
 955  * multi channel buffered serial port controller
 956  */
 957
 958 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
 959         .sysc_offs      = 0x008c,
 960         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
 961                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 962         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 963         .sysc_fields    = &omap_hwmod_sysc_type1,
 964 };
 965
 966 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
 967         .name = "mcbsp",
 968         .sysc = &omap3xxx_mcbsp_sysc,
 969         .rev  = MCBSP_CONFIG_TYPE3,
 970 };
 971
 972 /* McBSP functional clock mapping */
 973 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
 974         { .role = "pad_fck", .clk = "mcbsp_clks" },
 975         { .role = "prcm_fck", .clk = "core_96m_fck" },
 976 };
 977
 978 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
 979         { .role = "pad_fck", .clk = "mcbsp_clks" },
 980         { .role = "prcm_fck", .clk = "per_96m_fck" },
 981 };
 982
 983 /* mcbsp1 */
 984
 985 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
 986         .name           = "mcbsp1",
 987         .class          = &omap3xxx_mcbsp_hwmod_class,
 988         .main_clk       = "mcbsp1_fck",
 989         .prcm           = {
 990                 .omap2 = {
 991                         .module_offs = CORE_MOD,
 992                         .idlest_reg_id = 1,
 993                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
 994                 },
 995         },
 996         .opt_clks       = mcbsp15_opt_clks,
 997         .opt_clks_cnt   = ARRAY_SIZE(mcbsp15_opt_clks),
 998 };
 999
1000 /* mcbsp2 */
1001
1002 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1003         .sidetone       = "mcbsp2_sidetone",
1004 };
1005
1006 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1007         .name           = "mcbsp2",
1008         .class          = &omap3xxx_mcbsp_hwmod_class,
1009         .main_clk       = "mcbsp2_fck",
1010         .prcm           = {
1011                 .omap2 = {
1012                         .module_offs = OMAP3430_PER_MOD,
1013                         .idlest_reg_id = 1,
1014                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1015                 },
1016         },
1017         .opt_clks       = mcbsp234_opt_clks,
1018         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1019         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
1020 };
1021
1022 /* mcbsp3 */
1023
1024 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1025         .sidetone       = "mcbsp3_sidetone",
1026 };
1027
1028 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1029         .name           = "mcbsp3",
1030         .class          = &omap3xxx_mcbsp_hwmod_class,
1031         .main_clk       = "mcbsp3_fck",
1032         .prcm           = {
1033                 .omap2 = {
1034                         .module_offs = OMAP3430_PER_MOD,
1035                         .idlest_reg_id = 1,
1036                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1037                 },
1038         },
1039         .opt_clks       = mcbsp234_opt_clks,
1040         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1041         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
1042 };
1043
1044 /* mcbsp4 */
1045
1046
1047 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1048         .name           = "mcbsp4",
1049         .class          = &omap3xxx_mcbsp_hwmod_class,
1050         .main_clk       = "mcbsp4_fck",
1051         .prcm           = {
1052                 .omap2 = {
1053                         .module_offs = OMAP3430_PER_MOD,
1054                         .idlest_reg_id = 1,
1055                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1056                 },
1057         },
1058         .opt_clks       = mcbsp234_opt_clks,
1059         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1060 };
1061
1062 /* mcbsp5 */
1063
1064
1065 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1066         .name           = "mcbsp5",
1067         .class          = &omap3xxx_mcbsp_hwmod_class,
1068         .main_clk       = "mcbsp5_fck",
1069         .prcm           = {
1070                 .omap2 = {
1071                         .module_offs = CORE_MOD,
1072                         .idlest_reg_id = 1,
1073                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1074                 },
1075         },
1076         .opt_clks       = mcbsp15_opt_clks,
1077         .opt_clks_cnt   = ARRAY_SIZE(mcbsp15_opt_clks),
1078 };
1079
1080 /* 'mcbsp sidetone' class */
1081 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
1082         .sysc_offs      = 0x0010,
1083         .sysc_flags     = SYSC_HAS_AUTOIDLE,
1084         .sysc_fields    = &omap_hwmod_sysc_type1,
1085 };
1086
1087 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1088         .name = "mcbsp_sidetone",
1089         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
1090 };
1091
1092 /* mcbsp2_sidetone */
1093
1094 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1095         .name           = "mcbsp2_sidetone",
1096         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
1097         .main_clk       = "mcbsp2_ick",
1098         .flags          = HWMOD_NO_IDLEST,
1099 };
1100
1101 /* mcbsp3_sidetone */
1102
1103 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1104         .name           = "mcbsp3_sidetone",
1105         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
1106         .main_clk       = "mcbsp3_ick",
1107         .flags          = HWMOD_NO_IDLEST,
1108 };
1109
1110 /* SR common */
1111 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1112         .sysc_offs      = 0x24,
1113         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1114         .sysc_fields    = &omap34xx_sr_sysc_fields,
1115 };
1116
1117 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1118         .name = "smartreflex",
1119         .sysc = &omap34xx_sr_sysc,
1120         .rev  = 1,
1121 };
1122
1123 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1124         .sysc_offs      = 0x38,
1125         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1126         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1127                         SYSC_NO_CACHE),
1128         .sysc_fields    = &omap36xx_sr_sysc_fields,
1129 };
1130
1131 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1132         .name = "smartreflex",
1133         .sysc = &omap36xx_sr_sysc,
1134         .rev  = 2,
1135 };
1136
1137 /* SR1 */
1138 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1139         .sensor_voltdm_name   = "mpu_iva",
1140 };
1141
1142
1143 static struct omap_hwmod omap34xx_sr1_hwmod = {
1144         .name           = "smartreflex_mpu_iva",
1145         .class          = &omap34xx_smartreflex_hwmod_class,
1146         .main_clk       = "sr1_fck",
1147         .prcm           = {
1148                 .omap2 = {
1149                         .module_offs = WKUP_MOD,
1150                         .idlest_reg_id = 1,
1151                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1152                 },
1153         },
1154         .dev_attr       = &sr1_dev_attr,
1155         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1156 };
1157
1158 static struct omap_hwmod omap36xx_sr1_hwmod = {
1159         .name           = "smartreflex_mpu_iva",
1160         .class          = &omap36xx_smartreflex_hwmod_class,
1161         .main_clk       = "sr1_fck",
1162         .prcm           = {
1163                 .omap2 = {
1164                         .module_offs = WKUP_MOD,
1165                         .idlest_reg_id = 1,
1166                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1167                 },
1168         },
1169         .dev_attr       = &sr1_dev_attr,
1170 };
1171
1172 /* SR2 */
1173 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1174         .sensor_voltdm_name     = "core",
1175 };
1176
1177
1178 static struct omap_hwmod omap34xx_sr2_hwmod = {
1179         .name           = "smartreflex_core",
1180         .class          = &omap34xx_smartreflex_hwmod_class,
1181         .main_clk       = "sr2_fck",
1182         .prcm           = {
1183                 .omap2 = {
1184                         .module_offs = WKUP_MOD,
1185                         .idlest_reg_id = 1,
1186                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1187                 },
1188         },
1189         .dev_attr       = &sr2_dev_attr,
1190         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1191 };
1192
1193 static struct omap_hwmod omap36xx_sr2_hwmod = {
1194         .name           = "smartreflex_core",
1195         .class          = &omap36xx_smartreflex_hwmod_class,
1196         .main_clk       = "sr2_fck",
1197         .prcm           = {
1198                 .omap2 = {
1199                         .module_offs = WKUP_MOD,
1200                         .idlest_reg_id = 1,
1201                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1202                 },
1203         },
1204         .dev_attr       = &sr2_dev_attr,
1205 };
1206
1207 /*
1208  * 'mailbox' class
1209  * mailbox module allowing communication between the on-chip processors
1210  * using a queued mailbox-interrupt mechanism.
1211  */
1212
1213 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1214         .rev_offs       = 0x000,
1215         .sysc_offs      = 0x010,
1216         .syss_offs      = 0x014,
1217         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1218                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1219         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1220         .sysc_fields    = &omap_hwmod_sysc_type1,
1221 };
1222
1223 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1224         .name = "mailbox",
1225         .sysc = &omap3xxx_mailbox_sysc,
1226 };
1227
1228 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1229         .name           = "mailbox",
1230         .class          = &omap3xxx_mailbox_hwmod_class,
1231         .main_clk       = "mailboxes_ick",
1232         .prcm           = {
1233                 .omap2 = {
1234                         .module_offs = CORE_MOD,
1235                         .idlest_reg_id = 1,
1236                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1237                 },
1238         },
1239 };
1240
1241 /*
1242  * 'mcspi' class
1243  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1244  * bus
1245  */
1246
1247 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1248         .rev_offs       = 0x0000,
1249         .sysc_offs      = 0x0010,
1250         .syss_offs      = 0x0014,
1251         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1252                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1253                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1254         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1255         .sysc_fields    = &omap_hwmod_sysc_type1,
1256 };
1257
1258 static struct omap_hwmod_class omap34xx_mcspi_class = {
1259         .name = "mcspi",
1260         .sysc = &omap34xx_mcspi_sysc,
1261         .rev = OMAP3_MCSPI_REV,
1262 };
1263
1264 /* mcspi1 */
1265 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1266         .num_chipselect = 4,
1267 };
1268
1269 static struct omap_hwmod omap34xx_mcspi1 = {
1270         .name           = "mcspi1",
1271         .main_clk       = "mcspi1_fck",
1272         .prcm           = {
1273                 .omap2 = {
1274                         .module_offs = CORE_MOD,
1275                         .idlest_reg_id = 1,
1276                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1277                 },
1278         },
1279         .class          = &omap34xx_mcspi_class,
1280         .dev_attr       = &omap_mcspi1_dev_attr,
1281 };
1282
1283 /* mcspi2 */
1284 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1285         .num_chipselect = 2,
1286 };
1287
1288 static struct omap_hwmod omap34xx_mcspi2 = {
1289         .name           = "mcspi2",
1290         .main_clk       = "mcspi2_fck",
1291         .prcm           = {
1292                 .omap2 = {
1293                         .module_offs = CORE_MOD,
1294                         .idlest_reg_id = 1,
1295                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1296                 },
1297         },
1298         .class          = &omap34xx_mcspi_class,
1299         .dev_attr       = &omap_mcspi2_dev_attr,
1300 };
1301
1302 /* mcspi3 */
1303
1304
1305 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1306         .num_chipselect = 2,
1307 };
1308
1309 static struct omap_hwmod omap34xx_mcspi3 = {
1310         .name           = "mcspi3",
1311         .main_clk       = "mcspi3_fck",
1312         .prcm           = {
1313                 .omap2 = {
1314                         .module_offs = CORE_MOD,
1315                         .idlest_reg_id = 1,
1316                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1317                 },
1318         },
1319         .class          = &omap34xx_mcspi_class,
1320         .dev_attr       = &omap_mcspi3_dev_attr,
1321 };
1322
1323 /* mcspi4 */
1324
1325
1326 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1327         .num_chipselect = 1,
1328 };
1329
1330 static struct omap_hwmod omap34xx_mcspi4 = {
1331         .name           = "mcspi4",
1332         .main_clk       = "mcspi4_fck",
1333         .prcm           = {
1334                 .omap2 = {
1335                         .module_offs = CORE_MOD,
1336                         .idlest_reg_id = 1,
1337                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1338                 },
1339         },
1340         .class          = &omap34xx_mcspi_class,
1341         .dev_attr       = &omap_mcspi4_dev_attr,
1342 };
1343
1344 /* usbhsotg */
1345 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1346         .rev_offs       = 0x0400,
1347         .sysc_offs      = 0x0404,
1348         .syss_offs      = 0x0408,
1349         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1350                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1351                           SYSC_HAS_AUTOIDLE),
1352         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1353                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1354         .sysc_fields    = &omap_hwmod_sysc_type1,
1355 };
1356
1357 static struct omap_hwmod_class usbotg_class = {
1358         .name = "usbotg",
1359         .sysc = &omap3xxx_usbhsotg_sysc,
1360 };
1361
1362 /* usb_otg_hs */
1363
1364 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1365         .name           = "usb_otg_hs",
1366         .main_clk       = "hsotgusb_ick",
1367         .prcm           = {
1368                 .omap2 = {
1369                         .module_offs = CORE_MOD,
1370                         .idlest_reg_id = 1,
1371                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1372                 },
1373         },
1374         .class          = &usbotg_class,
1375
1376         /*
1377          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
1378          * broken when autoidle is enabled
1379          * workaround is to disable the autoidle bit at module level.
1380          *
1381          * Enabling the device in any other MIDLEMODE setting but force-idle
1382          * causes core_pwrdm not enter idle states at least on OMAP3630.
1383          * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
1384          * signal when MIDLEMODE is set to force-idle.
1385          */
1386         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE |
1387                           HWMOD_FORCE_MSTANDBY | HWMOD_RECONFIG_IO_CHAIN,
1388 };
1389
1390 /* usb_otg_hs */
1391
1392 static struct omap_hwmod_class am35xx_usbotg_class = {
1393         .name = "am35xx_usbotg",
1394 };
1395
1396 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1397         .name           = "am35x_otg_hs",
1398         .main_clk       = "hsotgusb_fck",
1399         .class          = &am35xx_usbotg_class,
1400         .flags          = HWMOD_NO_IDLEST,
1401 };
1402
1403 /* MMC/SD/SDIO common */
1404 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1405         .rev_offs       = 0x1fc,
1406         .sysc_offs      = 0x10,
1407         .syss_offs      = 0x14,
1408         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1409                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1410                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1411         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1412         .sysc_fields    = &omap_hwmod_sysc_type1,
1413 };
1414
1415 static struct omap_hwmod_class omap34xx_mmc_class = {
1416         .name = "mmc",
1417         .sysc = &omap34xx_mmc_sysc,
1418 };
1419
1420 /* MMC/SD/SDIO1 */
1421
1422
1423
1424 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1425         { .role = "dbck", .clk = "omap_32k_fck", },
1426 };
1427
1428 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1429         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1430 };
1431
1432 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1433 static struct omap_hsmmc_dev_attr mmc1_pre_es3_dev_attr = {
1434         .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1435                   OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1436 };
1437
1438 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1439         .name           = "mmc1",
1440         .opt_clks       = omap34xx_mmc1_opt_clks,
1441         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1442         .main_clk       = "mmchs1_fck",
1443         .prcm           = {
1444                 .omap2 = {
1445                         .module_offs = CORE_MOD,
1446                         .idlest_reg_id = 1,
1447                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1448                 },
1449         },
1450         .dev_attr       = &mmc1_pre_es3_dev_attr,
1451         .class          = &omap34xx_mmc_class,
1452 };
1453
1454 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1455         .name           = "mmc1",
1456         .opt_clks       = omap34xx_mmc1_opt_clks,
1457         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1458         .main_clk       = "mmchs1_fck",
1459         .prcm           = {
1460                 .omap2 = {
1461                         .module_offs = CORE_MOD,
1462                         .idlest_reg_id = 1,
1463                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1464                 },
1465         },
1466         .dev_attr       = &mmc1_dev_attr,
1467         .class          = &omap34xx_mmc_class,
1468 };
1469
1470 /* MMC/SD/SDIO2 */
1471
1472
1473
1474 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1475         { .role = "dbck", .clk = "omap_32k_fck", },
1476 };
1477
1478 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1479 static struct omap_hsmmc_dev_attr mmc2_pre_es3_dev_attr = {
1480         .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1481 };
1482
1483 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1484         .name           = "mmc2",
1485         .opt_clks       = omap34xx_mmc2_opt_clks,
1486         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1487         .main_clk       = "mmchs2_fck",
1488         .prcm           = {
1489                 .omap2 = {
1490                         .module_offs = CORE_MOD,
1491                         .idlest_reg_id = 1,
1492                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1493                 },
1494         },
1495         .dev_attr       = &mmc2_pre_es3_dev_attr,
1496         .class          = &omap34xx_mmc_class,
1497 };
1498
1499 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1500         .name           = "mmc2",
1501         .opt_clks       = omap34xx_mmc2_opt_clks,
1502         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1503         .main_clk       = "mmchs2_fck",
1504         .prcm           = {
1505                 .omap2 = {
1506                         .module_offs = CORE_MOD,
1507                         .idlest_reg_id = 1,
1508                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1509                 },
1510         },
1511         .class          = &omap34xx_mmc_class,
1512 };
1513
1514 /* MMC/SD/SDIO3 */
1515
1516
1517
1518 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1519         { .role = "dbck", .clk = "omap_32k_fck", },
1520 };
1521
1522 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1523         .name           = "mmc3",
1524         .opt_clks       = omap34xx_mmc3_opt_clks,
1525         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1526         .main_clk       = "mmchs3_fck",
1527         .prcm           = {
1528                 .omap2 = {
1529                         .module_offs = CORE_MOD,
1530                         .idlest_reg_id = 1,
1531                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1532                 },
1533         },
1534         .class          = &omap34xx_mmc_class,
1535 };
1536
1537 /*
1538  * 'usb_host_hs' class
1539  * high-speed multi-port usb host controller
1540  */
1541
1542 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1543         .rev_offs       = 0x0000,
1544         .sysc_offs      = 0x0010,
1545         .syss_offs      = 0x0014,
1546         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1547                            SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1548                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1549                            SYSS_HAS_RESET_STATUS),
1550         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1551                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1552         .sysc_fields    = &omap_hwmod_sysc_type1,
1553 };
1554
1555 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1556         .name = "usb_host_hs",
1557         .sysc = &omap3xxx_usb_host_hs_sysc,
1558 };
1559
1560
1561 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1562         .name           = "usb_host_hs",
1563         .class          = &omap3xxx_usb_host_hs_hwmod_class,
1564         .clkdm_name     = "usbhost_clkdm",
1565         .main_clk       = "usbhost_48m_fck",
1566         .prcm = {
1567                 .omap2 = {
1568                         .module_offs = OMAP3430ES2_USBHOST_MOD,
1569                         .idlest_reg_id = 1,
1570                         .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1571                 },
1572         },
1573
1574         /*
1575          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1576          * id: i660
1577          *
1578          * Description:
1579          * In the following configuration :
1580          * - USBHOST module is set to smart-idle mode
1581          * - PRCM asserts idle_req to the USBHOST module ( This typically
1582          *   happens when the system is going to a low power mode : all ports
1583          *   have been suspended, the master part of the USBHOST module has
1584          *   entered the standby state, and SW has cut the functional clocks)
1585          * - an USBHOST interrupt occurs before the module is able to answer
1586          *   idle_ack, typically a remote wakeup IRQ.
1587          * Then the USB HOST module will enter a deadlock situation where it
1588          * is no more accessible nor functional.
1589          *
1590          * Workaround:
1591          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1592          */
1593
1594         /*
1595          * Errata: USB host EHCI may stall when entering smart-standby mode
1596          * Id: i571
1597          *
1598          * Description:
1599          * When the USBHOST module is set to smart-standby mode, and when it is
1600          * ready to enter the standby state (i.e. all ports are suspended and
1601          * all attached devices are in suspend mode), then it can wrongly assert
1602          * the Mstandby signal too early while there are still some residual OCP
1603          * transactions ongoing. If this condition occurs, the internal state
1604          * machine may go to an undefined state and the USB link may be stuck
1605          * upon the next resume.
1606          *
1607          * Workaround:
1608          * Don't use smart standby; use only force standby,
1609          * hence HWMOD_SWSUP_MSTANDBY
1610          */
1611
1612         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1613 };
1614
1615 /*
1616  * 'usb_tll_hs' class
1617  * usb_tll_hs module is the adapter on the usb_host_hs ports
1618  */
1619 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
1620         .rev_offs       = 0x0000,
1621         .sysc_offs      = 0x0010,
1622         .syss_offs      = 0x0014,
1623         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1624                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1625                            SYSC_HAS_AUTOIDLE),
1626         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1627         .sysc_fields    = &omap_hwmod_sysc_type1,
1628 };
1629
1630 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
1631         .name = "usb_tll_hs",
1632         .sysc = &omap3xxx_usb_tll_hs_sysc,
1633 };
1634
1635
1636 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
1637         .name           = "usb_tll_hs",
1638         .class          = &omap3xxx_usb_tll_hs_hwmod_class,
1639         .clkdm_name     = "core_l4_clkdm",
1640         .main_clk       = "usbtll_fck",
1641         .prcm = {
1642                 .omap2 = {
1643                         .module_offs = CORE_MOD,
1644                         .idlest_reg_id = 3,
1645                         .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
1646                 },
1647         },
1648 };
1649
1650 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
1651         .name           = "hdq1w",
1652         .main_clk       = "hdq_fck",
1653         .prcm           = {
1654                 .omap2 = {
1655                         .module_offs = CORE_MOD,
1656                         .idlest_reg_id = 1,
1657                         .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
1658                 },
1659         },
1660         .class          = &omap2_hdq1w_class,
1661 };
1662
1663 /* SAD2D */
1664 static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
1665         { .name = "rst_modem_pwron_sw", .rst_shift = 0 },
1666         { .name = "rst_modem_sw", .rst_shift = 1 },
1667 };
1668
1669 static struct omap_hwmod_class omap3xxx_sad2d_class = {
1670         .name                   = "sad2d",
1671 };
1672
1673 static struct omap_hwmod omap3xxx_sad2d_hwmod = {
1674         .name           = "sad2d",
1675         .rst_lines      = omap3xxx_sad2d_resets,
1676         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_sad2d_resets),
1677         .main_clk       = "sad2d_ick",
1678         .prcm           = {
1679                 .omap2 = {
1680                         .module_offs = CORE_MOD,
1681                         .idlest_reg_id = 1,
1682                         .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
1683                 },
1684         },
1685         .class          = &omap3xxx_sad2d_class,
1686 };
1687
1688 /*
1689  * '32K sync counter' class
1690  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
1691  */
1692 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
1693         .rev_offs       = 0x0000,
1694         .sysc_offs      = 0x0004,
1695         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1696         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
1697         .sysc_fields    = &omap_hwmod_sysc_type1,
1698 };
1699
1700 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
1701         .name   = "counter",
1702         .sysc   = &omap3xxx_counter_sysc,
1703 };
1704
1705 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
1706         .name           = "counter_32k",
1707         .class          = &omap3xxx_counter_hwmod_class,
1708         .clkdm_name     = "wkup_clkdm",
1709         .flags          = HWMOD_SWSUP_SIDLE,
1710         .main_clk       = "wkup_32k_fck",
1711         .prcm           = {
1712                 .omap2  = {
1713                         .module_offs = WKUP_MOD,
1714                         .idlest_reg_id = 1,
1715                         .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
1716                 },
1717         },
1718 };
1719
1720 /*
1721  * 'gpmc' class
1722  * general purpose memory controller
1723  */
1724
1725 static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
1726         .rev_offs       = 0x0000,
1727         .sysc_offs      = 0x0010,
1728         .syss_offs      = 0x0014,
1729         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1730                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1731         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1732         .sysc_fields    = &omap_hwmod_sysc_type1,
1733 };
1734
1735 static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
1736         .name   = "gpmc",
1737         .sysc   = &omap3xxx_gpmc_sysc,
1738 };
1739
1740 static struct omap_hwmod omap3xxx_gpmc_hwmod = {
1741         .name           = "gpmc",
1742         .class          = &omap3xxx_gpmc_hwmod_class,
1743         .clkdm_name     = "core_l3_clkdm",
1744         .main_clk       = "gpmc_fck",
1745         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
1746         .flags          = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
1747 };
1748
1749 /*
1750  * interfaces
1751  */
1752
1753 /* L3 -> L4_CORE interface */
1754 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
1755         .master = &omap3xxx_l3_main_hwmod,
1756         .slave  = &omap3xxx_l4_core_hwmod,
1757         .user   = OCP_USER_MPU | OCP_USER_SDMA,
1758 };
1759
1760 /* L3 -> L4_PER interface */
1761 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
1762         .master = &omap3xxx_l3_main_hwmod,
1763         .slave  = &omap3xxx_l4_per_hwmod,
1764         .user   = OCP_USER_MPU | OCP_USER_SDMA,
1765 };
1766
1767
1768 /* MPU -> L3 interface */
1769 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
1770         .master   = &omap3xxx_mpu_hwmod,
1771         .slave    = &omap3xxx_l3_main_hwmod,
1772         .user   = OCP_USER_MPU,
1773 };
1774
1775
1776 /* l3 -> debugss */
1777 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
1778         .master         = &omap3xxx_l3_main_hwmod,
1779         .slave          = &omap3xxx_debugss_hwmod,
1780         .user           = OCP_USER_MPU,
1781 };
1782
1783 /* DSS -> l3 */
1784 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
1785         .master         = &omap3430es1_dss_core_hwmod,
1786         .slave          = &omap3xxx_l3_main_hwmod,
1787         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1788 };
1789
1790 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
1791         .master         = &omap3xxx_dss_core_hwmod,
1792         .slave          = &omap3xxx_l3_main_hwmod,
1793         .fw = {
1794                 .omap2 = {
1795                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
1796                         .flags  = OMAP_FIREWALL_L3,
1797                 },
1798         },
1799         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1800 };
1801
1802 /* l3_core -> usbhsotg interface */
1803 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
1804         .master         = &omap3xxx_usbhsotg_hwmod,
1805         .slave          = &omap3xxx_l3_main_hwmod,
1806         .clk            = "core_l3_ick",
1807         .user           = OCP_USER_MPU,
1808 };
1809
1810 /* l3_core -> am35xx_usbhsotg interface */
1811 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
1812         .master         = &am35xx_usbhsotg_hwmod,
1813         .slave          = &omap3xxx_l3_main_hwmod,
1814         .clk            = "hsotgusb_ick",
1815         .user           = OCP_USER_MPU,
1816 };
1817
1818 /* l3_core -> sad2d interface */
1819 static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
1820         .master         = &omap3xxx_sad2d_hwmod,
1821         .slave          = &omap3xxx_l3_main_hwmod,
1822         .clk            = "core_l3_ick",
1823         .user           = OCP_USER_MPU,
1824 };
1825
1826 /* L4_CORE -> L4_WKUP interface */
1827 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
1828         .master = &omap3xxx_l4_core_hwmod,
1829         .slave  = &omap3xxx_l4_wkup_hwmod,
1830         .user   = OCP_USER_MPU | OCP_USER_SDMA,
1831 };
1832
1833 /* L4 CORE -> MMC1 interface */
1834 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
1835         .master         = &omap3xxx_l4_core_hwmod,
1836         .slave          = &omap3xxx_pre_es3_mmc1_hwmod,
1837         .clk            = "mmchs1_ick",
1838         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1839         .flags          = OMAP_FIREWALL_L4,
1840 };
1841
1842 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
1843         .master         = &omap3xxx_l4_core_hwmod,
1844         .slave          = &omap3xxx_es3plus_mmc1_hwmod,
1845         .clk            = "mmchs1_ick",
1846         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1847         .flags          = OMAP_FIREWALL_L4,
1848 };
1849
1850 /* L4 CORE -> MMC2 interface */
1851 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
1852         .master         = &omap3xxx_l4_core_hwmod,
1853         .slave          = &omap3xxx_pre_es3_mmc2_hwmod,
1854         .clk            = "mmchs2_ick",
1855         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1856         .flags          = OMAP_FIREWALL_L4,
1857 };
1858
1859 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
1860         .master         = &omap3xxx_l4_core_hwmod,
1861         .slave          = &omap3xxx_es3plus_mmc2_hwmod,
1862         .clk            = "mmchs2_ick",
1863         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1864         .flags          = OMAP_FIREWALL_L4,
1865 };
1866
1867 /* L4 CORE -> MMC3 interface */
1868
1869 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
1870         .master         = &omap3xxx_l4_core_hwmod,
1871         .slave          = &omap3xxx_mmc3_hwmod,
1872         .clk            = "mmchs3_ick",
1873         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1874         .flags          = OMAP_FIREWALL_L4,
1875 };
1876
1877 /* L4 CORE -> UART1 interface */
1878
1879 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
1880         .master         = &omap3xxx_l4_core_hwmod,
1881         .slave          = &omap3xxx_uart1_hwmod,
1882         .clk            = "uart1_ick",
1883         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1884 };
1885
1886 /* L4 CORE -> UART2 interface */
1887
1888 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
1889         .master         = &omap3xxx_l4_core_hwmod,
1890         .slave          = &omap3xxx_uart2_hwmod,
1891         .clk            = "uart2_ick",
1892         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1893 };
1894
1895 /* L4 PER -> UART3 interface */
1896
1897 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
1898         .master         = &omap3xxx_l4_per_hwmod,
1899         .slave          = &omap3xxx_uart3_hwmod,
1900         .clk            = "uart3_ick",
1901         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1902 };
1903
1904 /* L4 PER -> UART4 interface */
1905
1906 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
1907         .master         = &omap3xxx_l4_per_hwmod,
1908         .slave          = &omap36xx_uart4_hwmod,
1909         .clk            = "uart4_ick",
1910         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1911 };
1912
1913 /* AM35xx: L4 CORE -> UART4 interface */
1914
1915 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
1916         .master         = &omap3xxx_l4_core_hwmod,
1917         .slave          = &am35xx_uart4_hwmod,
1918         .clk            = "uart4_ick",
1919         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1920 };
1921
1922 /* L4 CORE -> I2C1 interface */
1923 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
1924         .master         = &omap3xxx_l4_core_hwmod,
1925         .slave          = &omap3xxx_i2c1_hwmod,
1926         .clk            = "i2c1_ick",
1927         .fw = {
1928                 .omap2 = {
1929                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
1930                         .l4_prot_group = 7,
1931                         .flags  = OMAP_FIREWALL_L4,
1932                 },
1933         },
1934         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1935 };
1936
1937 /* L4 CORE -> I2C2 interface */
1938 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
1939         .master         = &omap3xxx_l4_core_hwmod,
1940         .slave          = &omap3xxx_i2c2_hwmod,
1941         .clk            = "i2c2_ick",
1942         .fw = {
1943                 .omap2 = {
1944                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
1945                         .l4_prot_group = 7,
1946                         .flags = OMAP_FIREWALL_L4,
1947                 },
1948         },
1949         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1950 };
1951
1952 /* L4 CORE -> I2C3 interface */
1953
1954 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
1955         .master         = &omap3xxx_l4_core_hwmod,
1956         .slave          = &omap3xxx_i2c3_hwmod,
1957         .clk            = "i2c3_ick",
1958         .fw = {
1959                 .omap2 = {
1960                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
1961                         .l4_prot_group = 7,
1962                         .flags = OMAP_FIREWALL_L4,
1963                 },
1964         },
1965         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1966 };
1967
1968 /* L4 CORE -> SR1 interface */
1969 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
1970         .master         = &omap3xxx_l4_core_hwmod,
1971         .slave          = &omap34xx_sr1_hwmod,
1972         .clk            = "sr_l4_ick",
1973         .user           = OCP_USER_MPU,
1974 };
1975
1976 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
1977         .master         = &omap3xxx_l4_core_hwmod,
1978         .slave          = &omap36xx_sr1_hwmod,
1979         .clk            = "sr_l4_ick",
1980         .user           = OCP_USER_MPU,
1981 };
1982
1983 /* L4 CORE -> SR2 interface */
1984
1985 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
1986         .master         = &omap3xxx_l4_core_hwmod,
1987         .slave          = &omap34xx_sr2_hwmod,
1988         .clk            = "sr_l4_ick",
1989         .user           = OCP_USER_MPU,
1990 };
1991
1992 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
1993         .master         = &omap3xxx_l4_core_hwmod,
1994         .slave          = &omap36xx_sr2_hwmod,
1995         .clk            = "sr_l4_ick",
1996         .user           = OCP_USER_MPU,
1997 };
1998
1999
2000 /* l4_core -> usbhsotg  */
2001 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2002         .master         = &omap3xxx_l4_core_hwmod,
2003         .slave          = &omap3xxx_usbhsotg_hwmod,
2004         .clk            = "l4_ick",
2005         .user           = OCP_USER_MPU,
2006 };
2007
2008
2009 /* l4_core -> usbhsotg  */
2010 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2011         .master         = &omap3xxx_l4_core_hwmod,
2012         .slave          = &am35xx_usbhsotg_hwmod,
2013         .clk            = "hsotgusb_ick",
2014         .user           = OCP_USER_MPU,
2015 };
2016
2017 /* L4_WKUP -> L4_SEC interface */
2018 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2019         .master = &omap3xxx_l4_wkup_hwmod,
2020         .slave  = &omap3xxx_l4_sec_hwmod,
2021         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2022 };
2023
2024 /* IVA2 <- L3 interface */
2025 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2026         .master         = &omap3xxx_l3_main_hwmod,
2027         .slave          = &omap3xxx_iva_hwmod,
2028         .clk            = "core_l3_ick",
2029         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2030 };
2031
2032
2033 /* l4_wkup -> timer1 */
2034 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2035         .master         = &omap3xxx_l4_wkup_hwmod,
2036         .slave          = &omap3xxx_timer1_hwmod,
2037         .clk            = "gpt1_ick",
2038         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2039 };
2040
2041
2042 /* l4_per -> timer2 */
2043 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2044         .master         = &omap3xxx_l4_per_hwmod,
2045         .slave          = &omap3xxx_timer2_hwmod,
2046         .clk            = "gpt2_ick",
2047         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2048 };
2049
2050
2051 /* l4_per -> timer3 */
2052 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2053         .master         = &omap3xxx_l4_per_hwmod,
2054         .slave          = &omap3xxx_timer3_hwmod,
2055         .clk            = "gpt3_ick",
2056         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2057 };
2058
2059
2060 /* l4_per -> timer4 */
2061 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2062         .master         = &omap3xxx_l4_per_hwmod,
2063         .slave          = &omap3xxx_timer4_hwmod,
2064         .clk            = "gpt4_ick",
2065         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2066 };
2067
2068
2069 /* l4_per -> timer5 */
2070 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2071         .master         = &omap3xxx_l4_per_hwmod,
2072         .slave          = &omap3xxx_timer5_hwmod,
2073         .clk            = "gpt5_ick",
2074         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2075 };
2076
2077
2078 /* l4_per -> timer6 */
2079 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2080         .master         = &omap3xxx_l4_per_hwmod,
2081         .slave          = &omap3xxx_timer6_hwmod,
2082         .clk            = "gpt6_ick",
2083         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2084 };
2085
2086
2087 /* l4_per -> timer7 */
2088 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2089         .master         = &omap3xxx_l4_per_hwmod,
2090         .slave          = &omap3xxx_timer7_hwmod,
2091         .clk            = "gpt7_ick",
2092         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2093 };
2094
2095
2096 /* l4_per -> timer8 */
2097 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2098         .master         = &omap3xxx_l4_per_hwmod,
2099         .slave          = &omap3xxx_timer8_hwmod,
2100         .clk            = "gpt8_ick",
2101         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2102 };
2103
2104
2105 /* l4_per -> timer9 */
2106 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2107         .master         = &omap3xxx_l4_per_hwmod,
2108         .slave          = &omap3xxx_timer9_hwmod,
2109         .clk            = "gpt9_ick",
2110         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2111 };
2112
2113 /* l4_core -> timer10 */
2114 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2115         .master         = &omap3xxx_l4_core_hwmod,
2116         .slave          = &omap3xxx_timer10_hwmod,
2117         .clk            = "gpt10_ick",
2118         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2119 };
2120
2121 /* l4_core -> timer11 */
2122 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2123         .master         = &omap3xxx_l4_core_hwmod,
2124         .slave          = &omap3xxx_timer11_hwmod,
2125         .clk            = "gpt11_ick",
2126         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2127 };
2128
2129
2130 /* l4_core -> timer12 */
2131 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2132         .master         = &omap3xxx_l4_sec_hwmod,
2133         .slave          = &omap3xxx_timer12_hwmod,
2134         .clk            = "gpt12_ick",
2135         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2136 };
2137
2138 /* l4_wkup -> wd_timer2 */
2139
2140 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2141         .master         = &omap3xxx_l4_wkup_hwmod,
2142         .slave          = &omap3xxx_wd_timer2_hwmod,
2143         .clk            = "wdt2_ick",
2144         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2145 };
2146
2147 /* l4_core -> dss */
2148 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2149         .master         = &omap3xxx_l4_core_hwmod,
2150         .slave          = &omap3430es1_dss_core_hwmod,
2151         .clk            = "dss_ick",
2152         .fw = {
2153                 .omap2 = {
2154                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2155                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2156                         .flags  = OMAP_FIREWALL_L4,
2157                 },
2158         },
2159         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2160 };
2161
2162 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2163         .master         = &omap3xxx_l4_core_hwmod,
2164         .slave          = &omap3xxx_dss_core_hwmod,
2165         .clk            = "dss_ick",
2166         .fw = {
2167                 .omap2 = {
2168                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2169                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2170                         .flags  = OMAP_FIREWALL_L4,
2171                 },
2172         },
2173         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2174 };
2175
2176 /* l4_core -> dss_dispc */
2177 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2178         .master         = &omap3xxx_l4_core_hwmod,
2179         .slave          = &omap3xxx_dss_dispc_hwmod,
2180         .clk            = "dss_ick",
2181         .fw = {
2182                 .omap2 = {
2183                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2184                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2185                         .flags  = OMAP_FIREWALL_L4,
2186                 },
2187         },
2188         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2189 };
2190
2191 /* l4_core -> dss_dsi1 */
2192 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2193         .master         = &omap3xxx_l4_core_hwmod,
2194         .slave          = &omap3xxx_dss_dsi1_hwmod,
2195         .clk            = "dss_ick",
2196         .fw = {
2197                 .omap2 = {
2198                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2199                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2200                         .flags  = OMAP_FIREWALL_L4,
2201                 },
2202         },
2203         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2204 };
2205
2206 /* l4_core -> dss_rfbi */
2207 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2208         .master         = &omap3xxx_l4_core_hwmod,
2209         .slave          = &omap3xxx_dss_rfbi_hwmod,
2210         .clk            = "dss_ick",
2211         .fw = {
2212                 .omap2 = {
2213                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2214                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2215                         .flags  = OMAP_FIREWALL_L4,
2216                 },
2217         },
2218         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2219 };
2220
2221 /* l4_core -> dss_venc */
2222 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2223         .master         = &omap3xxx_l4_core_hwmod,
2224         .slave          = &omap3xxx_dss_venc_hwmod,
2225         .clk            = "dss_ick",
2226         .fw = {
2227                 .omap2 = {
2228                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2229                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2230                         .flags  = OMAP_FIREWALL_L4,
2231                 },
2232         },
2233         .flags          = OCPIF_SWSUP_IDLE,
2234         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2235 };
2236
2237 /* l4_wkup -> gpio1 */
2238
2239 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2240         .master         = &omap3xxx_l4_wkup_hwmod,
2241         .slave          = &omap3xxx_gpio1_hwmod,
2242         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2243 };
2244
2245 /* l4_per -> gpio2 */
2246
2247 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2248         .master         = &omap3xxx_l4_per_hwmod,
2249         .slave          = &omap3xxx_gpio2_hwmod,
2250         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2251 };
2252
2253 /* l4_per -> gpio3 */
2254
2255 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2256         .master         = &omap3xxx_l4_per_hwmod,
2257         .slave          = &omap3xxx_gpio3_hwmod,
2258         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2259 };
2260
2261 /*
2262  * 'mmu' class
2263  * The memory management unit performs virtual to physical address translation
2264  * for its requestors.
2265  */
2266
2267 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2268         .rev_offs       = 0x000,
2269         .sysc_offs      = 0x010,
2270         .syss_offs      = 0x014,
2271         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2272                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2273         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2274         .sysc_fields    = &omap_hwmod_sysc_type1,
2275 };
2276
2277 static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
2278         .name = "mmu",
2279         .sysc = &mmu_sysc,
2280 };
2281
2282 /* mmu isp */
2283 static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
2284
2285 /* l4_core -> mmu isp */
2286 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
2287         .master         = &omap3xxx_l4_core_hwmod,
2288         .slave          = &omap3xxx_mmu_isp_hwmod,
2289         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2290 };
2291
2292 static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
2293         .name           = "mmu_isp",
2294         .class          = &omap3xxx_mmu_hwmod_class,
2295         .main_clk       = "cam_ick",
2296         .flags          = HWMOD_NO_IDLEST,
2297 };
2298
2299 /* mmu iva */
2300
2301 static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
2302
2303 static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
2304         { .name = "mmu", .rst_shift = 1, .st_shift = 9 },
2305 };
2306
2307 /* l3_main -> iva mmu */
2308 static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
2309         .master         = &omap3xxx_l3_main_hwmod,
2310         .slave          = &omap3xxx_mmu_iva_hwmod,
2311         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2312 };
2313
2314 static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
2315         .name           = "mmu_iva",
2316         .class          = &omap3xxx_mmu_hwmod_class,
2317         .clkdm_name     = "iva2_clkdm",
2318         .rst_lines      = omap3xxx_mmu_iva_resets,
2319         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_mmu_iva_resets),
2320         .main_clk       = "iva2_ck",
2321         .prcm = {
2322                 .omap2 = {
2323                         .module_offs = OMAP3430_IVA2_MOD,
2324                         .idlest_reg_id = 1,
2325                         .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
2326                 },
2327         },
2328         .flags          = HWMOD_NO_IDLEST,
2329 };
2330
2331 /* l4_per -> gpio4 */
2332
2333 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
2334         .master         = &omap3xxx_l4_per_hwmod,
2335         .slave          = &omap3xxx_gpio4_hwmod,
2336         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2337 };
2338
2339 /* l4_per -> gpio5 */
2340
2341 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2342         .master         = &omap3xxx_l4_per_hwmod,
2343         .slave          = &omap3xxx_gpio5_hwmod,
2344         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2345 };
2346
2347 /* l4_per -> gpio6 */
2348
2349 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2350         .master         = &omap3xxx_l4_per_hwmod,
2351         .slave          = &omap3xxx_gpio6_hwmod,
2352         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2353 };
2354
2355 /* dma_system -> L3 */
2356 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2357         .master         = &omap3xxx_dma_system_hwmod,
2358         .slave          = &omap3xxx_l3_main_hwmod,
2359         .clk            = "core_l3_ick",
2360         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2361 };
2362
2363 /* l4_cfg -> dma_system */
2364 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2365         .master         = &omap3xxx_l4_core_hwmod,
2366         .slave          = &omap3xxx_dma_system_hwmod,
2367         .clk            = "core_l4_ick",
2368         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2369 };
2370
2371
2372 /* l4_core -> mcbsp1 */
2373 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2374         .master         = &omap3xxx_l4_core_hwmod,
2375         .slave          = &omap3xxx_mcbsp1_hwmod,
2376         .clk            = "mcbsp1_ick",
2377         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2378 };
2379
2380
2381 /* l4_per -> mcbsp2 */
2382 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2383         .master         = &omap3xxx_l4_per_hwmod,
2384         .slave          = &omap3xxx_mcbsp2_hwmod,
2385         .clk            = "mcbsp2_ick",
2386         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2387 };
2388
2389
2390 /* l4_per -> mcbsp3 */
2391 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2392         .master         = &omap3xxx_l4_per_hwmod,
2393         .slave          = &omap3xxx_mcbsp3_hwmod,
2394         .clk            = "mcbsp3_ick",
2395         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2396 };
2397
2398
2399 /* l4_per -> mcbsp4 */
2400 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2401         .master         = &omap3xxx_l4_per_hwmod,
2402         .slave          = &omap3xxx_mcbsp4_hwmod,
2403         .clk            = "mcbsp4_ick",
2404         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2405 };
2406
2407
2408 /* l4_core -> mcbsp5 */
2409 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2410         .master         = &omap3xxx_l4_core_hwmod,
2411         .slave          = &omap3xxx_mcbsp5_hwmod,
2412         .clk            = "mcbsp5_ick",
2413         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2414 };
2415
2416
2417 /* l4_per -> mcbsp2_sidetone */
2418 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2419         .master         = &omap3xxx_l4_per_hwmod,
2420         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
2421         .clk            = "mcbsp2_ick",
2422         .user           = OCP_USER_MPU,
2423 };
2424
2425
2426 /* l4_per -> mcbsp3_sidetone */
2427 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2428         .master         = &omap3xxx_l4_per_hwmod,
2429         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
2430         .clk            = "mcbsp3_ick",
2431         .user           = OCP_USER_MPU,
2432 };
2433
2434 /* l4_core -> mailbox */
2435 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2436         .master         = &omap3xxx_l4_core_hwmod,
2437         .slave          = &omap3xxx_mailbox_hwmod,
2438         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2439 };
2440
2441 /* l4 core -> mcspi1 interface */
2442 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2443         .master         = &omap3xxx_l4_core_hwmod,
2444         .slave          = &omap34xx_mcspi1,
2445         .clk            = "mcspi1_ick",
2446         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2447 };
2448
2449 /* l4 core -> mcspi2 interface */
2450 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2451         .master         = &omap3xxx_l4_core_hwmod,
2452         .slave          = &omap34xx_mcspi2,
2453         .clk            = "mcspi2_ick",
2454         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2455 };
2456
2457 /* l4 core -> mcspi3 interface */
2458 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2459         .master         = &omap3xxx_l4_core_hwmod,
2460         .slave          = &omap34xx_mcspi3,
2461         .clk            = "mcspi3_ick",
2462         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2463 };
2464
2465 /* l4 core -> mcspi4 interface */
2466
2467 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2468         .master         = &omap3xxx_l4_core_hwmod,
2469         .slave          = &omap34xx_mcspi4,
2470         .clk            = "mcspi4_ick",
2471         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2472 };
2473
2474 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
2475         .master         = &omap3xxx_usb_host_hs_hwmod,
2476         .slave          = &omap3xxx_l3_main_hwmod,
2477         .clk            = "core_l3_ick",
2478         .user           = OCP_USER_MPU,
2479 };
2480
2481
2482 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
2483         .master         = &omap3xxx_l4_core_hwmod,
2484         .slave          = &omap3xxx_usb_host_hs_hwmod,
2485         .clk            = "usbhost_ick",
2486         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2487 };
2488
2489
2490 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
2491         .master         = &omap3xxx_l4_core_hwmod,
2492         .slave          = &omap3xxx_usb_tll_hs_hwmod,
2493         .clk            = "usbtll_ick",
2494         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2495 };
2496
2497 /* l4_core -> hdq1w interface */
2498 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
2499         .master         = &omap3xxx_l4_core_hwmod,
2500         .slave          = &omap3xxx_hdq1w_hwmod,
2501         .clk            = "hdq_ick",
2502         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2503         .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
2504 };
2505
2506 /* l4_wkup -> 32ksync_counter */
2507
2508
2509 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
2510         .master         = &omap3xxx_l4_wkup_hwmod,
2511         .slave          = &omap3xxx_counter_32k_hwmod,
2512         .clk            = "omap_32ksync_ick",
2513         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2514 };
2515
2516 /* am35xx has Davinci MDIO & EMAC */
2517 static struct omap_hwmod_class am35xx_mdio_class = {
2518         .name = "davinci_mdio",
2519 };
2520
2521 static struct omap_hwmod am35xx_mdio_hwmod = {
2522         .name           = "davinci_mdio",
2523         .class          = &am35xx_mdio_class,
2524         .flags          = HWMOD_NO_IDLEST,
2525 };
2526
2527 /*
2528  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
2529  * but this will probably require some additional hwmod core support,
2530  * so is left as a future to-do item.
2531  */
2532 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
2533         .master         = &am35xx_mdio_hwmod,
2534         .slave          = &omap3xxx_l3_main_hwmod,
2535         .clk            = "emac_fck",
2536         .user           = OCP_USER_MPU,
2537 };
2538
2539 /* l4_core -> davinci mdio  */
2540 /*
2541  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
2542  * but this will probably require some additional hwmod core support,
2543  * so is left as a future to-do item.
2544  */
2545 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
2546         .master         = &omap3xxx_l4_core_hwmod,
2547         .slave          = &am35xx_mdio_hwmod,
2548         .clk            = "emac_fck",
2549         .user           = OCP_USER_MPU,
2550 };
2551
2552 static struct omap_hwmod_class am35xx_emac_class = {
2553         .name = "davinci_emac",
2554 };
2555
2556 static struct omap_hwmod am35xx_emac_hwmod = {
2557         .name           = "davinci_emac",
2558         .class          = &am35xx_emac_class,
2559         /*
2560          * According to Mark Greer, the MPU will not return from WFI
2561          * when the EMAC signals an interrupt.
2562          * http://www.spinics.net/lists/arm-kernel/msg174734.html
2563          */
2564         .flags          = (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI),
2565 };
2566
2567 /* l3_core -> davinci emac interface */
2568 /*
2569  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
2570  * but this will probably require some additional hwmod core support,
2571  * so is left as a future to-do item.
2572  */
2573 static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
2574         .master         = &am35xx_emac_hwmod,
2575         .slave          = &omap3xxx_l3_main_hwmod,
2576         .clk            = "emac_ick",
2577         .user           = OCP_USER_MPU,
2578 };
2579
2580 /* l4_core -> davinci emac  */
2581 /*
2582  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
2583  * but this will probably require some additional hwmod core support,
2584  * so is left as a future to-do item.
2585  */
2586 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
2587         .master         = &omap3xxx_l4_core_hwmod,
2588         .slave          = &am35xx_emac_hwmod,
2589         .clk            = "emac_ick",
2590         .user           = OCP_USER_MPU,
2591 };
2592
2593 static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
2594         .master         = &omap3xxx_l3_main_hwmod,
2595         .slave          = &omap3xxx_gpmc_hwmod,
2596         .clk            = "core_l3_ick",
2597         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2598 };
2599
2600 /* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */
2601 static struct omap_hwmod_class_sysconfig omap3_sham_sysc = {
2602         .rev_offs       = 0x5c,
2603         .sysc_offs      = 0x60,
2604         .syss_offs      = 0x64,
2605         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2606                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2607         .sysc_fields    = &omap3_sham_sysc_fields,
2608 };
2609
2610 static struct omap_hwmod_class omap3xxx_sham_class = {
2611         .name   = "sham",
2612         .sysc   = &omap3_sham_sysc,
2613 };
2614
2615
2616
2617 static struct omap_hwmod omap3xxx_sham_hwmod = {
2618         .name           = "sham",
2619         .main_clk       = "sha12_ick",
2620         .prcm           = {
2621                 .omap2 = {
2622                         .module_offs = CORE_MOD,
2623                         .idlest_reg_id = 1,
2624                         .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT,
2625                 },
2626         },
2627         .class          = &omap3xxx_sham_class,
2628 };
2629
2630
2631 static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
2632         .master         = &omap3xxx_l4_core_hwmod,
2633         .slave          = &omap3xxx_sham_hwmod,
2634         .clk            = "sha12_ick",
2635         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2636 };
2637
2638 /* l4_core -> AES */
2639 static struct omap_hwmod_class_sysconfig omap3_aes_sysc = {
2640         .rev_offs       = 0x44,
2641         .sysc_offs      = 0x48,
2642         .syss_offs      = 0x4c,
2643         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2644                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2645         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2646         .sysc_fields    = &omap3xxx_aes_sysc_fields,
2647 };
2648
2649 static struct omap_hwmod_class omap3xxx_aes_class = {
2650         .name   = "aes",
2651         .sysc   = &omap3_aes_sysc,
2652 };
2653
2654
2655 static struct omap_hwmod omap3xxx_aes_hwmod = {
2656         .name           = "aes",
2657         .main_clk       = "aes2_ick",
2658         .prcm           = {
2659                 .omap2 = {
2660                         .module_offs = CORE_MOD,
2661                         .idlest_reg_id = 1,
2662                         .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT,
2663                 },
2664         },
2665         .class          = &omap3xxx_aes_class,
2666 };
2667
2668
2669 static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
2670         .master         = &omap3xxx_l4_core_hwmod,
2671         .slave          = &omap3xxx_aes_hwmod,
2672         .clk            = "aes2_ick",
2673         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2674 };
2675
2676 /*
2677  * 'ssi' class
2678  * synchronous serial interface (multichannel and full-duplex serial if)
2679  */
2680
2681 static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = {
2682         .rev_offs       = 0x0000,
2683         .sysc_offs      = 0x0010,
2684         .syss_offs      = 0x0014,
2685         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_MIDLEMODE |
2686                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2687         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2688         .sysc_fields    = &omap_hwmod_sysc_type1,
2689 };
2690
2691 static struct omap_hwmod_class omap3xxx_ssi_hwmod_class = {
2692         .name   = "ssi",
2693         .sysc   = &omap34xx_ssi_sysc,
2694 };
2695
2696 static struct omap_hwmod omap3xxx_ssi_hwmod = {
2697         .name           = "ssi",
2698         .class          = &omap3xxx_ssi_hwmod_class,
2699         .clkdm_name     = "core_l4_clkdm",
2700         .main_clk       = "ssi_ssr_fck",
2701         .prcm           = {
2702                 .omap2 = {
2703                         .module_offs            = CORE_MOD,
2704                         .idlest_reg_id          = 1,
2705                         .idlest_idle_bit        = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
2706                 },
2707         },
2708 };
2709
2710 /* L4 CORE -> SSI */
2711 static struct omap_hwmod_ocp_if omap3xxx_l4_core__ssi = {
2712         .master         = &omap3xxx_l4_core_hwmod,
2713         .slave          = &omap3xxx_ssi_hwmod,
2714         .clk            = "ssi_ick",
2715         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2716 };
2717
2718 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
2719         &omap3xxx_l3_main__l4_core,
2720         &omap3xxx_l3_main__l4_per,
2721         &omap3xxx_mpu__l3_main,
2722         &omap3xxx_l3_main__l4_debugss,
2723         &omap3xxx_l4_core__l4_wkup,
2724         &omap3xxx_l4_core__mmc3,
2725         &omap3_l4_core__uart1,
2726         &omap3_l4_core__uart2,
2727         &omap3_l4_per__uart3,
2728         &omap3_l4_core__i2c1,
2729         &omap3_l4_core__i2c2,
2730         &omap3_l4_core__i2c3,
2731         &omap3xxx_l4_wkup__l4_sec,
2732         &omap3xxx_l4_wkup__timer1,
2733         &omap3xxx_l4_per__timer2,
2734         &omap3xxx_l4_per__timer3,
2735         &omap3xxx_l4_per__timer4,
2736         &omap3xxx_l4_per__timer5,
2737         &omap3xxx_l4_per__timer6,
2738         &omap3xxx_l4_per__timer7,
2739         &omap3xxx_l4_per__timer8,
2740         &omap3xxx_l4_per__timer9,
2741         &omap3xxx_l4_core__timer10,
2742         &omap3xxx_l4_core__timer11,
2743         &omap3xxx_l4_wkup__wd_timer2,
2744         &omap3xxx_l4_wkup__gpio1,
2745         &omap3xxx_l4_per__gpio2,
2746         &omap3xxx_l4_per__gpio3,
2747         &omap3xxx_l4_per__gpio4,
2748         &omap3xxx_l4_per__gpio5,
2749         &omap3xxx_l4_per__gpio6,
2750         &omap3xxx_dma_system__l3,
2751         &omap3xxx_l4_core__dma_system,
2752         &omap3xxx_l4_core__mcbsp1,
2753         &omap3xxx_l4_per__mcbsp2,
2754         &omap3xxx_l4_per__mcbsp3,
2755         &omap3xxx_l4_per__mcbsp4,
2756         &omap3xxx_l4_core__mcbsp5,
2757         &omap3xxx_l4_per__mcbsp2_sidetone,
2758         &omap3xxx_l4_per__mcbsp3_sidetone,
2759         &omap34xx_l4_core__mcspi1,
2760         &omap34xx_l4_core__mcspi2,
2761         &omap34xx_l4_core__mcspi3,
2762         &omap34xx_l4_core__mcspi4,
2763         &omap3xxx_l4_wkup__counter_32k,
2764         &omap3xxx_l3_main__gpmc,
2765         NULL,
2766 };
2767
2768 /* GP-only hwmod links */
2769 static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
2770         &omap3xxx_l4_sec__timer12,
2771         NULL,
2772 };
2773
2774 static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
2775         &omap3xxx_l4_sec__timer12,
2776         NULL,
2777 };
2778
2779 static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
2780         &omap3xxx_l4_sec__timer12,
2781         NULL,
2782 };
2783
2784 /* crypto hwmod links */
2785 static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = {
2786         &omap3xxx_l4_core__sham,
2787         NULL,
2788 };
2789
2790 static struct omap_hwmod_ocp_if *omap34xx_aes_hwmod_ocp_ifs[] __initdata = {
2791         &omap3xxx_l4_core__aes,
2792         NULL,
2793 };
2794
2795 static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = {
2796         &omap3xxx_l4_core__sham,
2797         NULL
2798 };
2799
2800 static struct omap_hwmod_ocp_if *omap36xx_aes_hwmod_ocp_ifs[] __initdata = {
2801         &omap3xxx_l4_core__aes,
2802         NULL
2803 };
2804
2805 /*
2806  * Apparently the SHA/MD5 and AES accelerator IP blocks are
2807  * only present on some AM35xx chips, and no one knows which
2808  * ones.  See
2809  * http://www.spinics.net/lists/arm-kernel/msg215466.html So
2810  * if you need these IP blocks on an AM35xx, try uncommenting
2811  * the following lines.
2812  */
2813 static struct omap_hwmod_ocp_if *am35xx_sham_hwmod_ocp_ifs[] __initdata = {
2814         /* &omap3xxx_l4_core__sham, */
2815         NULL
2816 };
2817
2818 static struct omap_hwmod_ocp_if *am35xx_aes_hwmod_ocp_ifs[] __initdata = {
2819         /* &omap3xxx_l4_core__aes, */
2820         NULL,
2821 };
2822
2823 /* 3430ES1-only hwmod links */
2824 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
2825         &omap3430es1_dss__l3,
2826         &omap3430es1_l4_core__dss,
2827         NULL,
2828 };
2829
2830 /* 3430ES2+-only hwmod links */
2831 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
2832         &omap3xxx_dss__l3,
2833         &omap3xxx_l4_core__dss,
2834         &omap3xxx_usbhsotg__l3,
2835         &omap3xxx_l4_core__usbhsotg,
2836         &omap3xxx_usb_host_hs__l3_main_2,
2837         &omap3xxx_l4_core__usb_host_hs,
2838         &omap3xxx_l4_core__usb_tll_hs,
2839         NULL,
2840 };
2841
2842 /* <= 3430ES3-only hwmod links */
2843 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
2844         &omap3xxx_l4_core__pre_es3_mmc1,
2845         &omap3xxx_l4_core__pre_es3_mmc2,
2846         NULL,
2847 };
2848
2849 /* 3430ES3+-only hwmod links */
2850 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
2851         &omap3xxx_l4_core__es3plus_mmc1,
2852         &omap3xxx_l4_core__es3plus_mmc2,
2853         NULL,
2854 };
2855
2856 /* 34xx-only hwmod links (all ES revisions) */
2857 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
2858         &omap3xxx_l3__iva,
2859         &omap34xx_l4_core__sr1,
2860         &omap34xx_l4_core__sr2,
2861         &omap3xxx_l4_core__mailbox,
2862         &omap3xxx_l4_core__hdq1w,
2863         &omap3xxx_sad2d__l3,
2864         &omap3xxx_l4_core__mmu_isp,
2865         &omap3xxx_l3_main__mmu_iva,
2866         &omap3xxx_l4_core__ssi,
2867         NULL,
2868 };
2869
2870 /* 36xx-only hwmod links (all ES revisions) */
2871 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
2872         &omap3xxx_l3__iva,
2873         &omap36xx_l4_per__uart4,
2874         &omap3xxx_dss__l3,
2875         &omap3xxx_l4_core__dss,
2876         &omap36xx_l4_core__sr1,
2877         &omap36xx_l4_core__sr2,
2878         &omap3xxx_usbhsotg__l3,
2879         &omap3xxx_l4_core__usbhsotg,
2880         &omap3xxx_l4_core__mailbox,
2881         &omap3xxx_usb_host_hs__l3_main_2,
2882         &omap3xxx_l4_core__usb_host_hs,
2883         &omap3xxx_l4_core__usb_tll_hs,
2884         &omap3xxx_l4_core__es3plus_mmc1,
2885         &omap3xxx_l4_core__es3plus_mmc2,
2886         &omap3xxx_l4_core__hdq1w,
2887         &omap3xxx_sad2d__l3,
2888         &omap3xxx_l4_core__mmu_isp,
2889         &omap3xxx_l3_main__mmu_iva,
2890         &omap3xxx_l4_core__ssi,
2891         NULL,
2892 };
2893
2894 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
2895         &omap3xxx_dss__l3,
2896         &omap3xxx_l4_core__dss,
2897         &am35xx_usbhsotg__l3,
2898         &am35xx_l4_core__usbhsotg,
2899         &am35xx_l4_core__uart4,
2900         &omap3xxx_usb_host_hs__l3_main_2,
2901         &omap3xxx_l4_core__usb_host_hs,
2902         &omap3xxx_l4_core__usb_tll_hs,
2903         &omap3xxx_l4_core__es3plus_mmc1,
2904         &omap3xxx_l4_core__es3plus_mmc2,
2905         &omap3xxx_l4_core__hdq1w,
2906         &am35xx_mdio__l3,
2907         &am35xx_l4_core__mdio,
2908         &am35xx_emac__l3,
2909         &am35xx_l4_core__emac,
2910         NULL,
2911 };
2912
2913 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
2914         &omap3xxx_l4_core__dss_dispc,
2915         &omap3xxx_l4_core__dss_dsi1,
2916         &omap3xxx_l4_core__dss_rfbi,
2917         &omap3xxx_l4_core__dss_venc,
2918         NULL,
2919 };
2920
2921 /**
2922  * omap3xxx_hwmod_is_hs_ip_block_usable - is a security IP block accessible?
2923  * @bus: struct device_node * for the top-level OMAP DT data
2924  * @dev_name: device name used in the DT file
2925  *
2926  * Determine whether a "secure" IP block @dev_name is usable by Linux.
2927  * There doesn't appear to be a 100% reliable way to determine this,
2928  * so we rely on heuristics.  If @bus is null, meaning there's no DT
2929  * data, then we only assume the IP block is accessible if the OMAP is
2930  * fused as a 'general-purpose' SoC.  If however DT data is present,
2931  * test to see if the IP block is described in the DT data and set to
2932  * 'status = "okay"'.  If so then we assume the ODM has configured the
2933  * OMAP firewalls to allow access to the IP block.
2934  *
2935  * Return: 0 if device named @dev_name is not likely to be accessible,
2936  * or 1 if it is likely to be accessible.
2937  */
2938 static bool __init omap3xxx_hwmod_is_hs_ip_block_usable(struct device_node *bus,
2939                                                         const char *dev_name)
2940 {
2941         struct device_node *node;
2942         bool available;
2943
2944         if (!bus)
2945                 return omap_type() == OMAP2_DEVICE_TYPE_GP;
2946
2947         node = of_get_child_by_name(bus, dev_name);
2948         available = of_device_is_available(node);
2949         of_node_put(node);
2950
2951         return available;
2952 }
2953
2954 int __init omap3xxx_hwmod_init(void)
2955 {
2956         int r;
2957         struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL, **h_sham = NULL;
2958         struct omap_hwmod_ocp_if **h_aes = NULL;
2959         struct device_node *bus;
2960         unsigned int rev;
2961
2962         omap_hwmod_init();
2963
2964         /* Register hwmod links common to all OMAP3 */
2965         r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
2966         if (r < 0)
2967                 return r;
2968
2969         rev = omap_rev();
2970
2971         /*
2972          * Register hwmod links common to individual OMAP3 families, all
2973          * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
2974          * All possible revisions should be included in this conditional.
2975          */
2976         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
2977             rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
2978             rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
2979                 h = omap34xx_hwmod_ocp_ifs;
2980                 h_gp = omap34xx_gp_hwmod_ocp_ifs;
2981                 h_sham = omap34xx_sham_hwmod_ocp_ifs;
2982                 h_aes = omap34xx_aes_hwmod_ocp_ifs;
2983         } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
2984                 h = am35xx_hwmod_ocp_ifs;
2985                 h_gp = am35xx_gp_hwmod_ocp_ifs;
2986                 h_sham = am35xx_sham_hwmod_ocp_ifs;
2987                 h_aes = am35xx_aes_hwmod_ocp_ifs;
2988         } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
2989                    rev == OMAP3630_REV_ES1_2) {
2990                 h = omap36xx_hwmod_ocp_ifs;
2991                 h_gp = omap36xx_gp_hwmod_ocp_ifs;
2992                 h_sham = omap36xx_sham_hwmod_ocp_ifs;
2993                 h_aes = omap36xx_aes_hwmod_ocp_ifs;
2994         } else {
2995                 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
2996                 return -EINVAL;
2997         }
2998
2999         r = omap_hwmod_register_links(h);
3000         if (r < 0)
3001                 return r;
3002
3003         /* Register GP-only hwmod links. */
3004         if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) {
3005                 r = omap_hwmod_register_links(h_gp);
3006                 if (r < 0)
3007                         return r;
3008         }
3009
3010         /*
3011          * Register crypto hwmod links only if they are not disabled in DT.
3012          * If DT information is missing, enable them only for GP devices.
3013          */
3014
3015         bus = of_find_node_by_name(NULL, "ocp");
3016
3017         if (h_sham && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "sham")) {
3018                 r = omap_hwmod_register_links(h_sham);
3019                 if (r < 0)
3020                         goto put_node;
3021         }
3022
3023         if (h_aes && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "aes")) {
3024                 r = omap_hwmod_register_links(h_aes);
3025                 if (r < 0)
3026                         goto put_node;
3027         }
3028         of_node_put(bus);
3029
3030         /*
3031          * Register hwmod links specific to certain ES levels of a
3032          * particular family of silicon (e.g., 34xx ES1.0)
3033          */
3034         h = NULL;
3035         if (rev == OMAP3430_REV_ES1_0) {
3036                 h = omap3430es1_hwmod_ocp_ifs;
3037         } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3038                    rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3039                    rev == OMAP3430_REV_ES3_1_2) {
3040                 h = omap3430es2plus_hwmod_ocp_ifs;
3041         }
3042
3043         if (h) {
3044                 r = omap_hwmod_register_links(h);
3045                 if (r < 0)
3046                         return r;
3047         }
3048
3049         h = NULL;
3050         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3051             rev == OMAP3430_REV_ES2_1) {
3052                 h = omap3430_pre_es3_hwmod_ocp_ifs;
3053         } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3054                    rev == OMAP3430_REV_ES3_1_2) {
3055                 h = omap3430_es3plus_hwmod_ocp_ifs;
3056         }
3057
3058         if (h)
3059                 r = omap_hwmod_register_links(h);
3060         if (r < 0)
3061                 return r;
3062
3063         /*
3064          * DSS code presumes that dss_core hwmod is handled first,
3065          * _before_ any other DSS related hwmods so register common
3066          * DSS hwmod links last to ensure that dss_core is already
3067          * registered.  Otherwise some change things may happen, for
3068          * ex. if dispc is handled before dss_core and DSS is enabled
3069          * in bootloader DISPC will be reset with outputs enabled
3070          * which sometimes leads to unrecoverable L3 error.  XXX The
3071          * long-term fix to this is to ensure hwmods are set up in
3072          * dependency order in the hwmod core code.
3073          */
3074         r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
3075
3076         return r;
3077
3078 put_node:
3079         of_node_put(bus);
3080         return r;
3081 }