arch/arm/mach-omap2/omap_hwmod_33xx_data.c

   1 /*
   2  * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
   3  *
   4  * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This file is automatically generated from the AM33XX hardware databases.
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include "omap_hwmod.h"
  18 #include "omap_hwmod_common_data.h"
  19
  20 #include "control.h"
  21 #include "cm33xx.h"
  22 #include "prm33xx.h"
  23 #include "prm-regbits-33xx.h"
  24 #include "wd_timer.h"
  25 #include "omap_hwmod_33xx_43xx_common_data.h"
  26
  27 /*
  28  * IP blocks
  29  */
  30
  31 /* emif */
  32 static struct omap_hwmod am33xx_emif_hwmod = {
  33         .name           = "emif",
  34         .class          = &am33xx_emif_hwmod_class,
  35         .clkdm_name     = "l3_clkdm",
  36         .flags          = HWMOD_INIT_NO_IDLE,
  37         .main_clk       = "dpll_ddr_m2_div2_ck",
  38         .prcm           = {
  39                 .omap4  = {
  40                         .clkctrl_offs   = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
  41                         .modulemode     = MODULEMODE_SWCTRL,
  42                 },
  43         },
  44 };
  45
  46 /* l4_hs */
  47 static struct omap_hwmod am33xx_l4_hs_hwmod = {
  48         .name           = "l4_hs",
  49         .class          = &am33xx_l4_hwmod_class,
  50         .clkdm_name     = "l4hs_clkdm",
  51         .flags          = HWMOD_INIT_NO_IDLE,
  52         .main_clk       = "l4hs_gclk",
  53         .prcm           = {
  54                 .omap4  = {
  55                         .clkctrl_offs   = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
  56                         .modulemode     = MODULEMODE_SWCTRL,
  57                 },
  58         },
  59 };
  60
  61 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
  62         { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
  63 };
  64
  65 /* wkup_m3  */
  66 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
  67         .name           = "wkup_m3",
  68         .class          = &am33xx_wkup_m3_hwmod_class,
  69         .clkdm_name     = "l4_wkup_aon_clkdm",
  70         /* Keep hardreset asserted */
  71         .flags          = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
  72         .main_clk       = "dpll_core_m4_div2_ck",
  73         .prcm           = {
  74                 .omap4  = {
  75                         .clkctrl_offs   = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
  76                         .rstctrl_offs   = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
  77                         .rstst_offs     = AM33XX_RM_WKUP_RSTST_OFFSET,
  78                         .modulemode     = MODULEMODE_SWCTRL,
  79                 },
  80         },
  81         .rst_lines      = am33xx_wkup_m3_resets,
  82         .rst_lines_cnt  = ARRAY_SIZE(am33xx_wkup_m3_resets),
  83 };
  84
  85 /*
  86  * 'adc/tsc' class
  87  * TouchScreen Controller (Anolog-To-Digital Converter)
  88  */
  89 static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
  90         .rev_offs       = 0x00,
  91         .sysc_offs      = 0x10,
  92         .sysc_flags     = SYSC_HAS_SIDLEMODE,
  93         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  94                         SIDLE_SMART_WKUP),
  95         .sysc_fields    = &omap_hwmod_sysc_type2,
  96 };
  97
  98 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
  99         .name           = "adc_tsc",
 100         .sysc           = &am33xx_adc_tsc_sysc,
 101 };
 102
 103 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
 104         .name           = "adc_tsc",
 105         .class          = &am33xx_adc_tsc_hwmod_class,
 106         .clkdm_name     = "l4_wkup_clkdm",
 107         .main_clk       = "adc_tsc_fck",
 108         .prcm           = {
 109                 .omap4  = {
 110                         .clkctrl_offs   = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
 111                         .modulemode     = MODULEMODE_SWCTRL,
 112                 },
 113         },
 114 };
 115
 116 /*
 117  * Modules omap_hwmod structures
 118  *
 119  * The following IPs are excluded for the moment because:
 120  * - They do not need an explicit SW control using omap_hwmod API.
 121  * - They still need to be validated with the driver
 122  *   properly adapted to omap_hwmod / omap_device
 123  *
 124  *    - cEFUSE (doesn't fall under any ocp_if)
 125  *    - clkdiv32k
 126  *    - ocp watch point
 127  */
 128 #if 0
 129 /*
 130  * 'cefuse' class
 131  */
 132 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
 133         .name           = "cefuse",
 134 };
 135
 136 static struct omap_hwmod am33xx_cefuse_hwmod = {
 137         .name           = "cefuse",
 138         .class          = &am33xx_cefuse_hwmod_class,
 139         .clkdm_name     = "l4_cefuse_clkdm",
 140         .main_clk       = "cefuse_fck",
 141         .prcm           = {
 142                 .omap4  = {
 143                         .clkctrl_offs   = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
 144                         .modulemode     = MODULEMODE_SWCTRL,
 145                 },
 146         },
 147 };
 148
 149 /*
 150  * 'clkdiv32k' class
 151  */
 152 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
 153         .name           = "clkdiv32k",
 154 };
 155
 156 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
 157         .name           = "clkdiv32k",
 158         .class          = &am33xx_clkdiv32k_hwmod_class,
 159         .clkdm_name     = "clk_24mhz_clkdm",
 160         .main_clk       = "clkdiv32k_ick",
 161         .prcm           = {
 162                 .omap4  = {
 163                         .clkctrl_offs   = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
 164                         .modulemode     = MODULEMODE_SWCTRL,
 165                 },
 166         },
 167 };
 168
 169 /* ocpwp */
 170 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
 171         .name           = "ocpwp",
 172 };
 173
 174 static struct omap_hwmod am33xx_ocpwp_hwmod = {
 175         .name           = "ocpwp",
 176         .class          = &am33xx_ocpwp_hwmod_class,
 177         .clkdm_name     = "l4ls_clkdm",
 178         .main_clk       = "l4ls_gclk",
 179         .prcm           = {
 180                 .omap4  = {
 181                         .clkctrl_offs   = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
 182                         .modulemode     = MODULEMODE_SWCTRL,
 183                 },
 184         },
 185 };
 186 #endif
 187
 188 /*
 189  * 'debugss' class
 190  * debug sub system
 191  */
 192 static struct omap_hwmod_opt_clk debugss_opt_clks[] = {
 193         { .role = "dbg_sysclk", .clk = "dbg_sysclk_ck" },
 194         { .role = "dbg_clka", .clk = "dbg_clka_ck" },
 195 };
 196
 197 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
 198         .name           = "debugss",
 199 };
 200
 201 static struct omap_hwmod am33xx_debugss_hwmod = {
 202         .name           = "debugss",
 203         .class          = &am33xx_debugss_hwmod_class,
 204         .clkdm_name     = "l3_aon_clkdm",
 205         .main_clk       = "trace_clk_div_ck",
 206         .prcm           = {
 207                 .omap4  = {
 208                         .clkctrl_offs   = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
 209                         .modulemode     = MODULEMODE_SWCTRL,
 210                 },
 211         },
 212         .opt_clks       = debugss_opt_clks,
 213         .opt_clks_cnt   = ARRAY_SIZE(debugss_opt_clks),
 214 };
 215
 216 static struct omap_hwmod am33xx_control_hwmod = {
 217         .name           = "control",
 218         .class          = &am33xx_control_hwmod_class,
 219         .clkdm_name     = "l4_wkup_clkdm",
 220         .flags          = HWMOD_INIT_NO_IDLE,
 221         .main_clk       = "dpll_core_m4_div2_ck",
 222         .prcm           = {
 223                 .omap4  = {
 224                         .clkctrl_offs   = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
 225                         .modulemode     = MODULEMODE_SWCTRL,
 226                 },
 227         },
 228 };
 229
 230 /* lcdc */
 231 static struct omap_hwmod_class_sysconfig lcdc_sysc = {
 232         .rev_offs       = 0x0,
 233         .sysc_offs      = 0x54,
 234         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
 235         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 236         .sysc_fields    = &omap_hwmod_sysc_type2,
 237 };
 238
 239 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
 240         .name           = "lcdc",
 241         .sysc           = &lcdc_sysc,
 242 };
 243
 244 static struct omap_hwmod am33xx_lcdc_hwmod = {
 245         .name           = "lcdc",
 246         .class          = &am33xx_lcdc_hwmod_class,
 247         .clkdm_name     = "lcdc_clkdm",
 248         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 249         .main_clk       = "lcd_gclk",
 250         .prcm           = {
 251                 .omap4  = {
 252                         .clkctrl_offs   = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
 253                         .modulemode     = MODULEMODE_SWCTRL,
 254                 },
 255         },
 256 };
 257
 258 /*
 259  * 'usb_otg' class
 260  * high-speed on-the-go universal serial bus (usb_otg) controller
 261  */
 262 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
 263         .rev_offs       = 0x0,
 264         .sysc_offs      = 0x10,
 265         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
 266         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 267                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 268         .sysc_fields    = &omap_hwmod_sysc_type2,
 269 };
 270
 271 static struct omap_hwmod_class am33xx_usbotg_class = {
 272         .name           = "usbotg",
 273         .sysc           = &am33xx_usbhsotg_sysc,
 274 };
 275
 276 static struct omap_hwmod am33xx_usbss_hwmod = {
 277         .name           = "usb_otg_hs",
 278         .class          = &am33xx_usbotg_class,
 279         .clkdm_name     = "l3s_clkdm",
 280         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 281         .main_clk       = "usbotg_fck",
 282         .prcm           = {
 283                 .omap4  = {
 284                         .clkctrl_offs   = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
 285                         .modulemode     = MODULEMODE_SWCTRL,
 286                 },
 287         },
 288 };
 289
 290
 291 /*
 292  * Interfaces
 293  */
 294
 295 /* l3 main -> emif */
 296 static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
 297         .master         = &am33xx_l3_main_hwmod,
 298         .slave          = &am33xx_emif_hwmod,
 299         .clk            = "dpll_core_m4_ck",
 300         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 301 };
 302
 303 /* l3 main -> l4 hs */
 304 static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
 305         .master         = &am33xx_l3_main_hwmod,
 306         .slave          = &am33xx_l4_hs_hwmod,
 307         .clk            = "l3s_gclk",
 308         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 309 };
 310
 311 /* wkup m3 -> l4 wkup */
 312 static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
 313         .master         = &am33xx_wkup_m3_hwmod,
 314         .slave          = &am33xx_l4_wkup_hwmod,
 315         .clk            = "dpll_core_m4_div2_ck",
 316         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 317 };
 318
 319 /* l4 wkup -> wkup m3 */
 320 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
 321         .master         = &am33xx_l4_wkup_hwmod,
 322         .slave          = &am33xx_wkup_m3_hwmod,
 323         .clk            = "dpll_core_m4_div2_ck",
 324         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 325 };
 326
 327 /* l4 hs -> pru-icss */
 328 static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
 329         .master         = &am33xx_l4_hs_hwmod,
 330         .slave          = &am33xx_pruss_hwmod,
 331         .clk            = "dpll_core_m4_ck",
 332         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 333 };
 334
 335 /* l3_main -> debugss */
 336 static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = {
 337         .master         = &am33xx_l3_main_hwmod,
 338         .slave          = &am33xx_debugss_hwmod,
 339         .clk            = "dpll_core_m4_ck",
 340         .user           = OCP_USER_MPU,
 341 };
 342
 343 /* l4 wkup -> smartreflex0 */
 344 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
 345         .master         = &am33xx_l4_wkup_hwmod,
 346         .slave          = &am33xx_smartreflex0_hwmod,
 347         .clk            = "dpll_core_m4_div2_ck",
 348         .user           = OCP_USER_MPU,
 349 };
 350
 351 /* l4 wkup -> smartreflex1 */
 352 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
 353         .master         = &am33xx_l4_wkup_hwmod,
 354         .slave          = &am33xx_smartreflex1_hwmod,
 355         .clk            = "dpll_core_m4_div2_ck",
 356         .user           = OCP_USER_MPU,
 357 };
 358
 359 /* l4 wkup -> control */
 360 static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
 361         .master         = &am33xx_l4_wkup_hwmod,
 362         .slave          = &am33xx_control_hwmod,
 363         .clk            = "dpll_core_m4_div2_ck",
 364         .user           = OCP_USER_MPU,
 365 };
 366
 367 /* L4 WKUP -> ADC_TSC */
 368 static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
 369         .master         = &am33xx_l4_wkup_hwmod,
 370         .slave          = &am33xx_adc_tsc_hwmod,
 371         .clk            = "dpll_core_m4_div2_ck",
 372         .user           = OCP_USER_MPU,
 373 };
 374
 375 static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
 376         .master         = &am33xx_l3_main_hwmod,
 377         .slave          = &am33xx_lcdc_hwmod,
 378         .clk            = "dpll_core_m4_ck",
 379         .user           = OCP_USER_MPU,
 380 };
 381
 382 /* l4 wkup -> timer1 */
 383 static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
 384         .master         = &am33xx_l4_wkup_hwmod,
 385         .slave          = &am33xx_timer1_hwmod,
 386         .clk            = "dpll_core_m4_div2_ck",
 387         .user           = OCP_USER_MPU,
 388 };
 389
 390 /* l4 wkup -> wd_timer1 */
 391 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
 392         .master         = &am33xx_l4_wkup_hwmod,
 393         .slave          = &am33xx_wd_timer1_hwmod,
 394         .clk            = "dpll_core_m4_div2_ck",
 395         .user           = OCP_USER_MPU,
 396 };
 397
 398 /* usbss */
 399 /* l3 s -> USBSS interface */
 400 static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
 401         .master         = &am33xx_l3_s_hwmod,
 402         .slave          = &am33xx_usbss_hwmod,
 403         .clk            = "l3s_gclk",
 404         .user           = OCP_USER_MPU,
 405         .flags          = OCPIF_SWSUP_IDLE,
 406 };
 407
 408 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
 409         &am33xx_l3_main__emif,
 410         &am33xx_mpu__l3_main,
 411         &am33xx_mpu__prcm,
 412         &am33xx_l3_s__l4_ls,
 413         &am33xx_l3_s__l4_wkup,
 414         &am33xx_l3_main__l4_hs,
 415         &am33xx_l3_main__l3_s,
 416         &am33xx_l3_main__l3_instr,
 417         &am33xx_l3_main__gfx,
 418         &am33xx_l3_s__l3_main,
 419         &am33xx_pruss__l3_main,
 420         &am33xx_wkup_m3__l4_wkup,
 421         &am33xx_gfx__l3_main,
 422         &am33xx_l3_main__debugss,
 423         &am33xx_l4_wkup__wkup_m3,
 424         &am33xx_l4_wkup__control,
 425         &am33xx_l4_wkup__smartreflex0,
 426         &am33xx_l4_wkup__smartreflex1,
 427         &am33xx_l4_wkup__timer1,
 428         &am33xx_l4_wkup__rtc,
 429         &am33xx_l4_wkup__adc_tsc,
 430         &am33xx_l4_wkup__wd_timer1,
 431         &am33xx_l4_hs__pruss,
 432         &am33xx_l4_per__dcan0,
 433         &am33xx_l4_per__dcan1,
 434         &am33xx_l4_per__mailbox,
 435         &am33xx_l4_ls__mcasp0,
 436         &am33xx_l4_ls__mcasp1,
 437         &am33xx_l4_ls__timer2,
 438         &am33xx_l4_ls__timer3,
 439         &am33xx_l4_ls__timer4,
 440         &am33xx_l4_ls__timer5,
 441         &am33xx_l4_ls__timer6,
 442         &am33xx_l4_ls__timer7,
 443         &am33xx_l3_main__tpcc,
 444         &am33xx_l4_ls__spinlock,
 445         &am33xx_l4_ls__elm,
 446         &am33xx_l4_ls__epwmss0,
 447         &am33xx_l4_ls__epwmss1,
 448         &am33xx_l4_ls__epwmss2,
 449         &am33xx_l3_s__gpmc,
 450         &am33xx_l3_main__lcdc,
 451         &am33xx_l4_ls__mcspi0,
 452         &am33xx_l4_ls__mcspi1,
 453         &am33xx_l3_main__tptc0,
 454         &am33xx_l3_main__tptc1,
 455         &am33xx_l3_main__tptc2,
 456         &am33xx_l3_main__ocmc,
 457         &am33xx_l3_s__usbss,
 458         &am33xx_l3_main__sha0,
 459         &am33xx_l3_main__aes0,
 460         &am33xx_l4_per__rng,
 461         NULL,
 462 };
 463
 464 int __init am33xx_hwmod_init(void)
 465 {
 466         omap_hwmod_am33xx_reg();
 467         omap_hwmod_init();
 468         return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
 469 }