arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c

   1 /*
   2  *
   3  * Copyright (C) 2013 Texas Instruments Incorporated
   4  *
   5  * Hwmod common for AM335x and AM43x
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/types.h>
  18
  19 #include "omap_hwmod.h"
  20 #include "wd_timer.h"
  21 #include "cm33xx.h"
  22 #include "prm33xx.h"
  23 #include "omap_hwmod_33xx_43xx_common_data.h"
  24 #include "prcm43xx.h"
  25 #include "common.h"
  26
  27 #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
  28 #define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
  29 #define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
  30 #define PRCM_FLAGS(oh, flag) ((oh).prcm.omap4.flags = (flag))
  31
  32 /*
  33  * 'l3' class
  34  * instance(s): l3_main, l3_s, l3_instr
  35  */
  36 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
  37         .name           = "l3",
  38 };
  39
  40 struct omap_hwmod am33xx_l3_main_hwmod = {
  41         .name           = "l3_main",
  42         .class          = &am33xx_l3_hwmod_class,
  43         .clkdm_name     = "l3_clkdm",
  44         .flags          = HWMOD_INIT_NO_IDLE,
  45         .main_clk       = "l3_gclk",
  46         .prcm           = {
  47                 .omap4  = {
  48                         .modulemode     = MODULEMODE_SWCTRL,
  49                 },
  50         },
  51 };
  52
  53 /* l3_s */
  54 struct omap_hwmod am33xx_l3_s_hwmod = {
  55         .name           = "l3_s",
  56         .class          = &am33xx_l3_hwmod_class,
  57         .clkdm_name     = "l3s_clkdm",
  58 };
  59
  60 /* l3_instr */
  61 struct omap_hwmod am33xx_l3_instr_hwmod = {
  62         .name           = "l3_instr",
  63         .class          = &am33xx_l3_hwmod_class,
  64         .clkdm_name     = "l3_clkdm",
  65         .flags          = HWMOD_INIT_NO_IDLE,
  66         .main_clk       = "l3_gclk",
  67         .prcm           = {
  68                 .omap4  = {
  69                         .modulemode     = MODULEMODE_SWCTRL,
  70                 },
  71         },
  72 };
  73
  74 /*
  75  * 'l4' class
  76  * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
  77  */
  78 struct omap_hwmod_class am33xx_l4_hwmod_class = {
  79         .name           = "l4",
  80 };
  81
  82 /* l4_ls */
  83 struct omap_hwmod am33xx_l4_ls_hwmod = {
  84         .name           = "l4_ls",
  85         .class          = &am33xx_l4_hwmod_class,
  86         .clkdm_name     = "l4ls_clkdm",
  87         .flags          = HWMOD_INIT_NO_IDLE,
  88         .main_clk       = "l4ls_gclk",
  89         .prcm           = {
  90                 .omap4  = {
  91                         .modulemode     = MODULEMODE_SWCTRL,
  92                 },
  93         },
  94 };
  95
  96 /* l4_wkup */
  97 struct omap_hwmod am33xx_l4_wkup_hwmod = {
  98         .name           = "l4_wkup",
  99         .class          = &am33xx_l4_hwmod_class,
 100         .clkdm_name     = "l4_wkup_clkdm",
 101         .flags          = HWMOD_INIT_NO_IDLE,
 102         .prcm           = {
 103                 .omap4  = {
 104                         .modulemode     = MODULEMODE_SWCTRL,
 105                 },
 106         },
 107 };
 108
 109 /*
 110  * 'mpu' class
 111  */
 112 static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
 113         .name   = "mpu",
 114 };
 115
 116 struct omap_hwmod am33xx_mpu_hwmod = {
 117         .name           = "mpu",
 118         .class          = &am33xx_mpu_hwmod_class,
 119         .clkdm_name     = "mpu_clkdm",
 120         .flags          = HWMOD_INIT_NO_IDLE,
 121         .main_clk       = "dpll_mpu_m2_ck",
 122         .prcm           = {
 123                 .omap4  = {
 124                         .modulemode     = MODULEMODE_SWCTRL,
 125                 },
 126         },
 127 };
 128
 129 /*
 130  * 'wakeup m3' class
 131  * Wakeup controller sub-system under wakeup domain
 132  */
 133 struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
 134         .name           = "wkup_m3",
 135 };
 136
 137 /*
 138  * 'pru-icss' class
 139  * Programmable Real-Time Unit and Industrial Communication Subsystem
 140  */
 141 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
 142         .name   = "pruss",
 143 };
 144
 145 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
 146         { .name = "pruss", .rst_shift = 1 },
 147 };
 148
 149 /* pru-icss */
 150 /* Pseudo hwmod for reset control purpose only */
 151 struct omap_hwmod am33xx_pruss_hwmod = {
 152         .name           = "pruss",
 153         .class          = &am33xx_pruss_hwmod_class,
 154         .clkdm_name     = "pruss_ocp_clkdm",
 155         .main_clk       = "pruss_ocp_gclk",
 156         .prcm           = {
 157                 .omap4  = {
 158                         .modulemode     = MODULEMODE_SWCTRL,
 159                 },
 160         },
 161         .rst_lines      = am33xx_pruss_resets,
 162         .rst_lines_cnt  = ARRAY_SIZE(am33xx_pruss_resets),
 163 };
 164
 165 /* gfx */
 166 /* Pseudo hwmod for reset control purpose only */
 167 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
 168         .name   = "gfx",
 169 };
 170
 171 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
 172         { .name = "gfx", .rst_shift = 0, .st_shift = 0},
 173 };
 174
 175 struct omap_hwmod am33xx_gfx_hwmod = {
 176         .name           = "gfx",
 177         .class          = &am33xx_gfx_hwmod_class,
 178         .clkdm_name     = "gfx_l3_clkdm",
 179         .main_clk       = "gfx_fck_div_ck",
 180         .prcm           = {
 181                 .omap4  = {
 182                         .modulemode     = MODULEMODE_SWCTRL,
 183                 },
 184         },
 185         .rst_lines      = am33xx_gfx_resets,
 186         .rst_lines_cnt  = ARRAY_SIZE(am33xx_gfx_resets),
 187 };
 188
 189 /*
 190  * 'prcm' class
 191  * power and reset manager (whole prcm infrastructure)
 192  */
 193 static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
 194         .name   = "prcm",
 195 };
 196
 197 /* prcm */
 198 struct omap_hwmod am33xx_prcm_hwmod = {
 199         .name           = "prcm",
 200         .class          = &am33xx_prcm_hwmod_class,
 201         .clkdm_name     = "l4_wkup_clkdm",
 202 };
 203
 204 /*
 205  * 'emif' class
 206  * instance(s): emif
 207  */
 208 static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
 209         .rev_offs       = 0x0000,
 210 };
 211
 212 struct omap_hwmod_class am33xx_emif_hwmod_class = {
 213         .name           = "emif",
 214         .sysc           = &am33xx_emif_sysc,
 215 };
 216
 217 /*
 218  * 'aes0' class
 219  */
 220 static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
 221         .rev_offs       = 0x80,
 222         .sysc_offs      = 0x84,
 223         .syss_offs      = 0x88,
 224         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 225 };
 226
 227 static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
 228         .name           = "aes0",
 229         .sysc           = &am33xx_aes0_sysc,
 230 };
 231
 232 struct omap_hwmod am33xx_aes0_hwmod = {
 233         .name           = "aes",
 234         .class          = &am33xx_aes0_hwmod_class,
 235         .clkdm_name     = "l3_clkdm",
 236         .main_clk       = "aes0_fck",
 237         .prcm           = {
 238                 .omap4  = {
 239                         .modulemode     = MODULEMODE_SWCTRL,
 240                 },
 241         },
 242 };
 243
 244 /* sha0 HIB2 (the 'P' (public) device) */
 245 static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
 246         .rev_offs       = 0x100,
 247         .sysc_offs      = 0x110,
 248         .syss_offs      = 0x114,
 249         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 250 };
 251
 252 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
 253         .name           = "sha0",
 254         .sysc           = &am33xx_sha0_sysc,
 255 };
 256
 257 struct omap_hwmod am33xx_sha0_hwmod = {
 258         .name           = "sham",
 259         .class          = &am33xx_sha0_hwmod_class,
 260         .clkdm_name     = "l3_clkdm",
 261         .main_clk       = "l3_gclk",
 262         .prcm           = {
 263                 .omap4  = {
 264                         .modulemode     = MODULEMODE_SWCTRL,
 265                 },
 266         },
 267 };
 268
 269 /* rng */
 270 static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = {
 271         .rev_offs       = 0x1fe0,
 272         .sysc_offs      = 0x1fe4,
 273         .sysc_flags     = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
 274         .idlemodes      = SIDLE_FORCE | SIDLE_NO,
 275         .sysc_fields    = &omap_hwmod_sysc_type1,
 276 };
 277
 278 static struct omap_hwmod_class am33xx_rng_hwmod_class = {
 279         .name           = "rng",
 280         .sysc           = &am33xx_rng_sysc,
 281 };
 282
 283 struct omap_hwmod am33xx_rng_hwmod = {
 284         .name           = "rng",
 285         .class          = &am33xx_rng_hwmod_class,
 286         .clkdm_name     = "l4ls_clkdm",
 287         .flags          = HWMOD_SWSUP_SIDLE,
 288         .main_clk       = "rng_fck",
 289         .prcm           = {
 290                 .omap4  = {
 291                         .modulemode     = MODULEMODE_SWCTRL,
 292                 },
 293         },
 294 };
 295
 296 /* ocmcram */
 297 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
 298         .name = "ocmcram",
 299 };
 300
 301 struct omap_hwmod am33xx_ocmcram_hwmod = {
 302         .name           = "ocmcram",
 303         .class          = &am33xx_ocmcram_hwmod_class,
 304         .clkdm_name     = "l3_clkdm",
 305         .flags          = HWMOD_INIT_NO_IDLE,
 306         .main_clk       = "l3_gclk",
 307         .prcm           = {
 308                 .omap4  = {
 309                         .modulemode     = MODULEMODE_SWCTRL,
 310                 },
 311         },
 312 };
 313
 314 /* 'smartreflex' class */
 315 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
 316         .name           = "smartreflex",
 317 };
 318
 319 /* smartreflex0 */
 320 struct omap_hwmod am33xx_smartreflex0_hwmod = {
 321         .name           = "smartreflex0",
 322         .class          = &am33xx_smartreflex_hwmod_class,
 323         .clkdm_name     = "l4_wkup_clkdm",
 324         .main_clk       = "smartreflex0_fck",
 325         .prcm           = {
 326                 .omap4  = {
 327                         .modulemode     = MODULEMODE_SWCTRL,
 328                 },
 329         },
 330 };
 331
 332 /* smartreflex1 */
 333 struct omap_hwmod am33xx_smartreflex1_hwmod = {
 334         .name           = "smartreflex1",
 335         .class          = &am33xx_smartreflex_hwmod_class,
 336         .clkdm_name     = "l4_wkup_clkdm",
 337         .main_clk       = "smartreflex1_fck",
 338         .prcm           = {
 339                 .omap4  = {
 340                         .modulemode     = MODULEMODE_SWCTRL,
 341                 },
 342         },
 343 };
 344
 345 /*
 346  * 'control' module class
 347  */
 348 struct omap_hwmod_class am33xx_control_hwmod_class = {
 349         .name           = "control",
 350 };
 351
 352 /*
 353  * 'cpgmac' class
 354  * cpsw/cpgmac sub system
 355  */
 356 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
 357         .rev_offs       = 0x0,
 358         .sysc_offs      = 0x8,
 359         .syss_offs      = 0x4,
 360         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 361                            SYSS_HAS_RESET_STATUS),
 362         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
 363                            MSTANDBY_NO),
 364         .sysc_fields    = &omap_hwmod_sysc_type3,
 365 };
 366
 367 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
 368         .name           = "cpgmac0",
 369         .sysc           = &am33xx_cpgmac_sysc,
 370 };
 371
 372 struct omap_hwmod am33xx_cpgmac0_hwmod = {
 373         .name           = "cpgmac0",
 374         .class          = &am33xx_cpgmac0_hwmod_class,
 375         .clkdm_name     = "cpsw_125mhz_clkdm",
 376         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 377         .main_clk       = "cpsw_125mhz_gclk",
 378         .mpu_rt_idx     = 1,
 379         .prcm           = {
 380                 .omap4  = {
 381                         .modulemode     = MODULEMODE_SWCTRL,
 382                 },
 383         },
 384 };
 385
 386 /*
 387  * mdio class
 388  */
 389 static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
 390         .name           = "davinci_mdio",
 391 };
 392
 393 struct omap_hwmod am33xx_mdio_hwmod = {
 394         .name           = "davinci_mdio",
 395         .class          = &am33xx_mdio_hwmod_class,
 396         .clkdm_name     = "cpsw_125mhz_clkdm",
 397         .main_clk       = "cpsw_125mhz_gclk",
 398 };
 399
 400 /*
 401  * dcan class
 402  */
 403 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
 404         .name = "d_can",
 405 };
 406
 407 /* dcan0 */
 408 struct omap_hwmod am33xx_dcan0_hwmod = {
 409         .name           = "d_can0",
 410         .class          = &am33xx_dcan_hwmod_class,
 411         .clkdm_name     = "l4ls_clkdm",
 412         .main_clk       = "dcan0_fck",
 413         .prcm           = {
 414                 .omap4  = {
 415                         .modulemode     = MODULEMODE_SWCTRL,
 416                 },
 417         },
 418 };
 419
 420 /* dcan1 */
 421 struct omap_hwmod am33xx_dcan1_hwmod = {
 422         .name           = "d_can1",
 423         .class          = &am33xx_dcan_hwmod_class,
 424         .clkdm_name     = "l4ls_clkdm",
 425         .main_clk       = "dcan1_fck",
 426         .prcm           = {
 427                 .omap4  = {
 428                         .modulemode     = MODULEMODE_SWCTRL,
 429                 },
 430         },
 431 };
 432
 433 /* elm */
 434 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
 435         .rev_offs       = 0x0000,
 436         .sysc_offs      = 0x0010,
 437         .syss_offs      = 0x0014,
 438         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 439                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 440                         SYSS_HAS_RESET_STATUS),
 441         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 442         .sysc_fields    = &omap_hwmod_sysc_type1,
 443 };
 444
 445 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
 446         .name           = "elm",
 447         .sysc           = &am33xx_elm_sysc,
 448 };
 449
 450 struct omap_hwmod am33xx_elm_hwmod = {
 451         .name           = "elm",
 452         .class          = &am33xx_elm_hwmod_class,
 453         .clkdm_name     = "l4ls_clkdm",
 454         .main_clk       = "l4ls_gclk",
 455         .prcm           = {
 456                 .omap4  = {
 457                         .modulemode     = MODULEMODE_SWCTRL,
 458                 },
 459         },
 460 };
 461
 462 /* pwmss  */
 463 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
 464         .rev_offs       = 0x0,
 465         .sysc_offs      = 0x4,
 466         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
 467         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 468                         SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 469                         MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 470         .sysc_fields    = &omap_hwmod_sysc_type2,
 471 };
 472
 473 struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
 474         .name           = "epwmss",
 475         .sysc           = &am33xx_epwmss_sysc,
 476 };
 477
 478 /* epwmss0 */
 479 struct omap_hwmod am33xx_epwmss0_hwmod = {
 480         .name           = "epwmss0",
 481         .class          = &am33xx_epwmss_hwmod_class,
 482         .clkdm_name     = "l4ls_clkdm",
 483         .main_clk       = "l4ls_gclk",
 484         .prcm           = {
 485                 .omap4  = {
 486                         .modulemode     = MODULEMODE_SWCTRL,
 487                 },
 488         },
 489 };
 490
 491 /* epwmss1 */
 492 struct omap_hwmod am33xx_epwmss1_hwmod = {
 493         .name           = "epwmss1",
 494         .class          = &am33xx_epwmss_hwmod_class,
 495         .clkdm_name     = "l4ls_clkdm",
 496         .main_clk       = "l4ls_gclk",
 497         .prcm           = {
 498                 .omap4  = {
 499                         .modulemode     = MODULEMODE_SWCTRL,
 500                 },
 501         },
 502 };
 503
 504 /* epwmss2 */
 505 struct omap_hwmod am33xx_epwmss2_hwmod = {
 506         .name           = "epwmss2",
 507         .class          = &am33xx_epwmss_hwmod_class,
 508         .clkdm_name     = "l4ls_clkdm",
 509         .main_clk       = "l4ls_gclk",
 510         .prcm           = {
 511                 .omap4  = {
 512                         .modulemode     = MODULEMODE_SWCTRL,
 513                 },
 514         },
 515 };
 516
 517 /*
 518  * 'gpio' class: for gpio 0,1,2,3
 519  */
 520 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
 521         .rev_offs       = 0x0000,
 522         .sysc_offs      = 0x0010,
 523         .syss_offs      = 0x0114,
 524         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 525                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 526                           SYSS_HAS_RESET_STATUS),
 527         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 528                           SIDLE_SMART_WKUP),
 529         .sysc_fields    = &omap_hwmod_sysc_type1,
 530 };
 531
 532 static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
 533         .name           = "gpio",
 534         .sysc           = &am33xx_gpio_sysc,
 535 };
 536
 537 /* gpio1 */
 538 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 539         { .role = "dbclk", .clk = "gpio1_dbclk" },
 540 };
 541
 542 static struct omap_hwmod am33xx_gpio1_hwmod = {
 543         .name           = "gpio2",
 544         .class          = &am33xx_gpio_hwmod_class,
 545         .clkdm_name     = "l4ls_clkdm",
 546         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 547         .main_clk       = "l4ls_gclk",
 548         .prcm           = {
 549                 .omap4  = {
 550                         .modulemode     = MODULEMODE_SWCTRL,
 551                 },
 552         },
 553         .opt_clks       = gpio1_opt_clks,
 554         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 555 };
 556
 557 /* gpio2 */
 558 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 559         { .role = "dbclk", .clk = "gpio2_dbclk" },
 560 };
 561
 562 static struct omap_hwmod am33xx_gpio2_hwmod = {
 563         .name           = "gpio3",
 564         .class          = &am33xx_gpio_hwmod_class,
 565         .clkdm_name     = "l4ls_clkdm",
 566         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 567         .main_clk       = "l4ls_gclk",
 568         .prcm           = {
 569                 .omap4  = {
 570                         .modulemode     = MODULEMODE_SWCTRL,
 571                 },
 572         },
 573         .opt_clks       = gpio2_opt_clks,
 574         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 575 };
 576
 577 /* gpio3 */
 578 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 579         { .role = "dbclk", .clk = "gpio3_dbclk" },
 580 };
 581
 582 static struct omap_hwmod am33xx_gpio3_hwmod = {
 583         .name           = "gpio4",
 584         .class          = &am33xx_gpio_hwmod_class,
 585         .clkdm_name     = "l4ls_clkdm",
 586         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 587         .main_clk       = "l4ls_gclk",
 588         .prcm           = {
 589                 .omap4  = {
 590                         .modulemode     = MODULEMODE_SWCTRL,
 591                 },
 592         },
 593         .opt_clks       = gpio3_opt_clks,
 594         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 595 };
 596
 597 /* gpmc */
 598 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
 599         .rev_offs       = 0x0,
 600         .sysc_offs      = 0x10,
 601         .syss_offs      = 0x14,
 602         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 603                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 604         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 605         .sysc_fields    = &omap_hwmod_sysc_type1,
 606 };
 607
 608 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
 609         .name           = "gpmc",
 610         .sysc           = &gpmc_sysc,
 611 };
 612
 613 struct omap_hwmod am33xx_gpmc_hwmod = {
 614         .name           = "gpmc",
 615         .class          = &am33xx_gpmc_hwmod_class,
 616         .clkdm_name     = "l3s_clkdm",
 617         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
 618         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
 619         .main_clk       = "l3s_gclk",
 620         .prcm           = {
 621                 .omap4  = {
 622                         .modulemode     = MODULEMODE_SWCTRL,
 623                 },
 624         },
 625 };
 626
 627 /*
 628  * 'mailbox' class
 629  * mailbox module allowing communication between the on-chip processors using a
 630  * queued mailbox-interrupt mechanism.
 631  */
 632 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
 633         .rev_offs       = 0x0000,
 634         .sysc_offs      = 0x0010,
 635         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 636                           SYSC_HAS_SOFTRESET),
 637         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 638         .sysc_fields    = &omap_hwmod_sysc_type2,
 639 };
 640
 641 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
 642         .name   = "mailbox",
 643         .sysc   = &am33xx_mailbox_sysc,
 644 };
 645
 646 struct omap_hwmod am33xx_mailbox_hwmod = {
 647         .name           = "mailbox",
 648         .class          = &am33xx_mailbox_hwmod_class,
 649         .clkdm_name     = "l4ls_clkdm",
 650         .main_clk       = "l4ls_gclk",
 651         .prcm = {
 652                 .omap4 = {
 653                         .modulemode     = MODULEMODE_SWCTRL,
 654                 },
 655         },
 656 };
 657
 658 /*
 659  * 'mcasp' class
 660  */
 661 static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
 662         .rev_offs       = 0x0,
 663         .sysc_offs      = 0x4,
 664         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 665         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 666         .sysc_fields    = &omap_hwmod_sysc_type3,
 667 };
 668
 669 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
 670         .name           = "mcasp",
 671         .sysc           = &am33xx_mcasp_sysc,
 672 };
 673
 674 /* mcasp0 */
 675 struct omap_hwmod am33xx_mcasp0_hwmod = {
 676         .name           = "mcasp0",
 677         .class          = &am33xx_mcasp_hwmod_class,
 678         .clkdm_name     = "l3s_clkdm",
 679         .main_clk       = "mcasp0_fck",
 680         .prcm           = {
 681                 .omap4  = {
 682                         .modulemode     = MODULEMODE_SWCTRL,
 683                 },
 684         },
 685 };
 686
 687 /* mcasp1 */
 688 struct omap_hwmod am33xx_mcasp1_hwmod = {
 689         .name           = "mcasp1",
 690         .class          = &am33xx_mcasp_hwmod_class,
 691         .clkdm_name     = "l3s_clkdm",
 692         .main_clk       = "mcasp1_fck",
 693         .prcm           = {
 694                 .omap4  = {
 695                         .modulemode     = MODULEMODE_SWCTRL,
 696                 },
 697         },
 698 };
 699
 700 /*
 701  * 'rtc' class
 702  * rtc subsystem
 703  */
 704 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
 705         .rev_offs       = 0x0074,
 706         .sysc_offs      = 0x0078,
 707         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 708         .idlemodes      = (SIDLE_FORCE | SIDLE_NO |
 709                           SIDLE_SMART | SIDLE_SMART_WKUP),
 710         .sysc_fields    = &omap_hwmod_sysc_type3,
 711 };
 712
 713 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
 714         .name           = "rtc",
 715         .sysc           = &am33xx_rtc_sysc,
 716         .unlock         = &omap_hwmod_rtc_unlock,
 717         .lock           = &omap_hwmod_rtc_lock,
 718 };
 719
 720 struct omap_hwmod am33xx_rtc_hwmod = {
 721         .name           = "rtc",
 722         .class          = &am33xx_rtc_hwmod_class,
 723         .clkdm_name     = "l4_rtc_clkdm",
 724         .main_clk       = "clk_32768_ck",
 725         .prcm           = {
 726                 .omap4  = {
 727                         .modulemode     = MODULEMODE_SWCTRL,
 728                 },
 729         },
 730 };
 731
 732 /* 'spi' class */
 733 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
 734         .rev_offs       = 0x0000,
 735         .sysc_offs      = 0x0110,
 736         .syss_offs      = 0x0114,
 737         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 738                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 739                           SYSS_HAS_RESET_STATUS),
 740         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 741         .sysc_fields    = &omap_hwmod_sysc_type1,
 742 };
 743
 744 struct omap_hwmod_class am33xx_spi_hwmod_class = {
 745         .name           = "mcspi",
 746         .sysc           = &am33xx_mcspi_sysc,
 747 };
 748
 749 /* spi0 */
 750 struct omap_hwmod am33xx_spi0_hwmod = {
 751         .name           = "spi0",
 752         .class          = &am33xx_spi_hwmod_class,
 753         .clkdm_name     = "l4ls_clkdm",
 754         .main_clk       = "dpll_per_m2_div4_ck",
 755         .prcm           = {
 756                 .omap4  = {
 757                         .modulemode     = MODULEMODE_SWCTRL,
 758                 },
 759         },
 760 };
 761
 762 /* spi1 */
 763 struct omap_hwmod am33xx_spi1_hwmod = {
 764         .name           = "spi1",
 765         .class          = &am33xx_spi_hwmod_class,
 766         .clkdm_name     = "l4ls_clkdm",
 767         .main_clk       = "dpll_per_m2_div4_ck",
 768         .prcm           = {
 769                 .omap4  = {
 770                         .modulemode     = MODULEMODE_SWCTRL,
 771                 },
 772         },
 773 };
 774
 775 /*
 776  * 'spinlock' class
 777  * spinlock provides hardware assistance for synchronizing the
 778  * processes running on multiple processors
 779  */
 780
 781 static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc = {
 782         .rev_offs       = 0x0000,
 783         .sysc_offs      = 0x0010,
 784         .syss_offs      = 0x0014,
 785         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 786                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 787                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 788         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 789         .sysc_fields    = &omap_hwmod_sysc_type1,
 790 };
 791
 792 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
 793         .name           = "spinlock",
 794         .sysc           = &am33xx_spinlock_sysc,
 795 };
 796
 797 struct omap_hwmod am33xx_spinlock_hwmod = {
 798         .name           = "spinlock",
 799         .class          = &am33xx_spinlock_hwmod_class,
 800         .clkdm_name     = "l4ls_clkdm",
 801         .main_clk       = "l4ls_gclk",
 802         .prcm           = {
 803                 .omap4  = {
 804                         .modulemode     = MODULEMODE_SWCTRL,
 805                 },
 806         },
 807 };
 808
 809 /* 'timer 2-7' class */
 810 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
 811         .rev_offs       = 0x0000,
 812         .sysc_offs      = 0x0010,
 813         .syss_offs      = 0x0014,
 814         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 815         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 816                           SIDLE_SMART_WKUP),
 817         .sysc_fields    = &omap_hwmod_sysc_type2,
 818 };
 819
 820 struct omap_hwmod_class am33xx_timer_hwmod_class = {
 821         .name           = "timer",
 822         .sysc           = &am33xx_timer_sysc,
 823 };
 824
 825 /* timer1 1ms */
 826 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
 827         .rev_offs       = 0x0000,
 828         .sysc_offs      = 0x0010,
 829         .syss_offs      = 0x0014,
 830         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 831                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 832                         SYSS_HAS_RESET_STATUS),
 833         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 834         .sysc_fields    = &omap_hwmod_sysc_type1,
 835 };
 836
 837 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
 838         .name           = "timer",
 839         .sysc           = &am33xx_timer1ms_sysc,
 840 };
 841
 842 struct omap_hwmod am33xx_timer1_hwmod = {
 843         .name           = "timer1",
 844         .class          = &am33xx_timer1ms_hwmod_class,
 845         .clkdm_name     = "l4_wkup_clkdm",
 846         .main_clk       = "timer1_fck",
 847         .prcm           = {
 848                 .omap4  = {
 849                         .modulemode     = MODULEMODE_SWCTRL,
 850                 },
 851         },
 852 };
 853
 854 struct omap_hwmod am33xx_timer2_hwmod = {
 855         .name           = "timer2",
 856         .class          = &am33xx_timer_hwmod_class,
 857         .clkdm_name     = "l4ls_clkdm",
 858         .main_clk       = "timer2_fck",
 859         .prcm           = {
 860                 .omap4  = {
 861                         .modulemode     = MODULEMODE_SWCTRL,
 862                 },
 863         },
 864 };
 865
 866 struct omap_hwmod am33xx_timer3_hwmod = {
 867         .name           = "timer3",
 868         .class          = &am33xx_timer_hwmod_class,
 869         .clkdm_name     = "l4ls_clkdm",
 870         .main_clk       = "timer3_fck",
 871         .prcm           = {
 872                 .omap4  = {
 873                         .modulemode     = MODULEMODE_SWCTRL,
 874                 },
 875         },
 876 };
 877
 878 struct omap_hwmod am33xx_timer4_hwmod = {
 879         .name           = "timer4",
 880         .class          = &am33xx_timer_hwmod_class,
 881         .clkdm_name     = "l4ls_clkdm",
 882         .main_clk       = "timer4_fck",
 883         .prcm           = {
 884                 .omap4  = {
 885                         .modulemode     = MODULEMODE_SWCTRL,
 886                 },
 887         },
 888 };
 889
 890 struct omap_hwmod am33xx_timer5_hwmod = {
 891         .name           = "timer5",
 892         .class          = &am33xx_timer_hwmod_class,
 893         .clkdm_name     = "l4ls_clkdm",
 894         .main_clk       = "timer5_fck",
 895         .prcm           = {
 896                 .omap4  = {
 897                         .modulemode     = MODULEMODE_SWCTRL,
 898                 },
 899         },
 900 };
 901
 902 struct omap_hwmod am33xx_timer6_hwmod = {
 903         .name           = "timer6",
 904         .class          = &am33xx_timer_hwmod_class,
 905         .clkdm_name     = "l4ls_clkdm",
 906         .main_clk       = "timer6_fck",
 907         .prcm           = {
 908                 .omap4  = {
 909                         .modulemode     = MODULEMODE_SWCTRL,
 910                 },
 911         },
 912 };
 913
 914 struct omap_hwmod am33xx_timer7_hwmod = {
 915         .name           = "timer7",
 916         .class          = &am33xx_timer_hwmod_class,
 917         .clkdm_name     = "l4ls_clkdm",
 918         .main_clk       = "timer7_fck",
 919         .prcm           = {
 920                 .omap4  = {
 921                         .modulemode     = MODULEMODE_SWCTRL,
 922                 },
 923         },
 924 };
 925
 926 /* tpcc */
 927 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
 928         .name           = "tpcc",
 929 };
 930
 931 struct omap_hwmod am33xx_tpcc_hwmod = {
 932         .name           = "tpcc",
 933         .class          = &am33xx_tpcc_hwmod_class,
 934         .clkdm_name     = "l3_clkdm",
 935         .main_clk       = "l3_gclk",
 936         .prcm           = {
 937                 .omap4  = {
 938                         .modulemode     = MODULEMODE_SWCTRL,
 939                 },
 940         },
 941 };
 942
 943 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
 944         .rev_offs       = 0x0,
 945         .sysc_offs      = 0x10,
 946         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 947                           SYSC_HAS_MIDLEMODE),
 948         .idlemodes      = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
 949         .sysc_fields    = &omap_hwmod_sysc_type2,
 950 };
 951
 952 /* 'tptc' class */
 953 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
 954         .name           = "tptc",
 955         .sysc           = &am33xx_tptc_sysc,
 956 };
 957
 958 /* tptc0 */
 959 struct omap_hwmod am33xx_tptc0_hwmod = {
 960         .name           = "tptc0",
 961         .class          = &am33xx_tptc_hwmod_class,
 962         .clkdm_name     = "l3_clkdm",
 963         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 964         .main_clk       = "l3_gclk",
 965         .prcm           = {
 966                 .omap4  = {
 967                         .modulemode     = MODULEMODE_SWCTRL,
 968                 },
 969         },
 970 };
 971
 972 /* tptc1 */
 973 struct omap_hwmod am33xx_tptc1_hwmod = {
 974         .name           = "tptc1",
 975         .class          = &am33xx_tptc_hwmod_class,
 976         .clkdm_name     = "l3_clkdm",
 977         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 978         .main_clk       = "l3_gclk",
 979         .prcm           = {
 980                 .omap4  = {
 981                         .modulemode     = MODULEMODE_SWCTRL,
 982                 },
 983         },
 984 };
 985
 986 /* tptc2 */
 987 struct omap_hwmod am33xx_tptc2_hwmod = {
 988         .name           = "tptc2",
 989         .class          = &am33xx_tptc_hwmod_class,
 990         .clkdm_name     = "l3_clkdm",
 991         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 992         .main_clk       = "l3_gclk",
 993         .prcm           = {
 994                 .omap4  = {
 995                         .modulemode     = MODULEMODE_SWCTRL,
 996                 },
 997         },
 998 };
 999
1000 /* 'wd_timer' class */
1001 static struct omap_hwmod_class_sysconfig wdt_sysc = {
1002         .rev_offs       = 0x0,
1003         .sysc_offs      = 0x10,
1004         .syss_offs      = 0x14,
1005         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1006                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1007         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1008                         SIDLE_SMART_WKUP),
1009         .sysc_fields    = &omap_hwmod_sysc_type1,
1010 };
1011
1012 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
1013         .name           = "wd_timer",
1014         .sysc           = &wdt_sysc,
1015         .pre_shutdown   = &omap2_wd_timer_disable,
1016 };
1017
1018 /*
1019  * XXX: device.c file uses hardcoded name for watchdog timer
1020  * driver "wd_timer2, so we are also using same name as of now...
1021  */
1022 struct omap_hwmod am33xx_wd_timer1_hwmod = {
1023         .name           = "wd_timer2",
1024         .class          = &am33xx_wd_timer_hwmod_class,
1025         .clkdm_name     = "l4_wkup_clkdm",
1026         .flags          = HWMOD_SWSUP_SIDLE,
1027         .main_clk       = "wdt1_fck",
1028         .prcm           = {
1029                 .omap4  = {
1030                         .modulemode     = MODULEMODE_SWCTRL,
1031                 },
1032         },
1033 };
1034
1035 static void omap_hwmod_am33xx_clkctrl(void)
1036 {
1037         CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1038         CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1039         CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET);
1040         CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1041         CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1042         CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1043         CLKCTRL(am33xx_gpio1_hwmod, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1044         CLKCTRL(am33xx_gpio2_hwmod, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1045         CLKCTRL(am33xx_gpio3_hwmod, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1046         CLKCTRL(am33xx_mailbox_hwmod, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1047         CLKCTRL(am33xx_mcasp0_hwmod, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1048         CLKCTRL(am33xx_mcasp1_hwmod, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1049         CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1050         CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1051         CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1052         CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1053         CLKCTRL(am33xx_timer3_hwmod, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1054         CLKCTRL(am33xx_timer4_hwmod, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1055         CLKCTRL(am33xx_timer5_hwmod, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1056         CLKCTRL(am33xx_timer6_hwmod, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1057         CLKCTRL(am33xx_timer7_hwmod, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1058         CLKCTRL(am33xx_smartreflex0_hwmod,
1059                 AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1060         CLKCTRL(am33xx_smartreflex1_hwmod,
1061                 AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1062         CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1063         CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1064         CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1065         PRCM_FLAGS(am33xx_rtc_hwmod, HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET);
1066         CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1067         CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1068         CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1069         CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
1070         CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1071         CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1072         CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1073         CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1074         CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1075         CLKCTRL(am33xx_cpgmac0_hwmod, AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1076         CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1077         CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1078         CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1079         CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1080         CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1081         CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET);
1082         CLKCTRL(am33xx_rng_hwmod, AM33XX_CM_PER_RNG_CLKCTRL_OFFSET);
1083 }
1084
1085 static void omap_hwmod_am33xx_rst(void)
1086 {
1087         RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET);
1088         RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET);
1089         RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET);
1090 }
1091
1092 void omap_hwmod_am33xx_reg(void)
1093 {
1094         omap_hwmod_am33xx_clkctrl();
1095         omap_hwmod_am33xx_rst();
1096 }
1097
1098 static void omap_hwmod_am43xx_clkctrl(void)
1099 {
1100         CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1101         CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1102         CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET);
1103         CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1104         CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1105         CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1106         CLKCTRL(am33xx_gpio1_hwmod, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1107         CLKCTRL(am33xx_gpio2_hwmod, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1108         CLKCTRL(am33xx_gpio3_hwmod, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1109         CLKCTRL(am33xx_mailbox_hwmod, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1110         CLKCTRL(am33xx_mcasp0_hwmod, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1111         CLKCTRL(am33xx_mcasp1_hwmod, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1112         CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1113         CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1114         CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1115         CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1116         CLKCTRL(am33xx_timer3_hwmod, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1117         CLKCTRL(am33xx_timer4_hwmod, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1118         CLKCTRL(am33xx_timer5_hwmod, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1119         CLKCTRL(am33xx_timer6_hwmod, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1120         CLKCTRL(am33xx_timer7_hwmod, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1121         CLKCTRL(am33xx_smartreflex0_hwmod,
1122                 AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1123         CLKCTRL(am33xx_smartreflex1_hwmod,
1124                 AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1125         CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1126         CLKCTRL(am33xx_wd_timer1_hwmod, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1127         CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1128         CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1129         CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1130         CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1131         CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
1132         CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1133         CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1134         CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1135         CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1136         CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1137         CLKCTRL(am33xx_cpgmac0_hwmod, AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1138         CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1139         CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1140         CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1141         CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1142         CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1143         CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET);
1144         CLKCTRL(am33xx_rng_hwmod, AM43XX_CM_PER_RNG_CLKCTRL_OFFSET);
1145 }
1146
1147 static void omap_hwmod_am43xx_rst(void)
1148 {
1149         RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET);
1150         RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET);
1151         RSTST(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTST_OFFSET);
1152         RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET);
1153 }
1154
1155 void omap_hwmod_am43xx_reg(void)
1156 {
1157         omap_hwmod_am43xx_clkctrl();
1158         omap_hwmod_am43xx_rst();
1159 }