arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c

   1 /*
   2  * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
   3  *
   4  * Copyright (C) 2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/platform_data/gpio-omap.h>
  13 #include <linux/omap-dma.h>
  14 #include <plat/dmtimer.h>
  15 #include <linux/platform_data/spi-omap2-mcspi.h>
  16
  17 #include "omap_hwmod.h"
  18 #include "omap_hwmod_common_data.h"
  19 #include "cm-regbits-24xx.h"
  20 #include "prm-regbits-24xx.h"
  21 #include "wd_timer.h"
  22
  23 static struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
  24         { .name = "dispc", .dma_req = 5 },
  25         { .dma_req = -1, },
  26 };
  27
  28 /*
  29  * 'dispc' class
  30  * display controller
  31  */
  32
  33 static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
  34         .rev_offs       = 0x0000,
  35         .sysc_offs      = 0x0010,
  36         .syss_offs      = 0x0014,
  37         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
  38                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
  39         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  40                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
  41         .sysc_fields    = &omap_hwmod_sysc_type1,
  42 };
  43
  44 struct omap_hwmod_class omap2_dispc_hwmod_class = {
  45         .name   = "dispc",
  46         .sysc   = &omap2_dispc_sysc,
  47 };
  48
  49 /* OMAP2xxx Timer Common */
  50 static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
  51         .rev_offs       = 0x0000,
  52         .sysc_offs      = 0x0010,
  53         .syss_offs      = 0x0014,
  54         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
  55                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  56                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  57         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  58         .sysc_fields    = &omap_hwmod_sysc_type1,
  59 };
  60
  61 struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
  62         .name   = "timer",
  63         .sysc   = &omap2xxx_timer_sysc,
  64 };
  65
  66 /*
  67  * 'wd_timer' class
  68  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
  69  * overflow condition
  70  */
  71
  72 static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
  73         .rev_offs       = 0x0000,
  74         .sysc_offs      = 0x0010,
  75         .syss_offs      = 0x0014,
  76         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
  77                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  78         .sysc_fields    = &omap_hwmod_sysc_type1,
  79 };
  80
  81 struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
  82         .name           = "wd_timer",
  83         .sysc           = &omap2xxx_wd_timer_sysc,
  84         .pre_shutdown   = &omap2_wd_timer_disable,
  85         .reset          = &omap2_wd_timer_reset,
  86 };
  87
  88 /*
  89  * 'gpio' class
  90  * general purpose io module
  91  */
  92 static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
  93         .rev_offs       = 0x0000,
  94         .sysc_offs      = 0x0010,
  95         .syss_offs      = 0x0014,
  96         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
  97                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
  98                            SYSS_HAS_RESET_STATUS),
  99         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 100         .sysc_fields    = &omap_hwmod_sysc_type1,
 101 };
 102
 103 struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
 104         .name = "gpio",
 105         .sysc = &omap2xxx_gpio_sysc,
 106         .rev = 0,
 107 };
 108
 109 /* system dma */
 110 static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
 111         .rev_offs       = 0x0000,
 112         .sysc_offs      = 0x002c,
 113         .syss_offs      = 0x0028,
 114         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
 115                            SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
 116                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 117         .idlemodes      = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 118         .sysc_fields    = &omap_hwmod_sysc_type1,
 119 };
 120
 121 struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
 122         .name   = "dma",
 123         .sysc   = &omap2xxx_dma_sysc,
 124 };
 125
 126 /*
 127  * 'mailbox' class
 128  * mailbox module allowing communication between the on-chip processors
 129  * using a queued mailbox-interrupt mechanism.
 130  */
 131
 132 static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
 133         .rev_offs       = 0x000,
 134         .sysc_offs      = 0x010,
 135         .syss_offs      = 0x014,
 136         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 137                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 138         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 139         .sysc_fields    = &omap_hwmod_sysc_type1,
 140 };
 141
 142 struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
 143         .name   = "mailbox",
 144         .sysc   = &omap2xxx_mailbox_sysc,
 145 };
 146
 147 /*
 148  * 'mcspi' class
 149  * multichannel serial port interface (mcspi) / master/slave synchronous serial
 150  * bus
 151  */
 152
 153 static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
 154         .rev_offs       = 0x0000,
 155         .sysc_offs      = 0x0010,
 156         .syss_offs      = 0x0014,
 157         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 158                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 159                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 160         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 161         .sysc_fields    = &omap_hwmod_sysc_type1,
 162 };
 163
 164 struct omap_hwmod_class omap2xxx_mcspi_class = {
 165         .name   = "mcspi",
 166         .sysc   = &omap2xxx_mcspi_sysc,
 167         .rev    = OMAP2_MCSPI_REV,
 168 };
 169
 170 /*
 171  * 'gpmc' class
 172  * general purpose memory controller
 173  */
 174
 175 static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = {
 176         .rev_offs       = 0x0000,
 177         .sysc_offs      = 0x0010,
 178         .syss_offs      = 0x0014,
 179         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 180                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 181         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 182         .sysc_fields    = &omap_hwmod_sysc_type1,
 183 };
 184
 185 static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = {
 186         .name   = "gpmc",
 187         .sysc   = &omap2xxx_gpmc_sysc,
 188 };
 189
 190 /*
 191  * IP blocks
 192  */
 193
 194 /* L3 */
 195 struct omap_hwmod omap2xxx_l3_main_hwmod = {
 196         .name           = "l3_main",
 197         .class          = &l3_hwmod_class,
 198         .flags          = HWMOD_NO_IDLEST,
 199 };
 200
 201 /* L4 CORE */
 202 struct omap_hwmod omap2xxx_l4_core_hwmod = {
 203         .name           = "l4_core",
 204         .class          = &l4_hwmod_class,
 205         .flags          = HWMOD_NO_IDLEST,
 206 };
 207
 208 /* L4 WKUP */
 209 struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
 210         .name           = "l4_wkup",
 211         .class          = &l4_hwmod_class,
 212         .flags          = HWMOD_NO_IDLEST,
 213 };
 214
 215 /* MPU */
 216 struct omap_hwmod omap2xxx_mpu_hwmod = {
 217         .name           = "mpu",
 218         .class          = &mpu_hwmod_class,
 219         .main_clk       = "mpu_ck",
 220 };
 221
 222 /* IVA2 */
 223 struct omap_hwmod omap2xxx_iva_hwmod = {
 224         .name           = "iva",
 225         .class          = &iva_hwmod_class,
 226 };
 227
 228 /* always-on timers dev attribute */
 229 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 230         .timer_capability       = OMAP_TIMER_ALWON,
 231 };
 232
 233 /* pwm timers dev attribute */
 234 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 235         .timer_capability       = OMAP_TIMER_HAS_PWM,
 236 };
 237
 238 /* timers with DSP interrupt dev attribute */
 239 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
 240         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
 241 };
 242
 243 /* timer1 */
 244
 245 struct omap_hwmod omap2xxx_timer1_hwmod = {
 246         .name           = "timer1",
 247         .main_clk       = "gpt1_fck",
 248         .prcm           = {
 249                 .omap2 = {
 250                         .prcm_reg_id = 1,
 251                         .module_bit = OMAP24XX_EN_GPT1_SHIFT,
 252                         .module_offs = WKUP_MOD,
 253                         .idlest_reg_id = 1,
 254                         .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
 255                 },
 256         },
 257         .dev_attr       = &capability_alwon_dev_attr,
 258         .class          = &omap2xxx_timer_hwmod_class,
 259         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 260 };
 261
 262 /* timer2 */
 263
 264 struct omap_hwmod omap2xxx_timer2_hwmod = {
 265         .name           = "timer2",
 266         .main_clk       = "gpt2_fck",
 267         .prcm           = {
 268                 .omap2 = {
 269                         .prcm_reg_id = 1,
 270                         .module_bit = OMAP24XX_EN_GPT2_SHIFT,
 271                         .module_offs = CORE_MOD,
 272                         .idlest_reg_id = 1,
 273                         .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
 274                 },
 275         },
 276         .class          = &omap2xxx_timer_hwmod_class,
 277         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 278 };
 279
 280 /* timer3 */
 281
 282 struct omap_hwmod omap2xxx_timer3_hwmod = {
 283         .name           = "timer3",
 284         .main_clk       = "gpt3_fck",
 285         .prcm           = {
 286                 .omap2 = {
 287                         .prcm_reg_id = 1,
 288                         .module_bit = OMAP24XX_EN_GPT3_SHIFT,
 289                         .module_offs = CORE_MOD,
 290                         .idlest_reg_id = 1,
 291                         .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
 292                 },
 293         },
 294         .class          = &omap2xxx_timer_hwmod_class,
 295         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 296 };
 297
 298 /* timer4 */
 299
 300 struct omap_hwmod omap2xxx_timer4_hwmod = {
 301         .name           = "timer4",
 302         .main_clk       = "gpt4_fck",
 303         .prcm           = {
 304                 .omap2 = {
 305                         .prcm_reg_id = 1,
 306                         .module_bit = OMAP24XX_EN_GPT4_SHIFT,
 307                         .module_offs = CORE_MOD,
 308                         .idlest_reg_id = 1,
 309                         .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
 310                 },
 311         },
 312         .class          = &omap2xxx_timer_hwmod_class,
 313         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 314 };
 315
 316 /* timer5 */
 317
 318 struct omap_hwmod omap2xxx_timer5_hwmod = {
 319         .name           = "timer5",
 320         .main_clk       = "gpt5_fck",
 321         .prcm           = {
 322                 .omap2 = {
 323                         .prcm_reg_id = 1,
 324                         .module_bit = OMAP24XX_EN_GPT5_SHIFT,
 325                         .module_offs = CORE_MOD,
 326                         .idlest_reg_id = 1,
 327                         .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
 328                 },
 329         },
 330         .dev_attr       = &capability_dsp_dev_attr,
 331         .class          = &omap2xxx_timer_hwmod_class,
 332         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 333 };
 334
 335 /* timer6 */
 336
 337 struct omap_hwmod omap2xxx_timer6_hwmod = {
 338         .name           = "timer6",
 339         .main_clk       = "gpt6_fck",
 340         .prcm           = {
 341                 .omap2 = {
 342                         .prcm_reg_id = 1,
 343                         .module_bit = OMAP24XX_EN_GPT6_SHIFT,
 344                         .module_offs = CORE_MOD,
 345                         .idlest_reg_id = 1,
 346                         .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
 347                 },
 348         },
 349         .dev_attr       = &capability_dsp_dev_attr,
 350         .class          = &omap2xxx_timer_hwmod_class,
 351         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 352 };
 353
 354 /* timer7 */
 355
 356 struct omap_hwmod omap2xxx_timer7_hwmod = {
 357         .name           = "timer7",
 358         .main_clk       = "gpt7_fck",
 359         .prcm           = {
 360                 .omap2 = {
 361                         .prcm_reg_id = 1,
 362                         .module_bit = OMAP24XX_EN_GPT7_SHIFT,
 363                         .module_offs = CORE_MOD,
 364                         .idlest_reg_id = 1,
 365                         .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
 366                 },
 367         },
 368         .dev_attr       = &capability_dsp_dev_attr,
 369         .class          = &omap2xxx_timer_hwmod_class,
 370         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 371 };
 372
 373 /* timer8 */
 374
 375 struct omap_hwmod omap2xxx_timer8_hwmod = {
 376         .name           = "timer8",
 377         .main_clk       = "gpt8_fck",
 378         .prcm           = {
 379                 .omap2 = {
 380                         .prcm_reg_id = 1,
 381                         .module_bit = OMAP24XX_EN_GPT8_SHIFT,
 382                         .module_offs = CORE_MOD,
 383                         .idlest_reg_id = 1,
 384                         .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
 385                 },
 386         },
 387         .dev_attr       = &capability_dsp_dev_attr,
 388         .class          = &omap2xxx_timer_hwmod_class,
 389         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 390 };
 391
 392 /* timer9 */
 393
 394 struct omap_hwmod omap2xxx_timer9_hwmod = {
 395         .name           = "timer9",
 396         .main_clk       = "gpt9_fck",
 397         .prcm           = {
 398                 .omap2 = {
 399                         .prcm_reg_id = 1,
 400                         .module_bit = OMAP24XX_EN_GPT9_SHIFT,
 401                         .module_offs = CORE_MOD,
 402                         .idlest_reg_id = 1,
 403                         .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
 404                 },
 405         },
 406         .dev_attr       = &capability_pwm_dev_attr,
 407         .class          = &omap2xxx_timer_hwmod_class,
 408         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 409 };
 410
 411 /* timer10 */
 412
 413 struct omap_hwmod omap2xxx_timer10_hwmod = {
 414         .name           = "timer10",
 415         .main_clk       = "gpt10_fck",
 416         .prcm           = {
 417                 .omap2 = {
 418                         .prcm_reg_id = 1,
 419                         .module_bit = OMAP24XX_EN_GPT10_SHIFT,
 420                         .module_offs = CORE_MOD,
 421                         .idlest_reg_id = 1,
 422                         .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
 423                 },
 424         },
 425         .dev_attr       = &capability_pwm_dev_attr,
 426         .class          = &omap2xxx_timer_hwmod_class,
 427         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 428 };
 429
 430 /* timer11 */
 431
 432 struct omap_hwmod omap2xxx_timer11_hwmod = {
 433         .name           = "timer11",
 434         .main_clk       = "gpt11_fck",
 435         .prcm           = {
 436                 .omap2 = {
 437                         .prcm_reg_id = 1,
 438                         .module_bit = OMAP24XX_EN_GPT11_SHIFT,
 439                         .module_offs = CORE_MOD,
 440                         .idlest_reg_id = 1,
 441                         .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
 442                 },
 443         },
 444         .dev_attr       = &capability_pwm_dev_attr,
 445         .class          = &omap2xxx_timer_hwmod_class,
 446         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 447 };
 448
 449 /* timer12 */
 450
 451 struct omap_hwmod omap2xxx_timer12_hwmod = {
 452         .name           = "timer12",
 453         .main_clk       = "gpt12_fck",
 454         .prcm           = {
 455                 .omap2 = {
 456                         .prcm_reg_id = 1,
 457                         .module_bit = OMAP24XX_EN_GPT12_SHIFT,
 458                         .module_offs = CORE_MOD,
 459                         .idlest_reg_id = 1,
 460                         .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
 461                 },
 462         },
 463         .dev_attr       = &capability_pwm_dev_attr,
 464         .class          = &omap2xxx_timer_hwmod_class,
 465         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 466 };
 467
 468 /* wd_timer2 */
 469 struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
 470         .name           = "wd_timer2",
 471         .class          = &omap2xxx_wd_timer_hwmod_class,
 472         .main_clk       = "mpu_wdt_fck",
 473         .prcm           = {
 474                 .omap2 = {
 475                         .prcm_reg_id = 1,
 476                         .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
 477                         .module_offs = WKUP_MOD,
 478                         .idlest_reg_id = 1,
 479                         .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
 480                 },
 481         },
 482 };
 483
 484 /* UART1 */
 485
 486 struct omap_hwmod omap2xxx_uart1_hwmod = {
 487         .name           = "uart1",
 488         .main_clk       = "uart1_fck",
 489         .flags          = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
 490         .prcm           = {
 491                 .omap2 = {
 492                         .module_offs = CORE_MOD,
 493                         .prcm_reg_id = 1,
 494                         .module_bit = OMAP24XX_EN_UART1_SHIFT,
 495                         .idlest_reg_id = 1,
 496                         .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
 497                 },
 498         },
 499         .class          = &omap2_uart_class,
 500 };
 501
 502 /* UART2 */
 503
 504 struct omap_hwmod omap2xxx_uart2_hwmod = {
 505         .name           = "uart2",
 506         .main_clk       = "uart2_fck",
 507         .flags          = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
 508         .prcm           = {
 509                 .omap2 = {
 510                         .module_offs = CORE_MOD,
 511                         .prcm_reg_id = 1,
 512                         .module_bit = OMAP24XX_EN_UART2_SHIFT,
 513                         .idlest_reg_id = 1,
 514                         .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
 515                 },
 516         },
 517         .class          = &omap2_uart_class,
 518 };
 519
 520 /* UART3 */
 521
 522 struct omap_hwmod omap2xxx_uart3_hwmod = {
 523         .name           = "uart3",
 524         .main_clk       = "uart3_fck",
 525         .flags          = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
 526         .prcm           = {
 527                 .omap2 = {
 528                         .module_offs = CORE_MOD,
 529                         .prcm_reg_id = 2,
 530                         .module_bit = OMAP24XX_EN_UART3_SHIFT,
 531                         .idlest_reg_id = 2,
 532                         .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
 533                 },
 534         },
 535         .class          = &omap2_uart_class,
 536 };
 537
 538 /* dss */
 539
 540 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 541         /*
 542          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
 543          * driver does not use these clocks.
 544          */
 545         { .role = "tv_clk", .clk = "dss_54m_fck" },
 546         { .role = "sys_clk", .clk = "dss2_fck" },
 547 };
 548
 549 struct omap_hwmod omap2xxx_dss_core_hwmod = {
 550         .name           = "dss_core",
 551         .class          = &omap2_dss_hwmod_class,
 552         .main_clk       = "dss1_fck", /* instead of dss_fck */
 553         .sdma_reqs      = omap2xxx_dss_sdma_chs,
 554         .prcm           = {
 555                 .omap2 = {
 556                         .prcm_reg_id = 1,
 557                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 558                         .module_offs = CORE_MOD,
 559                         .idlest_reg_id = 1,
 560                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
 561                 },
 562         },
 563         .opt_clks       = dss_opt_clks,
 564         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 565         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 566 };
 567
 568 struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
 569         .name           = "dss_dispc",
 570         .class          = &omap2_dispc_hwmod_class,
 571         .main_clk       = "dss1_fck",
 572         .prcm           = {
 573                 .omap2 = {
 574                         .prcm_reg_id = 1,
 575                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 576                         .module_offs = CORE_MOD,
 577                         .idlest_reg_id = 1,
 578                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
 579                 },
 580         },
 581         .flags          = HWMOD_NO_IDLEST,
 582         .dev_attr       = &omap2_3_dss_dispc_dev_attr,
 583 };
 584
 585 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 586         { .role = "ick", .clk = "dss_ick" },
 587 };
 588
 589 struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
 590         .name           = "dss_rfbi",
 591         .class          = &omap2_rfbi_hwmod_class,
 592         .main_clk       = "dss1_fck",
 593         .prcm           = {
 594                 .omap2 = {
 595                         .prcm_reg_id = 1,
 596                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 597                         .module_offs = CORE_MOD,
 598                 },
 599         },
 600         .opt_clks       = dss_rfbi_opt_clks,
 601         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 602         .flags          = HWMOD_NO_IDLEST,
 603 };
 604
 605 struct omap_hwmod omap2xxx_dss_venc_hwmod = {
 606         .name           = "dss_venc",
 607         .class          = &omap2_venc_hwmod_class,
 608         .main_clk       = "dss_54m_fck",
 609         .prcm           = {
 610                 .omap2 = {
 611                         .prcm_reg_id = 1,
 612                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 613                         .module_offs = CORE_MOD,
 614                 },
 615         },
 616         .flags          = HWMOD_NO_IDLEST,
 617 };
 618
 619 /* gpio dev_attr */
 620 struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
 621         .bank_width = 32,
 622         .dbck_flag = false,
 623 };
 624
 625 /* gpio1 */
 626 struct omap_hwmod omap2xxx_gpio1_hwmod = {
 627         .name           = "gpio1",
 628         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 629         .main_clk       = "gpios_fck",
 630         .prcm           = {
 631                 .omap2 = {
 632                         .prcm_reg_id = 1,
 633                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
 634                         .module_offs = WKUP_MOD,
 635                         .idlest_reg_id = 1,
 636                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 637                 },
 638         },
 639         .class          = &omap2xxx_gpio_hwmod_class,
 640         .dev_attr       = &omap2xxx_gpio_dev_attr,
 641 };
 642
 643 /* gpio2 */
 644 struct omap_hwmod omap2xxx_gpio2_hwmod = {
 645         .name           = "gpio2",
 646         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 647         .main_clk       = "gpios_fck",
 648         .prcm           = {
 649                 .omap2 = {
 650                         .prcm_reg_id = 1,
 651                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
 652                         .module_offs = WKUP_MOD,
 653                         .idlest_reg_id = 1,
 654                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 655                 },
 656         },
 657         .class          = &omap2xxx_gpio_hwmod_class,
 658         .dev_attr       = &omap2xxx_gpio_dev_attr,
 659 };
 660
 661 /* gpio3 */
 662 struct omap_hwmod omap2xxx_gpio3_hwmod = {
 663         .name           = "gpio3",
 664         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 665         .main_clk       = "gpios_fck",
 666         .prcm           = {
 667                 .omap2 = {
 668                         .prcm_reg_id = 1,
 669                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
 670                         .module_offs = WKUP_MOD,
 671                         .idlest_reg_id = 1,
 672                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 673                 },
 674         },
 675         .class          = &omap2xxx_gpio_hwmod_class,
 676         .dev_attr       = &omap2xxx_gpio_dev_attr,
 677 };
 678
 679 /* gpio4 */
 680 struct omap_hwmod omap2xxx_gpio4_hwmod = {
 681         .name           = "gpio4",
 682         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 683         .main_clk       = "gpios_fck",
 684         .prcm           = {
 685                 .omap2 = {
 686                         .prcm_reg_id = 1,
 687                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
 688                         .module_offs = WKUP_MOD,
 689                         .idlest_reg_id = 1,
 690                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 691                 },
 692         },
 693         .class          = &omap2xxx_gpio_hwmod_class,
 694         .dev_attr       = &omap2xxx_gpio_dev_attr,
 695 };
 696
 697 /* mcspi1 */
 698 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
 699         .num_chipselect = 4,
 700 };
 701
 702 struct omap_hwmod omap2xxx_mcspi1_hwmod = {
 703         .name           = "mcspi1",
 704         .main_clk       = "mcspi1_fck",
 705         .prcm           = {
 706                 .omap2 = {
 707                         .module_offs = CORE_MOD,
 708                         .prcm_reg_id = 1,
 709                         .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
 710                         .idlest_reg_id = 1,
 711                         .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
 712                 },
 713         },
 714         .class          = &omap2xxx_mcspi_class,
 715         .dev_attr       = &omap_mcspi1_dev_attr,
 716 };
 717
 718 /* mcspi2 */
 719 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
 720         .num_chipselect = 2,
 721 };
 722
 723 struct omap_hwmod omap2xxx_mcspi2_hwmod = {
 724         .name           = "mcspi2",
 725         .main_clk       = "mcspi2_fck",
 726         .prcm           = {
 727                 .omap2 = {
 728                         .module_offs = CORE_MOD,
 729                         .prcm_reg_id = 1,
 730                         .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
 731                         .idlest_reg_id = 1,
 732                         .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
 733                 },
 734         },
 735         .class          = &omap2xxx_mcspi_class,
 736         .dev_attr       = &omap_mcspi2_dev_attr,
 737 };
 738
 739 static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
 740         .name   = "counter",
 741 };
 742
 743 struct omap_hwmod omap2xxx_counter_32k_hwmod = {
 744         .name           = "counter_32k",
 745         .main_clk       = "func_32k_ck",
 746         .prcm           = {
 747                 .omap2  = {
 748                         .module_offs = WKUP_MOD,
 749                         .prcm_reg_id = 1,
 750                         .module_bit = OMAP24XX_ST_32KSYNC_SHIFT,
 751                         .idlest_reg_id = 1,
 752                         .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
 753                 },
 754         },
 755         .class          = &omap2xxx_counter_hwmod_class,
 756 };
 757
 758 /* gpmc */
 759 struct omap_hwmod omap2xxx_gpmc_hwmod = {
 760         .name           = "gpmc",
 761         .class          = &omap2xxx_gpmc_hwmod_class,
 762         .main_clk       = "gpmc_fck",
 763         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
 764         .flags          = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
 765         .prcm           = {
 766                 .omap2  = {
 767                         .prcm_reg_id = 3,
 768                         .module_bit = OMAP24XX_EN_GPMC_MASK,
 769                         .module_offs = CORE_MOD,
 770                 },
 771         },
 772 };
 773
 774 /* RNG */
 775
 776 static struct omap_hwmod_class_sysconfig omap2_rng_sysc = {
 777         .rev_offs       = 0x3c,
 778         .sysc_offs      = 0x40,
 779         .syss_offs      = 0x44,
 780         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 781                            SYSS_HAS_RESET_STATUS),
 782         .sysc_fields    = &omap_hwmod_sysc_type1,
 783 };
 784
 785 static struct omap_hwmod_class omap2_rng_hwmod_class = {
 786         .name           = "rng",
 787         .sysc           = &omap2_rng_sysc,
 788 };
 789
 790 struct omap_hwmod omap2xxx_rng_hwmod = {
 791         .name           = "rng",
 792         .main_clk       = "l4_ck",
 793         .prcm           = {
 794                 .omap2 = {
 795                         .module_offs = CORE_MOD,
 796                         .prcm_reg_id = 4,
 797                         .module_bit = OMAP24XX_EN_RNG_SHIFT,
 798                         .idlest_reg_id = 4,
 799                         .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
 800                 },
 801         },
 802         /*
 803          * XXX The first read from the SYSSTATUS register of the RNG
 804          * after the SYSCONFIG SOFTRESET bit is set triggers an
 805          * imprecise external abort.  It's unclear why this happens.
 806          * Until this is analyzed, skip the IP block reset.
 807          */
 808         .flags          = HWMOD_INIT_NO_RESET,
 809         .class          = &omap2_rng_hwmod_class,
 810 };
 811
 812 /* SHAM */
 813
 814 static struct omap_hwmod_class_sysconfig omap2_sham_sysc = {
 815         .rev_offs       = 0x5c,
 816         .sysc_offs      = 0x60,
 817         .syss_offs      = 0x64,
 818         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 819                            SYSS_HAS_RESET_STATUS),
 820         .sysc_fields    = &omap_hwmod_sysc_type1,
 821 };
 822
 823 static struct omap_hwmod_class omap2xxx_sham_class = {
 824         .name   = "sham",
 825         .sysc   = &omap2_sham_sysc,
 826 };
 827
 828 struct omap_hwmod omap2xxx_sham_hwmod = {
 829         .name           = "sham",
 830         .main_clk       = "l4_ck",
 831         .prcm           = {
 832                 .omap2 = {
 833                         .module_offs = CORE_MOD,
 834                         .prcm_reg_id = 4,
 835                         .module_bit = OMAP24XX_EN_SHA_SHIFT,
 836                         .idlest_reg_id = 4,
 837                         .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT,
 838                 },
 839         },
 840         .class          = &omap2xxx_sham_class,
 841 };
 842
 843 /* AES */
 844
 845 static struct omap_hwmod_class_sysconfig omap2_aes_sysc = {
 846         .rev_offs       = 0x44,
 847         .sysc_offs      = 0x48,
 848         .syss_offs      = 0x4c,
 849         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 850                            SYSS_HAS_RESET_STATUS),
 851         .sysc_fields    = &omap_hwmod_sysc_type1,
 852 };
 853
 854 static struct omap_hwmod_class omap2xxx_aes_class = {
 855         .name   = "aes",
 856         .sysc   = &omap2_aes_sysc,
 857 };
 858
 859 struct omap_hwmod omap2xxx_aes_hwmod = {
 860         .name           = "aes",
 861         .main_clk       = "l4_ck",
 862         .prcm           = {
 863                 .omap2 = {
 864                         .module_offs = CORE_MOD,
 865                         .prcm_reg_id = 4,
 866                         .module_bit = OMAP24XX_EN_AES_SHIFT,
 867                         .idlest_reg_id = 4,
 868                         .idlest_idle_bit = OMAP24XX_ST_AES_SHIFT,
 869                 },
 870         },
 871         .class          = &omap2xxx_aes_class,
 872 };