2 * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
4 * Copyright (C) 2011 Nokia Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/platform_data/gpio-omap.h>
13 #include <linux/omap-dma.h>
14 #include <plat/dmtimer.h>
15 #include <linux/platform_data/spi-omap2-mcspi.h>
17 #include "omap_hwmod.h"
18 #include "omap_hwmod_common_data.h"
19 #include "cm-regbits-24xx.h"
20 #include "prm-regbits-24xx.h"
28 static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
32 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
33 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
34 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
35 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
36 .sysc_fields = &omap_hwmod_sysc_type1,
39 struct omap_hwmod_class omap2_dispc_hwmod_class = {
41 .sysc = &omap2_dispc_sysc,
44 /* OMAP2xxx Timer Common */
45 static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
49 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
50 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
51 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
52 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
53 .sysc_fields = &omap_hwmod_sysc_type1,
56 struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
58 .sysc = &omap2xxx_timer_sysc,
63 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
67 static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
71 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
72 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
73 .sysc_fields = &omap_hwmod_sysc_type1,
76 struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
78 .sysc = &omap2xxx_wd_timer_sysc,
79 .pre_shutdown = &omap2_wd_timer_disable,
80 .reset = &omap2_wd_timer_reset,
85 * general purpose io module
87 static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
91 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
92 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
93 SYSS_HAS_RESET_STATUS),
94 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
95 .sysc_fields = &omap_hwmod_sysc_type1,
98 struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
100 .sysc = &omap2xxx_gpio_sysc,
105 static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
109 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
110 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
111 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
112 .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
113 .sysc_fields = &omap_hwmod_sysc_type1,
116 struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
118 .sysc = &omap2xxx_dma_sysc,
123 * mailbox module allowing communication between the on-chip processors
124 * using a queued mailbox-interrupt mechanism.
127 static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
131 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
132 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
133 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
134 .sysc_fields = &omap_hwmod_sysc_type1,
137 struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
139 .sysc = &omap2xxx_mailbox_sysc,
144 * multichannel serial port interface (mcspi) / master/slave synchronous serial
148 static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
152 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
153 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
154 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
155 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
156 .sysc_fields = &omap_hwmod_sysc_type1,
159 struct omap_hwmod_class omap2xxx_mcspi_class = {
161 .sysc = &omap2xxx_mcspi_sysc,
162 .rev = OMAP2_MCSPI_REV,
167 * general purpose memory controller
170 static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = {
174 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
175 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
176 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
177 .sysc_fields = &omap_hwmod_sysc_type1,
180 static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = {
182 .sysc = &omap2xxx_gpmc_sysc,
190 struct omap_hwmod omap2xxx_l3_main_hwmod = {
192 .class = &l3_hwmod_class,
193 .flags = HWMOD_NO_IDLEST,
197 struct omap_hwmod omap2xxx_l4_core_hwmod = {
199 .class = &l4_hwmod_class,
200 .flags = HWMOD_NO_IDLEST,
204 struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
206 .class = &l4_hwmod_class,
207 .flags = HWMOD_NO_IDLEST,
211 struct omap_hwmod omap2xxx_mpu_hwmod = {
213 .class = &mpu_hwmod_class,
214 .main_clk = "mpu_ck",
218 struct omap_hwmod omap2xxx_iva_hwmod = {
220 .class = &iva_hwmod_class,
223 /* always-on timers dev attribute */
224 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
225 .timer_capability = OMAP_TIMER_ALWON,
228 /* pwm timers dev attribute */
229 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
230 .timer_capability = OMAP_TIMER_HAS_PWM,
233 /* timers with DSP interrupt dev attribute */
234 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
235 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
240 struct omap_hwmod omap2xxx_timer1_hwmod = {
242 .main_clk = "gpt1_fck",
245 .module_offs = WKUP_MOD,
247 .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
250 .dev_attr = &capability_alwon_dev_attr,
251 .class = &omap2xxx_timer_hwmod_class,
252 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
257 struct omap_hwmod omap2xxx_timer2_hwmod = {
259 .main_clk = "gpt2_fck",
262 .module_offs = CORE_MOD,
264 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
267 .class = &omap2xxx_timer_hwmod_class,
268 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
273 struct omap_hwmod omap2xxx_timer3_hwmod = {
275 .main_clk = "gpt3_fck",
278 .module_offs = CORE_MOD,
280 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
283 .class = &omap2xxx_timer_hwmod_class,
284 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
289 struct omap_hwmod omap2xxx_timer4_hwmod = {
291 .main_clk = "gpt4_fck",
294 .module_offs = CORE_MOD,
296 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
299 .class = &omap2xxx_timer_hwmod_class,
300 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
305 struct omap_hwmod omap2xxx_timer5_hwmod = {
307 .main_clk = "gpt5_fck",
310 .module_offs = CORE_MOD,
312 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
315 .dev_attr = &capability_dsp_dev_attr,
316 .class = &omap2xxx_timer_hwmod_class,
317 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
322 struct omap_hwmod omap2xxx_timer6_hwmod = {
324 .main_clk = "gpt6_fck",
327 .module_offs = CORE_MOD,
329 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
332 .dev_attr = &capability_dsp_dev_attr,
333 .class = &omap2xxx_timer_hwmod_class,
334 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
339 struct omap_hwmod omap2xxx_timer7_hwmod = {
341 .main_clk = "gpt7_fck",
344 .module_offs = CORE_MOD,
346 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
349 .dev_attr = &capability_dsp_dev_attr,
350 .class = &omap2xxx_timer_hwmod_class,
351 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
356 struct omap_hwmod omap2xxx_timer8_hwmod = {
358 .main_clk = "gpt8_fck",
361 .module_offs = CORE_MOD,
363 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
366 .dev_attr = &capability_dsp_dev_attr,
367 .class = &omap2xxx_timer_hwmod_class,
368 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
373 struct omap_hwmod omap2xxx_timer9_hwmod = {
375 .main_clk = "gpt9_fck",
378 .module_offs = CORE_MOD,
380 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
383 .dev_attr = &capability_pwm_dev_attr,
384 .class = &omap2xxx_timer_hwmod_class,
385 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
390 struct omap_hwmod omap2xxx_timer10_hwmod = {
392 .main_clk = "gpt10_fck",
395 .module_offs = CORE_MOD,
397 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
400 .dev_attr = &capability_pwm_dev_attr,
401 .class = &omap2xxx_timer_hwmod_class,
402 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
407 struct omap_hwmod omap2xxx_timer11_hwmod = {
409 .main_clk = "gpt11_fck",
412 .module_offs = CORE_MOD,
414 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
417 .dev_attr = &capability_pwm_dev_attr,
418 .class = &omap2xxx_timer_hwmod_class,
419 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
424 struct omap_hwmod omap2xxx_timer12_hwmod = {
426 .main_clk = "gpt12_fck",
429 .module_offs = CORE_MOD,
431 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
434 .dev_attr = &capability_pwm_dev_attr,
435 .class = &omap2xxx_timer_hwmod_class,
436 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
440 struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
442 .class = &omap2xxx_wd_timer_hwmod_class,
443 .main_clk = "mpu_wdt_fck",
446 .module_offs = WKUP_MOD,
448 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
455 struct omap_hwmod omap2xxx_uart1_hwmod = {
457 .main_clk = "uart1_fck",
458 .flags = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
461 .module_offs = CORE_MOD,
463 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
466 .class = &omap2_uart_class,
471 struct omap_hwmod omap2xxx_uart2_hwmod = {
473 .main_clk = "uart2_fck",
474 .flags = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
477 .module_offs = CORE_MOD,
479 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
482 .class = &omap2_uart_class,
487 struct omap_hwmod omap2xxx_uart3_hwmod = {
489 .main_clk = "uart3_fck",
490 .flags = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
493 .module_offs = CORE_MOD,
495 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
498 .class = &omap2_uart_class,
503 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
505 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
506 * driver does not use these clocks.
508 { .role = "tv_clk", .clk = "dss_54m_fck" },
509 { .role = "sys_clk", .clk = "dss2_fck" },
512 struct omap_hwmod omap2xxx_dss_core_hwmod = {
514 .class = &omap2_dss_hwmod_class,
515 .main_clk = "dss1_fck", /* instead of dss_fck */
518 .module_offs = CORE_MOD,
522 .opt_clks = dss_opt_clks,
523 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
524 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
527 struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
529 .class = &omap2_dispc_hwmod_class,
530 .main_clk = "dss1_fck",
533 .module_offs = CORE_MOD,
537 .flags = HWMOD_NO_IDLEST,
538 .dev_attr = &omap2_3_dss_dispc_dev_attr,
541 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
542 { .role = "ick", .clk = "dss_ick" },
545 struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
547 .class = &omap2_rfbi_hwmod_class,
548 .main_clk = "dss1_fck",
551 .module_offs = CORE_MOD,
554 .opt_clks = dss_rfbi_opt_clks,
555 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
556 .flags = HWMOD_NO_IDLEST,
559 struct omap_hwmod omap2xxx_dss_venc_hwmod = {
561 .class = &omap2_venc_hwmod_class,
562 .main_clk = "dss_54m_fck",
565 .module_offs = CORE_MOD,
568 .flags = HWMOD_NO_IDLEST,
572 struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
578 struct omap_hwmod omap2xxx_gpio1_hwmod = {
580 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
581 .main_clk = "gpios_fck",
584 .module_offs = WKUP_MOD,
586 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
589 .class = &omap2xxx_gpio_hwmod_class,
590 .dev_attr = &omap2xxx_gpio_dev_attr,
594 struct omap_hwmod omap2xxx_gpio2_hwmod = {
596 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
597 .main_clk = "gpios_fck",
600 .module_offs = WKUP_MOD,
602 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
605 .class = &omap2xxx_gpio_hwmod_class,
606 .dev_attr = &omap2xxx_gpio_dev_attr,
610 struct omap_hwmod omap2xxx_gpio3_hwmod = {
612 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
613 .main_clk = "gpios_fck",
616 .module_offs = WKUP_MOD,
618 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
621 .class = &omap2xxx_gpio_hwmod_class,
622 .dev_attr = &omap2xxx_gpio_dev_attr,
626 struct omap_hwmod omap2xxx_gpio4_hwmod = {
628 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
629 .main_clk = "gpios_fck",
632 .module_offs = WKUP_MOD,
634 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
637 .class = &omap2xxx_gpio_hwmod_class,
638 .dev_attr = &omap2xxx_gpio_dev_attr,
642 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
646 struct omap_hwmod omap2xxx_mcspi1_hwmod = {
648 .main_clk = "mcspi1_fck",
651 .module_offs = CORE_MOD,
653 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
656 .class = &omap2xxx_mcspi_class,
657 .dev_attr = &omap_mcspi1_dev_attr,
661 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
665 struct omap_hwmod omap2xxx_mcspi2_hwmod = {
667 .main_clk = "mcspi2_fck",
670 .module_offs = CORE_MOD,
672 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
675 .class = &omap2xxx_mcspi_class,
676 .dev_attr = &omap_mcspi2_dev_attr,
679 static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
683 struct omap_hwmod omap2xxx_counter_32k_hwmod = {
684 .name = "counter_32k",
685 .main_clk = "func_32k_ck",
688 .module_offs = WKUP_MOD,
690 .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
693 .class = &omap2xxx_counter_hwmod_class,
697 struct omap_hwmod omap2xxx_gpmc_hwmod = {
699 .class = &omap2xxx_gpmc_hwmod_class,
700 .main_clk = "gpmc_fck",
701 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
702 .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
705 .module_offs = CORE_MOD,
712 static struct omap_hwmod_class_sysconfig omap2_rng_sysc = {
716 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
717 SYSS_HAS_RESET_STATUS),
718 .sysc_fields = &omap_hwmod_sysc_type1,
721 static struct omap_hwmod_class omap2_rng_hwmod_class = {
723 .sysc = &omap2_rng_sysc,
726 struct omap_hwmod omap2xxx_rng_hwmod = {
731 .module_offs = CORE_MOD,
733 .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
737 * XXX The first read from the SYSSTATUS register of the RNG
738 * after the SYSCONFIG SOFTRESET bit is set triggers an
739 * imprecise external abort. It's unclear why this happens.
740 * Until this is analyzed, skip the IP block reset.
742 .flags = HWMOD_INIT_NO_RESET,
743 .class = &omap2_rng_hwmod_class,
748 static struct omap_hwmod_class_sysconfig omap2_sham_sysc = {
752 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
753 SYSS_HAS_RESET_STATUS),
754 .sysc_fields = &omap_hwmod_sysc_type1,
757 static struct omap_hwmod_class omap2xxx_sham_class = {
759 .sysc = &omap2_sham_sysc,
762 struct omap_hwmod omap2xxx_sham_hwmod = {
767 .module_offs = CORE_MOD,
769 .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT,
772 .class = &omap2xxx_sham_class,
777 static struct omap_hwmod_class_sysconfig omap2_aes_sysc = {
781 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
782 SYSS_HAS_RESET_STATUS),
783 .sysc_fields = &omap_hwmod_sysc_type1,
786 static struct omap_hwmod_class omap2xxx_aes_class = {
788 .sysc = &omap2_aes_sysc,
791 struct omap_hwmod omap2xxx_aes_hwmod = {
796 .module_offs = CORE_MOD,
798 .idlest_idle_bit = OMAP24XX_ST_AES_SHIFT,
801 .class = &omap2xxx_aes_class,