arch/arm/mach-omap2/omap_hwmod_2420_data.c

   1 /*
   2  * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
   3  *
   4  * Copyright (C) 2009-2010 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * XXX handle crossbar/shared link difference for L3?
  12  * XXX these should be marked initdata for multi-OMAP kernels
  13  */
  14 #include <plat/omap_hwmod.h>
  15 #include <mach/irqs.h>
  16 #include <plat/cpu.h>
  17 #include <plat/dma.h>
  18 #include <plat/serial.h>
  19 #include <plat/i2c.h>
  20 #include <plat/gpio.h>
  21 #include <plat/mcspi.h>
  22 #include <plat/dmtimer.h>
  23 #include <plat/l3_2xxx.h>
  24 #include <plat/l4_2xxx.h>
  25
  26 #include "omap_hwmod_common_data.h"
  27
  28 #include "cm-regbits-24xx.h"
  29 #include "prm-regbits-24xx.h"
  30 #include "wd_timer.h"
  31
  32 /*
  33  * OMAP2420 hardware module integration data
  34  *
  35  * ALl of the data in this section should be autogeneratable from the
  36  * TI hardware database or other technical documentation.  Data that
  37  * is driver-specific or driver-kernel integration-specific belongs
  38  * elsewhere.
  39  */
  40
  41 static struct omap_hwmod omap2420_mpu_hwmod;
  42 static struct omap_hwmod omap2420_iva_hwmod;
  43 static struct omap_hwmod omap2420_l3_main_hwmod;
  44 static struct omap_hwmod omap2420_l4_core_hwmod;
  45 static struct omap_hwmod omap2420_dss_core_hwmod;
  46 static struct omap_hwmod omap2420_dss_dispc_hwmod;
  47 static struct omap_hwmod omap2420_dss_rfbi_hwmod;
  48 static struct omap_hwmod omap2420_dss_venc_hwmod;
  49 static struct omap_hwmod omap2420_wd_timer2_hwmod;
  50 static struct omap_hwmod omap2420_gpio1_hwmod;
  51 static struct omap_hwmod omap2420_gpio2_hwmod;
  52 static struct omap_hwmod omap2420_gpio3_hwmod;
  53 static struct omap_hwmod omap2420_gpio4_hwmod;
  54 static struct omap_hwmod omap2420_dma_system_hwmod;
  55 static struct omap_hwmod omap2420_mcspi1_hwmod;
  56 static struct omap_hwmod omap2420_mcspi2_hwmod;
  57
  58 /* L3 -> L4_CORE interface */
  59 static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
  60         .master = &omap2420_l3_main_hwmod,
  61         .slave  = &omap2420_l4_core_hwmod,
  62         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  63 };
  64
  65 /* MPU -> L3 interface */
  66 static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = {
  67         .master = &omap2420_mpu_hwmod,
  68         .slave  = &omap2420_l3_main_hwmod,
  69         .user   = OCP_USER_MPU,
  70 };
  71
  72 /* Slave interfaces on the L3 interconnect */
  73 static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = {
  74         &omap2420_mpu__l3_main,
  75 };
  76
  77 /* DSS -> l3 */
  78 static struct omap_hwmod_ocp_if omap2420_dss__l3 = {
  79         .master         = &omap2420_dss_core_hwmod,
  80         .slave          = &omap2420_l3_main_hwmod,
  81         .fw = {
  82                 .omap2 = {
  83                         .l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
  84                         .flags  = OMAP_FIREWALL_L3,
  85                 }
  86         },
  87         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  88 };
  89
  90 /* Master interfaces on the L3 interconnect */
  91 static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = {
  92         &omap2420_l3_main__l4_core,
  93 };
  94
  95 /* L3 */
  96 static struct omap_hwmod omap2420_l3_main_hwmod = {
  97         .name           = "l3_main",
  98         .class          = &l3_hwmod_class,
  99         .masters        = omap2420_l3_main_masters,
 100         .masters_cnt    = ARRAY_SIZE(omap2420_l3_main_masters),
 101         .slaves         = omap2420_l3_main_slaves,
 102         .slaves_cnt     = ARRAY_SIZE(omap2420_l3_main_slaves),
 103         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 104         .flags          = HWMOD_NO_IDLEST,
 105 };
 106
 107 static struct omap_hwmod omap2420_l4_wkup_hwmod;
 108 static struct omap_hwmod omap2420_uart1_hwmod;
 109 static struct omap_hwmod omap2420_uart2_hwmod;
 110 static struct omap_hwmod omap2420_uart3_hwmod;
 111 static struct omap_hwmod omap2420_i2c1_hwmod;
 112 static struct omap_hwmod omap2420_i2c2_hwmod;
 113 static struct omap_hwmod omap2420_mcbsp1_hwmod;
 114 static struct omap_hwmod omap2420_mcbsp2_hwmod;
 115
 116 /* l4 core -> mcspi1 interface */
 117 static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = {
 118         {
 119                 .pa_start       = 0x48098000,
 120                 .pa_end         = 0x480980ff,
 121                 .flags          = ADDR_TYPE_RT,
 122         },
 123 };
 124
 125 static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
 126         .master         = &omap2420_l4_core_hwmod,
 127         .slave          = &omap2420_mcspi1_hwmod,
 128         .clk            = "mcspi1_ick",
 129         .addr           = omap2420_mcspi1_addr_space,
 130         .addr_cnt       = ARRAY_SIZE(omap2420_mcspi1_addr_space),
 131         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 132 };
 133
 134 /* l4 core -> mcspi2 interface */
 135 static struct omap_hwmod_addr_space omap2420_mcspi2_addr_space[] = {
 136         {
 137                 .pa_start       = 0x4809a000,
 138                 .pa_end         = 0x4809a0ff,
 139                 .flags          = ADDR_TYPE_RT,
 140         },
 141 };
 142
 143 static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
 144         .master         = &omap2420_l4_core_hwmod,
 145         .slave          = &omap2420_mcspi2_hwmod,
 146         .clk            = "mcspi2_ick",
 147         .addr           = omap2420_mcspi2_addr_space,
 148         .addr_cnt       = ARRAY_SIZE(omap2420_mcspi2_addr_space),
 149         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 150 };
 151
 152 /* L4_CORE -> L4_WKUP interface */
 153 static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
 154         .master = &omap2420_l4_core_hwmod,
 155         .slave  = &omap2420_l4_wkup_hwmod,
 156         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 157 };
 158
 159 /* L4 CORE -> UART1 interface */
 160 static struct omap_hwmod_addr_space omap2420_uart1_addr_space[] = {
 161         {
 162                 .pa_start       = OMAP2_UART1_BASE,
 163                 .pa_end         = OMAP2_UART1_BASE + SZ_8K - 1,
 164                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 165         },
 166 };
 167
 168 static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
 169         .master         = &omap2420_l4_core_hwmod,
 170         .slave          = &omap2420_uart1_hwmod,
 171         .clk            = "uart1_ick",
 172         .addr           = omap2420_uart1_addr_space,
 173         .addr_cnt       = ARRAY_SIZE(omap2420_uart1_addr_space),
 174         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 175 };
 176
 177 /* L4 CORE -> UART2 interface */
 178 static struct omap_hwmod_addr_space omap2420_uart2_addr_space[] = {
 179         {
 180                 .pa_start       = OMAP2_UART2_BASE,
 181                 .pa_end         = OMAP2_UART2_BASE + SZ_1K - 1,
 182                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 183         },
 184 };
 185
 186 static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
 187         .master         = &omap2420_l4_core_hwmod,
 188         .slave          = &omap2420_uart2_hwmod,
 189         .clk            = "uart2_ick",
 190         .addr           = omap2420_uart2_addr_space,
 191         .addr_cnt       = ARRAY_SIZE(omap2420_uart2_addr_space),
 192         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 193 };
 194
 195 /* L4 PER -> UART3 interface */
 196 static struct omap_hwmod_addr_space omap2420_uart3_addr_space[] = {
 197         {
 198                 .pa_start       = OMAP2_UART3_BASE,
 199                 .pa_end         = OMAP2_UART3_BASE + SZ_1K - 1,
 200                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 201         },
 202 };
 203
 204 static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
 205         .master         = &omap2420_l4_core_hwmod,
 206         .slave          = &omap2420_uart3_hwmod,
 207         .clk            = "uart3_ick",
 208         .addr           = omap2420_uart3_addr_space,
 209         .addr_cnt       = ARRAY_SIZE(omap2420_uart3_addr_space),
 210         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 211 };
 212
 213 /* I2C IP block address space length (in bytes) */
 214 #define OMAP2_I2C_AS_LEN                128
 215
 216 /* L4 CORE -> I2C1 interface */
 217 static struct omap_hwmod_addr_space omap2420_i2c1_addr_space[] = {
 218         {
 219                 .pa_start       = 0x48070000,
 220                 .pa_end         = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
 221                 .flags          = ADDR_TYPE_RT,
 222         },
 223 };
 224
 225 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
 226         .master         = &omap2420_l4_core_hwmod,
 227         .slave          = &omap2420_i2c1_hwmod,
 228         .clk            = "i2c1_ick",
 229         .addr           = omap2420_i2c1_addr_space,
 230         .addr_cnt       = ARRAY_SIZE(omap2420_i2c1_addr_space),
 231         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 232 };
 233
 234 /* L4 CORE -> I2C2 interface */
 235 static struct omap_hwmod_addr_space omap2420_i2c2_addr_space[] = {
 236         {
 237                 .pa_start       = 0x48072000,
 238                 .pa_end         = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
 239                 .flags          = ADDR_TYPE_RT,
 240         },
 241 };
 242
 243 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
 244         .master         = &omap2420_l4_core_hwmod,
 245         .slave          = &omap2420_i2c2_hwmod,
 246         .clk            = "i2c2_ick",
 247         .addr           = omap2420_i2c2_addr_space,
 248         .addr_cnt       = ARRAY_SIZE(omap2420_i2c2_addr_space),
 249         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 250 };
 251
 252 /* Slave interfaces on the L4_CORE interconnect */
 253 static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
 254         &omap2420_l3_main__l4_core,
 255 };
 256
 257 /* Master interfaces on the L4_CORE interconnect */
 258 static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = {
 259         &omap2420_l4_core__l4_wkup,
 260         &omap2_l4_core__uart1,
 261         &omap2_l4_core__uart2,
 262         &omap2_l4_core__uart3,
 263         &omap2420_l4_core__i2c1,
 264         &omap2420_l4_core__i2c2
 265 };
 266
 267 /* L4 CORE */
 268 static struct omap_hwmod omap2420_l4_core_hwmod = {
 269         .name           = "l4_core",
 270         .class          = &l4_hwmod_class,
 271         .masters        = omap2420_l4_core_masters,
 272         .masters_cnt    = ARRAY_SIZE(omap2420_l4_core_masters),
 273         .slaves         = omap2420_l4_core_slaves,
 274         .slaves_cnt     = ARRAY_SIZE(omap2420_l4_core_slaves),
 275         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 276         .flags          = HWMOD_NO_IDLEST,
 277 };
 278
 279 /* Slave interfaces on the L4_WKUP interconnect */
 280 static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = {
 281         &omap2420_l4_core__l4_wkup,
 282 };
 283
 284 /* Master interfaces on the L4_WKUP interconnect */
 285 static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = {
 286 };
 287
 288 /* L4 WKUP */
 289 static struct omap_hwmod omap2420_l4_wkup_hwmod = {
 290         .name           = "l4_wkup",
 291         .class          = &l4_hwmod_class,
 292         .masters        = omap2420_l4_wkup_masters,
 293         .masters_cnt    = ARRAY_SIZE(omap2420_l4_wkup_masters),
 294         .slaves         = omap2420_l4_wkup_slaves,
 295         .slaves_cnt     = ARRAY_SIZE(omap2420_l4_wkup_slaves),
 296         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 297         .flags          = HWMOD_NO_IDLEST,
 298 };
 299
 300 /* Master interfaces on the MPU device */
 301 static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = {
 302         &omap2420_mpu__l3_main,
 303 };
 304
 305 /* MPU */
 306 static struct omap_hwmod omap2420_mpu_hwmod = {
 307         .name           = "mpu",
 308         .class          = &mpu_hwmod_class,
 309         .main_clk       = "mpu_ck",
 310         .masters        = omap2420_mpu_masters,
 311         .masters_cnt    = ARRAY_SIZE(omap2420_mpu_masters),
 312         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 313 };
 314
 315 /*
 316  * IVA1 interface data
 317  */
 318
 319 /* IVA <- L3 interface */
 320 static struct omap_hwmod_ocp_if omap2420_l3__iva = {
 321         .master         = &omap2420_l3_main_hwmod,
 322         .slave          = &omap2420_iva_hwmod,
 323         .clk            = "iva1_ifck",
 324         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 325 };
 326
 327 static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = {
 328         &omap2420_l3__iva,
 329 };
 330
 331 /*
 332  * IVA2 (IVA2)
 333  */
 334
 335 static struct omap_hwmod omap2420_iva_hwmod = {
 336         .name           = "iva",
 337         .class          = &iva_hwmod_class,
 338         .masters        = omap2420_iva_masters,
 339         .masters_cnt    = ARRAY_SIZE(omap2420_iva_masters),
 340         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 341 };
 342
 343 /* Timer Common */
 344 static struct omap_hwmod_class_sysconfig omap2420_timer_sysc = {
 345         .rev_offs       = 0x0000,
 346         .sysc_offs      = 0x0010,
 347         .syss_offs      = 0x0014,
 348         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 349                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 350                            SYSC_HAS_AUTOIDLE),
 351         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 352         .sysc_fields    = &omap_hwmod_sysc_type1,
 353 };
 354
 355 static struct omap_hwmod_class omap2420_timer_hwmod_class = {
 356         .name = "timer",
 357         .sysc = &omap2420_timer_sysc,
 358         .rev = OMAP_TIMER_IP_VERSION_1,
 359 };
 360
 361 /* timer1 */
 362 static struct omap_hwmod omap2420_timer1_hwmod;
 363 static struct omap_hwmod_irq_info omap2420_timer1_mpu_irqs[] = {
 364         { .irq = 37, },
 365 };
 366
 367 static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
 368         {
 369                 .pa_start       = 0x48028000,
 370                 .pa_end         = 0x48028000 + SZ_1K - 1,
 371                 .flags          = ADDR_TYPE_RT
 372         },
 373 };
 374
 375 /* l4_wkup -> timer1 */
 376 static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
 377         .master         = &omap2420_l4_wkup_hwmod,
 378         .slave          = &omap2420_timer1_hwmod,
 379         .clk            = "gpt1_ick",
 380         .addr           = omap2420_timer1_addrs,
 381         .addr_cnt       = ARRAY_SIZE(omap2420_timer1_addrs),
 382         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 383 };
 384
 385 /* timer1 slave port */
 386 static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = {
 387         &omap2420_l4_wkup__timer1,
 388 };
 389
 390 /* timer1 hwmod */
 391 static struct omap_hwmod omap2420_timer1_hwmod = {
 392         .name           = "timer1",
 393         .mpu_irqs       = omap2420_timer1_mpu_irqs,
 394         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer1_mpu_irqs),
 395         .main_clk       = "gpt1_fck",
 396         .prcm           = {
 397                 .omap2 = {
 398                         .prcm_reg_id = 1,
 399                         .module_bit = OMAP24XX_EN_GPT1_SHIFT,
 400                         .module_offs = WKUP_MOD,
 401                         .idlest_reg_id = 1,
 402                         .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
 403                 },
 404         },
 405         .slaves         = omap2420_timer1_slaves,
 406         .slaves_cnt     = ARRAY_SIZE(omap2420_timer1_slaves),
 407         .class          = &omap2420_timer_hwmod_class,
 408         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 409 };
 410
 411 /* timer2 */
 412 static struct omap_hwmod omap2420_timer2_hwmod;
 413 static struct omap_hwmod_irq_info omap2420_timer2_mpu_irqs[] = {
 414         { .irq = 38, },
 415 };
 416
 417 static struct omap_hwmod_addr_space omap2420_timer2_addrs[] = {
 418         {
 419                 .pa_start       = 0x4802a000,
 420                 .pa_end         = 0x4802a000 + SZ_1K - 1,
 421                 .flags          = ADDR_TYPE_RT
 422         },
 423 };
 424
 425 /* l4_core -> timer2 */
 426 static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
 427         .master         = &omap2420_l4_core_hwmod,
 428         .slave          = &omap2420_timer2_hwmod,
 429         .clk            = "gpt2_ick",
 430         .addr           = omap2420_timer2_addrs,
 431         .addr_cnt       = ARRAY_SIZE(omap2420_timer2_addrs),
 432         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 433 };
 434
 435 /* timer2 slave port */
 436 static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = {
 437         &omap2420_l4_core__timer2,
 438 };
 439
 440 /* timer2 hwmod */
 441 static struct omap_hwmod omap2420_timer2_hwmod = {
 442         .name           = "timer2",
 443         .mpu_irqs       = omap2420_timer2_mpu_irqs,
 444         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer2_mpu_irqs),
 445         .main_clk       = "gpt2_fck",
 446         .prcm           = {
 447                 .omap2 = {
 448                         .prcm_reg_id = 1,
 449                         .module_bit = OMAP24XX_EN_GPT2_SHIFT,
 450                         .module_offs = CORE_MOD,
 451                         .idlest_reg_id = 1,
 452                         .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
 453                 },
 454         },
 455         .slaves         = omap2420_timer2_slaves,
 456         .slaves_cnt     = ARRAY_SIZE(omap2420_timer2_slaves),
 457         .class          = &omap2420_timer_hwmod_class,
 458         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 459 };
 460
 461 /* timer3 */
 462 static struct omap_hwmod omap2420_timer3_hwmod;
 463 static struct omap_hwmod_irq_info omap2420_timer3_mpu_irqs[] = {
 464         { .irq = 39, },
 465 };
 466
 467 static struct omap_hwmod_addr_space omap2420_timer3_addrs[] = {
 468         {
 469                 .pa_start       = 0x48078000,
 470                 .pa_end         = 0x48078000 + SZ_1K - 1,
 471                 .flags          = ADDR_TYPE_RT
 472         },
 473 };
 474
 475 /* l4_core -> timer3 */
 476 static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
 477         .master         = &omap2420_l4_core_hwmod,
 478         .slave          = &omap2420_timer3_hwmod,
 479         .clk            = "gpt3_ick",
 480         .addr           = omap2420_timer3_addrs,
 481         .addr_cnt       = ARRAY_SIZE(omap2420_timer3_addrs),
 482         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 483 };
 484
 485 /* timer3 slave port */
 486 static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = {
 487         &omap2420_l4_core__timer3,
 488 };
 489
 490 /* timer3 hwmod */
 491 static struct omap_hwmod omap2420_timer3_hwmod = {
 492         .name           = "timer3",
 493         .mpu_irqs       = omap2420_timer3_mpu_irqs,
 494         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer3_mpu_irqs),
 495         .main_clk       = "gpt3_fck",
 496         .prcm           = {
 497                 .omap2 = {
 498                         .prcm_reg_id = 1,
 499                         .module_bit = OMAP24XX_EN_GPT3_SHIFT,
 500                         .module_offs = CORE_MOD,
 501                         .idlest_reg_id = 1,
 502                         .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
 503                 },
 504         },
 505         .slaves         = omap2420_timer3_slaves,
 506         .slaves_cnt     = ARRAY_SIZE(omap2420_timer3_slaves),
 507         .class          = &omap2420_timer_hwmod_class,
 508         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 509 };
 510
 511 /* timer4 */
 512 static struct omap_hwmod omap2420_timer4_hwmod;
 513 static struct omap_hwmod_irq_info omap2420_timer4_mpu_irqs[] = {
 514         { .irq = 40, },
 515 };
 516
 517 static struct omap_hwmod_addr_space omap2420_timer4_addrs[] = {
 518         {
 519                 .pa_start       = 0x4807a000,
 520                 .pa_end         = 0x4807a000 + SZ_1K - 1,
 521                 .flags          = ADDR_TYPE_RT
 522         },
 523 };
 524
 525 /* l4_core -> timer4 */
 526 static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
 527         .master         = &omap2420_l4_core_hwmod,
 528         .slave          = &omap2420_timer4_hwmod,
 529         .clk            = "gpt4_ick",
 530         .addr           = omap2420_timer4_addrs,
 531         .addr_cnt       = ARRAY_SIZE(omap2420_timer4_addrs),
 532         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 533 };
 534
 535 /* timer4 slave port */
 536 static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = {
 537         &omap2420_l4_core__timer4,
 538 };
 539
 540 /* timer4 hwmod */
 541 static struct omap_hwmod omap2420_timer4_hwmod = {
 542         .name           = "timer4",
 543         .mpu_irqs       = omap2420_timer4_mpu_irqs,
 544         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer4_mpu_irqs),
 545         .main_clk       = "gpt4_fck",
 546         .prcm           = {
 547                 .omap2 = {
 548                         .prcm_reg_id = 1,
 549                         .module_bit = OMAP24XX_EN_GPT4_SHIFT,
 550                         .module_offs = CORE_MOD,
 551                         .idlest_reg_id = 1,
 552                         .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
 553                 },
 554         },
 555         .slaves         = omap2420_timer4_slaves,
 556         .slaves_cnt     = ARRAY_SIZE(omap2420_timer4_slaves),
 557         .class          = &omap2420_timer_hwmod_class,
 558         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 559 };
 560
 561 /* timer5 */
 562 static struct omap_hwmod omap2420_timer5_hwmod;
 563 static struct omap_hwmod_irq_info omap2420_timer5_mpu_irqs[] = {
 564         { .irq = 41, },
 565 };
 566
 567 static struct omap_hwmod_addr_space omap2420_timer5_addrs[] = {
 568         {
 569                 .pa_start       = 0x4807c000,
 570                 .pa_end         = 0x4807c000 + SZ_1K - 1,
 571                 .flags          = ADDR_TYPE_RT
 572         },
 573 };
 574
 575 /* l4_core -> timer5 */
 576 static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
 577         .master         = &omap2420_l4_core_hwmod,
 578         .slave          = &omap2420_timer5_hwmod,
 579         .clk            = "gpt5_ick",
 580         .addr           = omap2420_timer5_addrs,
 581         .addr_cnt       = ARRAY_SIZE(omap2420_timer5_addrs),
 582         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 583 };
 584
 585 /* timer5 slave port */
 586 static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = {
 587         &omap2420_l4_core__timer5,
 588 };
 589
 590 /* timer5 hwmod */
 591 static struct omap_hwmod omap2420_timer5_hwmod = {
 592         .name           = "timer5",
 593         .mpu_irqs       = omap2420_timer5_mpu_irqs,
 594         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer5_mpu_irqs),
 595         .main_clk       = "gpt5_fck",
 596         .prcm           = {
 597                 .omap2 = {
 598                         .prcm_reg_id = 1,
 599                         .module_bit = OMAP24XX_EN_GPT5_SHIFT,
 600                         .module_offs = CORE_MOD,
 601                         .idlest_reg_id = 1,
 602                         .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
 603                 },
 604         },
 605         .slaves         = omap2420_timer5_slaves,
 606         .slaves_cnt     = ARRAY_SIZE(omap2420_timer5_slaves),
 607         .class          = &omap2420_timer_hwmod_class,
 608         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 609 };
 610
 611
 612 /* timer6 */
 613 static struct omap_hwmod omap2420_timer6_hwmod;
 614 static struct omap_hwmod_irq_info omap2420_timer6_mpu_irqs[] = {
 615         { .irq = 42, },
 616 };
 617
 618 static struct omap_hwmod_addr_space omap2420_timer6_addrs[] = {
 619         {
 620                 .pa_start       = 0x4807e000,
 621                 .pa_end         = 0x4807e000 + SZ_1K - 1,
 622                 .flags          = ADDR_TYPE_RT
 623         },
 624 };
 625
 626 /* l4_core -> timer6 */
 627 static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
 628         .master         = &omap2420_l4_core_hwmod,
 629         .slave          = &omap2420_timer6_hwmod,
 630         .clk            = "gpt6_ick",
 631         .addr           = omap2420_timer6_addrs,
 632         .addr_cnt       = ARRAY_SIZE(omap2420_timer6_addrs),
 633         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 634 };
 635
 636 /* timer6 slave port */
 637 static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = {
 638         &omap2420_l4_core__timer6,
 639 };
 640
 641 /* timer6 hwmod */
 642 static struct omap_hwmod omap2420_timer6_hwmod = {
 643         .name           = "timer6",
 644         .mpu_irqs       = omap2420_timer6_mpu_irqs,
 645         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer6_mpu_irqs),
 646         .main_clk       = "gpt6_fck",
 647         .prcm           = {
 648                 .omap2 = {
 649                         .prcm_reg_id = 1,
 650                         .module_bit = OMAP24XX_EN_GPT6_SHIFT,
 651                         .module_offs = CORE_MOD,
 652                         .idlest_reg_id = 1,
 653                         .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
 654                 },
 655         },
 656         .slaves         = omap2420_timer6_slaves,
 657         .slaves_cnt     = ARRAY_SIZE(omap2420_timer6_slaves),
 658         .class          = &omap2420_timer_hwmod_class,
 659         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 660 };
 661
 662 /* timer7 */
 663 static struct omap_hwmod omap2420_timer7_hwmod;
 664 static struct omap_hwmod_irq_info omap2420_timer7_mpu_irqs[] = {
 665         { .irq = 43, },
 666 };
 667
 668 static struct omap_hwmod_addr_space omap2420_timer7_addrs[] = {
 669         {
 670                 .pa_start       = 0x48080000,
 671                 .pa_end         = 0x48080000 + SZ_1K - 1,
 672                 .flags          = ADDR_TYPE_RT
 673         },
 674 };
 675
 676 /* l4_core -> timer7 */
 677 static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
 678         .master         = &omap2420_l4_core_hwmod,
 679         .slave          = &omap2420_timer7_hwmod,
 680         .clk            = "gpt7_ick",
 681         .addr           = omap2420_timer7_addrs,
 682         .addr_cnt       = ARRAY_SIZE(omap2420_timer7_addrs),
 683         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 684 };
 685
 686 /* timer7 slave port */
 687 static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = {
 688         &omap2420_l4_core__timer7,
 689 };
 690
 691 /* timer7 hwmod */
 692 static struct omap_hwmod omap2420_timer7_hwmod = {
 693         .name           = "timer7",
 694         .mpu_irqs       = omap2420_timer7_mpu_irqs,
 695         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer7_mpu_irqs),
 696         .main_clk       = "gpt7_fck",
 697         .prcm           = {
 698                 .omap2 = {
 699                         .prcm_reg_id = 1,
 700                         .module_bit = OMAP24XX_EN_GPT7_SHIFT,
 701                         .module_offs = CORE_MOD,
 702                         .idlest_reg_id = 1,
 703                         .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
 704                 },
 705         },
 706         .slaves         = omap2420_timer7_slaves,
 707         .slaves_cnt     = ARRAY_SIZE(omap2420_timer7_slaves),
 708         .class          = &omap2420_timer_hwmod_class,
 709         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 710 };
 711
 712 /* timer8 */
 713 static struct omap_hwmod omap2420_timer8_hwmod;
 714 static struct omap_hwmod_irq_info omap2420_timer8_mpu_irqs[] = {
 715         { .irq = 44, },
 716 };
 717
 718 static struct omap_hwmod_addr_space omap2420_timer8_addrs[] = {
 719         {
 720                 .pa_start       = 0x48082000,
 721                 .pa_end         = 0x48082000 + SZ_1K - 1,
 722                 .flags          = ADDR_TYPE_RT
 723         },
 724 };
 725
 726 /* l4_core -> timer8 */
 727 static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
 728         .master         = &omap2420_l4_core_hwmod,
 729         .slave          = &omap2420_timer8_hwmod,
 730         .clk            = "gpt8_ick",
 731         .addr           = omap2420_timer8_addrs,
 732         .addr_cnt       = ARRAY_SIZE(omap2420_timer8_addrs),
 733         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 734 };
 735
 736 /* timer8 slave port */
 737 static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = {
 738         &omap2420_l4_core__timer8,
 739 };
 740
 741 /* timer8 hwmod */
 742 static struct omap_hwmod omap2420_timer8_hwmod = {
 743         .name           = "timer8",
 744         .mpu_irqs       = omap2420_timer8_mpu_irqs,
 745         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer8_mpu_irqs),
 746         .main_clk       = "gpt8_fck",
 747         .prcm           = {
 748                 .omap2 = {
 749                         .prcm_reg_id = 1,
 750                         .module_bit = OMAP24XX_EN_GPT8_SHIFT,
 751                         .module_offs = CORE_MOD,
 752                         .idlest_reg_id = 1,
 753                         .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
 754                 },
 755         },
 756         .slaves         = omap2420_timer8_slaves,
 757         .slaves_cnt     = ARRAY_SIZE(omap2420_timer8_slaves),
 758         .class          = &omap2420_timer_hwmod_class,
 759         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 760 };
 761
 762 /* timer9 */
 763 static struct omap_hwmod omap2420_timer9_hwmod;
 764 static struct omap_hwmod_irq_info omap2420_timer9_mpu_irqs[] = {
 765         { .irq = 45, },
 766 };
 767
 768 static struct omap_hwmod_addr_space omap2420_timer9_addrs[] = {
 769         {
 770                 .pa_start       = 0x48084000,
 771                 .pa_end         = 0x48084000 + SZ_1K - 1,
 772                 .flags          = ADDR_TYPE_RT
 773         },
 774 };
 775
 776 /* l4_core -> timer9 */
 777 static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
 778         .master         = &omap2420_l4_core_hwmod,
 779         .slave          = &omap2420_timer9_hwmod,
 780         .clk            = "gpt9_ick",
 781         .addr           = omap2420_timer9_addrs,
 782         .addr_cnt       = ARRAY_SIZE(omap2420_timer9_addrs),
 783         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 784 };
 785
 786 /* timer9 slave port */
 787 static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = {
 788         &omap2420_l4_core__timer9,
 789 };
 790
 791 /* timer9 hwmod */
 792 static struct omap_hwmod omap2420_timer9_hwmod = {
 793         .name           = "timer9",
 794         .mpu_irqs       = omap2420_timer9_mpu_irqs,
 795         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer9_mpu_irqs),
 796         .main_clk       = "gpt9_fck",
 797         .prcm           = {
 798                 .omap2 = {
 799                         .prcm_reg_id = 1,
 800                         .module_bit = OMAP24XX_EN_GPT9_SHIFT,
 801                         .module_offs = CORE_MOD,
 802                         .idlest_reg_id = 1,
 803                         .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
 804                 },
 805         },
 806         .slaves         = omap2420_timer9_slaves,
 807         .slaves_cnt     = ARRAY_SIZE(omap2420_timer9_slaves),
 808         .class          = &omap2420_timer_hwmod_class,
 809         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 810 };
 811
 812 /* timer10 */
 813 static struct omap_hwmod omap2420_timer10_hwmod;
 814 static struct omap_hwmod_irq_info omap2420_timer10_mpu_irqs[] = {
 815         { .irq = 46, },
 816 };
 817
 818 static struct omap_hwmod_addr_space omap2420_timer10_addrs[] = {
 819         {
 820                 .pa_start       = 0x48086000,
 821                 .pa_end         = 0x48086000 + SZ_1K - 1,
 822                 .flags          = ADDR_TYPE_RT
 823         },
 824 };
 825
 826 /* l4_core -> timer10 */
 827 static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
 828         .master         = &omap2420_l4_core_hwmod,
 829         .slave          = &omap2420_timer10_hwmod,
 830         .clk            = "gpt10_ick",
 831         .addr           = omap2420_timer10_addrs,
 832         .addr_cnt       = ARRAY_SIZE(omap2420_timer10_addrs),
 833         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 834 };
 835
 836 /* timer10 slave port */
 837 static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = {
 838         &omap2420_l4_core__timer10,
 839 };
 840
 841 /* timer10 hwmod */
 842 static struct omap_hwmod omap2420_timer10_hwmod = {
 843         .name           = "timer10",
 844         .mpu_irqs       = omap2420_timer10_mpu_irqs,
 845         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer10_mpu_irqs),
 846         .main_clk       = "gpt10_fck",
 847         .prcm           = {
 848                 .omap2 = {
 849                         .prcm_reg_id = 1,
 850                         .module_bit = OMAP24XX_EN_GPT10_SHIFT,
 851                         .module_offs = CORE_MOD,
 852                         .idlest_reg_id = 1,
 853                         .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
 854                 },
 855         },
 856         .slaves         = omap2420_timer10_slaves,
 857         .slaves_cnt     = ARRAY_SIZE(omap2420_timer10_slaves),
 858         .class          = &omap2420_timer_hwmod_class,
 859         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 860 };
 861
 862 /* timer11 */
 863 static struct omap_hwmod omap2420_timer11_hwmod;
 864 static struct omap_hwmod_irq_info omap2420_timer11_mpu_irqs[] = {
 865         { .irq = 47, },
 866 };
 867
 868 static struct omap_hwmod_addr_space omap2420_timer11_addrs[] = {
 869         {
 870                 .pa_start       = 0x48088000,
 871                 .pa_end         = 0x48088000 + SZ_1K - 1,
 872                 .flags          = ADDR_TYPE_RT
 873         },
 874 };
 875
 876 /* l4_core -> timer11 */
 877 static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
 878         .master         = &omap2420_l4_core_hwmod,
 879         .slave          = &omap2420_timer11_hwmod,
 880         .clk            = "gpt11_ick",
 881         .addr           = omap2420_timer11_addrs,
 882         .addr_cnt       = ARRAY_SIZE(omap2420_timer11_addrs),
 883         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 884 };
 885
 886 /* timer11 slave port */
 887 static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = {
 888         &omap2420_l4_core__timer11,
 889 };
 890
 891 /* timer11 hwmod */
 892 static struct omap_hwmod omap2420_timer11_hwmod = {
 893         .name           = "timer11",
 894         .mpu_irqs       = omap2420_timer11_mpu_irqs,
 895         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer11_mpu_irqs),
 896         .main_clk       = "gpt11_fck",
 897         .prcm           = {
 898                 .omap2 = {
 899                         .prcm_reg_id = 1,
 900                         .module_bit = OMAP24XX_EN_GPT11_SHIFT,
 901                         .module_offs = CORE_MOD,
 902                         .idlest_reg_id = 1,
 903                         .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
 904                 },
 905         },
 906         .slaves         = omap2420_timer11_slaves,
 907         .slaves_cnt     = ARRAY_SIZE(omap2420_timer11_slaves),
 908         .class          = &omap2420_timer_hwmod_class,
 909         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 910 };
 911
 912 /* timer12 */
 913 static struct omap_hwmod omap2420_timer12_hwmod;
 914 static struct omap_hwmod_irq_info omap2420_timer12_mpu_irqs[] = {
 915         { .irq = 48, },
 916 };
 917
 918 static struct omap_hwmod_addr_space omap2420_timer12_addrs[] = {
 919         {
 920                 .pa_start       = 0x4808a000,
 921                 .pa_end         = 0x4808a000 + SZ_1K - 1,
 922                 .flags          = ADDR_TYPE_RT
 923         },
 924 };
 925
 926 /* l4_core -> timer12 */
 927 static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = {
 928         .master         = &omap2420_l4_core_hwmod,
 929         .slave          = &omap2420_timer12_hwmod,
 930         .clk            = "gpt12_ick",
 931         .addr           = omap2420_timer12_addrs,
 932         .addr_cnt       = ARRAY_SIZE(omap2420_timer12_addrs),
 933         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 934 };
 935
 936 /* timer12 slave port */
 937 static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = {
 938         &omap2420_l4_core__timer12,
 939 };
 940
 941 /* timer12 hwmod */
 942 static struct omap_hwmod omap2420_timer12_hwmod = {
 943         .name           = "timer12",
 944         .mpu_irqs       = omap2420_timer12_mpu_irqs,
 945         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer12_mpu_irqs),
 946         .main_clk       = "gpt12_fck",
 947         .prcm           = {
 948                 .omap2 = {
 949                         .prcm_reg_id = 1,
 950                         .module_bit = OMAP24XX_EN_GPT12_SHIFT,
 951                         .module_offs = CORE_MOD,
 952                         .idlest_reg_id = 1,
 953                         .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
 954                 },
 955         },
 956         .slaves         = omap2420_timer12_slaves,
 957         .slaves_cnt     = ARRAY_SIZE(omap2420_timer12_slaves),
 958         .class          = &omap2420_timer_hwmod_class,
 959         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 960 };
 961
 962 /* l4_wkup -> wd_timer2 */
 963 static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
 964         {
 965                 .pa_start       = 0x48022000,
 966                 .pa_end         = 0x4802207f,
 967                 .flags          = ADDR_TYPE_RT
 968         },
 969 };
 970
 971 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
 972         .master         = &omap2420_l4_wkup_hwmod,
 973         .slave          = &omap2420_wd_timer2_hwmod,
 974         .clk            = "mpu_wdt_ick",
 975         .addr           = omap2420_wd_timer2_addrs,
 976         .addr_cnt       = ARRAY_SIZE(omap2420_wd_timer2_addrs),
 977         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 978 };
 979
 980 /*
 981  * 'wd_timer' class
 982  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 983  * overflow condition
 984  */
 985
 986 static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = {
 987         .rev_offs       = 0x0000,
 988         .sysc_offs      = 0x0010,
 989         .syss_offs      = 0x0014,
 990         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
 991                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 992         .sysc_fields    = &omap_hwmod_sysc_type1,
 993 };
 994
 995 static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = {
 996         .name           = "wd_timer",
 997         .sysc           = &omap2420_wd_timer_sysc,
 998         .pre_shutdown   = &omap2_wd_timer_disable
 999 };
1000
1001 /* wd_timer2 */
1002 static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
1003         &omap2420_l4_wkup__wd_timer2,
1004 };
1005
1006 static struct omap_hwmod omap2420_wd_timer2_hwmod = {
1007         .name           = "wd_timer2",
1008         .class          = &omap2420_wd_timer_hwmod_class,
1009         .main_clk       = "mpu_wdt_fck",
1010         .prcm           = {
1011                 .omap2 = {
1012                         .prcm_reg_id = 1,
1013                         .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1014                         .module_offs = WKUP_MOD,
1015                         .idlest_reg_id = 1,
1016                         .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
1017                 },
1018         },
1019         .slaves         = omap2420_wd_timer2_slaves,
1020         .slaves_cnt     = ARRAY_SIZE(omap2420_wd_timer2_slaves),
1021         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1022 };
1023
1024 /* UART */
1025
1026 static struct omap_hwmod_class_sysconfig uart_sysc = {
1027         .rev_offs       = 0x50,
1028         .sysc_offs      = 0x54,
1029         .syss_offs      = 0x58,
1030         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
1031                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1032                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1033         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1034         .sysc_fields    = &omap_hwmod_sysc_type1,
1035 };
1036
1037 static struct omap_hwmod_class uart_class = {
1038         .name = "uart",
1039         .sysc = &uart_sysc,
1040 };
1041
1042 /* UART1 */
1043
1044 static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
1045         { .irq = INT_24XX_UART1_IRQ, },
1046 };
1047
1048 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
1049         { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
1050         { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
1051 };
1052
1053 static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
1054         &omap2_l4_core__uart1,
1055 };
1056
1057 static struct omap_hwmod omap2420_uart1_hwmod = {
1058         .name           = "uart1",
1059         .mpu_irqs       = uart1_mpu_irqs,
1060         .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
1061         .sdma_reqs      = uart1_sdma_reqs,
1062         .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
1063         .main_clk       = "uart1_fck",
1064         .prcm           = {
1065                 .omap2 = {
1066                         .module_offs = CORE_MOD,
1067                         .prcm_reg_id = 1,
1068                         .module_bit = OMAP24XX_EN_UART1_SHIFT,
1069                         .idlest_reg_id = 1,
1070                         .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
1071                 },
1072         },
1073         .slaves         = omap2420_uart1_slaves,
1074         .slaves_cnt     = ARRAY_SIZE(omap2420_uart1_slaves),
1075         .class          = &uart_class,
1076         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1077 };
1078
1079 /* UART2 */
1080
1081 static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
1082         { .irq = INT_24XX_UART2_IRQ, },
1083 };
1084
1085 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
1086         { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
1087         { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
1088 };
1089
1090 static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
1091         &omap2_l4_core__uart2,
1092 };
1093
1094 static struct omap_hwmod omap2420_uart2_hwmod = {
1095         .name           = "uart2",
1096         .mpu_irqs       = uart2_mpu_irqs,
1097         .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
1098         .sdma_reqs      = uart2_sdma_reqs,
1099         .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
1100         .main_clk       = "uart2_fck",
1101         .prcm           = {
1102                 .omap2 = {
1103                         .module_offs = CORE_MOD,
1104                         .prcm_reg_id = 1,
1105                         .module_bit = OMAP24XX_EN_UART2_SHIFT,
1106                         .idlest_reg_id = 1,
1107                         .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
1108                 },
1109         },
1110         .slaves         = omap2420_uart2_slaves,
1111         .slaves_cnt     = ARRAY_SIZE(omap2420_uart2_slaves),
1112         .class          = &uart_class,
1113         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1114 };
1115
1116 /* UART3 */
1117
1118 static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
1119         { .irq = INT_24XX_UART3_IRQ, },
1120 };
1121
1122 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
1123         { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
1124         { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
1125 };
1126
1127 static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
1128         &omap2_l4_core__uart3,
1129 };
1130
1131 static struct omap_hwmod omap2420_uart3_hwmod = {
1132         .name           = "uart3",
1133         .mpu_irqs       = uart3_mpu_irqs,
1134         .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
1135         .sdma_reqs      = uart3_sdma_reqs,
1136         .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
1137         .main_clk       = "uart3_fck",
1138         .prcm           = {
1139                 .omap2 = {
1140                         .module_offs = CORE_MOD,
1141                         .prcm_reg_id = 2,
1142                         .module_bit = OMAP24XX_EN_UART3_SHIFT,
1143                         .idlest_reg_id = 2,
1144                         .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
1145                 },
1146         },
1147         .slaves         = omap2420_uart3_slaves,
1148         .slaves_cnt     = ARRAY_SIZE(omap2420_uart3_slaves),
1149         .class          = &uart_class,
1150         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1151 };
1152
1153 /*
1154  * 'dss' class
1155  * display sub-system
1156  */
1157
1158 static struct omap_hwmod_class_sysconfig omap2420_dss_sysc = {
1159         .rev_offs       = 0x0000,
1160         .sysc_offs      = 0x0010,
1161         .syss_offs      = 0x0014,
1162         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1163         .sysc_fields    = &omap_hwmod_sysc_type1,
1164 };
1165
1166 static struct omap_hwmod_class omap2420_dss_hwmod_class = {
1167         .name = "dss",
1168         .sysc = &omap2420_dss_sysc,
1169 };
1170
1171 static struct omap_hwmod_dma_info omap2420_dss_sdma_chs[] = {
1172         { .name = "dispc", .dma_req = 5 },
1173 };
1174
1175 /* dss */
1176 /* dss master ports */
1177 static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = {
1178         &omap2420_dss__l3,
1179 };
1180
1181 static struct omap_hwmod_addr_space omap2420_dss_addrs[] = {
1182         {
1183                 .pa_start       = 0x48050000,
1184                 .pa_end         = 0x480503FF,
1185                 .flags          = ADDR_TYPE_RT
1186         },
1187 };
1188
1189 /* l4_core -> dss */
1190 static struct omap_hwmod_ocp_if omap2420_l4_core__dss = {
1191         .master         = &omap2420_l4_core_hwmod,
1192         .slave          = &omap2420_dss_core_hwmod,
1193         .clk            = "dss_ick",
1194         .addr           = omap2420_dss_addrs,
1195         .addr_cnt       = ARRAY_SIZE(omap2420_dss_addrs),
1196         .fw = {
1197                 .omap2 = {
1198                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
1199                         .flags  = OMAP_FIREWALL_L4,
1200                 }
1201         },
1202         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1203 };
1204
1205 /* dss slave ports */
1206 static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = {
1207         &omap2420_l4_core__dss,
1208 };
1209
1210 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1211         { .role = "tv_clk", .clk = "dss_54m_fck" },
1212         { .role = "sys_clk", .clk = "dss2_fck" },
1213 };
1214
1215 static struct omap_hwmod omap2420_dss_core_hwmod = {
1216         .name           = "dss_core",
1217         .class          = &omap2420_dss_hwmod_class,
1218         .main_clk       = "dss1_fck", /* instead of dss_fck */
1219         .sdma_reqs      = omap2420_dss_sdma_chs,
1220         .sdma_reqs_cnt  = ARRAY_SIZE(omap2420_dss_sdma_chs),
1221         .prcm           = {
1222                 .omap2 = {
1223                         .prcm_reg_id = 1,
1224                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1225                         .module_offs = CORE_MOD,
1226                         .idlest_reg_id = 1,
1227                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
1228                 },
1229         },
1230         .opt_clks       = dss_opt_clks,
1231         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1232         .slaves         = omap2420_dss_slaves,
1233         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_slaves),
1234         .masters        = omap2420_dss_masters,
1235         .masters_cnt    = ARRAY_SIZE(omap2420_dss_masters),
1236         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1237         .flags          = HWMOD_NO_IDLEST,
1238 };
1239
1240 /*
1241  * 'dispc' class
1242  * display controller
1243  */
1244
1245 static struct omap_hwmod_class_sysconfig omap2420_dispc_sysc = {
1246         .rev_offs       = 0x0000,
1247         .sysc_offs      = 0x0010,
1248         .syss_offs      = 0x0014,
1249         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
1250                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1251         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1252                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1253         .sysc_fields    = &omap_hwmod_sysc_type1,
1254 };
1255
1256 static struct omap_hwmod_class omap2420_dispc_hwmod_class = {
1257         .name = "dispc",
1258         .sysc = &omap2420_dispc_sysc,
1259 };
1260
1261 static struct omap_hwmod_irq_info omap2420_dispc_irqs[] = {
1262         { .irq = 25 },
1263 };
1264
1265 static struct omap_hwmod_addr_space omap2420_dss_dispc_addrs[] = {
1266         {
1267                 .pa_start       = 0x48050400,
1268                 .pa_end         = 0x480507FF,
1269                 .flags          = ADDR_TYPE_RT
1270         },
1271 };
1272
1273 /* l4_core -> dss_dispc */
1274 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
1275         .master         = &omap2420_l4_core_hwmod,
1276         .slave          = &omap2420_dss_dispc_hwmod,
1277         .clk            = "dss_ick",
1278         .addr           = omap2420_dss_dispc_addrs,
1279         .addr_cnt       = ARRAY_SIZE(omap2420_dss_dispc_addrs),
1280         .fw = {
1281                 .omap2 = {
1282                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
1283                         .flags  = OMAP_FIREWALL_L4,
1284                 }
1285         },
1286         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1287 };
1288
1289 /* dss_dispc slave ports */
1290 static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = {
1291         &omap2420_l4_core__dss_dispc,
1292 };
1293
1294 static struct omap_hwmod omap2420_dss_dispc_hwmod = {
1295         .name           = "dss_dispc",
1296         .class          = &omap2420_dispc_hwmod_class,
1297         .mpu_irqs       = omap2420_dispc_irqs,
1298         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_dispc_irqs),
1299         .main_clk       = "dss1_fck",
1300         .prcm           = {
1301                 .omap2 = {
1302                         .prcm_reg_id = 1,
1303                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1304                         .module_offs = CORE_MOD,
1305                         .idlest_reg_id = 1,
1306                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
1307                 },
1308         },
1309         .slaves         = omap2420_dss_dispc_slaves,
1310         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_dispc_slaves),
1311         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1312         .flags          = HWMOD_NO_IDLEST,
1313 };
1314
1315 /*
1316  * 'rfbi' class
1317  * remote frame buffer interface
1318  */
1319
1320 static struct omap_hwmod_class_sysconfig omap2420_rfbi_sysc = {
1321         .rev_offs       = 0x0000,
1322         .sysc_offs      = 0x0010,
1323         .syss_offs      = 0x0014,
1324         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1325                            SYSC_HAS_AUTOIDLE),
1326         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1327         .sysc_fields    = &omap_hwmod_sysc_type1,
1328 };
1329
1330 static struct omap_hwmod_class omap2420_rfbi_hwmod_class = {
1331         .name = "rfbi",
1332         .sysc = &omap2420_rfbi_sysc,
1333 };
1334
1335 static struct omap_hwmod_addr_space omap2420_dss_rfbi_addrs[] = {
1336         {
1337                 .pa_start       = 0x48050800,
1338                 .pa_end         = 0x48050BFF,
1339                 .flags          = ADDR_TYPE_RT
1340         },
1341 };
1342
1343 /* l4_core -> dss_rfbi */
1344 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {
1345         .master         = &omap2420_l4_core_hwmod,
1346         .slave          = &omap2420_dss_rfbi_hwmod,
1347         .clk            = "dss_ick",
1348         .addr           = omap2420_dss_rfbi_addrs,
1349         .addr_cnt       = ARRAY_SIZE(omap2420_dss_rfbi_addrs),
1350         .fw = {
1351                 .omap2 = {
1352                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
1353                         .flags  = OMAP_FIREWALL_L4,
1354                 }
1355         },
1356         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1357 };
1358
1359 /* dss_rfbi slave ports */
1360 static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
1361         &omap2420_l4_core__dss_rfbi,
1362 };
1363
1364 static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
1365         .name           = "dss_rfbi",
1366         .class          = &omap2420_rfbi_hwmod_class,
1367         .main_clk       = "dss1_fck",
1368         .prcm           = {
1369                 .omap2 = {
1370                         .prcm_reg_id = 1,
1371                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1372                         .module_offs = CORE_MOD,
1373                 },
1374         },
1375         .slaves         = omap2420_dss_rfbi_slaves,
1376         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_rfbi_slaves),
1377         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1378         .flags          = HWMOD_NO_IDLEST,
1379 };
1380
1381 /*
1382  * 'venc' class
1383  * video encoder
1384  */
1385
1386 static struct omap_hwmod_class omap2420_venc_hwmod_class = {
1387         .name = "venc",
1388 };
1389
1390 /* dss_venc */
1391 static struct omap_hwmod_addr_space omap2420_dss_venc_addrs[] = {
1392         {
1393                 .pa_start       = 0x48050C00,
1394                 .pa_end         = 0x48050FFF,
1395                 .flags          = ADDR_TYPE_RT
1396         },
1397 };
1398
1399 /* l4_core -> dss_venc */
1400 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
1401         .master         = &omap2420_l4_core_hwmod,
1402         .slave          = &omap2420_dss_venc_hwmod,
1403         .clk            = "dss_54m_fck",
1404         .addr           = omap2420_dss_venc_addrs,
1405         .addr_cnt       = ARRAY_SIZE(omap2420_dss_venc_addrs),
1406         .fw = {
1407                 .omap2 = {
1408                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
1409                         .flags  = OMAP_FIREWALL_L4,
1410                 }
1411         },
1412         .flags          = OCPIF_SWSUP_IDLE,
1413         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1414 };
1415
1416 /* dss_venc slave ports */
1417 static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
1418         &omap2420_l4_core__dss_venc,
1419 };
1420
1421 static struct omap_hwmod omap2420_dss_venc_hwmod = {
1422         .name           = "dss_venc",
1423         .class          = &omap2420_venc_hwmod_class,
1424         .main_clk       = "dss1_fck",
1425         .prcm           = {
1426                 .omap2 = {
1427                         .prcm_reg_id = 1,
1428                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1429                         .module_offs = CORE_MOD,
1430                 },
1431         },
1432         .slaves         = omap2420_dss_venc_slaves,
1433         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_venc_slaves),
1434         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1435         .flags          = HWMOD_NO_IDLEST,
1436 };
1437
1438 /* I2C common */
1439 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1440         .rev_offs       = 0x00,
1441         .sysc_offs      = 0x20,
1442         .syss_offs      = 0x10,
1443         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1444         .sysc_fields    = &omap_hwmod_sysc_type1,
1445 };
1446
1447 static struct omap_hwmod_class i2c_class = {
1448         .name           = "i2c",
1449         .sysc           = &i2c_sysc,
1450 };
1451
1452 static struct omap_i2c_dev_attr i2c_dev_attr;
1453
1454 /* I2C1 */
1455
1456 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1457         { .irq = INT_24XX_I2C1_IRQ, },
1458 };
1459
1460 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
1461         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
1462         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
1463 };
1464
1465 static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
1466         &omap2420_l4_core__i2c1,
1467 };
1468
1469 static struct omap_hwmod omap2420_i2c1_hwmod = {
1470         .name           = "i2c1",
1471         .mpu_irqs       = i2c1_mpu_irqs,
1472         .mpu_irqs_cnt   = ARRAY_SIZE(i2c1_mpu_irqs),
1473         .sdma_reqs      = i2c1_sdma_reqs,
1474         .sdma_reqs_cnt  = ARRAY_SIZE(i2c1_sdma_reqs),
1475         .main_clk       = "i2c1_fck",
1476         .prcm           = {
1477                 .omap2 = {
1478                         .module_offs = CORE_MOD,
1479                         .prcm_reg_id = 1,
1480                         .module_bit = OMAP2420_EN_I2C1_SHIFT,
1481                         .idlest_reg_id = 1,
1482                         .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
1483                 },
1484         },
1485         .slaves         = omap2420_i2c1_slaves,
1486         .slaves_cnt     = ARRAY_SIZE(omap2420_i2c1_slaves),
1487         .class          = &i2c_class,
1488         .dev_attr       = &i2c_dev_attr,
1489         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1490         .flags          = HWMOD_16BIT_REG,
1491 };
1492
1493 /* I2C2 */
1494
1495 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1496         { .irq = INT_24XX_I2C2_IRQ, },
1497 };
1498
1499 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
1500         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
1501         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
1502 };
1503
1504 static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
1505         &omap2420_l4_core__i2c2,
1506 };
1507
1508 static struct omap_hwmod omap2420_i2c2_hwmod = {
1509         .name           = "i2c2",
1510         .mpu_irqs       = i2c2_mpu_irqs,
1511         .mpu_irqs_cnt   = ARRAY_SIZE(i2c2_mpu_irqs),
1512         .sdma_reqs      = i2c2_sdma_reqs,
1513         .sdma_reqs_cnt  = ARRAY_SIZE(i2c2_sdma_reqs),
1514         .main_clk       = "i2c2_fck",
1515         .prcm           = {
1516                 .omap2 = {
1517                         .module_offs = CORE_MOD,
1518                         .prcm_reg_id = 1,
1519                         .module_bit = OMAP2420_EN_I2C2_SHIFT,
1520                         .idlest_reg_id = 1,
1521                         .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
1522                 },
1523         },
1524         .slaves         = omap2420_i2c2_slaves,
1525         .slaves_cnt     = ARRAY_SIZE(omap2420_i2c2_slaves),
1526         .class          = &i2c_class,
1527         .dev_attr       = &i2c_dev_attr,
1528         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1529         .flags          = HWMOD_16BIT_REG,
1530 };
1531
1532 /* l4_wkup -> gpio1 */
1533 static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
1534         {
1535                 .pa_start       = 0x48018000,
1536                 .pa_end         = 0x480181ff,
1537                 .flags          = ADDR_TYPE_RT
1538         },
1539 };
1540
1541 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
1542         .master         = &omap2420_l4_wkup_hwmod,
1543         .slave          = &omap2420_gpio1_hwmod,
1544         .clk            = "gpios_ick",
1545         .addr           = omap2420_gpio1_addr_space,
1546         .addr_cnt       = ARRAY_SIZE(omap2420_gpio1_addr_space),
1547         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1548 };
1549
1550 /* l4_wkup -> gpio2 */
1551 static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
1552         {
1553                 .pa_start       = 0x4801a000,
1554                 .pa_end         = 0x4801a1ff,
1555                 .flags          = ADDR_TYPE_RT
1556         },
1557 };
1558
1559 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
1560         .master         = &omap2420_l4_wkup_hwmod,
1561         .slave          = &omap2420_gpio2_hwmod,
1562         .clk            = "gpios_ick",
1563         .addr           = omap2420_gpio2_addr_space,
1564         .addr_cnt       = ARRAY_SIZE(omap2420_gpio2_addr_space),
1565         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1566 };
1567
1568 /* l4_wkup -> gpio3 */
1569 static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
1570         {
1571                 .pa_start       = 0x4801c000,
1572                 .pa_end         = 0x4801c1ff,
1573                 .flags          = ADDR_TYPE_RT
1574         },
1575 };
1576
1577 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
1578         .master         = &omap2420_l4_wkup_hwmod,
1579         .slave          = &omap2420_gpio3_hwmod,
1580         .clk            = "gpios_ick",
1581         .addr           = omap2420_gpio3_addr_space,
1582         .addr_cnt       = ARRAY_SIZE(omap2420_gpio3_addr_space),
1583         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1584 };
1585
1586 /* l4_wkup -> gpio4 */
1587 static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
1588         {
1589                 .pa_start       = 0x4801e000,
1590                 .pa_end         = 0x4801e1ff,
1591                 .flags          = ADDR_TYPE_RT
1592         },
1593 };
1594
1595 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
1596         .master         = &omap2420_l4_wkup_hwmod,
1597         .slave          = &omap2420_gpio4_hwmod,
1598         .clk            = "gpios_ick",
1599         .addr           = omap2420_gpio4_addr_space,
1600         .addr_cnt       = ARRAY_SIZE(omap2420_gpio4_addr_space),
1601         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1602 };
1603
1604 /* gpio dev_attr */
1605 static struct omap_gpio_dev_attr gpio_dev_attr = {
1606         .bank_width = 32,
1607         .dbck_flag = false,
1608 };
1609
1610 static struct omap_hwmod_class_sysconfig omap242x_gpio_sysc = {
1611         .rev_offs       = 0x0000,
1612         .sysc_offs      = 0x0010,
1613         .syss_offs      = 0x0014,
1614         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1615                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1616                            SYSS_HAS_RESET_STATUS),
1617         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1618         .sysc_fields    = &omap_hwmod_sysc_type1,
1619 };
1620
1621 /*
1622  * 'gpio' class
1623  * general purpose io module
1624  */
1625 static struct omap_hwmod_class omap242x_gpio_hwmod_class = {
1626         .name = "gpio",
1627         .sysc = &omap242x_gpio_sysc,
1628         .rev = 0,
1629 };
1630
1631 /* gpio1 */
1632 static struct omap_hwmod_irq_info omap242x_gpio1_irqs[] = {
1633         { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
1634 };
1635
1636 static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
1637         &omap2420_l4_wkup__gpio1,
1638 };
1639
1640 static struct omap_hwmod omap2420_gpio1_hwmod = {
1641         .name           = "gpio1",
1642         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1643         .mpu_irqs       = omap242x_gpio1_irqs,
1644         .mpu_irqs_cnt   = ARRAY_SIZE(omap242x_gpio1_irqs),
1645         .main_clk       = "gpios_fck",
1646         .prcm           = {
1647                 .omap2 = {
1648                         .prcm_reg_id = 1,
1649                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1650                         .module_offs = WKUP_MOD,
1651                         .idlest_reg_id = 1,
1652                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1653                 },
1654         },
1655         .slaves         = omap2420_gpio1_slaves,
1656         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio1_slaves),
1657         .class          = &omap242x_gpio_hwmod_class,
1658         .dev_attr       = &gpio_dev_attr,
1659         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1660 };
1661
1662 /* gpio2 */
1663 static struct omap_hwmod_irq_info omap242x_gpio2_irqs[] = {
1664         { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
1665 };
1666
1667 static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
1668         &omap2420_l4_wkup__gpio2,
1669 };
1670
1671 static struct omap_hwmod omap2420_gpio2_hwmod = {
1672         .name           = "gpio2",
1673         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1674         .mpu_irqs       = omap242x_gpio2_irqs,
1675         .mpu_irqs_cnt   = ARRAY_SIZE(omap242x_gpio2_irqs),
1676         .main_clk       = "gpios_fck",
1677         .prcm           = {
1678                 .omap2 = {
1679                         .prcm_reg_id = 1,
1680                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1681                         .module_offs = WKUP_MOD,
1682                         .idlest_reg_id = 1,
1683                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1684                 },
1685         },
1686         .slaves         = omap2420_gpio2_slaves,
1687         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio2_slaves),
1688         .class          = &omap242x_gpio_hwmod_class,
1689         .dev_attr       = &gpio_dev_attr,
1690         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1691 };
1692
1693 /* gpio3 */
1694 static struct omap_hwmod_irq_info omap242x_gpio3_irqs[] = {
1695         { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
1696 };
1697
1698 static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
1699         &omap2420_l4_wkup__gpio3,
1700 };
1701
1702 static struct omap_hwmod omap2420_gpio3_hwmod = {
1703         .name           = "gpio3",
1704         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1705         .mpu_irqs       = omap242x_gpio3_irqs,
1706         .mpu_irqs_cnt   = ARRAY_SIZE(omap242x_gpio3_irqs),
1707         .main_clk       = "gpios_fck",
1708         .prcm           = {
1709                 .omap2 = {
1710                         .prcm_reg_id = 1,
1711                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1712                         .module_offs = WKUP_MOD,
1713                         .idlest_reg_id = 1,
1714                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1715                 },
1716         },
1717         .slaves         = omap2420_gpio3_slaves,
1718         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio3_slaves),
1719         .class          = &omap242x_gpio_hwmod_class,
1720         .dev_attr       = &gpio_dev_attr,
1721         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1722 };
1723
1724 /* gpio4 */
1725 static struct omap_hwmod_irq_info omap242x_gpio4_irqs[] = {
1726         { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
1727 };
1728
1729 static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
1730         &omap2420_l4_wkup__gpio4,
1731 };
1732
1733 static struct omap_hwmod omap2420_gpio4_hwmod = {
1734         .name           = "gpio4",
1735         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1736         .mpu_irqs       = omap242x_gpio4_irqs,
1737         .mpu_irqs_cnt   = ARRAY_SIZE(omap242x_gpio4_irqs),
1738         .main_clk       = "gpios_fck",
1739         .prcm           = {
1740                 .omap2 = {
1741                         .prcm_reg_id = 1,
1742                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1743                         .module_offs = WKUP_MOD,
1744                         .idlest_reg_id = 1,
1745                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1746                 },
1747         },
1748         .slaves         = omap2420_gpio4_slaves,
1749         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio4_slaves),
1750         .class          = &omap242x_gpio_hwmod_class,
1751         .dev_attr       = &gpio_dev_attr,
1752         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1753 };
1754
1755 /* system dma */
1756 static struct omap_hwmod_class_sysconfig omap2420_dma_sysc = {
1757         .rev_offs       = 0x0000,
1758         .sysc_offs      = 0x002c,
1759         .syss_offs      = 0x0028,
1760         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
1761                            SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
1762                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1763         .idlemodes      = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1764         .sysc_fields    = &omap_hwmod_sysc_type1,
1765 };
1766
1767 static struct omap_hwmod_class omap2420_dma_hwmod_class = {
1768         .name = "dma",
1769         .sysc = &omap2420_dma_sysc,
1770 };
1771
1772 /* dma attributes */
1773 static struct omap_dma_dev_attr dma_dev_attr = {
1774         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1775                                                 IS_CSSA_32 | IS_CDSA_32,
1776         .lch_count = 32,
1777 };
1778
1779 static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = {
1780         { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
1781         { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
1782         { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
1783         { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
1784 };
1785
1786 static struct omap_hwmod_addr_space omap2420_dma_system_addrs[] = {
1787         {
1788                 .pa_start       = 0x48056000,
1789                 .pa_end         = 0x48056fff,
1790                 .flags          = ADDR_TYPE_RT
1791         },
1792 };
1793
1794 /* dma_system -> L3 */
1795 static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
1796         .master         = &omap2420_dma_system_hwmod,
1797         .slave          = &omap2420_l3_main_hwmod,
1798         .clk            = "core_l3_ck",
1799         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1800 };
1801
1802 /* dma_system master ports */
1803 static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = {
1804         &omap2420_dma_system__l3,
1805 };
1806
1807 /* l4_core -> dma_system */
1808 static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
1809         .master         = &omap2420_l4_core_hwmod,
1810         .slave          = &omap2420_dma_system_hwmod,
1811         .clk            = "sdma_ick",
1812         .addr           = omap2420_dma_system_addrs,
1813         .addr_cnt       = ARRAY_SIZE(omap2420_dma_system_addrs),
1814         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1815 };
1816
1817 /* dma_system slave ports */
1818 static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = {
1819         &omap2420_l4_core__dma_system,
1820 };
1821
1822 static struct omap_hwmod omap2420_dma_system_hwmod = {
1823         .name           = "dma",
1824         .class          = &omap2420_dma_hwmod_class,
1825         .mpu_irqs       = omap2420_dma_system_irqs,
1826         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_dma_system_irqs),
1827         .main_clk       = "core_l3_ck",
1828         .slaves         = omap2420_dma_system_slaves,
1829         .slaves_cnt     = ARRAY_SIZE(omap2420_dma_system_slaves),
1830         .masters        = omap2420_dma_system_masters,
1831         .masters_cnt    = ARRAY_SIZE(omap2420_dma_system_masters),
1832         .dev_attr       = &dma_dev_attr,
1833         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1834         .flags          = HWMOD_NO_IDLEST,
1835 };
1836
1837 /*
1838  * 'mailbox' class
1839  * mailbox module allowing communication between the on-chip processors
1840  * using a queued mailbox-interrupt mechanism.
1841  */
1842
1843 static struct omap_hwmod_class_sysconfig omap2420_mailbox_sysc = {
1844         .rev_offs       = 0x000,
1845         .sysc_offs      = 0x010,
1846         .syss_offs      = 0x014,
1847         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1848                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1849         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1850         .sysc_fields    = &omap_hwmod_sysc_type1,
1851 };
1852
1853 static struct omap_hwmod_class omap2420_mailbox_hwmod_class = {
1854         .name = "mailbox",
1855         .sysc = &omap2420_mailbox_sysc,
1856 };
1857
1858 /* mailbox */
1859 static struct omap_hwmod omap2420_mailbox_hwmod;
1860 static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
1861         { .name = "dsp", .irq = 26 },
1862         { .name = "iva", .irq = 34 },
1863 };
1864
1865 static struct omap_hwmod_addr_space omap2420_mailbox_addrs[] = {
1866         {
1867                 .pa_start       = 0x48094000,
1868                 .pa_end         = 0x480941ff,
1869                 .flags          = ADDR_TYPE_RT,
1870         },
1871 };
1872
1873 /* l4_core -> mailbox */
1874 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
1875         .master         = &omap2420_l4_core_hwmod,
1876         .slave          = &omap2420_mailbox_hwmod,
1877         .addr           = omap2420_mailbox_addrs,
1878         .addr_cnt       = ARRAY_SIZE(omap2420_mailbox_addrs),
1879         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1880 };
1881
1882 /* mailbox slave ports */
1883 static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = {
1884         &omap2420_l4_core__mailbox,
1885 };
1886
1887 static struct omap_hwmod omap2420_mailbox_hwmod = {
1888         .name           = "mailbox",
1889         .class          = &omap2420_mailbox_hwmod_class,
1890         .mpu_irqs       = omap2420_mailbox_irqs,
1891         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_mailbox_irqs),
1892         .main_clk       = "mailboxes_ick",
1893         .prcm           = {
1894                 .omap2 = {
1895                         .prcm_reg_id = 1,
1896                         .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1897                         .module_offs = CORE_MOD,
1898                         .idlest_reg_id = 1,
1899                         .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
1900                 },
1901         },
1902         .slaves         = omap2420_mailbox_slaves,
1903         .slaves_cnt     = ARRAY_SIZE(omap2420_mailbox_slaves),
1904         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1905 };
1906
1907 /*
1908  * 'mcspi' class
1909  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1910  * bus
1911  */
1912
1913 static struct omap_hwmod_class_sysconfig omap2420_mcspi_sysc = {
1914         .rev_offs       = 0x0000,
1915         .sysc_offs      = 0x0010,
1916         .syss_offs      = 0x0014,
1917         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1918                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1919                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1920         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1921         .sysc_fields    = &omap_hwmod_sysc_type1,
1922 };
1923
1924 static struct omap_hwmod_class omap2420_mcspi_class = {
1925         .name = "mcspi",
1926         .sysc = &omap2420_mcspi_sysc,
1927         .rev = OMAP2_MCSPI_REV,
1928 };
1929
1930 /* mcspi1 */
1931 static struct omap_hwmod_irq_info omap2420_mcspi1_mpu_irqs[] = {
1932         { .irq = 65 },
1933 };
1934
1935 static struct omap_hwmod_dma_info omap2420_mcspi1_sdma_reqs[] = {
1936         { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
1937         { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
1938         { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
1939         { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
1940         { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
1941         { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
1942         { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
1943         { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
1944 };
1945
1946 static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = {
1947         &omap2420_l4_core__mcspi1,
1948 };
1949
1950 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1951         .num_chipselect = 4,
1952 };
1953
1954 static struct omap_hwmod omap2420_mcspi1_hwmod = {
1955         .name           = "mcspi1_hwmod",
1956         .mpu_irqs       = omap2420_mcspi1_mpu_irqs,
1957         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_mcspi1_mpu_irqs),
1958         .sdma_reqs      = omap2420_mcspi1_sdma_reqs,
1959         .sdma_reqs_cnt  = ARRAY_SIZE(omap2420_mcspi1_sdma_reqs),
1960         .main_clk       = "mcspi1_fck",
1961         .prcm           = {
1962                 .omap2 = {
1963                         .module_offs = CORE_MOD,
1964                         .prcm_reg_id = 1,
1965                         .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1966                         .idlest_reg_id = 1,
1967                         .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
1968                 },
1969         },
1970         .slaves         = omap2420_mcspi1_slaves,
1971         .slaves_cnt     = ARRAY_SIZE(omap2420_mcspi1_slaves),
1972         .class          = &omap2420_mcspi_class,
1973         .dev_attr       = &omap_mcspi1_dev_attr,
1974         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1975 };
1976
1977 /* mcspi2 */
1978 static struct omap_hwmod_irq_info omap2420_mcspi2_mpu_irqs[] = {
1979         { .irq = 66 },
1980 };
1981
1982 static struct omap_hwmod_dma_info omap2420_mcspi2_sdma_reqs[] = {
1983         { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
1984         { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
1985         { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
1986         { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
1987 };
1988
1989 static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = {
1990         &omap2420_l4_core__mcspi2,
1991 };
1992
1993 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1994         .num_chipselect = 2,
1995 };
1996
1997 static struct omap_hwmod omap2420_mcspi2_hwmod = {
1998         .name           = "mcspi2_hwmod",
1999         .mpu_irqs       = omap2420_mcspi2_mpu_irqs,
2000         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_mcspi2_mpu_irqs),
2001         .sdma_reqs      = omap2420_mcspi2_sdma_reqs,
2002         .sdma_reqs_cnt  = ARRAY_SIZE(omap2420_mcspi2_sdma_reqs),
2003         .main_clk       = "mcspi2_fck",
2004         .prcm           = {
2005                 .omap2 = {
2006                         .module_offs = CORE_MOD,
2007                         .prcm_reg_id = 1,
2008                         .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
2009                         .idlest_reg_id = 1,
2010                         .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
2011                 },
2012         },
2013         .slaves         = omap2420_mcspi2_slaves,
2014         .slaves_cnt     = ARRAY_SIZE(omap2420_mcspi2_slaves),
2015         .class          = &omap2420_mcspi_class,
2016         .dev_attr       = &omap_mcspi2_dev_attr,
2017         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
2018 };
2019
2020 /*
2021  * 'mcbsp' class
2022  * multi channel buffered serial port controller
2023  */
2024
2025 static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
2026         .name = "mcbsp",
2027 };
2028
2029 /* mcbsp1 */
2030 static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
2031         { .name = "tx", .irq = 59 },
2032         { .name = "rx", .irq = 60 },
2033 };
2034
2035 static struct omap_hwmod_dma_info omap2420_mcbsp1_sdma_chs[] = {
2036         { .name = "rx", .dma_req = 32 },
2037         { .name = "tx", .dma_req = 31 },
2038 };
2039
2040 static struct omap_hwmod_addr_space omap2420_mcbsp1_addrs[] = {
2041         {
2042                 .name           = "mpu",
2043                 .pa_start       = 0x48074000,
2044                 .pa_end         = 0x480740ff,
2045                 .flags          = ADDR_TYPE_RT
2046         },
2047 };
2048
2049 /* l4_core -> mcbsp1 */
2050 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
2051         .master         = &omap2420_l4_core_hwmod,
2052         .slave          = &omap2420_mcbsp1_hwmod,
2053         .clk            = "mcbsp1_ick",
2054         .addr           = omap2420_mcbsp1_addrs,
2055         .addr_cnt       = ARRAY_SIZE(omap2420_mcbsp1_addrs),
2056         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2057 };
2058
2059 /* mcbsp1 slave ports */
2060 static struct omap_hwmod_ocp_if *omap2420_mcbsp1_slaves[] = {
2061         &omap2420_l4_core__mcbsp1,
2062 };
2063
2064 static struct omap_hwmod omap2420_mcbsp1_hwmod = {
2065         .name           = "mcbsp1",
2066         .class          = &omap2420_mcbsp_hwmod_class,
2067         .mpu_irqs       = omap2420_mcbsp1_irqs,
2068         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_mcbsp1_irqs),
2069         .sdma_reqs      = omap2420_mcbsp1_sdma_chs,
2070         .sdma_reqs_cnt  = ARRAY_SIZE(omap2420_mcbsp1_sdma_chs),
2071         .main_clk       = "mcbsp1_fck",
2072         .prcm           = {
2073                 .omap2 = {
2074                         .prcm_reg_id = 1,
2075                         .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
2076                         .module_offs = CORE_MOD,
2077                         .idlest_reg_id = 1,
2078                         .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
2079                 },
2080         },
2081         .slaves         = omap2420_mcbsp1_slaves,
2082         .slaves_cnt     = ARRAY_SIZE(omap2420_mcbsp1_slaves),
2083         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
2084 };
2085
2086 /* mcbsp2 */
2087 static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
2088         { .name = "tx", .irq = 62 },
2089         { .name = "rx", .irq = 63 },
2090 };
2091
2092 static struct omap_hwmod_dma_info omap2420_mcbsp2_sdma_chs[] = {
2093         { .name = "rx", .dma_req = 34 },
2094         { .name = "tx", .dma_req = 33 },
2095 };
2096
2097 static struct omap_hwmod_addr_space omap2420_mcbsp2_addrs[] = {
2098         {
2099                 .name           = "mpu",
2100                 .pa_start       = 0x48076000,
2101                 .pa_end         = 0x480760ff,
2102                 .flags          = ADDR_TYPE_RT
2103         },
2104 };
2105
2106 /* l4_core -> mcbsp2 */
2107 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
2108         .master         = &omap2420_l4_core_hwmod,
2109         .slave          = &omap2420_mcbsp2_hwmod,
2110         .clk            = "mcbsp2_ick",
2111         .addr           = omap2420_mcbsp2_addrs,
2112         .addr_cnt       = ARRAY_SIZE(omap2420_mcbsp2_addrs),
2113         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2114 };
2115
2116 /* mcbsp2 slave ports */
2117 static struct omap_hwmod_ocp_if *omap2420_mcbsp2_slaves[] = {
2118         &omap2420_l4_core__mcbsp2,
2119 };
2120
2121 static struct omap_hwmod omap2420_mcbsp2_hwmod = {
2122         .name           = "mcbsp2",
2123         .class          = &omap2420_mcbsp_hwmod_class,
2124         .mpu_irqs       = omap2420_mcbsp2_irqs,
2125         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_mcbsp2_irqs),
2126         .sdma_reqs      = omap2420_mcbsp2_sdma_chs,
2127         .sdma_reqs_cnt  = ARRAY_SIZE(omap2420_mcbsp2_sdma_chs),
2128         .main_clk       = "mcbsp2_fck",
2129         .prcm           = {
2130                 .omap2 = {
2131                         .prcm_reg_id = 1,
2132                         .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
2133                         .module_offs = CORE_MOD,
2134                         .idlest_reg_id = 1,
2135                         .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
2136                 },
2137         },
2138         .slaves         = omap2420_mcbsp2_slaves,
2139         .slaves_cnt     = ARRAY_SIZE(omap2420_mcbsp2_slaves),
2140         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
2141 };
2142
2143 static __initdata struct omap_hwmod *omap2420_hwmods[] = {
2144         &omap2420_l3_main_hwmod,
2145         &omap2420_l4_core_hwmod,
2146         &omap2420_l4_wkup_hwmod,
2147         &omap2420_mpu_hwmod,
2148         &omap2420_iva_hwmod,
2149
2150         &omap2420_timer1_hwmod,
2151         &omap2420_timer2_hwmod,
2152         &omap2420_timer3_hwmod,
2153         &omap2420_timer4_hwmod,
2154         &omap2420_timer5_hwmod,
2155         &omap2420_timer6_hwmod,
2156         &omap2420_timer7_hwmod,
2157         &omap2420_timer8_hwmod,
2158         &omap2420_timer9_hwmod,
2159         &omap2420_timer10_hwmod,
2160         &omap2420_timer11_hwmod,
2161         &omap2420_timer12_hwmod,
2162
2163         &omap2420_wd_timer2_hwmod,
2164         &omap2420_uart1_hwmod,
2165         &omap2420_uart2_hwmod,
2166         &omap2420_uart3_hwmod,
2167         /* dss class */
2168         &omap2420_dss_core_hwmod,
2169         &omap2420_dss_dispc_hwmod,
2170         &omap2420_dss_rfbi_hwmod,
2171         &omap2420_dss_venc_hwmod,
2172         /* i2c class */
2173         &omap2420_i2c1_hwmod,
2174         &omap2420_i2c2_hwmod,
2175
2176         /* gpio class */
2177         &omap2420_gpio1_hwmod,
2178         &omap2420_gpio2_hwmod,
2179         &omap2420_gpio3_hwmod,
2180         &omap2420_gpio4_hwmod,
2181
2182         /* dma_system class*/
2183         &omap2420_dma_system_hwmod,
2184
2185         /* mailbox class */
2186         &omap2420_mailbox_hwmod,
2187
2188         /* mcbsp class */
2189         &omap2420_mcbsp1_hwmod,
2190         &omap2420_mcbsp2_hwmod,
2191
2192         /* mcspi class */
2193         &omap2420_mcspi1_hwmod,
2194         &omap2420_mcspi2_hwmod,
2195         NULL,
2196 };
2197
2198 int __init omap2420_hwmod_init(void)
2199 {
2200         return omap_hwmod_register(omap2420_hwmods);
2201 }