arch/arm/mach-omap2/io.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * linux/arch/arm/mach-omap2/io.c
   4  *
   5  * OMAP2 I/O mapping code
   6  *
   7  * Copyright (C) 2005 Nokia Corporation
   8  * Copyright (C) 2007-2009 Texas Instruments
   9  *
  10  * Author:
  11  *      Juha Yrjola <juha.yrjola@nokia.com>
  12  *      Syed Khasim <x0khasim@ti.com>
  13  *
  14  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  15  */
  16 #include <linux/module.h>
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/io.h>
  20 #include <linux/clk.h>
  21
  22 #include <asm/tlb.h>
  23 #include <asm/mach/map.h>
  24
  25 #include <linux/omap-dma.h>
  26
  27 #include "omap_hwmod.h"
  28 #include "soc.h"
  29 #include "iomap.h"
  30 #include "voltage.h"
  31 #include "powerdomain.h"
  32 #include "clockdomain.h"
  33 #include "common.h"
  34 #include "clock.h"
  35 #include "clock2xxx.h"
  36 #include "clock3xxx.h"
  37 #include "sdrc.h"
  38 #include "control.h"
  39 #include "serial.h"
  40 #include "sram.h"
  41 #include "cm2xxx.h"
  42 #include "cm3xxx.h"
  43 #include "cm33xx.h"
  44 #include "cm44xx.h"
  45 #include "prm.h"
  46 #include "cm.h"
  47 #include "prcm_mpu44xx.h"
  48 #include "prminst44xx.h"
  49 #include "prm2xxx.h"
  50 #include "prm3xxx.h"
  51 #include "prm33xx.h"
  52 #include "prm44xx.h"
  53 #include "opp2xxx.h"
  54
  55 /*
  56  * omap_clk_soc_init: points to a function that does the SoC-specific
  57  * clock initializations
  58  */
  59 static int (*omap_clk_soc_init)(void);
  60
  61 /*
  62  * The machine specific code may provide the extra mapping besides the
  63  * default mapping provided here.
  64  */
  65
  66 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
  67 static struct map_desc omap24xx_io_desc[] __initdata = {
  68         {
  69                 .virtual        = L3_24XX_VIRT,
  70                 .pfn            = __phys_to_pfn(L3_24XX_PHYS),
  71                 .length         = L3_24XX_SIZE,
  72                 .type           = MT_DEVICE
  73         },
  74         {
  75                 .virtual        = L4_24XX_VIRT,
  76                 .pfn            = __phys_to_pfn(L4_24XX_PHYS),
  77                 .length         = L4_24XX_SIZE,
  78                 .type           = MT_DEVICE
  79         },
  80 };
  81
  82 #ifdef CONFIG_SOC_OMAP2420
  83 static struct map_desc omap242x_io_desc[] __initdata = {
  84         {
  85                 .virtual        = DSP_MEM_2420_VIRT,
  86                 .pfn            = __phys_to_pfn(DSP_MEM_2420_PHYS),
  87                 .length         = DSP_MEM_2420_SIZE,
  88                 .type           = MT_DEVICE
  89         },
  90         {
  91                 .virtual        = DSP_IPI_2420_VIRT,
  92                 .pfn            = __phys_to_pfn(DSP_IPI_2420_PHYS),
  93                 .length         = DSP_IPI_2420_SIZE,
  94                 .type           = MT_DEVICE
  95         },
  96         {
  97                 .virtual        = DSP_MMU_2420_VIRT,
  98                 .pfn            = __phys_to_pfn(DSP_MMU_2420_PHYS),
  99                 .length         = DSP_MMU_2420_SIZE,
 100                 .type           = MT_DEVICE
 101         },
 102 };
 103
 104 #endif
 105
 106 #ifdef CONFIG_SOC_OMAP2430
 107 static struct map_desc omap243x_io_desc[] __initdata = {
 108         {
 109                 .virtual        = L4_WK_243X_VIRT,
 110                 .pfn            = __phys_to_pfn(L4_WK_243X_PHYS),
 111                 .length         = L4_WK_243X_SIZE,
 112                 .type           = MT_DEVICE
 113         },
 114         {
 115                 .virtual        = OMAP243X_GPMC_VIRT,
 116                 .pfn            = __phys_to_pfn(OMAP243X_GPMC_PHYS),
 117                 .length         = OMAP243X_GPMC_SIZE,
 118                 .type           = MT_DEVICE
 119         },
 120         {
 121                 .virtual        = OMAP243X_SDRC_VIRT,
 122                 .pfn            = __phys_to_pfn(OMAP243X_SDRC_PHYS),
 123                 .length         = OMAP243X_SDRC_SIZE,
 124                 .type           = MT_DEVICE
 125         },
 126         {
 127                 .virtual        = OMAP243X_SMS_VIRT,
 128                 .pfn            = __phys_to_pfn(OMAP243X_SMS_PHYS),
 129                 .length         = OMAP243X_SMS_SIZE,
 130                 .type           = MT_DEVICE
 131         },
 132 };
 133 #endif
 134 #endif
 135
 136 #ifdef  CONFIG_ARCH_OMAP3
 137 static struct map_desc omap34xx_io_desc[] __initdata = {
 138         {
 139                 .virtual        = L3_34XX_VIRT,
 140                 .pfn            = __phys_to_pfn(L3_34XX_PHYS),
 141                 .length         = L3_34XX_SIZE,
 142                 .type           = MT_DEVICE
 143         },
 144         {
 145                 .virtual        = L4_34XX_VIRT,
 146                 .pfn            = __phys_to_pfn(L4_34XX_PHYS),
 147                 .length         = L4_34XX_SIZE,
 148                 .type           = MT_DEVICE
 149         },
 150         {
 151                 .virtual        = OMAP34XX_GPMC_VIRT,
 152                 .pfn            = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
 153                 .length         = OMAP34XX_GPMC_SIZE,
 154                 .type           = MT_DEVICE
 155         },
 156         {
 157                 .virtual        = OMAP343X_SMS_VIRT,
 158                 .pfn            = __phys_to_pfn(OMAP343X_SMS_PHYS),
 159                 .length         = OMAP343X_SMS_SIZE,
 160                 .type           = MT_DEVICE
 161         },
 162         {
 163                 .virtual        = OMAP343X_SDRC_VIRT,
 164                 .pfn            = __phys_to_pfn(OMAP343X_SDRC_PHYS),
 165                 .length         = OMAP343X_SDRC_SIZE,
 166                 .type           = MT_DEVICE
 167         },
 168         {
 169                 .virtual        = L4_PER_34XX_VIRT,
 170                 .pfn            = __phys_to_pfn(L4_PER_34XX_PHYS),
 171                 .length         = L4_PER_34XX_SIZE,
 172                 .type           = MT_DEVICE
 173         },
 174         {
 175                 .virtual        = L4_EMU_34XX_VIRT,
 176                 .pfn            = __phys_to_pfn(L4_EMU_34XX_PHYS),
 177                 .length         = L4_EMU_34XX_SIZE,
 178                 .type           = MT_DEVICE
 179         },
 180 };
 181 #endif
 182
 183 #ifdef CONFIG_SOC_TI81XX
 184 static struct map_desc omapti81xx_io_desc[] __initdata = {
 185         {
 186                 .virtual        = L4_34XX_VIRT,
 187                 .pfn            = __phys_to_pfn(L4_34XX_PHYS),
 188                 .length         = L4_34XX_SIZE,
 189                 .type           = MT_DEVICE
 190         }
 191 };
 192 #endif
 193
 194 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
 195 static struct map_desc omapam33xx_io_desc[] __initdata = {
 196         {
 197                 .virtual        = L4_34XX_VIRT,
 198                 .pfn            = __phys_to_pfn(L4_34XX_PHYS),
 199                 .length         = L4_34XX_SIZE,
 200                 .type           = MT_DEVICE
 201         },
 202         {
 203                 .virtual        = L4_WK_AM33XX_VIRT,
 204                 .pfn            = __phys_to_pfn(L4_WK_AM33XX_PHYS),
 205                 .length         = L4_WK_AM33XX_SIZE,
 206                 .type           = MT_DEVICE
 207         }
 208 };
 209 #endif
 210
 211 #ifdef  CONFIG_ARCH_OMAP4
 212 static struct map_desc omap44xx_io_desc[] __initdata = {
 213         {
 214                 .virtual        = L3_44XX_VIRT,
 215                 .pfn            = __phys_to_pfn(L3_44XX_PHYS),
 216                 .length         = L3_44XX_SIZE,
 217                 .type           = MT_DEVICE,
 218         },
 219         {
 220                 .virtual        = L4_44XX_VIRT,
 221                 .pfn            = __phys_to_pfn(L4_44XX_PHYS),
 222                 .length         = L4_44XX_SIZE,
 223                 .type           = MT_DEVICE,
 224         },
 225         {
 226                 .virtual        = L4_PER_44XX_VIRT,
 227                 .pfn            = __phys_to_pfn(L4_PER_44XX_PHYS),
 228                 .length         = L4_PER_44XX_SIZE,
 229                 .type           = MT_DEVICE,
 230         },
 231 };
 232 #endif
 233
 234 #ifdef CONFIG_SOC_OMAP5
 235 static struct map_desc omap54xx_io_desc[] __initdata = {
 236         {
 237                 .virtual        = L3_54XX_VIRT,
 238                 .pfn            = __phys_to_pfn(L3_54XX_PHYS),
 239                 .length         = L3_54XX_SIZE,
 240                 .type           = MT_DEVICE,
 241         },
 242         {
 243                 .virtual        = L4_54XX_VIRT,
 244                 .pfn            = __phys_to_pfn(L4_54XX_PHYS),
 245                 .length         = L4_54XX_SIZE,
 246                 .type           = MT_DEVICE,
 247         },
 248         {
 249                 .virtual        = L4_WK_54XX_VIRT,
 250                 .pfn            = __phys_to_pfn(L4_WK_54XX_PHYS),
 251                 .length         = L4_WK_54XX_SIZE,
 252                 .type           = MT_DEVICE,
 253         },
 254         {
 255                 .virtual        = L4_PER_54XX_VIRT,
 256                 .pfn            = __phys_to_pfn(L4_PER_54XX_PHYS),
 257                 .length         = L4_PER_54XX_SIZE,
 258                 .type           = MT_DEVICE,
 259         },
 260 };
 261 #endif
 262
 263 #ifdef CONFIG_SOC_DRA7XX
 264 static struct map_desc dra7xx_io_desc[] __initdata = {
 265         {
 266                 .virtual        = L4_CFG_MPU_DRA7XX_VIRT,
 267                 .pfn            = __phys_to_pfn(L4_CFG_MPU_DRA7XX_PHYS),
 268                 .length         = L4_CFG_MPU_DRA7XX_SIZE,
 269                 .type           = MT_DEVICE,
 270         },
 271         {
 272                 .virtual        = L3_MAIN_SN_DRA7XX_VIRT,
 273                 .pfn            = __phys_to_pfn(L3_MAIN_SN_DRA7XX_PHYS),
 274                 .length         = L3_MAIN_SN_DRA7XX_SIZE,
 275                 .type           = MT_DEVICE,
 276         },
 277         {
 278                 .virtual        = L4_PER1_DRA7XX_VIRT,
 279                 .pfn            = __phys_to_pfn(L4_PER1_DRA7XX_PHYS),
 280                 .length         = L4_PER1_DRA7XX_SIZE,
 281                 .type           = MT_DEVICE,
 282         },
 283         {
 284                 .virtual        = L4_PER2_DRA7XX_VIRT,
 285                 .pfn            = __phys_to_pfn(L4_PER2_DRA7XX_PHYS),
 286                 .length         = L4_PER2_DRA7XX_SIZE,
 287                 .type           = MT_DEVICE,
 288         },
 289         {
 290                 .virtual        = L4_PER3_DRA7XX_VIRT,
 291                 .pfn            = __phys_to_pfn(L4_PER3_DRA7XX_PHYS),
 292                 .length         = L4_PER3_DRA7XX_SIZE,
 293                 .type           = MT_DEVICE,
 294         },
 295         {
 296                 .virtual        = L4_CFG_DRA7XX_VIRT,
 297                 .pfn            = __phys_to_pfn(L4_CFG_DRA7XX_PHYS),
 298                 .length         = L4_CFG_DRA7XX_SIZE,
 299                 .type           = MT_DEVICE,
 300         },
 301         {
 302                 .virtual        = L4_WKUP_DRA7XX_VIRT,
 303                 .pfn            = __phys_to_pfn(L4_WKUP_DRA7XX_PHYS),
 304                 .length         = L4_WKUP_DRA7XX_SIZE,
 305                 .type           = MT_DEVICE,
 306         },
 307 };
 308 #endif
 309
 310 #ifdef CONFIG_SOC_OMAP2420
 311 void __init omap242x_map_io(void)
 312 {
 313         iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
 314         iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
 315 }
 316 #endif
 317
 318 #ifdef CONFIG_SOC_OMAP2430
 319 void __init omap243x_map_io(void)
 320 {
 321         iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
 322         iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
 323 }
 324 #endif
 325
 326 #ifdef CONFIG_ARCH_OMAP3
 327 void __init omap3_map_io(void)
 328 {
 329         iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
 330 }
 331 #endif
 332
 333 #ifdef CONFIG_SOC_TI81XX
 334 void __init ti81xx_map_io(void)
 335 {
 336         iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
 337 }
 338 #endif
 339
 340 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
 341 void __init am33xx_map_io(void)
 342 {
 343         iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
 344 }
 345 #endif
 346
 347 #ifdef CONFIG_ARCH_OMAP4
 348 void __init omap4_map_io(void)
 349 {
 350         iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
 351         omap_barriers_init();
 352 }
 353 #endif
 354
 355 #ifdef CONFIG_SOC_OMAP5
 356 void __init omap5_map_io(void)
 357 {
 358         iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
 359         omap_barriers_init();
 360 }
 361 #endif
 362
 363 #ifdef CONFIG_SOC_DRA7XX
 364 void __init dra7xx_map_io(void)
 365 {
 366         iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc));
 367         omap_barriers_init();
 368 }
 369 #endif
 370 /*
 371  * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
 372  *
 373  * Sets the CORE DPLL3 M2 divider to the same value that it's at
 374  * currently.  This has the effect of setting the SDRC SDRAM AC timing
 375  * registers to the values currently defined by the kernel.  Currently
 376  * only defined for OMAP3; will return 0 if called on OMAP2.  Returns
 377  * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
 378  * or passes along the return value of clk_set_rate().
 379  */
 380 static int __init _omap2_init_reprogram_sdrc(void)
 381 {
 382         struct clk *dpll3_m2_ck;
 383         int v = -EINVAL;
 384         long rate;
 385
 386         if (!cpu_is_omap34xx())
 387                 return 0;
 388
 389         dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
 390         if (IS_ERR(dpll3_m2_ck))
 391                 return -EINVAL;
 392
 393         rate = clk_get_rate(dpll3_m2_ck);
 394         pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
 395         v = clk_set_rate(dpll3_m2_ck, rate);
 396         if (v)
 397                 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
 398
 399         clk_put(dpll3_m2_ck);
 400
 401         return v;
 402 }
 403
 404 static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
 405 {
 406         return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
 407 }
 408
 409 static void __init __maybe_unused omap_hwmod_init_postsetup(void)
 410 {
 411         u8 postsetup_state = _HWMOD_STATE_DEFAULT;
 412
 413         /* Set the default postsetup state for all hwmods */
 414         omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
 415 }
 416
 417 #ifdef CONFIG_SOC_OMAP2420
 418 void __init omap2420_init_early(void)
 419 {
 420         omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
 421         omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
 422                                OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
 423         omap2_control_base_init();
 424         omap2xxx_check_revision();
 425         omap2_prcm_base_init();
 426         omap2xxx_voltagedomains_init();
 427         omap242x_powerdomains_init();
 428         omap242x_clockdomains_init();
 429         omap2420_hwmod_init();
 430         omap_hwmod_init_postsetup();
 431         omap_clk_soc_init = omap2420_dt_clk_init;
 432         rate_table = omap2420_rate_table;
 433 }
 434
 435 void __init omap2420_init_late(void)
 436 {
 437         omap_pm_soc_init = omap2_pm_init;
 438 }
 439 #endif
 440
 441 #ifdef CONFIG_SOC_OMAP2430
 442 void __init omap2430_init_early(void)
 443 {
 444         omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
 445         omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
 446                                OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
 447         omap2_control_base_init();
 448         omap2xxx_check_revision();
 449         omap2_prcm_base_init();
 450         omap2xxx_voltagedomains_init();
 451         omap243x_powerdomains_init();
 452         omap243x_clockdomains_init();
 453         omap2430_hwmod_init();
 454         omap_hwmod_init_postsetup();
 455         omap_clk_soc_init = omap2430_dt_clk_init;
 456         rate_table = omap2430_rate_table;
 457 }
 458
 459 void __init omap2430_init_late(void)
 460 {
 461         omap_pm_soc_init = omap2_pm_init;
 462 }
 463 #endif
 464
 465 /*
 466  * Currently only board-omap3beagle.c should call this because of the
 467  * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
 468  */
 469 #ifdef CONFIG_ARCH_OMAP3
 470 void __init omap3_init_early(void)
 471 {
 472         omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
 473         omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
 474                                OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
 475         omap2_control_base_init();
 476         omap3xxx_check_revision();
 477         omap3xxx_check_features();
 478         omap2_prcm_base_init();
 479         omap3xxx_voltagedomains_init();
 480         omap3xxx_powerdomains_init();
 481         omap3xxx_clockdomains_init();
 482         omap3xxx_hwmod_init();
 483         omap_hwmod_init_postsetup();
 484 }
 485
 486 void __init omap3430_init_early(void)
 487 {
 488         omap3_init_early();
 489         omap_clk_soc_init = omap3430_dt_clk_init;
 490 }
 491
 492 void __init omap35xx_init_early(void)
 493 {
 494         omap3_init_early();
 495         omap_clk_soc_init = omap3430_dt_clk_init;
 496 }
 497
 498 void __init omap3630_init_early(void)
 499 {
 500         omap3_init_early();
 501         omap_clk_soc_init = omap3630_dt_clk_init;
 502 }
 503
 504 void __init am35xx_init_early(void)
 505 {
 506         omap3_init_early();
 507         omap_clk_soc_init = am35xx_dt_clk_init;
 508 }
 509
 510 void __init omap3_init_late(void)
 511 {
 512         omap_pm_soc_init = omap3_pm_init;
 513 }
 514
 515 void __init ti81xx_init_late(void)
 516 {
 517         omap_pm_soc_init = omap_pm_nop_init;
 518 }
 519 #endif
 520
 521 #ifdef CONFIG_SOC_TI81XX
 522 void __init ti814x_init_early(void)
 523 {
 524         omap2_set_globals_tap(TI814X_CLASS,
 525                               OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
 526         omap2_control_base_init();
 527         omap3xxx_check_revision();
 528         ti81xx_check_features();
 529         omap2_prcm_base_init();
 530         omap3xxx_voltagedomains_init();
 531         omap3xxx_powerdomains_init();
 532         ti814x_clockdomains_init();
 533         dm814x_hwmod_init();
 534         omap_hwmod_init_postsetup();
 535         omap_clk_soc_init = dm814x_dt_clk_init;
 536 }
 537
 538 void __init ti816x_init_early(void)
 539 {
 540         omap2_set_globals_tap(TI816X_CLASS,
 541                               OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
 542         omap2_control_base_init();
 543         omap3xxx_check_revision();
 544         ti81xx_check_features();
 545         omap2_prcm_base_init();
 546         omap3xxx_voltagedomains_init();
 547         omap3xxx_powerdomains_init();
 548         ti816x_clockdomains_init();
 549         dm816x_hwmod_init();
 550         omap_hwmod_init_postsetup();
 551         omap_clk_soc_init = dm816x_dt_clk_init;
 552 }
 553 #endif
 554
 555 #ifdef CONFIG_SOC_AM33XX
 556 void __init am33xx_init_early(void)
 557 {
 558         omap2_set_globals_tap(AM335X_CLASS,
 559                               AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
 560         omap2_control_base_init();
 561         omap3xxx_check_revision();
 562         am33xx_check_features();
 563         omap2_prcm_base_init();
 564         am33xx_powerdomains_init();
 565         am33xx_clockdomains_init();
 566         am33xx_hwmod_init();
 567         omap_hwmod_init_postsetup();
 568         omap_clk_soc_init = am33xx_dt_clk_init;
 569 }
 570
 571 void __init am33xx_init_late(void)
 572 {
 573         omap_pm_soc_init = amx3_common_pm_init;
 574 }
 575 #endif
 576
 577 #ifdef CONFIG_SOC_AM43XX
 578 void __init am43xx_init_early(void)
 579 {
 580         omap2_set_globals_tap(AM335X_CLASS,
 581                               AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
 582         omap2_control_base_init();
 583         omap3xxx_check_revision();
 584         am33xx_check_features();
 585         omap2_prcm_base_init();
 586         am43xx_powerdomains_init();
 587         am43xx_clockdomains_init();
 588         am43xx_hwmod_init();
 589         omap_hwmod_init_postsetup();
 590         omap_l2_cache_init();
 591         omap_clk_soc_init = am43xx_dt_clk_init;
 592 }
 593
 594 void __init am43xx_init_late(void)
 595 {
 596         omap_pm_soc_init = amx3_common_pm_init;
 597 }
 598 #endif
 599
 600 #ifdef CONFIG_ARCH_OMAP4
 601 void __init omap4430_init_early(void)
 602 {
 603         omap2_set_globals_tap(OMAP443X_CLASS,
 604                               OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
 605         omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
 606         omap2_control_base_init();
 607         omap4xxx_check_revision();
 608         omap4xxx_check_features();
 609         omap2_prcm_base_init();
 610         omap4_sar_ram_init();
 611         omap4_mpuss_early_init();
 612         omap4_pm_init_early();
 613         omap44xx_voltagedomains_init();
 614         omap44xx_powerdomains_init();
 615         omap44xx_clockdomains_init();
 616         omap44xx_hwmod_init();
 617         omap_hwmod_init_postsetup();
 618         omap_l2_cache_init();
 619         omap_clk_soc_init = omap4xxx_dt_clk_init;
 620 }
 621
 622 void __init omap4430_init_late(void)
 623 {
 624         omap_pm_soc_init = omap4_pm_init;
 625 }
 626 #endif
 627
 628 #ifdef CONFIG_SOC_OMAP5
 629 void __init omap5_init_early(void)
 630 {
 631         omap2_set_globals_tap(OMAP54XX_CLASS,
 632                               OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
 633         omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
 634         omap2_control_base_init();
 635         omap2_prcm_base_init();
 636         omap5xxx_check_revision();
 637         omap4_sar_ram_init();
 638         omap4_mpuss_early_init();
 639         omap4_pm_init_early();
 640         omap54xx_voltagedomains_init();
 641         omap54xx_powerdomains_init();
 642         omap54xx_clockdomains_init();
 643         omap54xx_hwmod_init();
 644         omap_hwmod_init_postsetup();
 645         omap_clk_soc_init = omap5xxx_dt_clk_init;
 646 }
 647
 648 void __init omap5_init_late(void)
 649 {
 650         omap_pm_soc_init = omap4_pm_init;
 651 }
 652 #endif
 653
 654 #ifdef CONFIG_SOC_DRA7XX
 655 void __init dra7xx_init_early(void)
 656 {
 657         omap2_set_globals_tap(DRA7XX_CLASS,
 658                               OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
 659         omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
 660         omap2_control_base_init();
 661         omap4_pm_init_early();
 662         omap2_prcm_base_init();
 663         dra7xxx_check_revision();
 664         dra7xx_powerdomains_init();
 665         dra7xx_clockdomains_init();
 666         dra7xx_hwmod_init();
 667         omap_hwmod_init_postsetup();
 668         omap_clk_soc_init = dra7xx_dt_clk_init;
 669 }
 670
 671 void __init dra7xx_init_late(void)
 672 {
 673         omap_pm_soc_init = omap4_pm_init;
 674 }
 675 #endif
 676
 677
 678 void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
 679                                       struct omap_sdrc_params *sdrc_cs1)
 680 {
 681         omap_sram_init();
 682
 683         if (cpu_is_omap24xx() || omap3_has_sdrc()) {
 684                 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
 685                 _omap2_init_reprogram_sdrc();
 686         }
 687 }
 688
 689 int __init omap_clk_init(void)
 690 {
 691         int ret = 0;
 692
 693         if (!omap_clk_soc_init)
 694                 return 0;
 695
 696         ti_clk_init_features();
 697
 698         omap2_clk_setup_ll_ops();
 699
 700         ret = omap_control_init();
 701         if (ret)
 702                 return ret;
 703
 704         ret = omap_prcm_init();
 705         if (ret)
 706                 return ret;
 707
 708         of_clk_init(NULL);
 709
 710         ti_dt_clk_init_retry_clks();
 711
 712         ti_dt_clockdomains_setup();
 713
 714         ret = omap_clk_soc_init();
 715
 716         return ret;
 717 }