2 * GPMC support functions
4 * Copyright (C) 2005-2006 Nokia Corporation
8 * Copyright (C) 2009 Texas Instruments
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/irq.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
22 #include <linux/ioport.h>
23 #include <linux/spinlock.h>
25 #include <linux/module.h>
26 #include <linux/interrupt.h>
28 #include <asm/mach-types.h>
29 #include <plat/gpmc.h>
31 #include <plat/sdrc.h>
33 /* GPMC register offsets */
34 #define GPMC_REVISION 0x00
35 #define GPMC_SYSCONFIG 0x10
36 #define GPMC_SYSSTATUS 0x14
37 #define GPMC_IRQSTATUS 0x18
38 #define GPMC_IRQENABLE 0x1c
39 #define GPMC_TIMEOUT_CONTROL 0x40
40 #define GPMC_ERR_ADDRESS 0x44
41 #define GPMC_ERR_TYPE 0x48
42 #define GPMC_CONFIG 0x50
43 #define GPMC_STATUS 0x54
44 #define GPMC_PREFETCH_CONFIG1 0x1e0
45 #define GPMC_PREFETCH_CONFIG2 0x1e4
46 #define GPMC_PREFETCH_CONTROL 0x1ec
47 #define GPMC_PREFETCH_STATUS 0x1f0
48 #define GPMC_ECC_CONFIG 0x1f4
49 #define GPMC_ECC_CONTROL 0x1f8
50 #define GPMC_ECC_SIZE_CONFIG 0x1fc
51 #define GPMC_ECC1_RESULT 0x200
52 #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
54 #define GPMC_CS0_OFFSET 0x60
55 #define GPMC_CS_SIZE 0x30
57 #define GPMC_MEM_START 0x00000000
58 #define GPMC_MEM_END 0x3FFFFFFF
59 #define BOOT_ROM_SPACE 0x100000 /* 1MB */
61 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
62 #define GPMC_SECTION_SHIFT 28 /* 128 MB */
64 #define CS_NUM_SHIFT 24
65 #define ENABLE_PREFETCH (0x1 << 7)
66 #define DMA_MPU_MODE 2
68 /* Structure to save gpmc cs context */
69 struct gpmc_cs_config {
81 * Structure to save/restore gpmc context
82 * to support core off on OMAP3
84 struct omap3_gpmc_regs {
92 struct gpmc_cs_config cs_context[GPMC_CS_NUM];
95 static struct resource gpmc_mem_root;
96 static struct resource gpmc_cs_mem[GPMC_CS_NUM];
97 static DEFINE_SPINLOCK(gpmc_mem_lock);
98 static unsigned int gpmc_cs_map; /* flag for cs which are initialized */
99 static int gpmc_ecc_used = -EINVAL; /* cs using ecc engine */
101 static void __iomem *gpmc_base;
103 static struct clk *gpmc_l3_clk;
105 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
107 static void gpmc_write_reg(int idx, u32 val)
109 __raw_writel(val, gpmc_base + idx);
112 static u32 gpmc_read_reg(int idx)
114 return __raw_readl(gpmc_base + idx);
117 static void gpmc_cs_write_byte(int cs, int idx, u8 val)
119 void __iomem *reg_addr;
121 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
122 __raw_writeb(val, reg_addr);
125 static u8 gpmc_cs_read_byte(int cs, int idx)
127 void __iomem *reg_addr;
129 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
130 return __raw_readb(reg_addr);
133 void gpmc_cs_write_reg(int cs, int idx, u32 val)
135 void __iomem *reg_addr;
137 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
138 __raw_writel(val, reg_addr);
141 u32 gpmc_cs_read_reg(int cs, int idx)
143 void __iomem *reg_addr;
145 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
146 return __raw_readl(reg_addr);
149 /* TODO: Add support for gpmc_fck to clock framework and use it */
150 unsigned long gpmc_get_fclk_period(void)
152 unsigned long rate = clk_get_rate(gpmc_l3_clk);
155 printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
160 rate = 1000000000 / rate; /* In picoseconds */
165 unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
167 unsigned long tick_ps;
169 /* Calculate in picosecs to yield more exact results */
170 tick_ps = gpmc_get_fclk_period();
172 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
175 unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
177 unsigned long tick_ps;
179 /* Calculate in picosecs to yield more exact results */
180 tick_ps = gpmc_get_fclk_period();
182 return (time_ps + tick_ps - 1) / tick_ps;
185 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
187 return ticks * gpmc_get_fclk_period() / 1000;
190 unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
192 unsigned long ticks = gpmc_ns_to_ticks(time_ns);
194 return ticks * gpmc_get_fclk_period() / 1000;
198 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
199 int time, const char *name)
201 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
206 int ticks, mask, nr_bits;
211 ticks = gpmc_ns_to_ticks(time);
212 nr_bits = end_bit - st_bit + 1;
213 if (ticks >= 1 << nr_bits) {
215 printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
216 cs, name, time, ticks, 1 << nr_bits);
221 mask = (1 << nr_bits) - 1;
222 l = gpmc_cs_read_reg(cs, reg);
225 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
226 cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
227 (l >> st_bit) & mask, time);
229 l &= ~(mask << st_bit);
230 l |= ticks << st_bit;
231 gpmc_cs_write_reg(cs, reg, l);
237 #define GPMC_SET_ONE(reg, st, end, field) \
238 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
239 t->field, #field) < 0) \
242 #define GPMC_SET_ONE(reg, st, end, field) \
243 if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
247 int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
252 l = sync_clk + (gpmc_get_fclk_period() - 1);
253 div = l / gpmc_get_fclk_period();
262 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
267 div = gpmc_cs_calc_divider(cs, t->sync_clk);
271 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
272 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
273 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
275 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
276 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
277 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
279 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
280 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
281 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
282 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
284 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
285 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
286 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
288 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
290 if (cpu_is_omap34xx()) {
291 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
292 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
295 /* caller is expected to have initialized CONFIG1 to cover
296 * at least sync vs async
298 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
299 if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
301 printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
302 cs, (div * gpmc_get_fclk_period()) / 1000, div);
306 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
312 static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
317 mask = (1 << GPMC_SECTION_SHIFT) - size;
318 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
320 l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
322 l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
323 l |= GPMC_CONFIG7_CSVALID;
324 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
327 static void gpmc_cs_disable_mem(int cs)
331 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
332 l &= ~GPMC_CONFIG7_CSVALID;
333 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
336 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
341 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
342 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
343 mask = (l >> 8) & 0x0f;
344 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
347 static int gpmc_cs_mem_enabled(int cs)
351 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
352 return l & GPMC_CONFIG7_CSVALID;
355 int gpmc_cs_set_reserved(int cs, int reserved)
357 if (cs > GPMC_CS_NUM)
360 gpmc_cs_map &= ~(1 << cs);
361 gpmc_cs_map |= (reserved ? 1 : 0) << cs;
366 int gpmc_cs_reserved(int cs)
368 if (cs > GPMC_CS_NUM)
371 return gpmc_cs_map & (1 << cs);
374 static unsigned long gpmc_mem_align(unsigned long size)
378 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
379 order = GPMC_CHUNK_SHIFT - 1;
388 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
390 struct resource *res = &gpmc_cs_mem[cs];
393 size = gpmc_mem_align(size);
394 spin_lock(&gpmc_mem_lock);
396 res->end = base + size - 1;
397 r = request_resource(&gpmc_mem_root, res);
398 spin_unlock(&gpmc_mem_lock);
403 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
405 struct resource *res = &gpmc_cs_mem[cs];
408 if (cs > GPMC_CS_NUM)
411 size = gpmc_mem_align(size);
412 if (size > (1 << GPMC_SECTION_SHIFT))
415 spin_lock(&gpmc_mem_lock);
416 if (gpmc_cs_reserved(cs)) {
420 if (gpmc_cs_mem_enabled(cs))
421 r = adjust_resource(res, res->start & ~(size - 1), size);
423 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
428 gpmc_cs_enable_mem(cs, res->start, resource_size(res));
430 gpmc_cs_set_reserved(cs, 1);
432 spin_unlock(&gpmc_mem_lock);
435 EXPORT_SYMBOL(gpmc_cs_request);
437 void gpmc_cs_free(int cs)
439 spin_lock(&gpmc_mem_lock);
440 if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) {
441 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
443 spin_unlock(&gpmc_mem_lock);
446 gpmc_cs_disable_mem(cs);
447 release_resource(&gpmc_cs_mem[cs]);
448 gpmc_cs_set_reserved(cs, 0);
449 spin_unlock(&gpmc_mem_lock);
451 EXPORT_SYMBOL(gpmc_cs_free);
454 * gpmc_read_status - read access request to get the different gpmc status
458 int gpmc_read_status(int cmd)
460 int status = -EINVAL;
464 case GPMC_GET_IRQ_STATUS:
465 status = gpmc_read_reg(GPMC_IRQSTATUS);
468 case GPMC_PREFETCH_FIFO_CNT:
469 regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
470 status = GPMC_PREFETCH_STATUS_FIFO_CNT(regval);
473 case GPMC_PREFETCH_COUNT:
474 regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
475 status = GPMC_PREFETCH_STATUS_COUNT(regval);
478 case GPMC_STATUS_BUFFER:
479 regval = gpmc_read_reg(GPMC_STATUS);
480 /* 1 : buffer is available to write */
481 status = regval & GPMC_STATUS_BUFF_EMPTY;
485 printk(KERN_ERR "gpmc_read_status: Not supported\n");
489 EXPORT_SYMBOL(gpmc_read_status);
492 * gpmc_cs_configure - write request to configure gpmc
493 * @cs: chip select number
495 * @wval: value to write
496 * @return status of the operation
498 int gpmc_cs_configure(int cs, int cmd, int wval)
504 case GPMC_ENABLE_IRQ:
505 gpmc_write_reg(GPMC_IRQENABLE, wval);
508 case GPMC_SET_IRQ_STATUS:
509 gpmc_write_reg(GPMC_IRQSTATUS, wval);
513 regval = gpmc_read_reg(GPMC_CONFIG);
515 regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
517 regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */
518 gpmc_write_reg(GPMC_CONFIG, regval);
521 case GPMC_CONFIG_RDY_BSY:
522 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
524 regval |= WR_RD_PIN_MONITORING;
526 regval &= ~WR_RD_PIN_MONITORING;
527 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
530 case GPMC_CONFIG_DEV_SIZE:
531 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
533 /* clear 2 target bits */
534 regval &= ~GPMC_CONFIG1_DEVICESIZE(3);
536 /* set the proper value */
537 regval |= GPMC_CONFIG1_DEVICESIZE(wval);
539 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
542 case GPMC_CONFIG_DEV_TYPE:
543 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
544 regval |= GPMC_CONFIG1_DEVICETYPE(wval);
545 if (wval == GPMC_DEVICETYPE_NOR)
546 regval |= GPMC_CONFIG1_MUXADDDATA;
547 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
551 printk(KERN_ERR "gpmc_configure_cs: Not supported\n");
557 EXPORT_SYMBOL(gpmc_cs_configure);
560 * gpmc_nand_read - nand specific read access request
561 * @cs: chip select number
564 int gpmc_nand_read(int cs, int cmd)
570 rval = gpmc_cs_read_byte(cs, GPMC_CS_NAND_DATA);
574 printk(KERN_ERR "gpmc_read_nand_ctrl: Not supported\n");
578 EXPORT_SYMBOL(gpmc_nand_read);
581 * gpmc_nand_write - nand specific write request
582 * @cs: chip select number
584 * @wval: value to write
586 int gpmc_nand_write(int cs, int cmd, int wval)
591 case GPMC_NAND_COMMAND:
592 gpmc_cs_write_byte(cs, GPMC_CS_NAND_COMMAND, wval);
595 case GPMC_NAND_ADDRESS:
596 gpmc_cs_write_byte(cs, GPMC_CS_NAND_ADDRESS, wval);
600 gpmc_cs_write_byte(cs, GPMC_CS_NAND_DATA, wval);
603 printk(KERN_ERR "gpmc_write_nand_ctrl: Not supported\n");
608 EXPORT_SYMBOL(gpmc_nand_write);
613 * gpmc_prefetch_enable - configures and starts prefetch transfer
614 * @cs: cs (chip select) number
615 * @fifo_th: fifo threshold to be used for read/ write
616 * @dma_mode: dma mode enable (1) or disable (0)
617 * @u32_count: number of bytes to be transferred
618 * @is_write: prefetch read(0) or write post(1) mode
620 int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
621 unsigned int u32_count, int is_write)
624 if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) {
625 pr_err("gpmc: fifo threshold is not supported\n");
627 } else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
628 /* Set the amount of bytes to be prefetched */
629 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
631 /* Set dma/mpu mode, the prefetch read / post write and
632 * enable the engine. Set which cs is has requested for.
634 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) |
635 PREFETCH_FIFOTHRESHOLD(fifo_th) |
637 (dma_mode << DMA_MPU_MODE) |
640 /* Start the prefetch engine */
641 gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1);
648 EXPORT_SYMBOL(gpmc_prefetch_enable);
651 * gpmc_prefetch_reset - disables and stops the prefetch engine
653 int gpmc_prefetch_reset(int cs)
657 /* check if the same module/cs is trying to reset */
658 config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
659 if (((config1 >> CS_NUM_SHIFT) & 0x7) != cs)
662 /* Stop the PFPW engine */
663 gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0);
665 /* Reset/disable the PFPW engine */
666 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0);
670 EXPORT_SYMBOL(gpmc_prefetch_reset);
672 static void __init gpmc_mem_init(void)
675 unsigned long boot_rom_space = 0;
677 /* never allocate the first page, to facilitate bug detection;
678 * even if we didn't boot from ROM.
680 boot_rom_space = BOOT_ROM_SPACE;
681 /* In apollon the CS0 is mapped as 0x0000 0000 */
682 if (machine_is_omap_apollon())
684 gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
685 gpmc_mem_root.end = GPMC_MEM_END;
687 /* Reserve all regions that has been set up by bootloader */
688 for (cs = 0; cs < GPMC_CS_NUM; cs++) {
691 if (!gpmc_cs_mem_enabled(cs))
693 gpmc_cs_get_memconf(cs, &base, &size);
694 if (gpmc_cs_insert_mem(cs, base, size) < 0)
699 static int __init gpmc_init(void)
702 int cs, ret = -EINVAL;
706 if (cpu_is_omap24xx()) {
708 if (cpu_is_omap2420())
709 l = OMAP2420_GPMC_BASE;
711 l = OMAP34XX_GPMC_BASE;
712 gpmc_irq = INT_34XX_GPMC_IRQ;
713 } else if (cpu_is_omap34xx()) {
715 l = OMAP34XX_GPMC_BASE;
716 gpmc_irq = INT_34XX_GPMC_IRQ;
717 } else if (cpu_is_omap44xx()) {
719 l = OMAP44XX_GPMC_BASE;
720 gpmc_irq = OMAP44XX_IRQ_GPMC;
726 gpmc_l3_clk = clk_get(NULL, ck);
727 if (IS_ERR(gpmc_l3_clk)) {
728 printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
732 gpmc_base = ioremap(l, SZ_4K);
734 clk_put(gpmc_l3_clk);
735 printk(KERN_ERR "Could not get GPMC register memory\n");
739 clk_enable(gpmc_l3_clk);
741 l = gpmc_read_reg(GPMC_REVISION);
742 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
743 /* Set smart idle mode and automatic L3 clock gating */
744 l = gpmc_read_reg(GPMC_SYSCONFIG);
746 l |= (0x02 << 3) | (1 << 0);
747 gpmc_write_reg(GPMC_SYSCONFIG, l);
750 /* initalize the irq_chained */
751 irq = OMAP_GPMC_IRQ_BASE;
752 for (cs = 0; cs < GPMC_CS_NUM; cs++) {
753 irq_set_chip_and_handler(irq, &dummy_irq_chip,
755 set_irq_flags(irq, IRQF_VALID);
759 ret = request_irq(gpmc_irq,
760 gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base);
762 pr_err("gpmc: irq-%d could not claim: err %d\n",
766 postcore_initcall(gpmc_init);
768 static irqreturn_t gpmc_handle_irq(int irq, void *dev)
772 /* check cs to invoke the irq */
773 cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7;
774 if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END)
775 generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs);
780 #ifdef CONFIG_ARCH_OMAP3
781 static struct omap3_gpmc_regs gpmc_context;
783 void omap3_gpmc_save_context(void)
787 gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
788 gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
789 gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
790 gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
791 gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
792 gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
793 gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
794 for (i = 0; i < GPMC_CS_NUM; i++) {
795 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
796 if (gpmc_context.cs_context[i].is_valid) {
797 gpmc_context.cs_context[i].config1 =
798 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
799 gpmc_context.cs_context[i].config2 =
800 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
801 gpmc_context.cs_context[i].config3 =
802 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
803 gpmc_context.cs_context[i].config4 =
804 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
805 gpmc_context.cs_context[i].config5 =
806 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
807 gpmc_context.cs_context[i].config6 =
808 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
809 gpmc_context.cs_context[i].config7 =
810 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
815 void omap3_gpmc_restore_context(void)
819 gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
820 gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
821 gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
822 gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
823 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
824 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
825 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
826 for (i = 0; i < GPMC_CS_NUM; i++) {
827 if (gpmc_context.cs_context[i].is_valid) {
828 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
829 gpmc_context.cs_context[i].config1);
830 gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
831 gpmc_context.cs_context[i].config2);
832 gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
833 gpmc_context.cs_context[i].config3);
834 gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
835 gpmc_context.cs_context[i].config4);
836 gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
837 gpmc_context.cs_context[i].config5);
838 gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
839 gpmc_context.cs_context[i].config6);
840 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
841 gpmc_context.cs_context[i].config7);
845 #endif /* CONFIG_ARCH_OMAP3 */
848 * gpmc_enable_hwecc - enable hardware ecc functionality
849 * @cs: chip select number
850 * @mode: read/write mode
851 * @dev_width: device bus width(1 for x16, 0 for x8)
852 * @ecc_size: bytes for which ECC will be generated
854 int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size)
858 /* check if ecc module is in used */
859 if (gpmc_ecc_used != -EINVAL)
864 /* clear ecc and enable bits */
865 val = ((0x00000001<<8) | 0x00000001);
866 gpmc_write_reg(GPMC_ECC_CONTROL, val);
868 /* program ecc and result sizes */
869 val = ((((ecc_size >> 1) - 1) << 22) | (0x0000000F));
870 gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, val);
874 gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
876 case GPMC_ECC_READSYN:
877 gpmc_write_reg(GPMC_ECC_CONTROL, 0x100);
880 gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
883 printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode);
887 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
888 val = (dev_width << 7) | (cs << 1) | (0x1);
889 gpmc_write_reg(GPMC_ECC_CONFIG, val);
892 EXPORT_SYMBOL_GPL(gpmc_enable_hwecc);
895 * gpmc_calculate_ecc - generate non-inverted ecc bytes
896 * @cs: chip select number
897 * @dat: data pointer over which ecc is computed
898 * @ecc_code: ecc code buffer
900 * Using non-inverted ECC is considered ugly since writing a blank
901 * page (padding) will clear the ECC bytes. This is not a problem as long
902 * no one is trying to write data on the seemingly unused page. Reading
903 * an erased page will produce an ECC mismatch between generated and read
904 * ECC bytes that has to be dealt with separately.
906 int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code)
908 unsigned int val = 0x0;
910 if (gpmc_ecc_used != cs)
913 /* read ecc result */
914 val = gpmc_read_reg(GPMC_ECC1_RESULT);
915 *ecc_code++ = val; /* P128e, ..., P1e */
916 *ecc_code++ = val >> 16; /* P128o, ..., P1o */
917 /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
918 *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
920 gpmc_ecc_used = -EINVAL;
923 EXPORT_SYMBOL_GPL(gpmc_calculate_ecc);
925 #ifdef CONFIG_ARCH_OMAP3
928 * gpmc_init_hwecc_bch - initialize hardware BCH ecc functionality
929 * @cs: chip select number
930 * @nsectors: how many 512-byte sectors to process
931 * @nerrors: how many errors to correct per sector (4 or 8)
933 * This function must be executed before any call to gpmc_enable_hwecc_bch.
935 int gpmc_init_hwecc_bch(int cs, int nsectors, int nerrors)
937 /* check if ecc module is in use */
938 if (gpmc_ecc_used != -EINVAL)
941 /* support only OMAP3 class */
942 if (!cpu_is_omap34xx()) {
943 printk(KERN_ERR "BCH ecc is not supported on this CPU\n");
948 * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1.
949 * Other chips may be added if confirmed to work.
951 if ((nerrors == 4) &&
952 (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) {
953 printk(KERN_ERR "BCH 4-bit mode is not supported on this CPU\n");
959 printk(KERN_ERR "BCH cannot process %d sectors (max is 8)\n",
966 EXPORT_SYMBOL_GPL(gpmc_init_hwecc_bch);
969 * gpmc_enable_hwecc_bch - enable hardware BCH ecc functionality
970 * @cs: chip select number
971 * @mode: read/write mode
972 * @dev_width: device bus width(1 for x16, 0 for x8)
973 * @nsectors: how many 512-byte sectors to process
974 * @nerrors: how many errors to correct per sector (4 or 8)
976 int gpmc_enable_hwecc_bch(int cs, int mode, int dev_width, int nsectors,
981 /* check if ecc module is in use */
982 if (gpmc_ecc_used != -EINVAL)
987 /* clear ecc and enable bits */
988 gpmc_write_reg(GPMC_ECC_CONTROL, 0x1);
991 * When using BCH, sector size is hardcoded to 512 bytes.
992 * Here we are using wrapping mode 6 both for reading and writing, with:
993 * size0 = 0 (no additional protected byte in spare area)
994 * size1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
996 gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, (32 << 22) | (0 << 12));
998 /* BCH configuration */
999 val = ((1 << 16) | /* enable BCH */
1000 (((nerrors == 8) ? 1 : 0) << 12) | /* 8 or 4 bits */
1001 (0x06 << 8) | /* wrap mode = 6 */
1002 (dev_width << 7) | /* bus width */
1003 (((nsectors-1) & 0x7) << 4) | /* number of sectors */
1004 (cs << 1) | /* ECC CS */
1005 (0x1)); /* enable ECC */
1007 gpmc_write_reg(GPMC_ECC_CONFIG, val);
1008 gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
1011 EXPORT_SYMBOL_GPL(gpmc_enable_hwecc_bch);
1014 * gpmc_calculate_ecc_bch4 - Generate 7 ecc bytes per sector of 512 data bytes
1015 * @cs: chip select number
1016 * @dat: The pointer to data on which ecc is computed
1017 * @ecc: The ecc output buffer
1019 int gpmc_calculate_ecc_bch4(int cs, const u_char *dat, u_char *ecc)
1022 unsigned long nsectors, reg, val1, val2;
1024 if (gpmc_ecc_used != cs)
1027 nsectors = ((gpmc_read_reg(GPMC_ECC_CONFIG) >> 4) & 0x7) + 1;
1029 for (i = 0; i < nsectors; i++) {
1031 reg = GPMC_ECC_BCH_RESULT_0 + 16*i;
1033 /* Read hw-computed remainder */
1034 val1 = gpmc_read_reg(reg + 0);
1035 val2 = gpmc_read_reg(reg + 4);
1038 * Add constant polynomial to remainder, in order to get an ecc
1039 * sequence of 0xFFs for a buffer filled with 0xFFs; and
1040 * left-justify the resulting polynomial.
1042 *ecc++ = 0x28 ^ ((val2 >> 12) & 0xFF);
1043 *ecc++ = 0x13 ^ ((val2 >> 4) & 0xFF);
1044 *ecc++ = 0xcc ^ (((val2 & 0xF) << 4)|((val1 >> 28) & 0xF));
1045 *ecc++ = 0x39 ^ ((val1 >> 20) & 0xFF);
1046 *ecc++ = 0x96 ^ ((val1 >> 12) & 0xFF);
1047 *ecc++ = 0xac ^ ((val1 >> 4) & 0xFF);
1048 *ecc++ = 0x7f ^ ((val1 & 0xF) << 4);
1051 gpmc_ecc_used = -EINVAL;
1054 EXPORT_SYMBOL_GPL(gpmc_calculate_ecc_bch4);
1057 * gpmc_calculate_ecc_bch8 - Generate 13 ecc bytes per block of 512 data bytes
1058 * @cs: chip select number
1059 * @dat: The pointer to data on which ecc is computed
1060 * @ecc: The ecc output buffer
1062 int gpmc_calculate_ecc_bch8(int cs, const u_char *dat, u_char *ecc)
1065 unsigned long nsectors, reg, val1, val2, val3, val4;
1067 if (gpmc_ecc_used != cs)
1070 nsectors = ((gpmc_read_reg(GPMC_ECC_CONFIG) >> 4) & 0x7) + 1;
1072 for (i = 0; i < nsectors; i++) {
1074 reg = GPMC_ECC_BCH_RESULT_0 + 16*i;
1076 /* Read hw-computed remainder */
1077 val1 = gpmc_read_reg(reg + 0);
1078 val2 = gpmc_read_reg(reg + 4);
1079 val3 = gpmc_read_reg(reg + 8);
1080 val4 = gpmc_read_reg(reg + 12);
1083 * Add constant polynomial to remainder, in order to get an ecc
1084 * sequence of 0xFFs for a buffer filled with 0xFFs.
1086 *ecc++ = 0xef ^ (val4 & 0xFF);
1087 *ecc++ = 0x51 ^ ((val3 >> 24) & 0xFF);
1088 *ecc++ = 0x2e ^ ((val3 >> 16) & 0xFF);
1089 *ecc++ = 0x09 ^ ((val3 >> 8) & 0xFF);
1090 *ecc++ = 0xed ^ (val3 & 0xFF);
1091 *ecc++ = 0x93 ^ ((val2 >> 24) & 0xFF);
1092 *ecc++ = 0x9a ^ ((val2 >> 16) & 0xFF);
1093 *ecc++ = 0xc2 ^ ((val2 >> 8) & 0xFF);
1094 *ecc++ = 0x97 ^ (val2 & 0xFF);
1095 *ecc++ = 0x79 ^ ((val1 >> 24) & 0xFF);
1096 *ecc++ = 0xe5 ^ ((val1 >> 16) & 0xFF);
1097 *ecc++ = 0x24 ^ ((val1 >> 8) & 0xFF);
1098 *ecc++ = 0xb5 ^ (val1 & 0xFF);
1101 gpmc_ecc_used = -EINVAL;
1104 EXPORT_SYMBOL_GPL(gpmc_calculate_ecc_bch8);
1106 #endif /* CONFIG_ARCH_OMAP3 */