arch/arm/mach-omap2/cpuidle34xx.c

   1 /*
   2  * linux/arch/arm/mach-omap2/cpuidle34xx.c
   3  *
   4  * OMAP3 CPU IDLE Routines
   5  *
   6  * Copyright (C) 2008 Texas Instruments, Inc.
   7  * Rajendra Nayak <rnayak@ti.com>
   8  *
   9  * Copyright (C) 2007 Texas Instruments, Inc.
  10  * Karthik Dasu <karthik-dp@ti.com>
  11  *
  12  * Copyright (C) 2006 Nokia Corporation
  13  * Tony Lindgren <tony@atomide.com>
  14  *
  15  * Copyright (C) 2005 Texas Instruments, Inc.
  16  * Richard Woodruff <r-woodruff2@ti.com>
  17  *
  18  * Based on pm.c for omap2
  19  *
  20  * This program is free software; you can redistribute it and/or modify
  21  * it under the terms of the GNU General Public License version 2 as
  22  * published by the Free Software Foundation.
  23  */
  24
  25 #include <linux/sched.h>
  26 #include <linux/cpuidle.h>
  27 #include <linux/export.h>
  28 #include <linux/cpu_pm.h>
  29
  30 #include <plat/prcm.h>
  31 #include <plat/irqs.h>
  32 #include "powerdomain.h"
  33 #include "clockdomain.h"
  34
  35 #include "pm.h"
  36 #include "control.h"
  37 #include "common.h"
  38
  39 #ifdef CONFIG_CPU_IDLE
  40
  41 /* Mach specific information to be recorded in the C-state driver_data */
  42 struct omap3_idle_statedata {
  43         u32 mpu_state;
  44         u32 core_state;
  45 };
  46
  47 static struct omap3_idle_statedata omap3_idle_data[] = {
  48         {
  49                 .mpu_state = PWRDM_POWER_ON,
  50                 .core_state = PWRDM_POWER_ON,
  51         },
  52         {
  53                 .mpu_state = PWRDM_POWER_ON,
  54                 .core_state = PWRDM_POWER_ON,
  55         },
  56         {
  57                 .mpu_state = PWRDM_POWER_RET,
  58                 .core_state = PWRDM_POWER_ON,
  59         },
  60         {
  61                 .mpu_state = PWRDM_POWER_OFF,
  62                 .core_state = PWRDM_POWER_ON,
  63         },
  64         {
  65                 .mpu_state = PWRDM_POWER_RET,
  66                 .core_state = PWRDM_POWER_RET,
  67         },
  68         {
  69                 .mpu_state = PWRDM_POWER_OFF,
  70                 .core_state = PWRDM_POWER_RET,
  71         },
  72         {
  73                 .mpu_state = PWRDM_POWER_OFF,
  74                 .core_state = PWRDM_POWER_OFF,
  75         },
  76 };
  77
  78 static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
  79
  80 static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
  81                                 struct clockdomain *clkdm)
  82 {
  83         clkdm_allow_idle(clkdm);
  84         return 0;
  85 }
  86
  87 static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
  88                                 struct clockdomain *clkdm)
  89 {
  90         clkdm_deny_idle(clkdm);
  91         return 0;
  92 }
  93
  94 static int __omap3_enter_idle(struct cpuidle_device *dev,
  95                                 struct cpuidle_driver *drv,
  96                                 int index)
  97 {
  98         struct omap3_idle_statedata *cx = &omap3_idle_data[index];
  99         u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
 100
 101         local_fiq_disable();
 102
 103         pwrdm_set_next_pwrst(mpu_pd, mpu_state);
 104         pwrdm_set_next_pwrst(core_pd, core_state);
 105
 106         if (omap_irq_pending() || need_resched())
 107                 goto return_sleep_time;
 108
 109         /* Deny idle for C1 */
 110         if (index == 0) {
 111                 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
 112                 pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
 113         }
 114
 115         /*
 116          * Call idle CPU PM enter notifier chain so that
 117          * VFP context is saved.
 118          */
 119         if (mpu_state == PWRDM_POWER_OFF)
 120                 cpu_pm_enter();
 121
 122         /* Execute ARM wfi */
 123         omap_sram_idle();
 124
 125         /*
 126          * Call idle CPU PM enter notifier chain to restore
 127          * VFP context.
 128          */
 129         if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
 130                 cpu_pm_exit();
 131
 132         /* Re-allow idle for C1 */
 133         if (index == 0) {
 134                 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
 135                 pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
 136         }
 137
 138 return_sleep_time:
 139
 140         local_fiq_enable();
 141
 142         return index;
 143 }
 144
 145 /**
 146  * omap3_enter_idle - Programs OMAP3 to enter the specified state
 147  * @dev: cpuidle device
 148  * @drv: cpuidle driver
 149  * @index: the index of state to be entered
 150  *
 151  * Called from the CPUidle framework to program the device to the
 152  * specified target state selected by the governor.
 153  */
 154 static inline int omap3_enter_idle(struct cpuidle_device *dev,
 155                                 struct cpuidle_driver *drv,
 156                                 int index)
 157 {
 158         return cpuidle_wrap_enter(dev, drv, index, __omap3_enter_idle);
 159 }
 160
 161 /**
 162  * next_valid_state - Find next valid C-state
 163  * @dev: cpuidle device
 164  * @drv: cpuidle driver
 165  * @index: Index of currently selected c-state
 166  *
 167  * If the state corresponding to index is valid, index is returned back
 168  * to the caller. Else, this function searches for a lower c-state which is
 169  * still valid (as defined in omap3_power_states[]) and returns its index.
 170  *
 171  * A state is valid if the 'valid' field is enabled and
 172  * if it satisfies the enable_off_mode condition.
 173  */
 174 static int next_valid_state(struct cpuidle_device *dev,
 175                             struct cpuidle_driver *drv, int index)
 176 {
 177         struct omap3_idle_statedata *cx = &omap3_idle_data[index];
 178         u32 mpu_deepest_state = PWRDM_POWER_RET;
 179         u32 core_deepest_state = PWRDM_POWER_RET;
 180         int idx;
 181         int next_index = -1;
 182
 183         if (enable_off_mode) {
 184                 mpu_deepest_state = PWRDM_POWER_OFF;
 185                 /*
 186                  * Erratum i583: valable for ES rev < Es1.2 on 3630.
 187                  * CORE OFF mode is not supported in a stable form, restrict
 188                  * instead the CORE state to RET.
 189                  */
 190                 if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
 191                         core_deepest_state = PWRDM_POWER_OFF;
 192         }
 193
 194         /* Check if current state is valid */
 195         if ((cx->mpu_state >= mpu_deepest_state) &&
 196             (cx->core_state >= core_deepest_state))
 197                 return index;
 198
 199         /*
 200          * Drop to next valid state.
 201          * Start search from the next (lower) state.
 202          */
 203         for (idx = index - 1; idx >= 0; idx--) {
 204                 cx =  &omap3_idle_data[idx];
 205                 if ((cx->mpu_state >= mpu_deepest_state) &&
 206                     (cx->core_state >= core_deepest_state)) {
 207                         next_index = idx;
 208                         break;
 209                 }
 210         }
 211
 212         /*
 213          * C1 is always valid.
 214          * So, no need to check for 'next_index == -1' outside
 215          * this loop.
 216          */
 217
 218         return next_index;
 219 }
 220
 221 /**
 222  * omap3_enter_idle_bm - Checks for any bus activity
 223  * @dev: cpuidle device
 224  * @drv: cpuidle driver
 225  * @index: array index of target state to be programmed
 226  *
 227  * This function checks for any pending activity and then programs
 228  * the device to the specified or a safer state.
 229  */
 230 static int omap3_enter_idle_bm(struct cpuidle_device *dev,
 231                                 struct cpuidle_driver *drv,
 232                                int index)
 233 {
 234         int new_state_idx;
 235         u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
 236         struct omap3_idle_statedata *cx;
 237         int ret;
 238
 239         /*
 240          * Prevent idle completely if CAM is active.
 241          * CAM does not have wakeup capability in OMAP3.
 242          */
 243         cam_state = pwrdm_read_pwrst(cam_pd);
 244         if (cam_state == PWRDM_POWER_ON) {
 245                 new_state_idx = drv->safe_state_index;
 246                 goto select_state;
 247         }
 248
 249         /*
 250          * FIXME: we currently manage device-specific idle states
 251          *        for PER and CORE in combination with CPU-specific
 252          *        idle states.  This is wrong, and device-specific
 253          *        idle management needs to be separated out into
 254          *        its own code.
 255          */
 256
 257         /*
 258          * Prevent PER off if CORE is not in retention or off as this
 259          * would disable PER wakeups completely.
 260          */
 261         cx = &omap3_idle_data[index];
 262         core_next_state = cx->core_state;
 263         per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
 264         if ((per_next_state == PWRDM_POWER_OFF) &&
 265             (core_next_state > PWRDM_POWER_RET))
 266                 per_next_state = PWRDM_POWER_RET;
 267
 268         /* Are we changing PER target state? */
 269         if (per_next_state != per_saved_state)
 270                 pwrdm_set_next_pwrst(per_pd, per_next_state);
 271
 272         new_state_idx = next_valid_state(dev, drv, index);
 273
 274 select_state:
 275         ret = omap3_enter_idle(dev, drv, new_state_idx);
 276
 277         /* Restore original PER state if it was modified */
 278         if (per_next_state != per_saved_state)
 279                 pwrdm_set_next_pwrst(per_pd, per_saved_state);
 280
 281         return ret;
 282 }
 283
 284 DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
 285
 286 struct cpuidle_driver omap3_idle_driver = {
 287         .name =         "omap3_idle",
 288         .owner =        THIS_MODULE,
 289         .states = {
 290                 {
 291                         .enter            = omap3_enter_idle,
 292                         .exit_latency     = 2 + 2,
 293                         .target_residency = 5,
 294                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 295                         .name             = "C1",
 296                         .desc             = "MPU ON + CORE ON",
 297                 },
 298                 {
 299                         .enter            = omap3_enter_idle_bm,
 300                         .exit_latency     = 10 + 10,
 301                         .target_residency = 30,
 302                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 303                         .name             = "C2",
 304                         .desc             = "MPU ON + CORE ON",
 305                 },
 306                 {
 307                         .enter            = omap3_enter_idle_bm,
 308                         .exit_latency     = 50 + 50,
 309                         .target_residency = 300,
 310                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 311                         .name             = "C3",
 312                         .desc             = "MPU RET + CORE ON",
 313                 },
 314                 {
 315                         .enter            = omap3_enter_idle_bm,
 316                         .exit_latency     = 1500 + 1800,
 317                         .target_residency = 4000,
 318                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 319                         .name             = "C4",
 320                         .desc             = "MPU OFF + CORE ON",
 321                 },
 322                 {
 323                         .enter            = omap3_enter_idle_bm,
 324                         .exit_latency     = 2500 + 7500,
 325                         .target_residency = 12000,
 326                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 327                         .name             = "C5",
 328                         .desc             = "MPU RET + CORE RET",
 329                 },
 330                 {
 331                         .enter            = omap3_enter_idle_bm,
 332                         .exit_latency     = 3000 + 8500,
 333                         .target_residency = 15000,
 334                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 335                         .name             = "C6",
 336                         .desc             = "MPU OFF + CORE RET",
 337                 },
 338                 {
 339                         .enter            = omap3_enter_idle_bm,
 340                         .exit_latency     = 10000 + 30000,
 341                         .target_residency = 30000,
 342                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 343                         .name             = "C7",
 344                         .desc             = "MPU OFF + CORE OFF",
 345                 },
 346         },
 347         .state_count = ARRAY_SIZE(omap3_idle_data),
 348         .safe_state_index = 0,
 349 };
 350
 351 /**
 352  * omap3_idle_init - Init routine for OMAP3 idle
 353  *
 354  * Registers the OMAP3 specific cpuidle driver to the cpuidle
 355  * framework with the valid set of states.
 356  */
 357 int __init omap3_idle_init(void)
 358 {
 359         struct cpuidle_device *dev;
 360
 361         mpu_pd = pwrdm_lookup("mpu_pwrdm");
 362         core_pd = pwrdm_lookup("core_pwrdm");
 363         per_pd = pwrdm_lookup("per_pwrdm");
 364         cam_pd = pwrdm_lookup("cam_pwrdm");
 365
 366         if (!mpu_pd || !core_pd || !per_pd || !cam_pd)
 367                 return -ENODEV;
 368
 369         cpuidle_register_driver(&omap3_idle_driver);
 370
 371         dev = &per_cpu(omap3_idle_dev, smp_processor_id());
 372         dev->cpu = 0;
 373
 374         if (cpuidle_register_device(dev)) {
 375                 printk(KERN_ERR "%s: CPUidle register device failed\n",
 376                        __func__);
 377                 return -EIO;
 378         }
 379
 380         return 0;
 381 }
 382 #else
 383 int __init omap3_idle_init(void)
 384 {
 385         return 0;
 386 }
 387 #endif /* CONFIG_CPU_IDLE */