arch/arm/mach-omap2/clock3xxx_data.c

   1 /*
   2  * OMAP3 clock data
   3  *
   4  * Copyright (C) 2007-2010, 2012 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2011 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/clk.h>
  21 #include <linux/list.h>
  22 #include <linux/io.h>
  23
  24 #include <plat/clkdev_omap.h>
  25
  26 #include "soc.h"
  27 #include "iomap.h"
  28 #include "clock.h"
  29 #include "clock3xxx.h"
  30 #include "clock34xx.h"
  31 #include "clock36xx.h"
  32 #include "clock3517.h"
  33 #include "cm2xxx_3xxx.h"
  34 #include "cm-regbits-34xx.h"
  35 #include "prm2xxx_3xxx.h"
  36 #include "prm-regbits-34xx.h"
  37 #include "control.h"
  38
  39 /*
  40  * clocks
  41  */
  42
  43 #define OMAP_CM_REGADDR         OMAP34XX_CM_REGADDR
  44
  45 /* Maximum DPLL multiplier, divider values for OMAP3 */
  46 #define OMAP3_MAX_DPLL_MULT             2047
  47 #define OMAP3630_MAX_JTYPE_DPLL_MULT    4095
  48 #define OMAP3_MAX_DPLL_DIV              128
  49
  50 /*
  51  * DPLL1 supplies clock to the MPU.
  52  * DPLL2 supplies clock to the IVA2.
  53  * DPLL3 supplies CORE domain clocks.
  54  * DPLL4 supplies peripheral clocks.
  55  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  56  */
  57
  58 /* Forward declarations for DPLL bypass clocks */
  59 static struct clk dpll1_fck;
  60 static struct clk dpll2_fck;
  61
  62 /* PRM CLOCKS */
  63
  64 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  65 static struct clk omap_32k_fck = {
  66         .name           = "omap_32k_fck",
  67         .ops            = &clkops_null,
  68         .rate           = 32768,
  69 };
  70
  71 static struct clk secure_32k_fck = {
  72         .name           = "secure_32k_fck",
  73         .ops            = &clkops_null,
  74         .rate           = 32768,
  75 };
  76
  77 /* Virtual source clocks for osc_sys_ck */
  78 static struct clk virt_12m_ck = {
  79         .name           = "virt_12m_ck",
  80         .ops            = &clkops_null,
  81         .rate           = 12000000,
  82 };
  83
  84 static struct clk virt_13m_ck = {
  85         .name           = "virt_13m_ck",
  86         .ops            = &clkops_null,
  87         .rate           = 13000000,
  88 };
  89
  90 static struct clk virt_16_8m_ck = {
  91         .name           = "virt_16_8m_ck",
  92         .ops            = &clkops_null,
  93         .rate           = 16800000,
  94 };
  95
  96 static struct clk virt_38_4m_ck = {
  97         .name           = "virt_38_4m_ck",
  98         .ops            = &clkops_null,
  99         .rate           = 38400000,
 100 };
 101
 102 static const struct clksel_rate osc_sys_12m_rates[] = {
 103         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 104         { .div = 0 }
 105 };
 106
 107 static const struct clksel_rate osc_sys_13m_rates[] = {
 108         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 109         { .div = 0 }
 110 };
 111
 112 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 113         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
 114         { .div = 0 }
 115 };
 116
 117 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 118         { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
 119         { .div = 0 }
 120 };
 121
 122 static const struct clksel_rate osc_sys_26m_rates[] = {
 123         { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
 124         { .div = 0 }
 125 };
 126
 127 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 128         { .div = 1, .val = 4, .flags = RATE_IN_3XXX },
 129         { .div = 0 }
 130 };
 131
 132 static const struct clksel osc_sys_clksel[] = {
 133         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 134         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 135         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 136         { .parent = &virt_19200000_ck, .rates = osc_sys_19_2m_rates },
 137         { .parent = &virt_26000000_ck,   .rates = osc_sys_26m_rates },
 138         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 139         { .parent = NULL },
 140 };
 141
 142 /* Oscillator clock */
 143 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 144 static struct clk osc_sys_ck = {
 145         .name           = "osc_sys_ck",
 146         .ops            = &clkops_null,
 147         .init           = &omap2_init_clksel_parent,
 148         .clksel_reg     = OMAP3430_PRM_CLKSEL,
 149         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 150         .clksel         = osc_sys_clksel,
 151         /* REVISIT: deal with autoextclkmode? */
 152         .recalc         = &omap2_clksel_recalc,
 153 };
 154
 155 static const struct clksel_rate div2_rates[] = {
 156         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 157         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 158         { .div = 0 }
 159 };
 160
 161 static const struct clksel sys_clksel[] = {
 162         { .parent = &osc_sys_ck, .rates = div2_rates },
 163         { .parent = NULL }
 164 };
 165
 166 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 167 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 168 static struct clk sys_ck = {
 169         .name           = "sys_ck",
 170         .ops            = &clkops_null,
 171         .parent         = &osc_sys_ck,
 172         .init           = &omap2_init_clksel_parent,
 173         .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
 174         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 175         .clksel         = sys_clksel,
 176         .recalc         = &omap2_clksel_recalc,
 177 };
 178
 179 static struct clk sys_altclk = {
 180         .name           = "sys_altclk",
 181         .ops            = &clkops_null,
 182 };
 183
 184 /* Optional external clock input for some McBSPs */
 185 static struct clk mcbsp_clks = {
 186         .name           = "mcbsp_clks",
 187         .ops            = &clkops_null,
 188 };
 189
 190 /* PRM EXTERNAL CLOCK OUTPUT */
 191
 192 static struct clk sys_clkout1 = {
 193         .name           = "sys_clkout1",
 194         .ops            = &clkops_omap2_dflt,
 195         .parent         = &osc_sys_ck,
 196         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
 197         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 198         .recalc         = &followparent_recalc,
 199 };
 200
 201 /* DPLLS */
 202
 203 /* CM CLOCKS */
 204
 205 static const struct clksel_rate div16_dpll_rates[] = {
 206         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 207         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 208         { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
 209         { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
 210         { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
 211         { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
 212         { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
 213         { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
 214         { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
 215         { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
 216         { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
 217         { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
 218         { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
 219         { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
 220         { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
 221         { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
 222         { .div = 0 }
 223 };
 224
 225 static const struct clksel_rate dpll4_rates[] = {
 226         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 227         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 228         { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
 229         { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
 230         { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
 231         { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
 232         { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
 233         { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
 234         { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
 235         { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
 236         { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
 237         { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
 238         { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
 239         { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
 240         { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
 241         { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
 242         { .div = 17, .val = 17, .flags = RATE_IN_36XX },
 243         { .div = 18, .val = 18, .flags = RATE_IN_36XX },
 244         { .div = 19, .val = 19, .flags = RATE_IN_36XX },
 245         { .div = 20, .val = 20, .flags = RATE_IN_36XX },
 246         { .div = 21, .val = 21, .flags = RATE_IN_36XX },
 247         { .div = 22, .val = 22, .flags = RATE_IN_36XX },
 248         { .div = 23, .val = 23, .flags = RATE_IN_36XX },
 249         { .div = 24, .val = 24, .flags = RATE_IN_36XX },
 250         { .div = 25, .val = 25, .flags = RATE_IN_36XX },
 251         { .div = 26, .val = 26, .flags = RATE_IN_36XX },
 252         { .div = 27, .val = 27, .flags = RATE_IN_36XX },
 253         { .div = 28, .val = 28, .flags = RATE_IN_36XX },
 254         { .div = 29, .val = 29, .flags = RATE_IN_36XX },
 255         { .div = 30, .val = 30, .flags = RATE_IN_36XX },
 256         { .div = 31, .val = 31, .flags = RATE_IN_36XX },
 257         { .div = 32, .val = 32, .flags = RATE_IN_36XX },
 258         { .div = 0 }
 259 };
 260
 261 /* DPLL1 */
 262 /* MPU clock source */
 263 /* Type: DPLL */
 264 static struct dpll_data dpll1_dd = {
 265         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 266         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 267         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 268         .clk_bypass     = &dpll1_fck,
 269         .clk_ref        = &sys_ck,
 270         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 271         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 272         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 273         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 274         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 275         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 276         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 277         .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 278         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 279         .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 280         .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
 281         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 282         .min_divider    = 1,
 283         .max_divider    = OMAP3_MAX_DPLL_DIV,
 284 };
 285
 286 static struct clk dpll1_ck = {
 287         .name           = "dpll1_ck",
 288         .ops            = &clkops_omap3_noncore_dpll_ops,
 289         .parent         = &sys_ck,
 290         .dpll_data      = &dpll1_dd,
 291         .round_rate     = &omap2_dpll_round_rate,
 292         .set_rate       = &omap3_noncore_dpll_set_rate,
 293         .clkdm_name     = "dpll1_clkdm",
 294         .recalc         = &omap3_dpll_recalc,
 295 };
 296
 297 /*
 298  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 299  * DPLL isn't bypassed.
 300  */
 301 static struct clk dpll1_x2_ck = {
 302         .name           = "dpll1_x2_ck",
 303         .ops            = &clkops_null,
 304         .parent         = &dpll1_ck,
 305         .clkdm_name     = "dpll1_clkdm",
 306         .recalc         = &omap3_clkoutx2_recalc,
 307 };
 308
 309 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 310 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 311         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 312         { .parent = NULL }
 313 };
 314
 315 /*
 316  * Does not exist in the TRM - needed to separate the M2 divider from
 317  * bypass selection in mpu_ck
 318  */
 319 static struct clk dpll1_x2m2_ck = {
 320         .name           = "dpll1_x2m2_ck",
 321         .ops            = &clkops_null,
 322         .parent         = &dpll1_x2_ck,
 323         .init           = &omap2_init_clksel_parent,
 324         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 325         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 326         .clksel         = div16_dpll1_x2m2_clksel,
 327         .clkdm_name     = "dpll1_clkdm",
 328         .recalc         = &omap2_clksel_recalc,
 329 };
 330
 331 /* DPLL2 */
 332 /* IVA2 clock source */
 333 /* Type: DPLL */
 334
 335 static struct dpll_data dpll2_dd = {
 336         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 337         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 338         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 339         .clk_bypass     = &dpll2_fck,
 340         .clk_ref        = &sys_ck,
 341         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 342         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 343         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 344         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 345                                 (1 << DPLL_LOW_POWER_BYPASS),
 346         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 347         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 348         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 349         .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 350         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 351         .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 352         .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
 353         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 354         .min_divider    = 1,
 355         .max_divider    = OMAP3_MAX_DPLL_DIV,
 356 };
 357
 358 static struct clk dpll2_ck = {
 359         .name           = "dpll2_ck",
 360         .ops            = &clkops_omap3_noncore_dpll_ops,
 361         .parent         = &sys_ck,
 362         .dpll_data      = &dpll2_dd,
 363         .round_rate     = &omap2_dpll_round_rate,
 364         .set_rate       = &omap3_noncore_dpll_set_rate,
 365         .clkdm_name     = "dpll2_clkdm",
 366         .recalc         = &omap3_dpll_recalc,
 367 };
 368
 369 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 370         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 371         { .parent = NULL }
 372 };
 373
 374 /*
 375  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 376  * or CLKOUTX2. CLKOUT seems most plausible.
 377  */
 378 static struct clk dpll2_m2_ck = {
 379         .name           = "dpll2_m2_ck",
 380         .ops            = &clkops_null,
 381         .parent         = &dpll2_ck,
 382         .init           = &omap2_init_clksel_parent,
 383         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
 384                                           OMAP3430_CM_CLKSEL2_PLL),
 385         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 386         .clksel         = div16_dpll2_m2x2_clksel,
 387         .clkdm_name     = "dpll2_clkdm",
 388         .recalc         = &omap2_clksel_recalc,
 389 };
 390
 391 /*
 392  * DPLL3
 393  * Source clock for all interfaces and for some device fclks
 394  * REVISIT: Also supports fast relock bypass - not included below
 395  */
 396 static struct dpll_data dpll3_dd = {
 397         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 398         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 399         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 400         .clk_bypass     = &sys_ck,
 401         .clk_ref        = &sys_ck,
 402         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
 403         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 404         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 405         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 406         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 407         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 408         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 409         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 410         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 411         .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
 412         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 413         .min_divider    = 1,
 414         .max_divider    = OMAP3_MAX_DPLL_DIV,
 415 };
 416
 417 static struct clk dpll3_ck = {
 418         .name           = "dpll3_ck",
 419         .ops            = &clkops_omap3_core_dpll_ops,
 420         .parent         = &sys_ck,
 421         .dpll_data      = &dpll3_dd,
 422         .round_rate     = &omap2_dpll_round_rate,
 423         .clkdm_name     = "dpll3_clkdm",
 424         .recalc         = &omap3_dpll_recalc,
 425 };
 426
 427 /*
 428  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 429  * DPLL isn't bypassed
 430  */
 431 static struct clk dpll3_x2_ck = {
 432         .name           = "dpll3_x2_ck",
 433         .ops            = &clkops_null,
 434         .parent         = &dpll3_ck,
 435         .clkdm_name     = "dpll3_clkdm",
 436         .recalc         = &omap3_clkoutx2_recalc,
 437 };
 438
 439 static const struct clksel_rate div31_dpll3_rates[] = {
 440         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 441         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 442         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS_36XX },
 443         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS_36XX },
 444         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
 445         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS_36XX },
 446         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS_36XX },
 447         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS_36XX },
 448         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS_36XX },
 449         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS_36XX },
 450         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS_36XX },
 451         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS_36XX },
 452         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS_36XX },
 453         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS_36XX },
 454         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS_36XX },
 455         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS_36XX },
 456         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS_36XX },
 457         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS_36XX },
 458         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS_36XX },
 459         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS_36XX },
 460         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS_36XX },
 461         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS_36XX },
 462         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS_36XX },
 463         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS_36XX },
 464         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS_36XX },
 465         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS_36XX },
 466         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS_36XX },
 467         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS_36XX },
 468         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS_36XX },
 469         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS_36XX },
 470         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS_36XX },
 471         { .div = 0 },
 472 };
 473
 474 static const struct clksel div31_dpll3m2_clksel[] = {
 475         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 476         { .parent = NULL }
 477 };
 478
 479 /* DPLL3 output M2 - primary control point for CORE speed */
 480 static struct clk dpll3_m2_ck = {
 481         .name           = "dpll3_m2_ck",
 482         .ops            = &clkops_null,
 483         .parent         = &dpll3_ck,
 484         .init           = &omap2_init_clksel_parent,
 485         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 486         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 487         .clksel         = div31_dpll3m2_clksel,
 488         .clkdm_name     = "dpll3_clkdm",
 489         .round_rate     = &omap2_clksel_round_rate,
 490         .set_rate       = &omap3_core_dpll_m2_set_rate,
 491         .recalc         = &omap2_clksel_recalc,
 492 };
 493
 494 static struct clk core_ck = {
 495         .name           = "core_ck",
 496         .ops            = &clkops_null,
 497         .parent         = &dpll3_m2_ck,
 498         .recalc         = &followparent_recalc,
 499 };
 500
 501 static struct clk dpll3_m2x2_ck = {
 502         .name           = "dpll3_m2x2_ck",
 503         .ops            = &clkops_null,
 504         .parent         = &dpll3_m2_ck,
 505         .clkdm_name     = "dpll3_clkdm",
 506         .recalc         = &omap3_clkoutx2_recalc,
 507 };
 508
 509 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 510 static const struct clksel div16_dpll3_clksel[] = {
 511         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 512         { .parent = NULL }
 513 };
 514
 515 /* This virtual clock is the source for dpll3_m3x2_ck */
 516 static struct clk dpll3_m3_ck = {
 517         .name           = "dpll3_m3_ck",
 518         .ops            = &clkops_null,
 519         .parent         = &dpll3_ck,
 520         .init           = &omap2_init_clksel_parent,
 521         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 522         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 523         .clksel         = div16_dpll3_clksel,
 524         .clkdm_name     = "dpll3_clkdm",
 525         .recalc         = &omap2_clksel_recalc,
 526 };
 527
 528 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 529 static struct clk dpll3_m3x2_ck = {
 530         .name           = "dpll3_m3x2_ck",
 531         .ops            = &clkops_omap2_dflt_wait,
 532         .parent         = &dpll3_m3_ck,
 533         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 534         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 535         .flags          = INVERT_ENABLE,
 536         .clkdm_name     = "dpll3_clkdm",
 537         .recalc         = &omap3_clkoutx2_recalc,
 538 };
 539
 540 static struct clk emu_core_alwon_ck = {
 541         .name           = "emu_core_alwon_ck",
 542         .ops            = &clkops_null,
 543         .parent         = &dpll3_m3x2_ck,
 544         .clkdm_name     = "dpll3_clkdm",
 545         .recalc         = &followparent_recalc,
 546 };
 547
 548 /* DPLL4 */
 549 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 550 /* Type: DPLL */
 551 static struct dpll_data dpll4_dd;
 552
 553 static struct dpll_data dpll4_dd_34xx __initdata = {
 554         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 555         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 556         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 557         .clk_bypass     = &sys_ck,
 558         .clk_ref        = &sys_ck,
 559         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 560         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 561         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 562         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 563         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 564         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 565         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 566         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 567         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 568         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 569         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 570         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 571         .min_divider    = 1,
 572         .max_divider    = OMAP3_MAX_DPLL_DIV,
 573 };
 574
 575 static struct dpll_data dpll4_dd_3630 __initdata = {
 576         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 577         .mult_mask      = OMAP3630_PERIPH_DPLL_MULT_MASK,
 578         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 579         .clk_bypass     = &sys_ck,
 580         .clk_ref        = &sys_ck,
 581         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 582         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 583         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 584         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 585         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 586         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 587         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 588         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 589         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 590         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 591         .dco_mask       = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK,
 592         .sddiv_mask     = OMAP3630_PERIPH_DPLL_SD_DIV_MASK,
 593         .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
 594         .min_divider    = 1,
 595         .max_divider    = OMAP3_MAX_DPLL_DIV,
 596         .flags          = DPLL_J_TYPE
 597 };
 598
 599 static struct clk dpll4_ck = {
 600         .name           = "dpll4_ck",
 601         .ops            = &clkops_omap3_noncore_dpll_ops,
 602         .parent         = &sys_ck,
 603         .dpll_data      = &dpll4_dd,
 604         .round_rate     = &omap2_dpll_round_rate,
 605         .set_rate       = &omap3_dpll4_set_rate,
 606         .clkdm_name     = "dpll4_clkdm",
 607         .recalc         = &omap3_dpll_recalc,
 608 };
 609
 610 /*
 611  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 612  * DPLL isn't bypassed --
 613  * XXX does this serve any downstream clocks?
 614  */
 615 static struct clk dpll4_x2_ck = {
 616         .name           = "dpll4_x2_ck",
 617         .ops            = &clkops_null,
 618         .parent         = &dpll4_ck,
 619         .clkdm_name     = "dpll4_clkdm",
 620         .recalc         = &omap3_clkoutx2_recalc,
 621 };
 622
 623 static const struct clksel dpll4_clksel[] = {
 624         { .parent = &dpll4_ck, .rates = dpll4_rates },
 625         { .parent = NULL }
 626 };
 627
 628 /* This virtual clock is the source for dpll4_m2x2_ck */
 629 static struct clk dpll4_m2_ck = {
 630         .name           = "dpll4_m2_ck",
 631         .ops            = &clkops_null,
 632         .parent         = &dpll4_ck,
 633         .init           = &omap2_init_clksel_parent,
 634         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 635         .clksel_mask    = OMAP3630_DIV_96M_MASK,
 636         .clksel         = dpll4_clksel,
 637         .clkdm_name     = "dpll4_clkdm",
 638         .recalc         = &omap2_clksel_recalc,
 639 };
 640
 641 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 642 static struct clk dpll4_m2x2_ck = {
 643         .name           = "dpll4_m2x2_ck",
 644         .ops            = &clkops_omap2_dflt_wait,
 645         .parent         = &dpll4_m2_ck,
 646         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 647         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 648         .flags          = INVERT_ENABLE,
 649         .clkdm_name     = "dpll4_clkdm",
 650         .recalc         = &omap3_clkoutx2_recalc,
 651 };
 652
 653 /*
 654  * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
 655  * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
 656  * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
 657  * CM_96K_(F)CLK.
 658  */
 659
 660 /* Adding 192MHz Clock node needed by SGX */
 661 static struct clk omap_192m_alwon_fck = {
 662         .name           = "omap_192m_alwon_fck",
 663         .ops            = &clkops_null,
 664         .parent         = &dpll4_m2x2_ck,
 665         .recalc         = &followparent_recalc,
 666 };
 667
 668 static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
 669         { .div = 1, .val = 1, .flags = RATE_IN_36XX },
 670         { .div = 2, .val = 2, .flags = RATE_IN_36XX },
 671         { .div = 0 }
 672 };
 673
 674 static const struct clksel omap_96m_alwon_fck_clksel[] = {
 675         { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
 676         { .parent = NULL }
 677 };
 678
 679 static const struct clksel_rate omap_96m_dpll_rates[] = {
 680         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 681         { .div = 0 }
 682 };
 683
 684 static const struct clksel_rate omap_96m_sys_rates[] = {
 685         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 686         { .div = 0 }
 687 };
 688
 689 static struct clk omap_96m_alwon_fck = {
 690         .name           = "omap_96m_alwon_fck",
 691         .ops            = &clkops_null,
 692         .parent         = &dpll4_m2x2_ck,
 693         .recalc         = &followparent_recalc,
 694 };
 695
 696 static struct clk omap_96m_alwon_fck_3630 = {
 697         .name           = "omap_96m_alwon_fck",
 698         .parent         = &omap_192m_alwon_fck,
 699         .init           = &omap2_init_clksel_parent,
 700         .ops            = &clkops_null,
 701         .recalc         = &omap2_clksel_recalc,
 702         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 703         .clksel_mask    = OMAP3630_CLKSEL_96M_MASK,
 704         .clksel         = omap_96m_alwon_fck_clksel
 705 };
 706
 707 static struct clk cm_96m_fck = {
 708         .name           = "cm_96m_fck",
 709         .ops            = &clkops_null,
 710         .parent         = &omap_96m_alwon_fck,
 711         .recalc         = &followparent_recalc,
 712 };
 713
 714 static const struct clksel omap_96m_fck_clksel[] = {
 715         { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
 716         { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
 717         { .parent = NULL }
 718 };
 719
 720 static struct clk omap_96m_fck = {
 721         .name           = "omap_96m_fck",
 722         .ops            = &clkops_null,
 723         .parent         = &sys_ck,
 724         .init           = &omap2_init_clksel_parent,
 725         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 726         .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
 727         .clksel         = omap_96m_fck_clksel,
 728         .recalc         = &omap2_clksel_recalc,
 729 };
 730
 731 /* This virtual clock is the source for dpll4_m3x2_ck */
 732 static struct clk dpll4_m3_ck = {
 733         .name           = "dpll4_m3_ck",
 734         .ops            = &clkops_null,
 735         .parent         = &dpll4_ck,
 736         .init           = &omap2_init_clksel_parent,
 737         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 738         .clksel_mask    = OMAP3630_CLKSEL_TV_MASK,
 739         .clksel         = dpll4_clksel,
 740         .clkdm_name     = "dpll4_clkdm",
 741         .recalc         = &omap2_clksel_recalc,
 742 };
 743
 744 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 745 static struct clk dpll4_m3x2_ck = {
 746         .name           = "dpll4_m3x2_ck",
 747         .ops            = &clkops_omap2_dflt_wait,
 748         .parent         = &dpll4_m3_ck,
 749         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 750         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 751         .flags          = INVERT_ENABLE,
 752         .clkdm_name     = "dpll4_clkdm",
 753         .recalc         = &omap3_clkoutx2_recalc,
 754 };
 755
 756 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 757         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 758         { .div = 0 }
 759 };
 760
 761 static const struct clksel_rate omap_54m_alt_rates[] = {
 762         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 763         { .div = 0 }
 764 };
 765
 766 static const struct clksel omap_54m_clksel[] = {
 767         { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
 768         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 769         { .parent = NULL }
 770 };
 771
 772 static struct clk omap_54m_fck = {
 773         .name           = "omap_54m_fck",
 774         .ops            = &clkops_null,
 775         .init           = &omap2_init_clksel_parent,
 776         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 777         .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
 778         .clksel         = omap_54m_clksel,
 779         .recalc         = &omap2_clksel_recalc,
 780 };
 781
 782 static const struct clksel_rate omap_48m_cm96m_rates[] = {
 783         { .div = 2, .val = 0, .flags = RATE_IN_3XXX },
 784         { .div = 0 }
 785 };
 786
 787 static const struct clksel_rate omap_48m_alt_rates[] = {
 788         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 789         { .div = 0 }
 790 };
 791
 792 static const struct clksel omap_48m_clksel[] = {
 793         { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 794         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 795         { .parent = NULL }
 796 };
 797
 798 static struct clk omap_48m_fck = {
 799         .name           = "omap_48m_fck",
 800         .ops            = &clkops_null,
 801         .init           = &omap2_init_clksel_parent,
 802         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 803         .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
 804         .clksel         = omap_48m_clksel,
 805         .recalc         = &omap2_clksel_recalc,
 806 };
 807
 808 static struct clk omap_12m_fck = {
 809         .name           = "omap_12m_fck",
 810         .ops            = &clkops_null,
 811         .parent         = &omap_48m_fck,
 812         .fixed_div      = 4,
 813         .recalc         = &omap_fixed_divisor_recalc,
 814 };
 815
 816 /* This virtual clock is the source for dpll4_m4x2_ck */
 817 static struct clk dpll4_m4_ck = {
 818         .name           = "dpll4_m4_ck",
 819         .ops            = &clkops_null,
 820         .parent         = &dpll4_ck,
 821         .init           = &omap2_init_clksel_parent,
 822         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 823         .clksel_mask    = OMAP3630_CLKSEL_DSS1_MASK,
 824         .clksel         = dpll4_clksel,
 825         .clkdm_name     = "dpll4_clkdm",
 826         .recalc         = &omap2_clksel_recalc,
 827         .set_rate       = &omap2_clksel_set_rate,
 828         .round_rate     = &omap2_clksel_round_rate,
 829 };
 830
 831 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 832 static struct clk dpll4_m4x2_ck = {
 833         .name           = "dpll4_m4x2_ck",
 834         .ops            = &clkops_omap2_dflt_wait,
 835         .parent         = &dpll4_m4_ck,
 836         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 837         .enable_bit     = OMAP3430_PWRDN_DSS1_SHIFT,
 838         .flags          = INVERT_ENABLE,
 839         .clkdm_name     = "dpll4_clkdm",
 840         .recalc         = &omap3_clkoutx2_recalc,
 841 };
 842
 843 /* This virtual clock is the source for dpll4_m5x2_ck */
 844 static struct clk dpll4_m5_ck = {
 845         .name           = "dpll4_m5_ck",
 846         .ops            = &clkops_null,
 847         .parent         = &dpll4_ck,
 848         .init           = &omap2_init_clksel_parent,
 849         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 850         .clksel_mask    = OMAP3630_CLKSEL_CAM_MASK,
 851         .clksel         = dpll4_clksel,
 852         .clkdm_name     = "dpll4_clkdm",
 853         .set_rate       = &omap2_clksel_set_rate,
 854         .round_rate     = &omap2_clksel_round_rate,
 855         .recalc         = &omap2_clksel_recalc,
 856 };
 857
 858 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 859 static struct clk dpll4_m5x2_ck = {
 860         .name           = "dpll4_m5x2_ck",
 861         .ops            = &clkops_omap2_dflt_wait,
 862         .parent         = &dpll4_m5_ck,
 863         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 864         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 865         .flags          = INVERT_ENABLE,
 866         .clkdm_name     = "dpll4_clkdm",
 867         .recalc         = &omap3_clkoutx2_recalc,
 868 };
 869
 870 /* This virtual clock is the source for dpll4_m6x2_ck */
 871 static struct clk dpll4_m6_ck = {
 872         .name           = "dpll4_m6_ck",
 873         .ops            = &clkops_null,
 874         .parent         = &dpll4_ck,
 875         .init           = &omap2_init_clksel_parent,
 876         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 877         .clksel_mask    = OMAP3630_DIV_DPLL4_MASK,
 878         .clksel         = dpll4_clksel,
 879         .clkdm_name     = "dpll4_clkdm",
 880         .recalc         = &omap2_clksel_recalc,
 881 };
 882
 883 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 884 static struct clk dpll4_m6x2_ck = {
 885         .name           = "dpll4_m6x2_ck",
 886         .ops            = &clkops_omap2_dflt_wait,
 887         .parent         = &dpll4_m6_ck,
 888         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 889         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 890         .flags          = INVERT_ENABLE,
 891         .clkdm_name     = "dpll4_clkdm",
 892         .recalc         = &omap3_clkoutx2_recalc,
 893 };
 894
 895 static struct clk emu_per_alwon_ck = {
 896         .name           = "emu_per_alwon_ck",
 897         .ops            = &clkops_null,
 898         .parent         = &dpll4_m6x2_ck,
 899         .clkdm_name     = "dpll4_clkdm",
 900         .recalc         = &followparent_recalc,
 901 };
 902
 903 /* DPLL5 */
 904 /* Supplies 120MHz clock, USIM source clock */
 905 /* Type: DPLL */
 906 /* 3430ES2 only */
 907 static struct dpll_data dpll5_dd = {
 908         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 909         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 910         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 911         .clk_bypass     = &sys_ck,
 912         .clk_ref        = &sys_ck,
 913         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 914         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 915         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 916         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 917         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 918         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 919         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 920         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 921         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 922         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 923         .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 924         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 925         .min_divider    = 1,
 926         .max_divider    = OMAP3_MAX_DPLL_DIV,
 927 };
 928
 929 static struct clk dpll5_ck = {
 930         .name           = "dpll5_ck",
 931         .ops            = &clkops_omap3_noncore_dpll_ops,
 932         .parent         = &sys_ck,
 933         .dpll_data      = &dpll5_dd,
 934         .round_rate     = &omap2_dpll_round_rate,
 935         .set_rate       = &omap3_noncore_dpll_set_rate,
 936         .clkdm_name     = "dpll5_clkdm",
 937         .recalc         = &omap3_dpll_recalc,
 938 };
 939
 940 static const struct clksel div16_dpll5_clksel[] = {
 941         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 942         { .parent = NULL }
 943 };
 944
 945 static struct clk dpll5_m2_ck = {
 946         .name           = "dpll5_m2_ck",
 947         .ops            = &clkops_null,
 948         .parent         = &dpll5_ck,
 949         .init           = &omap2_init_clksel_parent,
 950         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 951         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 952         .clksel         = div16_dpll5_clksel,
 953         .clkdm_name     = "dpll5_clkdm",
 954         .recalc         = &omap2_clksel_recalc,
 955 };
 956
 957 /* CM EXTERNAL CLOCK OUTPUTS */
 958
 959 static const struct clksel_rate clkout2_src_core_rates[] = {
 960         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 961         { .div = 0 }
 962 };
 963
 964 static const struct clksel_rate clkout2_src_sys_rates[] = {
 965         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 966         { .div = 0 }
 967 };
 968
 969 static const struct clksel_rate clkout2_src_96m_rates[] = {
 970         { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
 971         { .div = 0 }
 972 };
 973
 974 static const struct clksel_rate clkout2_src_54m_rates[] = {
 975         { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
 976         { .div = 0 }
 977 };
 978
 979 static const struct clksel clkout2_src_clksel[] = {
 980         { .parent = &core_ck,           .rates = clkout2_src_core_rates },
 981         { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
 982         { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
 983         { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
 984         { .parent = NULL }
 985 };
 986
 987 static struct clk clkout2_src_ck = {
 988         .name           = "clkout2_src_ck",
 989         .ops            = &clkops_omap2_dflt,
 990         .init           = &omap2_init_clksel_parent,
 991         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
 992         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
 993         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 994         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
 995         .clksel         = clkout2_src_clksel,
 996         .clkdm_name     = "core_clkdm",
 997         .recalc         = &omap2_clksel_recalc,
 998 };
 999
1000 static const struct clksel_rate sys_clkout2_rates[] = {
1001         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1002         { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
1003         { .div = 4, .val = 2, .flags = RATE_IN_3XXX },
1004         { .div = 8, .val = 3, .flags = RATE_IN_3XXX },
1005         { .div = 16, .val = 4, .flags = RATE_IN_3XXX },
1006         { .div = 0 },
1007 };
1008
1009 static const struct clksel sys_clkout2_clksel[] = {
1010         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1011         { .parent = NULL },
1012 };
1013
1014 static struct clk sys_clkout2 = {
1015         .name           = "sys_clkout2",
1016         .ops            = &clkops_null,
1017         .init           = &omap2_init_clksel_parent,
1018         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
1019         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
1020         .clksel         = sys_clkout2_clksel,
1021         .recalc         = &omap2_clksel_recalc,
1022         .round_rate     = &omap2_clksel_round_rate,
1023         .set_rate       = &omap2_clksel_set_rate
1024 };
1025
1026 /* CM OUTPUT CLOCKS */
1027
1028 static struct clk corex2_fck = {
1029         .name           = "corex2_fck",
1030         .ops            = &clkops_null,
1031         .parent         = &dpll3_m2x2_ck,
1032         .recalc         = &followparent_recalc,
1033 };
1034
1035 /* DPLL power domain clock controls */
1036
1037 static const struct clksel_rate div4_rates[] = {
1038         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1039         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
1040         { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
1041         { .div = 0 }
1042 };
1043
1044 static const struct clksel div4_core_clksel[] = {
1045         { .parent = &core_ck, .rates = div4_rates },
1046         { .parent = NULL }
1047 };
1048
1049 /*
1050  * REVISIT: Are these in DPLL power domain or CM power domain? docs
1051  * may be inconsistent here?
1052  */
1053 static struct clk dpll1_fck = {
1054         .name           = "dpll1_fck",
1055         .ops            = &clkops_null,
1056         .parent         = &core_ck,
1057         .init           = &omap2_init_clksel_parent,
1058         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1059         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1060         .clksel         = div4_core_clksel,
1061         .recalc         = &omap2_clksel_recalc,
1062 };
1063
1064 static struct clk mpu_ck = {
1065         .name           = "mpu_ck",
1066         .ops            = &clkops_null,
1067         .parent         = &dpll1_x2m2_ck,
1068         .clkdm_name     = "mpu_clkdm",
1069         .recalc         = &followparent_recalc,
1070 };
1071
1072 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1073 static const struct clksel_rate arm_fck_rates[] = {
1074         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1075         { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
1076         { .div = 0 },
1077 };
1078
1079 static const struct clksel arm_fck_clksel[] = {
1080         { .parent = &mpu_ck, .rates = arm_fck_rates },
1081         { .parent = NULL }
1082 };
1083
1084 static struct clk arm_fck = {
1085         .name           = "arm_fck",
1086         .ops            = &clkops_null,
1087         .parent         = &mpu_ck,
1088         .init           = &omap2_init_clksel_parent,
1089         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1090         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1091         .clksel         = arm_fck_clksel,
1092         .clkdm_name     = "mpu_clkdm",
1093         .recalc         = &omap2_clksel_recalc,
1094 };
1095
1096 /* XXX What about neon_clkdm ? */
1097
1098 /*
1099  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1100  * although it is referenced - so this is a guess
1101  */
1102 static struct clk emu_mpu_alwon_ck = {
1103         .name           = "emu_mpu_alwon_ck",
1104         .ops            = &clkops_null,
1105         .parent         = &mpu_ck,
1106         .recalc         = &followparent_recalc,
1107 };
1108
1109 static struct clk dpll2_fck = {
1110         .name           = "dpll2_fck",
1111         .ops            = &clkops_null,
1112         .parent         = &core_ck,
1113         .init           = &omap2_init_clksel_parent,
1114         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1115         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1116         .clksel         = div4_core_clksel,
1117         .recalc         = &omap2_clksel_recalc,
1118 };
1119
1120 static struct clk iva2_ck = {
1121         .name           = "iva2_ck",
1122         .ops            = &clkops_omap2_dflt_wait,
1123         .parent         = &dpll2_m2_ck,
1124         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1125         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1126         .clkdm_name     = "iva2_clkdm",
1127         .recalc         = &followparent_recalc,
1128 };
1129
1130 /* Common interface clocks */
1131
1132 static const struct clksel div2_core_clksel[] = {
1133         { .parent = &core_ck, .rates = div2_rates },
1134         { .parent = NULL }
1135 };
1136
1137 static struct clk l3_ick = {
1138         .name           = "l3_ick",
1139         .ops            = &clkops_null,
1140         .parent         = &core_ck,
1141         .init           = &omap2_init_clksel_parent,
1142         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1143         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1144         .clksel         = div2_core_clksel,
1145         .clkdm_name     = "core_l3_clkdm",
1146         .recalc         = &omap2_clksel_recalc,
1147 };
1148
1149 static const struct clksel div2_l3_clksel[] = {
1150         { .parent = &l3_ick, .rates = div2_rates },
1151         { .parent = NULL }
1152 };
1153
1154 static struct clk l4_ick = {
1155         .name           = "l4_ick",
1156         .ops            = &clkops_null,
1157         .parent         = &l3_ick,
1158         .init           = &omap2_init_clksel_parent,
1159         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1160         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1161         .clksel         = div2_l3_clksel,
1162         .clkdm_name     = "core_l4_clkdm",
1163         .recalc         = &omap2_clksel_recalc,
1164
1165 };
1166
1167 static const struct clksel div2_l4_clksel[] = {
1168         { .parent = &l4_ick, .rates = div2_rates },
1169         { .parent = NULL }
1170 };
1171
1172 static struct clk rm_ick = {
1173         .name           = "rm_ick",
1174         .ops            = &clkops_null,
1175         .parent         = &l4_ick,
1176         .init           = &omap2_init_clksel_parent,
1177         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1178         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1179         .clksel         = div2_l4_clksel,
1180         .recalc         = &omap2_clksel_recalc,
1181 };
1182
1183 /* GFX power domain */
1184
1185 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1186
1187 static const struct clksel gfx_l3_clksel[] = {
1188         { .parent = &l3_ick, .rates = gfx_l3_rates },
1189         { .parent = NULL }
1190 };
1191
1192 /*
1193  * Virtual parent clock for gfx_l3_ick and gfx_l3_fck
1194  * This interface clock does not have a CM_AUTOIDLE bit
1195  */
1196 static struct clk gfx_l3_ck = {
1197         .name           = "gfx_l3_ck",
1198         .ops            = &clkops_omap2_dflt_wait,
1199         .parent         = &l3_ick,
1200         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1201         .enable_bit     = OMAP_EN_GFX_SHIFT,
1202         .recalc         = &followparent_recalc,
1203 };
1204
1205 static struct clk gfx_l3_fck = {
1206         .name           = "gfx_l3_fck",
1207         .ops            = &clkops_null,
1208         .parent         = &gfx_l3_ck,
1209         .init           = &omap2_init_clksel_parent,
1210         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1211         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1212         .clksel         = gfx_l3_clksel,
1213         .clkdm_name     = "gfx_3430es1_clkdm",
1214         .recalc         = &omap2_clksel_recalc,
1215 };
1216
1217 static struct clk gfx_l3_ick = {
1218         .name           = "gfx_l3_ick",
1219         .ops            = &clkops_null,
1220         .parent         = &gfx_l3_ck,
1221         .clkdm_name     = "gfx_3430es1_clkdm",
1222         .recalc         = &followparent_recalc,
1223 };
1224
1225 static struct clk gfx_cg1_ck = {
1226         .name           = "gfx_cg1_ck",
1227         .ops            = &clkops_omap2_dflt_wait,
1228         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1229         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1230         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1231         .clkdm_name     = "gfx_3430es1_clkdm",
1232         .recalc         = &followparent_recalc,
1233 };
1234
1235 static struct clk gfx_cg2_ck = {
1236         .name           = "gfx_cg2_ck",
1237         .ops            = &clkops_omap2_dflt_wait,
1238         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1239         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1240         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1241         .clkdm_name     = "gfx_3430es1_clkdm",
1242         .recalc         = &followparent_recalc,
1243 };
1244
1245 /* SGX power domain - 3430ES2 only */
1246
1247 static const struct clksel_rate sgx_core_rates[] = {
1248         { .div = 2, .val = 5, .flags = RATE_IN_36XX },
1249         { .div = 3, .val = 0, .flags = RATE_IN_3XXX },
1250         { .div = 4, .val = 1, .flags = RATE_IN_3XXX },
1251         { .div = 6, .val = 2, .flags = RATE_IN_3XXX },
1252         { .div = 0 },
1253 };
1254
1255 static const struct clksel_rate sgx_192m_rates[] = {
1256         { .div = 1,  .val = 4, .flags = RATE_IN_36XX },
1257         { .div = 0 },
1258 };
1259
1260 static const struct clksel_rate sgx_corex2_rates[] = {
1261         { .div = 3, .val = 6, .flags = RATE_IN_36XX },
1262         { .div = 5, .val = 7, .flags = RATE_IN_36XX },
1263         { .div = 0 },
1264 };
1265
1266 static const struct clksel_rate sgx_96m_rates[] = {
1267         { .div = 1,  .val = 3, .flags = RATE_IN_3XXX },
1268         { .div = 0 },
1269 };
1270
1271 static const struct clksel sgx_clksel[] = {
1272         { .parent = &core_ck,    .rates = sgx_core_rates },
1273         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1274         { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
1275         { .parent = &corex2_fck, .rates = sgx_corex2_rates },
1276         { .parent = NULL }
1277 };
1278
1279 static struct clk sgx_fck = {
1280         .name           = "sgx_fck",
1281         .ops            = &clkops_omap2_dflt_wait,
1282         .init           = &omap2_init_clksel_parent,
1283         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1284         .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1285         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1286         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1287         .clksel         = sgx_clksel,
1288         .clkdm_name     = "sgx_clkdm",
1289         .recalc         = &omap2_clksel_recalc,
1290         .set_rate       = &omap2_clksel_set_rate,
1291         .round_rate     = &omap2_clksel_round_rate
1292 };
1293
1294 /* This interface clock does not have a CM_AUTOIDLE bit */
1295 static struct clk sgx_ick = {
1296         .name           = "sgx_ick",
1297         .ops            = &clkops_omap2_dflt_wait,
1298         .parent         = &l3_ick,
1299         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1300         .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1301         .clkdm_name     = "sgx_clkdm",
1302         .recalc         = &followparent_recalc,
1303 };
1304
1305 /* CORE power domain */
1306
1307 static struct clk d2d_26m_fck = {
1308         .name           = "d2d_26m_fck",
1309         .ops            = &clkops_omap2_dflt_wait,
1310         .parent         = &sys_ck,
1311         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1312         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1313         .clkdm_name     = "d2d_clkdm",
1314         .recalc         = &followparent_recalc,
1315 };
1316
1317 static struct clk modem_fck = {
1318         .name           = "modem_fck",
1319         .ops            = &clkops_omap2_mdmclk_dflt_wait,
1320         .parent         = &sys_ck,
1321         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1322         .enable_bit     = OMAP3430_EN_MODEM_SHIFT,
1323         .clkdm_name     = "d2d_clkdm",
1324         .recalc         = &followparent_recalc,
1325 };
1326
1327 static struct clk sad2d_ick = {
1328         .name           = "sad2d_ick",
1329         .ops            = &clkops_omap2_iclk_dflt_wait,
1330         .parent         = &l3_ick,
1331         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1332         .enable_bit     = OMAP3430_EN_SAD2D_SHIFT,
1333         .clkdm_name     = "d2d_clkdm",
1334         .recalc         = &followparent_recalc,
1335 };
1336
1337 static struct clk mad2d_ick = {
1338         .name           = "mad2d_ick",
1339         .ops            = &clkops_omap2_iclk_dflt_wait,
1340         .parent         = &l3_ick,
1341         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1342         .enable_bit     = OMAP3430_EN_MAD2D_SHIFT,
1343         .clkdm_name     = "d2d_clkdm",
1344         .recalc         = &followparent_recalc,
1345 };
1346
1347 static const struct clksel omap343x_gpt_clksel[] = {
1348         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1349         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1350         { .parent = NULL}
1351 };
1352
1353 static struct clk gpt10_fck = {
1354         .name           = "gpt10_fck",
1355         .ops            = &clkops_omap2_dflt_wait,
1356         .parent         = &sys_ck,
1357         .init           = &omap2_init_clksel_parent,
1358         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1359         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1360         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1361         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1362         .clksel         = omap343x_gpt_clksel,
1363         .clkdm_name     = "core_l4_clkdm",
1364         .recalc         = &omap2_clksel_recalc,
1365 };
1366
1367 static struct clk gpt11_fck = {
1368         .name           = "gpt11_fck",
1369         .ops            = &clkops_omap2_dflt_wait,
1370         .parent         = &sys_ck,
1371         .init           = &omap2_init_clksel_parent,
1372         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1373         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1374         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1375         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1376         .clksel         = omap343x_gpt_clksel,
1377         .clkdm_name     = "core_l4_clkdm",
1378         .recalc         = &omap2_clksel_recalc,
1379 };
1380
1381 static struct clk cpefuse_fck = {
1382         .name           = "cpefuse_fck",
1383         .ops            = &clkops_omap2_dflt,
1384         .parent         = &sys_ck,
1385         .clkdm_name     = "core_l4_clkdm",
1386         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1387         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1388         .recalc         = &followparent_recalc,
1389 };
1390
1391 static struct clk ts_fck = {
1392         .name           = "ts_fck",
1393         .ops            = &clkops_omap2_dflt,
1394         .parent         = &omap_32k_fck,
1395         .clkdm_name     = "core_l4_clkdm",
1396         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1397         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1398         .recalc         = &followparent_recalc,
1399 };
1400
1401 static struct clk usbtll_fck = {
1402         .name           = "usbtll_fck",
1403         .ops            = &clkops_omap2_dflt_wait,
1404         .parent         = &dpll5_m2_ck,
1405         .clkdm_name     = "core_l4_clkdm",
1406         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1407         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1408         .recalc         = &followparent_recalc,
1409 };
1410
1411 /* CORE 96M FCLK-derived clocks */
1412
1413 static struct clk core_96m_fck = {
1414         .name           = "core_96m_fck",
1415         .ops            = &clkops_null,
1416         .parent         = &omap_96m_fck,
1417         .clkdm_name     = "core_l4_clkdm",
1418         .recalc         = &followparent_recalc,
1419 };
1420
1421 static struct clk mmchs3_fck = {
1422         .name           = "mmchs3_fck",
1423         .ops            = &clkops_omap2_dflt_wait,
1424         .parent         = &core_96m_fck,
1425         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1426         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1427         .clkdm_name     = "core_l4_clkdm",
1428         .recalc         = &followparent_recalc,
1429 };
1430
1431 static struct clk mmchs2_fck = {
1432         .name           = "mmchs2_fck",
1433         .ops            = &clkops_omap2_dflt_wait,
1434         .parent         = &core_96m_fck,
1435         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1436         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1437         .clkdm_name     = "core_l4_clkdm",
1438         .recalc         = &followparent_recalc,
1439 };
1440
1441 static struct clk mspro_fck = {
1442         .name           = "mspro_fck",
1443         .ops            = &clkops_omap2_dflt_wait,
1444         .parent         = &core_96m_fck,
1445         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1446         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1447         .clkdm_name     = "core_l4_clkdm",
1448         .recalc         = &followparent_recalc,
1449 };
1450
1451 static struct clk mmchs1_fck = {
1452         .name           = "mmchs1_fck",
1453         .ops            = &clkops_omap2_dflt_wait,
1454         .parent         = &core_96m_fck,
1455         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1456         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1457         .clkdm_name     = "core_l4_clkdm",
1458         .recalc         = &followparent_recalc,
1459 };
1460
1461 static struct clk i2c3_fck = {
1462         .name           = "i2c3_fck",
1463         .ops            = &clkops_omap2_dflt_wait,
1464         .parent         = &core_96m_fck,
1465         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1466         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1467         .clkdm_name     = "core_l4_clkdm",
1468         .recalc         = &followparent_recalc,
1469 };
1470
1471 static struct clk i2c2_fck = {
1472         .name           = "i2c2_fck",
1473         .ops            = &clkops_omap2_dflt_wait,
1474         .parent         = &core_96m_fck,
1475         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1476         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1477         .clkdm_name     = "core_l4_clkdm",
1478         .recalc         = &followparent_recalc,
1479 };
1480
1481 static struct clk i2c1_fck = {
1482         .name           = "i2c1_fck",
1483         .ops            = &clkops_omap2_dflt_wait,
1484         .parent         = &core_96m_fck,
1485         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1486         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1487         .clkdm_name     = "core_l4_clkdm",
1488         .recalc         = &followparent_recalc,
1489 };
1490
1491 /*
1492  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1493  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1494  */
1495 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1496         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1497         { .div = 0 }
1498 };
1499
1500 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1501         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1502         { .div = 0 }
1503 };
1504
1505 static const struct clksel mcbsp_15_clksel[] = {
1506         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1507         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1508         { .parent = NULL }
1509 };
1510
1511 static struct clk mcbsp5_fck = {
1512         .name           = "mcbsp5_fck",
1513         .ops            = &clkops_omap2_dflt_wait,
1514         .init           = &omap2_init_clksel_parent,
1515         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1516         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1517         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1518         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1519         .clksel         = mcbsp_15_clksel,
1520         .clkdm_name     = "core_l4_clkdm",
1521         .recalc         = &omap2_clksel_recalc,
1522 };
1523
1524 static struct clk mcbsp1_fck = {
1525         .name           = "mcbsp1_fck",
1526         .ops            = &clkops_omap2_dflt_wait,
1527         .init           = &omap2_init_clksel_parent,
1528         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1529         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1530         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1531         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1532         .clksel         = mcbsp_15_clksel,
1533         .clkdm_name     = "core_l4_clkdm",
1534         .recalc         = &omap2_clksel_recalc,
1535 };
1536
1537 /* CORE_48M_FCK-derived clocks */
1538
1539 static struct clk core_48m_fck = {
1540         .name           = "core_48m_fck",
1541         .ops            = &clkops_null,
1542         .parent         = &omap_48m_fck,
1543         .clkdm_name     = "core_l4_clkdm",
1544         .recalc         = &followparent_recalc,
1545 };
1546
1547 static struct clk mcspi4_fck = {
1548         .name           = "mcspi4_fck",
1549         .ops            = &clkops_omap2_dflt_wait,
1550         .parent         = &core_48m_fck,
1551         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1552         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1553         .recalc         = &followparent_recalc,
1554         .clkdm_name     = "core_l4_clkdm",
1555 };
1556
1557 static struct clk mcspi3_fck = {
1558         .name           = "mcspi3_fck",
1559         .ops            = &clkops_omap2_dflt_wait,
1560         .parent         = &core_48m_fck,
1561         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1562         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1563         .recalc         = &followparent_recalc,
1564         .clkdm_name     = "core_l4_clkdm",
1565 };
1566
1567 static struct clk mcspi2_fck = {
1568         .name           = "mcspi2_fck",
1569         .ops            = &clkops_omap2_dflt_wait,
1570         .parent         = &core_48m_fck,
1571         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1572         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1573         .recalc         = &followparent_recalc,
1574         .clkdm_name     = "core_l4_clkdm",
1575 };
1576
1577 static struct clk mcspi1_fck = {
1578         .name           = "mcspi1_fck",
1579         .ops            = &clkops_omap2_dflt_wait,
1580         .parent         = &core_48m_fck,
1581         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1582         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1583         .recalc         = &followparent_recalc,
1584         .clkdm_name     = "core_l4_clkdm",
1585 };
1586
1587 static struct clk uart2_fck = {
1588         .name           = "uart2_fck",
1589         .ops            = &clkops_omap2_dflt_wait,
1590         .parent         = &core_48m_fck,
1591         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1592         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1593         .clkdm_name     = "core_l4_clkdm",
1594         .recalc         = &followparent_recalc,
1595 };
1596
1597 static struct clk uart1_fck = {
1598         .name           = "uart1_fck",
1599         .ops            = &clkops_omap2_dflt_wait,
1600         .parent         = &core_48m_fck,
1601         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1602         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1603         .clkdm_name     = "core_l4_clkdm",
1604         .recalc         = &followparent_recalc,
1605 };
1606
1607 static struct clk fshostusb_fck = {
1608         .name           = "fshostusb_fck",
1609         .ops            = &clkops_omap2_dflt_wait,
1610         .parent         = &core_48m_fck,
1611         .clkdm_name     = "core_l4_clkdm",
1612         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1613         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1614         .recalc         = &followparent_recalc,
1615 };
1616
1617 /* CORE_12M_FCK based clocks */
1618
1619 static struct clk core_12m_fck = {
1620         .name           = "core_12m_fck",
1621         .ops            = &clkops_null,
1622         .parent         = &omap_12m_fck,
1623         .clkdm_name     = "core_l4_clkdm",
1624         .recalc         = &followparent_recalc,
1625 };
1626
1627 static struct clk hdq_fck = {
1628         .name           = "hdq_fck",
1629         .ops            = &clkops_omap2_dflt_wait,
1630         .parent         = &core_12m_fck,
1631         .clkdm_name     = "core_l4_clkdm",
1632         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1633         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1634         .recalc         = &followparent_recalc,
1635 };
1636
1637 /* DPLL3-derived clock */
1638
1639 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1640         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1641         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
1642         { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
1643         { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
1644         { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
1645         { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
1646         { .div = 0 }
1647 };
1648
1649 static const struct clksel ssi_ssr_clksel[] = {
1650         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1651         { .parent = NULL }
1652 };
1653
1654 static struct clk ssi_ssr_fck_3430es1 = {
1655         .name           = "ssi_ssr_fck",
1656         .ops            = &clkops_omap2_dflt,
1657         .init           = &omap2_init_clksel_parent,
1658         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1659         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1660         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1661         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1662         .clksel         = ssi_ssr_clksel,
1663         .clkdm_name     = "core_l4_clkdm",
1664         .recalc         = &omap2_clksel_recalc,
1665 };
1666
1667 static struct clk ssi_ssr_fck_3430es2 = {
1668         .name           = "ssi_ssr_fck",
1669         .ops            = &clkops_omap3430es2_ssi_wait,
1670         .init           = &omap2_init_clksel_parent,
1671         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1672         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1673         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1674         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1675         .clksel         = ssi_ssr_clksel,
1676         .clkdm_name     = "core_l4_clkdm",
1677         .recalc         = &omap2_clksel_recalc,
1678 };
1679
1680 static struct clk ssi_sst_fck_3430es1 = {
1681         .name           = "ssi_sst_fck",
1682         .ops            = &clkops_null,
1683         .parent         = &ssi_ssr_fck_3430es1,
1684         .fixed_div      = 2,
1685         .recalc         = &omap_fixed_divisor_recalc,
1686 };
1687
1688 static struct clk ssi_sst_fck_3430es2 = {
1689         .name           = "ssi_sst_fck",
1690         .ops            = &clkops_null,
1691         .parent         = &ssi_ssr_fck_3430es2,
1692         .fixed_div      = 2,
1693         .recalc         = &omap_fixed_divisor_recalc,
1694 };
1695
1696
1697
1698 /* CORE_L3_ICK based clocks */
1699
1700 /*
1701  * XXX must add clk_enable/clk_disable for these if standard code won't
1702  * handle it
1703  */
1704 static struct clk core_l3_ick = {
1705         .name           = "core_l3_ick",
1706         .ops            = &clkops_null,
1707         .parent         = &l3_ick,
1708         .clkdm_name     = "core_l3_clkdm",
1709         .recalc         = &followparent_recalc,
1710 };
1711
1712 static struct clk hsotgusb_ick_3430es1 = {
1713         .name           = "hsotgusb_ick",
1714         .ops            = &clkops_omap2_iclk_dflt,
1715         .parent         = &core_l3_ick,
1716         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1717         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1718         .clkdm_name     = "core_l3_clkdm",
1719         .recalc         = &followparent_recalc,
1720 };
1721
1722 static struct clk hsotgusb_ick_3430es2 = {
1723         .name           = "hsotgusb_ick",
1724         .ops            = &clkops_omap3430es2_iclk_hsotgusb_wait,
1725         .parent         = &core_l3_ick,
1726         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1727         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1728         .clkdm_name     = "core_l3_clkdm",
1729         .recalc         = &followparent_recalc,
1730 };
1731
1732 /* This interface clock does not have a CM_AUTOIDLE bit */
1733 static struct clk sdrc_ick = {
1734         .name           = "sdrc_ick",
1735         .ops            = &clkops_omap2_dflt_wait,
1736         .parent         = &core_l3_ick,
1737         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1738         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1739         .flags          = ENABLE_ON_INIT,
1740         .clkdm_name     = "core_l3_clkdm",
1741         .recalc         = &followparent_recalc,
1742 };
1743
1744 static struct clk gpmc_fck = {
1745         .name           = "gpmc_fck",
1746         .ops            = &clkops_null,
1747         .parent         = &core_l3_ick,
1748         .flags          = ENABLE_ON_INIT, /* huh? */
1749         .clkdm_name     = "core_l3_clkdm",
1750         .recalc         = &followparent_recalc,
1751 };
1752
1753 /* SECURITY_L3_ICK based clocks */
1754
1755 static struct clk security_l3_ick = {
1756         .name           = "security_l3_ick",
1757         .ops            = &clkops_null,
1758         .parent         = &l3_ick,
1759         .recalc         = &followparent_recalc,
1760 };
1761
1762 static struct clk pka_ick = {
1763         .name           = "pka_ick",
1764         .ops            = &clkops_omap2_iclk_dflt_wait,
1765         .parent         = &security_l3_ick,
1766         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1767         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1768         .recalc         = &followparent_recalc,
1769 };
1770
1771 /* CORE_L4_ICK based clocks */
1772
1773 static struct clk core_l4_ick = {
1774         .name           = "core_l4_ick",
1775         .ops            = &clkops_null,
1776         .parent         = &l4_ick,
1777         .clkdm_name     = "core_l4_clkdm",
1778         .recalc         = &followparent_recalc,
1779 };
1780
1781 static struct clk usbtll_ick = {
1782         .name           = "usbtll_ick",
1783         .ops            = &clkops_omap2_iclk_dflt_wait,
1784         .parent         = &core_l4_ick,
1785         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1786         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1787         .clkdm_name     = "core_l4_clkdm",
1788         .recalc         = &followparent_recalc,
1789 };
1790
1791 static struct clk mmchs3_ick = {
1792         .name           = "mmchs3_ick",
1793         .ops            = &clkops_omap2_iclk_dflt_wait,
1794         .parent         = &core_l4_ick,
1795         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1796         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1797         .clkdm_name     = "core_l4_clkdm",
1798         .recalc         = &followparent_recalc,
1799 };
1800
1801 /* Intersystem Communication Registers - chassis mode only */
1802 static struct clk icr_ick = {
1803         .name           = "icr_ick",
1804         .ops            = &clkops_omap2_iclk_dflt_wait,
1805         .parent         = &core_l4_ick,
1806         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1807         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1808         .clkdm_name     = "core_l4_clkdm",
1809         .recalc         = &followparent_recalc,
1810 };
1811
1812 static struct clk aes2_ick = {
1813         .name           = "aes2_ick",
1814         .ops            = &clkops_omap2_iclk_dflt_wait,
1815         .parent         = &core_l4_ick,
1816         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1817         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1818         .clkdm_name     = "core_l4_clkdm",
1819         .recalc         = &followparent_recalc,
1820 };
1821
1822 static struct clk sha12_ick = {
1823         .name           = "sha12_ick",
1824         .ops            = &clkops_omap2_iclk_dflt_wait,
1825         .parent         = &core_l4_ick,
1826         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1827         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1828         .clkdm_name     = "core_l4_clkdm",
1829         .recalc         = &followparent_recalc,
1830 };
1831
1832 static struct clk des2_ick = {
1833         .name           = "des2_ick",
1834         .ops            = &clkops_omap2_iclk_dflt_wait,
1835         .parent         = &core_l4_ick,
1836         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1837         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1838         .clkdm_name     = "core_l4_clkdm",
1839         .recalc         = &followparent_recalc,
1840 };
1841
1842 static struct clk mmchs2_ick = {
1843         .name           = "mmchs2_ick",
1844         .ops            = &clkops_omap2_iclk_dflt_wait,
1845         .parent         = &core_l4_ick,
1846         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1847         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1848         .clkdm_name     = "core_l4_clkdm",
1849         .recalc         = &followparent_recalc,
1850 };
1851
1852 static struct clk mmchs1_ick = {
1853         .name           = "mmchs1_ick",
1854         .ops            = &clkops_omap2_iclk_dflt_wait,
1855         .parent         = &core_l4_ick,
1856         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1857         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1858         .clkdm_name     = "core_l4_clkdm",
1859         .recalc         = &followparent_recalc,
1860 };
1861
1862 static struct clk mspro_ick = {
1863         .name           = "mspro_ick",
1864         .ops            = &clkops_omap2_iclk_dflt_wait,
1865         .parent         = &core_l4_ick,
1866         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1867         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1868         .clkdm_name     = "core_l4_clkdm",
1869         .recalc         = &followparent_recalc,
1870 };
1871
1872 static struct clk hdq_ick = {
1873         .name           = "hdq_ick",
1874         .ops            = &clkops_omap2_iclk_dflt_wait,
1875         .parent         = &core_l4_ick,
1876         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1877         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1878         .clkdm_name     = "core_l4_clkdm",
1879         .recalc         = &followparent_recalc,
1880 };
1881
1882 static struct clk mcspi4_ick = {
1883         .name           = "mcspi4_ick",
1884         .ops            = &clkops_omap2_iclk_dflt_wait,
1885         .parent         = &core_l4_ick,
1886         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1887         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1888         .clkdm_name     = "core_l4_clkdm",
1889         .recalc         = &followparent_recalc,
1890 };
1891
1892 static struct clk mcspi3_ick = {
1893         .name           = "mcspi3_ick",
1894         .ops            = &clkops_omap2_iclk_dflt_wait,
1895         .parent         = &core_l4_ick,
1896         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1897         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1898         .clkdm_name     = "core_l4_clkdm",
1899         .recalc         = &followparent_recalc,
1900 };
1901
1902 static struct clk mcspi2_ick = {
1903         .name           = "mcspi2_ick",
1904         .ops            = &clkops_omap2_iclk_dflt_wait,
1905         .parent         = &core_l4_ick,
1906         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1907         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1908         .clkdm_name     = "core_l4_clkdm",
1909         .recalc         = &followparent_recalc,
1910 };
1911
1912 static struct clk mcspi1_ick = {
1913         .name           = "mcspi1_ick",
1914         .ops            = &clkops_omap2_iclk_dflt_wait,
1915         .parent         = &core_l4_ick,
1916         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1917         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1918         .clkdm_name     = "core_l4_clkdm",
1919         .recalc         = &followparent_recalc,
1920 };
1921
1922 static struct clk i2c3_ick = {
1923         .name           = "i2c3_ick",
1924         .ops            = &clkops_omap2_iclk_dflt_wait,
1925         .parent         = &core_l4_ick,
1926         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1927         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1928         .clkdm_name     = "core_l4_clkdm",
1929         .recalc         = &followparent_recalc,
1930 };
1931
1932 static struct clk i2c2_ick = {
1933         .name           = "i2c2_ick",
1934         .ops            = &clkops_omap2_iclk_dflt_wait,
1935         .parent         = &core_l4_ick,
1936         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1937         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1938         .clkdm_name     = "core_l4_clkdm",
1939         .recalc         = &followparent_recalc,
1940 };
1941
1942 static struct clk i2c1_ick = {
1943         .name           = "i2c1_ick",
1944         .ops            = &clkops_omap2_iclk_dflt_wait,
1945         .parent         = &core_l4_ick,
1946         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1947         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1948         .clkdm_name     = "core_l4_clkdm",
1949         .recalc         = &followparent_recalc,
1950 };
1951
1952 static struct clk uart2_ick = {
1953         .name           = "uart2_ick",
1954         .ops            = &clkops_omap2_iclk_dflt_wait,
1955         .parent         = &core_l4_ick,
1956         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1957         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1958         .clkdm_name     = "core_l4_clkdm",
1959         .recalc         = &followparent_recalc,
1960 };
1961
1962 static struct clk uart1_ick = {
1963         .name           = "uart1_ick",
1964         .ops            = &clkops_omap2_iclk_dflt_wait,
1965         .parent         = &core_l4_ick,
1966         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1967         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1968         .clkdm_name     = "core_l4_clkdm",
1969         .recalc         = &followparent_recalc,
1970 };
1971
1972 static struct clk gpt11_ick = {
1973         .name           = "gpt11_ick",
1974         .ops            = &clkops_omap2_iclk_dflt_wait,
1975         .parent         = &core_l4_ick,
1976         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1977         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1978         .clkdm_name     = "core_l4_clkdm",
1979         .recalc         = &followparent_recalc,
1980 };
1981
1982 static struct clk gpt10_ick = {
1983         .name           = "gpt10_ick",
1984         .ops            = &clkops_omap2_iclk_dflt_wait,
1985         .parent         = &core_l4_ick,
1986         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1987         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1988         .clkdm_name     = "core_l4_clkdm",
1989         .recalc         = &followparent_recalc,
1990 };
1991
1992 static struct clk mcbsp5_ick = {
1993         .name           = "mcbsp5_ick",
1994         .ops            = &clkops_omap2_iclk_dflt_wait,
1995         .parent         = &core_l4_ick,
1996         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1997         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1998         .clkdm_name     = "core_l4_clkdm",
1999         .recalc         = &followparent_recalc,
2000 };
2001
2002 static struct clk mcbsp1_ick = {
2003         .name           = "mcbsp1_ick",
2004         .ops            = &clkops_omap2_iclk_dflt_wait,
2005         .parent         = &core_l4_ick,
2006         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2007         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
2008         .clkdm_name     = "core_l4_clkdm",
2009         .recalc         = &followparent_recalc,
2010 };
2011
2012 static struct clk fac_ick = {
2013         .name           = "fac_ick",
2014         .ops            = &clkops_omap2_iclk_dflt_wait,
2015         .parent         = &core_l4_ick,
2016         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2017         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
2018         .clkdm_name     = "core_l4_clkdm",
2019         .recalc         = &followparent_recalc,
2020 };
2021
2022 static struct clk mailboxes_ick = {
2023         .name           = "mailboxes_ick",
2024         .ops            = &clkops_omap2_iclk_dflt_wait,
2025         .parent         = &core_l4_ick,
2026         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2027         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
2028         .clkdm_name     = "core_l4_clkdm",
2029         .recalc         = &followparent_recalc,
2030 };
2031
2032 static struct clk omapctrl_ick = {
2033         .name           = "omapctrl_ick",
2034         .ops            = &clkops_omap2_iclk_dflt_wait,
2035         .parent         = &core_l4_ick,
2036         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2037         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
2038         .flags          = ENABLE_ON_INIT,
2039         .clkdm_name     = "core_l4_clkdm",
2040         .recalc         = &followparent_recalc,
2041 };
2042
2043 /* SSI_L4_ICK based clocks */
2044
2045 static struct clk ssi_l4_ick = {
2046         .name           = "ssi_l4_ick",
2047         .ops            = &clkops_null,
2048         .parent         = &l4_ick,
2049         .clkdm_name     = "core_l4_clkdm",
2050         .recalc         = &followparent_recalc,
2051 };
2052
2053 static struct clk ssi_ick_3430es1 = {
2054         .name           = "ssi_ick",
2055         .ops            = &clkops_omap2_iclk_dflt,
2056         .parent         = &ssi_l4_ick,
2057         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2058         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2059         .clkdm_name     = "core_l4_clkdm",
2060         .recalc         = &followparent_recalc,
2061 };
2062
2063 static struct clk ssi_ick_3430es2 = {
2064         .name           = "ssi_ick",
2065         .ops            = &clkops_omap3430es2_iclk_ssi_wait,
2066         .parent         = &ssi_l4_ick,
2067         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2068         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2069         .clkdm_name     = "core_l4_clkdm",
2070         .recalc         = &followparent_recalc,
2071 };
2072
2073 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2074  * but l4_ick makes more sense to me */
2075
2076 static const struct clksel usb_l4_clksel[] = {
2077         { .parent = &l4_ick, .rates = div2_rates },
2078         { .parent = NULL },
2079 };
2080
2081 static struct clk usb_l4_ick = {
2082         .name           = "usb_l4_ick",
2083         .ops            = &clkops_omap2_iclk_dflt_wait,
2084         .parent         = &l4_ick,
2085         .init           = &omap2_init_clksel_parent,
2086         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2087         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2088         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2089         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2090         .clksel         = usb_l4_clksel,
2091         .clkdm_name     = "core_l4_clkdm",
2092         .recalc         = &omap2_clksel_recalc,
2093 };
2094
2095 /* SECURITY_L4_ICK2 based clocks */
2096
2097 static struct clk security_l4_ick2 = {
2098         .name           = "security_l4_ick2",
2099         .ops            = &clkops_null,
2100         .parent         = &l4_ick,
2101         .recalc         = &followparent_recalc,
2102 };
2103
2104 static struct clk aes1_ick = {
2105         .name           = "aes1_ick",
2106         .ops            = &clkops_omap2_iclk_dflt_wait,
2107         .parent         = &security_l4_ick2,
2108         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2109         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2110         .recalc         = &followparent_recalc,
2111 };
2112
2113 static struct clk rng_ick = {
2114         .name           = "rng_ick",
2115         .ops            = &clkops_omap2_iclk_dflt_wait,
2116         .parent         = &security_l4_ick2,
2117         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2118         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2119         .recalc         = &followparent_recalc,
2120 };
2121
2122 static struct clk sha11_ick = {
2123         .name           = "sha11_ick",
2124         .ops            = &clkops_omap2_iclk_dflt_wait,
2125         .parent         = &security_l4_ick2,
2126         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2127         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2128         .recalc         = &followparent_recalc,
2129 };
2130
2131 static struct clk des1_ick = {
2132         .name           = "des1_ick",
2133         .ops            = &clkops_omap2_iclk_dflt_wait,
2134         .parent         = &security_l4_ick2,
2135         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2136         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2137         .recalc         = &followparent_recalc,
2138 };
2139
2140 /* DSS */
2141 static struct clk dss1_alwon_fck_3430es1 = {
2142         .name           = "dss1_alwon_fck",
2143         .ops            = &clkops_omap2_dflt,
2144         .parent         = &dpll4_m4x2_ck,
2145         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2146         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2147         .clkdm_name     = "dss_clkdm",
2148         .recalc         = &followparent_recalc,
2149 };
2150
2151 static struct clk dss1_alwon_fck_3430es2 = {
2152         .name           = "dss1_alwon_fck",
2153         .ops            = &clkops_omap3430es2_dss_usbhost_wait,
2154         .parent         = &dpll4_m4x2_ck,
2155         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2156         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2157         .clkdm_name     = "dss_clkdm",
2158         .recalc         = &followparent_recalc,
2159 };
2160
2161 static struct clk dss_tv_fck = {
2162         .name           = "dss_tv_fck",
2163         .ops            = &clkops_omap2_dflt,
2164         .parent         = &omap_54m_fck,
2165         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2166         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2167         .clkdm_name     = "dss_clkdm",
2168         .recalc         = &followparent_recalc,
2169 };
2170
2171 static struct clk dss_96m_fck = {
2172         .name           = "dss_96m_fck",
2173         .ops            = &clkops_omap2_dflt,
2174         .parent         = &omap_96m_fck,
2175         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2176         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2177         .clkdm_name     = "dss_clkdm",
2178         .recalc         = &followparent_recalc,
2179 };
2180
2181 static struct clk dss2_alwon_fck = {
2182         .name           = "dss2_alwon_fck",
2183         .ops            = &clkops_omap2_dflt,
2184         .parent         = &sys_ck,
2185         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2186         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2187         .clkdm_name     = "dss_clkdm",
2188         .recalc         = &followparent_recalc,
2189 };
2190
2191 static struct clk dss_ick_3430es1 = {
2192         /* Handles both L3 and L4 clocks */
2193         .name           = "dss_ick",
2194         .ops            = &clkops_omap2_iclk_dflt,
2195         .parent         = &l4_ick,
2196         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2197         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2198         .clkdm_name     = "dss_clkdm",
2199         .recalc         = &followparent_recalc,
2200 };
2201
2202 static struct clk dss_ick_3430es2 = {
2203         /* Handles both L3 and L4 clocks */
2204         .name           = "dss_ick",
2205         .ops            = &clkops_omap3430es2_iclk_dss_usbhost_wait,
2206         .parent         = &l4_ick,
2207         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2208         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2209         .clkdm_name     = "dss_clkdm",
2210         .recalc         = &followparent_recalc,
2211 };
2212
2213 /* CAM */
2214
2215 static struct clk cam_mclk = {
2216         .name           = "cam_mclk",
2217         .ops            = &clkops_omap2_dflt,
2218         .parent         = &dpll4_m5x2_ck,
2219         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2220         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2221         .clkdm_name     = "cam_clkdm",
2222         .recalc         = &followparent_recalc,
2223 };
2224
2225 static struct clk cam_ick = {
2226         /* Handles both L3 and L4 clocks */
2227         .name           = "cam_ick",
2228         .ops            = &clkops_omap2_iclk_dflt,
2229         .parent         = &l4_ick,
2230         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2231         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2232         .clkdm_name     = "cam_clkdm",
2233         .recalc         = &followparent_recalc,
2234 };
2235
2236 static struct clk csi2_96m_fck = {
2237         .name           = "csi2_96m_fck",
2238         .ops            = &clkops_omap2_dflt,
2239         .parent         = &core_96m_fck,
2240         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2241         .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
2242         .clkdm_name     = "cam_clkdm",
2243         .recalc         = &followparent_recalc,
2244 };
2245
2246 /* USBHOST - 3430ES2 only */
2247
2248 static struct clk usbhost_120m_fck = {
2249         .name           = "usbhost_120m_fck",
2250         .ops            = &clkops_omap2_dflt,
2251         .parent         = &dpll5_m2_ck,
2252         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2253         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2254         .clkdm_name     = "usbhost_clkdm",
2255         .recalc         = &followparent_recalc,
2256 };
2257
2258 static struct clk usbhost_48m_fck = {
2259         .name           = "usbhost_48m_fck",
2260         .ops            = &clkops_omap3430es2_dss_usbhost_wait,
2261         .parent         = &omap_48m_fck,
2262         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2263         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2264         .clkdm_name     = "usbhost_clkdm",
2265         .recalc         = &followparent_recalc,
2266 };
2267
2268 static struct clk usbhost_ick = {
2269         /* Handles both L3 and L4 clocks */
2270         .name           = "usbhost_ick",
2271         .ops            = &clkops_omap3430es2_iclk_dss_usbhost_wait,
2272         .parent         = &l4_ick,
2273         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2274         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2275         .clkdm_name     = "usbhost_clkdm",
2276         .recalc         = &followparent_recalc,
2277 };
2278
2279 /* WKUP */
2280
2281 static const struct clksel_rate usim_96m_rates[] = {
2282         { .div = 2,  .val = 3, .flags = RATE_IN_3XXX },
2283         { .div = 4,  .val = 4, .flags = RATE_IN_3XXX },
2284         { .div = 8,  .val = 5, .flags = RATE_IN_3XXX },
2285         { .div = 10, .val = 6, .flags = RATE_IN_3XXX },
2286         { .div = 0 },
2287 };
2288
2289 static const struct clksel_rate usim_120m_rates[] = {
2290         { .div = 4,  .val = 7,  .flags = RATE_IN_3XXX },
2291         { .div = 8,  .val = 8,  .flags = RATE_IN_3XXX },
2292         { .div = 16, .val = 9,  .flags = RATE_IN_3XXX },
2293         { .div = 20, .val = 10, .flags = RATE_IN_3XXX },
2294         { .div = 0 },
2295 };
2296
2297 static const struct clksel usim_clksel[] = {
2298         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2299         { .parent = &dpll5_m2_ck,       .rates = usim_120m_rates },
2300         { .parent = &sys_ck,            .rates = div2_rates },
2301         { .parent = NULL },
2302 };
2303
2304 /* 3430ES2 only */
2305 static struct clk usim_fck = {
2306         .name           = "usim_fck",
2307         .ops            = &clkops_omap2_dflt_wait,
2308         .init           = &omap2_init_clksel_parent,
2309         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2310         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2311         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2312         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2313         .clksel         = usim_clksel,
2314         .recalc         = &omap2_clksel_recalc,
2315 };
2316
2317 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2318 static struct clk gpt1_fck = {
2319         .name           = "gpt1_fck",
2320         .ops            = &clkops_omap2_dflt_wait,
2321         .init           = &omap2_init_clksel_parent,
2322         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2323         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2324         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2325         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2326         .clksel         = omap343x_gpt_clksel,
2327         .clkdm_name     = "wkup_clkdm",
2328         .recalc         = &omap2_clksel_recalc,
2329 };
2330
2331 static struct clk wkup_32k_fck = {
2332         .name           = "wkup_32k_fck",
2333         .ops            = &clkops_null,
2334         .parent         = &omap_32k_fck,
2335         .clkdm_name     = "wkup_clkdm",
2336         .recalc         = &followparent_recalc,
2337 };
2338
2339 static struct clk gpio1_dbck = {
2340         .name           = "gpio1_dbck",
2341         .ops            = &clkops_omap2_dflt,
2342         .parent         = &wkup_32k_fck,
2343         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2344         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2345         .clkdm_name     = "wkup_clkdm",
2346         .recalc         = &followparent_recalc,
2347 };
2348
2349 static struct clk wdt2_fck = {
2350         .name           = "wdt2_fck",
2351         .ops            = &clkops_omap2_dflt_wait,
2352         .parent         = &wkup_32k_fck,
2353         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2354         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2355         .clkdm_name     = "wkup_clkdm",
2356         .recalc         = &followparent_recalc,
2357 };
2358
2359 static struct clk wkup_l4_ick = {
2360         .name           = "wkup_l4_ick",
2361         .ops            = &clkops_null,
2362         .parent         = &sys_ck,
2363         .clkdm_name     = "wkup_clkdm",
2364         .recalc         = &followparent_recalc,
2365 };
2366
2367 /* 3430ES2 only */
2368 /* Never specifically named in the TRM, so we have to infer a likely name */
2369 static struct clk usim_ick = {
2370         .name           = "usim_ick",
2371         .ops            = &clkops_omap2_iclk_dflt_wait,
2372         .parent         = &wkup_l4_ick,
2373         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2374         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2375         .clkdm_name     = "wkup_clkdm",
2376         .recalc         = &followparent_recalc,
2377 };
2378
2379 static struct clk wdt2_ick = {
2380         .name           = "wdt2_ick",
2381         .ops            = &clkops_omap2_iclk_dflt_wait,
2382         .parent         = &wkup_l4_ick,
2383         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2384         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2385         .clkdm_name     = "wkup_clkdm",
2386         .recalc         = &followparent_recalc,
2387 };
2388
2389 static struct clk wdt1_ick = {
2390         .name           = "wdt1_ick",
2391         .ops            = &clkops_omap2_iclk_dflt_wait,
2392         .parent         = &wkup_l4_ick,
2393         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2394         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2395         .clkdm_name     = "wkup_clkdm",
2396         .recalc         = &followparent_recalc,
2397 };
2398
2399 static struct clk gpio1_ick = {
2400         .name           = "gpio1_ick",
2401         .ops            = &clkops_omap2_iclk_dflt_wait,
2402         .parent         = &wkup_l4_ick,
2403         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2404         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2405         .clkdm_name     = "wkup_clkdm",
2406         .recalc         = &followparent_recalc,
2407 };
2408
2409 static struct clk omap_32ksync_ick = {
2410         .name           = "omap_32ksync_ick",
2411         .ops            = &clkops_omap2_iclk_dflt_wait,
2412         .parent         = &wkup_l4_ick,
2413         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2414         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2415         .clkdm_name     = "wkup_clkdm",
2416         .recalc         = &followparent_recalc,
2417 };
2418
2419 /* XXX This clock no longer exists in 3430 TRM rev F */
2420 static struct clk gpt12_ick = {
2421         .name           = "gpt12_ick",
2422         .ops            = &clkops_omap2_iclk_dflt_wait,
2423         .parent         = &wkup_l4_ick,
2424         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2425         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2426         .clkdm_name     = "wkup_clkdm",
2427         .recalc         = &followparent_recalc,
2428 };
2429
2430 static struct clk gpt1_ick = {
2431         .name           = "gpt1_ick",
2432         .ops            = &clkops_omap2_iclk_dflt_wait,
2433         .parent         = &wkup_l4_ick,
2434         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2435         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2436         .clkdm_name     = "wkup_clkdm",
2437         .recalc         = &followparent_recalc,
2438 };
2439
2440
2441
2442 /* PER clock domain */
2443
2444 static struct clk per_96m_fck = {
2445         .name           = "per_96m_fck",
2446         .ops            = &clkops_null,
2447         .parent         = &omap_96m_alwon_fck,
2448         .clkdm_name     = "per_clkdm",
2449         .recalc         = &followparent_recalc,
2450 };
2451
2452 static struct clk per_48m_fck = {
2453         .name           = "per_48m_fck",
2454         .ops            = &clkops_null,
2455         .parent         = &omap_48m_fck,
2456         .clkdm_name     = "per_clkdm",
2457         .recalc         = &followparent_recalc,
2458 };
2459
2460 static struct clk uart3_fck = {
2461         .name           = "uart3_fck",
2462         .ops            = &clkops_omap2_dflt_wait,
2463         .parent         = &per_48m_fck,
2464         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2465         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2466         .clkdm_name     = "per_clkdm",
2467         .recalc         = &followparent_recalc,
2468 };
2469
2470 static struct clk uart4_fck = {
2471         .name           = "uart4_fck",
2472         .ops            = &clkops_omap2_dflt_wait,
2473         .parent         = &per_48m_fck,
2474         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2475         .enable_bit     = OMAP3630_EN_UART4_SHIFT,
2476         .clkdm_name     = "per_clkdm",
2477         .recalc         = &followparent_recalc,
2478 };
2479
2480 static struct clk uart4_fck_am35xx = {
2481         .name           = "uart4_fck",
2482         .ops            = &clkops_omap2_dflt_wait,
2483         .parent         = &core_48m_fck,
2484         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2485         .enable_bit     = AM35XX_EN_UART4_SHIFT,
2486         .clkdm_name     = "core_l4_clkdm",
2487         .recalc         = &followparent_recalc,
2488 };
2489
2490 static struct clk gpt2_fck = {
2491         .name           = "gpt2_fck",
2492         .ops            = &clkops_omap2_dflt_wait,
2493         .init           = &omap2_init_clksel_parent,
2494         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2495         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2496         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2497         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2498         .clksel         = omap343x_gpt_clksel,
2499         .clkdm_name     = "per_clkdm",
2500         .recalc         = &omap2_clksel_recalc,
2501 };
2502
2503 static struct clk gpt3_fck = {
2504         .name           = "gpt3_fck",
2505         .ops            = &clkops_omap2_dflt_wait,
2506         .init           = &omap2_init_clksel_parent,
2507         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2508         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2509         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2510         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2511         .clksel         = omap343x_gpt_clksel,
2512         .clkdm_name     = "per_clkdm",
2513         .recalc         = &omap2_clksel_recalc,
2514 };
2515
2516 static struct clk gpt4_fck = {
2517         .name           = "gpt4_fck",
2518         .ops            = &clkops_omap2_dflt_wait,
2519         .init           = &omap2_init_clksel_parent,
2520         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2521         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2522         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2523         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2524         .clksel         = omap343x_gpt_clksel,
2525         .clkdm_name     = "per_clkdm",
2526         .recalc         = &omap2_clksel_recalc,
2527 };
2528
2529 static struct clk gpt5_fck = {
2530         .name           = "gpt5_fck",
2531         .ops            = &clkops_omap2_dflt_wait,
2532         .init           = &omap2_init_clksel_parent,
2533         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2534         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2535         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2536         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2537         .clksel         = omap343x_gpt_clksel,
2538         .clkdm_name     = "per_clkdm",
2539         .recalc         = &omap2_clksel_recalc,
2540 };
2541
2542 static struct clk gpt6_fck = {
2543         .name           = "gpt6_fck",
2544         .ops            = &clkops_omap2_dflt_wait,
2545         .init           = &omap2_init_clksel_parent,
2546         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2547         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2548         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2549         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2550         .clksel         = omap343x_gpt_clksel,
2551         .clkdm_name     = "per_clkdm",
2552         .recalc         = &omap2_clksel_recalc,
2553 };
2554
2555 static struct clk gpt7_fck = {
2556         .name           = "gpt7_fck",
2557         .ops            = &clkops_omap2_dflt_wait,
2558         .init           = &omap2_init_clksel_parent,
2559         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2560         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2561         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2562         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2563         .clksel         = omap343x_gpt_clksel,
2564         .clkdm_name     = "per_clkdm",
2565         .recalc         = &omap2_clksel_recalc,
2566 };
2567
2568 static struct clk gpt8_fck = {
2569         .name           = "gpt8_fck",
2570         .ops            = &clkops_omap2_dflt_wait,
2571         .init           = &omap2_init_clksel_parent,
2572         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2573         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2574         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2575         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2576         .clksel         = omap343x_gpt_clksel,
2577         .clkdm_name     = "per_clkdm",
2578         .recalc         = &omap2_clksel_recalc,
2579 };
2580
2581 static struct clk gpt9_fck = {
2582         .name           = "gpt9_fck",
2583         .ops            = &clkops_omap2_dflt_wait,
2584         .init           = &omap2_init_clksel_parent,
2585         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2586         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2587         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2588         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2589         .clksel         = omap343x_gpt_clksel,
2590         .clkdm_name     = "per_clkdm",
2591         .recalc         = &omap2_clksel_recalc,
2592 };
2593
2594 static struct clk per_32k_alwon_fck = {
2595         .name           = "per_32k_alwon_fck",
2596         .ops            = &clkops_null,
2597         .parent         = &omap_32k_fck,
2598         .clkdm_name     = "per_clkdm",
2599         .recalc         = &followparent_recalc,
2600 };
2601
2602 static struct clk gpio6_dbck = {
2603         .name           = "gpio6_dbck",
2604         .ops            = &clkops_omap2_dflt,
2605         .parent         = &per_32k_alwon_fck,
2606         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2607         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2608         .clkdm_name     = "per_clkdm",
2609         .recalc         = &followparent_recalc,
2610 };
2611
2612 static struct clk gpio5_dbck = {
2613         .name           = "gpio5_dbck",
2614         .ops            = &clkops_omap2_dflt,
2615         .parent         = &per_32k_alwon_fck,
2616         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2617         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2618         .clkdm_name     = "per_clkdm",
2619         .recalc         = &followparent_recalc,
2620 };
2621
2622 static struct clk gpio4_dbck = {
2623         .name           = "gpio4_dbck",
2624         .ops            = &clkops_omap2_dflt,
2625         .parent         = &per_32k_alwon_fck,
2626         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2627         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2628         .clkdm_name     = "per_clkdm",
2629         .recalc         = &followparent_recalc,
2630 };
2631
2632 static struct clk gpio3_dbck = {
2633         .name           = "gpio3_dbck",
2634         .ops            = &clkops_omap2_dflt,
2635         .parent         = &per_32k_alwon_fck,
2636         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2637         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2638         .clkdm_name     = "per_clkdm",
2639         .recalc         = &followparent_recalc,
2640 };
2641
2642 static struct clk gpio2_dbck = {
2643         .name           = "gpio2_dbck",
2644         .ops            = &clkops_omap2_dflt,
2645         .parent         = &per_32k_alwon_fck,
2646         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2647         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2648         .clkdm_name     = "per_clkdm",
2649         .recalc         = &followparent_recalc,
2650 };
2651
2652 static struct clk wdt3_fck = {
2653         .name           = "wdt3_fck",
2654         .ops            = &clkops_omap2_dflt_wait,
2655         .parent         = &per_32k_alwon_fck,
2656         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2657         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2658         .clkdm_name     = "per_clkdm",
2659         .recalc         = &followparent_recalc,
2660 };
2661
2662 static struct clk per_l4_ick = {
2663         .name           = "per_l4_ick",
2664         .ops            = &clkops_null,
2665         .parent         = &l4_ick,
2666         .clkdm_name     = "per_clkdm",
2667         .recalc         = &followparent_recalc,
2668 };
2669
2670 static struct clk gpio6_ick = {
2671         .name           = "gpio6_ick",
2672         .ops            = &clkops_omap2_iclk_dflt_wait,
2673         .parent         = &per_l4_ick,
2674         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2675         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2676         .clkdm_name     = "per_clkdm",
2677         .recalc         = &followparent_recalc,
2678 };
2679
2680 static struct clk gpio5_ick = {
2681         .name           = "gpio5_ick",
2682         .ops            = &clkops_omap2_iclk_dflt_wait,
2683         .parent         = &per_l4_ick,
2684         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2685         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2686         .clkdm_name     = "per_clkdm",
2687         .recalc         = &followparent_recalc,
2688 };
2689
2690 static struct clk gpio4_ick = {
2691         .name           = "gpio4_ick",
2692         .ops            = &clkops_omap2_iclk_dflt_wait,
2693         .parent         = &per_l4_ick,
2694         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2695         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2696         .clkdm_name     = "per_clkdm",
2697         .recalc         = &followparent_recalc,
2698 };
2699
2700 static struct clk gpio3_ick = {
2701         .name           = "gpio3_ick",
2702         .ops            = &clkops_omap2_iclk_dflt_wait,
2703         .parent         = &per_l4_ick,
2704         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2705         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2706         .clkdm_name     = "per_clkdm",
2707         .recalc         = &followparent_recalc,
2708 };
2709
2710 static struct clk gpio2_ick = {
2711         .name           = "gpio2_ick",
2712         .ops            = &clkops_omap2_iclk_dflt_wait,
2713         .parent         = &per_l4_ick,
2714         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2715         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2716         .clkdm_name     = "per_clkdm",
2717         .recalc         = &followparent_recalc,
2718 };
2719
2720 static struct clk wdt3_ick = {
2721         .name           = "wdt3_ick",
2722         .ops            = &clkops_omap2_iclk_dflt_wait,
2723         .parent         = &per_l4_ick,
2724         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2725         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2726         .clkdm_name     = "per_clkdm",
2727         .recalc         = &followparent_recalc,
2728 };
2729
2730 static struct clk uart3_ick = {
2731         .name           = "uart3_ick",
2732         .ops            = &clkops_omap2_iclk_dflt_wait,
2733         .parent         = &per_l4_ick,
2734         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2735         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2736         .clkdm_name     = "per_clkdm",
2737         .recalc         = &followparent_recalc,
2738 };
2739
2740 static struct clk uart4_ick = {
2741         .name           = "uart4_ick",
2742         .ops            = &clkops_omap2_iclk_dflt_wait,
2743         .parent         = &per_l4_ick,
2744         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2745         .enable_bit     = OMAP3630_EN_UART4_SHIFT,
2746         .clkdm_name     = "per_clkdm",
2747         .recalc         = &followparent_recalc,
2748 };
2749
2750 static struct clk gpt9_ick = {
2751         .name           = "gpt9_ick",
2752         .ops            = &clkops_omap2_iclk_dflt_wait,
2753         .parent         = &per_l4_ick,
2754         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2755         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2756         .clkdm_name     = "per_clkdm",
2757         .recalc         = &followparent_recalc,
2758 };
2759
2760 static struct clk gpt8_ick = {
2761         .name           = "gpt8_ick",
2762         .ops            = &clkops_omap2_iclk_dflt_wait,
2763         .parent         = &per_l4_ick,
2764         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2765         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2766         .clkdm_name     = "per_clkdm",
2767         .recalc         = &followparent_recalc,
2768 };
2769
2770 static struct clk gpt7_ick = {
2771         .name           = "gpt7_ick",
2772         .ops            = &clkops_omap2_iclk_dflt_wait,
2773         .parent         = &per_l4_ick,
2774         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2775         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2776         .clkdm_name     = "per_clkdm",
2777         .recalc         = &followparent_recalc,
2778 };
2779
2780 static struct clk gpt6_ick = {
2781         .name           = "gpt6_ick",
2782         .ops            = &clkops_omap2_iclk_dflt_wait,
2783         .parent         = &per_l4_ick,
2784         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2785         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2786         .clkdm_name     = "per_clkdm",
2787         .recalc         = &followparent_recalc,
2788 };
2789
2790 static struct clk gpt5_ick = {
2791         .name           = "gpt5_ick",
2792         .ops            = &clkops_omap2_iclk_dflt_wait,
2793         .parent         = &per_l4_ick,
2794         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2795         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2796         .clkdm_name     = "per_clkdm",
2797         .recalc         = &followparent_recalc,
2798 };
2799
2800 static struct clk gpt4_ick = {
2801         .name           = "gpt4_ick",
2802         .ops            = &clkops_omap2_iclk_dflt_wait,
2803         .parent         = &per_l4_ick,
2804         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2805         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2806         .clkdm_name     = "per_clkdm",
2807         .recalc         = &followparent_recalc,
2808 };
2809
2810 static struct clk gpt3_ick = {
2811         .name           = "gpt3_ick",
2812         .ops            = &clkops_omap2_iclk_dflt_wait,
2813         .parent         = &per_l4_ick,
2814         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2815         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2816         .clkdm_name     = "per_clkdm",
2817         .recalc         = &followparent_recalc,
2818 };
2819
2820 static struct clk gpt2_ick = {
2821         .name           = "gpt2_ick",
2822         .ops            = &clkops_omap2_iclk_dflt_wait,
2823         .parent         = &per_l4_ick,
2824         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2825         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2826         .clkdm_name     = "per_clkdm",
2827         .recalc         = &followparent_recalc,
2828 };
2829
2830 static struct clk mcbsp2_ick = {
2831         .name           = "mcbsp2_ick",
2832         .ops            = &clkops_omap2_iclk_dflt_wait,
2833         .parent         = &per_l4_ick,
2834         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2835         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2836         .clkdm_name     = "per_clkdm",
2837         .recalc         = &followparent_recalc,
2838 };
2839
2840 static struct clk mcbsp3_ick = {
2841         .name           = "mcbsp3_ick",
2842         .ops            = &clkops_omap2_iclk_dflt_wait,
2843         .parent         = &per_l4_ick,
2844         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2845         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2846         .clkdm_name     = "per_clkdm",
2847         .recalc         = &followparent_recalc,
2848 };
2849
2850 static struct clk mcbsp4_ick = {
2851         .name           = "mcbsp4_ick",
2852         .ops            = &clkops_omap2_iclk_dflt_wait,
2853         .parent         = &per_l4_ick,
2854         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2855         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2856         .clkdm_name     = "per_clkdm",
2857         .recalc         = &followparent_recalc,
2858 };
2859
2860 static const struct clksel mcbsp_234_clksel[] = {
2861         { .parent = &per_96m_fck,  .rates = common_mcbsp_96m_rates },
2862         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
2863         { .parent = NULL }
2864 };
2865
2866 static struct clk mcbsp2_fck = {
2867         .name           = "mcbsp2_fck",
2868         .ops            = &clkops_omap2_dflt_wait,
2869         .init           = &omap2_init_clksel_parent,
2870         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2871         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2872         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2873         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2874         .clksel         = mcbsp_234_clksel,
2875         .clkdm_name     = "per_clkdm",
2876         .recalc         = &omap2_clksel_recalc,
2877 };
2878
2879 static struct clk mcbsp3_fck = {
2880         .name           = "mcbsp3_fck",
2881         .ops            = &clkops_omap2_dflt_wait,
2882         .init           = &omap2_init_clksel_parent,
2883         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2884         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2885         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2886         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2887         .clksel         = mcbsp_234_clksel,
2888         .clkdm_name     = "per_clkdm",
2889         .recalc         = &omap2_clksel_recalc,
2890 };
2891
2892 static struct clk mcbsp4_fck = {
2893         .name           = "mcbsp4_fck",
2894         .ops            = &clkops_omap2_dflt_wait,
2895         .init           = &omap2_init_clksel_parent,
2896         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2897         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2898         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2899         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2900         .clksel         = mcbsp_234_clksel,
2901         .clkdm_name     = "per_clkdm",
2902         .recalc         = &omap2_clksel_recalc,
2903 };
2904
2905 /* EMU clocks */
2906
2907 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2908
2909 static const struct clksel_rate emu_src_sys_rates[] = {
2910         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
2911         { .div = 0 },
2912 };
2913
2914 static const struct clksel_rate emu_src_core_rates[] = {
2915         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2916         { .div = 0 },
2917 };
2918
2919 static const struct clksel_rate emu_src_per_rates[] = {
2920         { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
2921         { .div = 0 },
2922 };
2923
2924 static const struct clksel_rate emu_src_mpu_rates[] = {
2925         { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
2926         { .div = 0 },
2927 };
2928
2929 static const struct clksel emu_src_clksel[] = {
2930         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2931         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2932         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2933         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2934         { .parent = NULL },
2935 };
2936
2937 /*
2938  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2939  * to switch the source of some of the EMU clocks.
2940  * XXX Are there CLKEN bits for these EMU clks?
2941  */
2942 static struct clk emu_src_ck = {
2943         .name           = "emu_src_ck",
2944         .ops            = &clkops_null,
2945         .init           = &omap2_init_clksel_parent,
2946         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2947         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2948         .clksel         = emu_src_clksel,
2949         .clkdm_name     = "emu_clkdm",
2950         .recalc         = &omap2_clksel_recalc,
2951 };
2952
2953 static const struct clksel_rate pclk_emu_rates[] = {
2954         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2955         { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
2956         { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
2957         { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
2958         { .div = 0 },
2959 };
2960
2961 static const struct clksel pclk_emu_clksel[] = {
2962         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2963         { .parent = NULL },
2964 };
2965
2966 static struct clk pclk_fck = {
2967         .name           = "pclk_fck",
2968         .ops            = &clkops_null,
2969         .init           = &omap2_init_clksel_parent,
2970         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2971         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
2972         .clksel         = pclk_emu_clksel,
2973         .clkdm_name     = "emu_clkdm",
2974         .recalc         = &omap2_clksel_recalc,
2975 };
2976
2977 static const struct clksel_rate pclkx2_emu_rates[] = {
2978         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2979         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2980         { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
2981         { .div = 0 },
2982 };
2983
2984 static const struct clksel pclkx2_emu_clksel[] = {
2985         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2986         { .parent = NULL },
2987 };
2988
2989 static struct clk pclkx2_fck = {
2990         .name           = "pclkx2_fck",
2991         .ops            = &clkops_null,
2992         .init           = &omap2_init_clksel_parent,
2993         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2994         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
2995         .clksel         = pclkx2_emu_clksel,
2996         .clkdm_name     = "emu_clkdm",
2997         .recalc         = &omap2_clksel_recalc,
2998 };
2999
3000 static const struct clksel atclk_emu_clksel[] = {
3001         { .parent = &emu_src_ck, .rates = div2_rates },
3002         { .parent = NULL },
3003 };
3004
3005 static struct clk atclk_fck = {
3006         .name           = "atclk_fck",
3007         .ops            = &clkops_null,
3008         .init           = &omap2_init_clksel_parent,
3009         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3010         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
3011         .clksel         = atclk_emu_clksel,
3012         .clkdm_name     = "emu_clkdm",
3013         .recalc         = &omap2_clksel_recalc,
3014 };
3015
3016 static struct clk traceclk_src_fck = {
3017         .name           = "traceclk_src_fck",
3018         .ops            = &clkops_null,
3019         .init           = &omap2_init_clksel_parent,
3020         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3021         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
3022         .clksel         = emu_src_clksel,
3023         .clkdm_name     = "emu_clkdm",
3024         .recalc         = &omap2_clksel_recalc,
3025 };
3026
3027 static const struct clksel_rate traceclk_rates[] = {
3028         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
3029         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
3030         { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
3031         { .div = 0 },
3032 };
3033
3034 static const struct clksel traceclk_clksel[] = {
3035         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3036         { .parent = NULL },
3037 };
3038
3039 static struct clk traceclk_fck = {
3040         .name           = "traceclk_fck",
3041         .ops            = &clkops_null,
3042         .init           = &omap2_init_clksel_parent,
3043         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3044         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
3045         .clksel         = traceclk_clksel,
3046         .clkdm_name     = "emu_clkdm",
3047         .recalc         = &omap2_clksel_recalc,
3048 };
3049
3050 /* SR clocks */
3051
3052 /* SmartReflex fclk (VDD1) */
3053 static struct clk sr1_fck = {
3054         .name           = "sr1_fck",
3055         .ops            = &clkops_omap2_dflt_wait,
3056         .parent         = &sys_ck,
3057         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3058         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
3059         .clkdm_name     = "wkup_clkdm",
3060         .recalc         = &followparent_recalc,
3061 };
3062
3063 /* SmartReflex fclk (VDD2) */
3064 static struct clk sr2_fck = {
3065         .name           = "sr2_fck",
3066         .ops            = &clkops_omap2_dflt_wait,
3067         .parent         = &sys_ck,
3068         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3069         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3070         .clkdm_name     = "wkup_clkdm",
3071         .recalc         = &followparent_recalc,
3072 };
3073
3074 static struct clk sr_l4_ick = {
3075         .name           = "sr_l4_ick",
3076         .ops            = &clkops_null, /* RMK: missing? */
3077         .parent         = &l4_ick,
3078         .clkdm_name     = "core_l4_clkdm",
3079         .recalc         = &followparent_recalc,
3080 };
3081
3082 /* SECURE_32K_FCK clocks */
3083
3084 static struct clk gpt12_fck = {
3085         .name           = "gpt12_fck",
3086         .ops            = &clkops_null,
3087         .parent         = &secure_32k_fck,
3088         .clkdm_name     = "wkup_clkdm",
3089         .recalc         = &followparent_recalc,
3090 };
3091
3092 static struct clk wdt1_fck = {
3093         .name           = "wdt1_fck",
3094         .ops            = &clkops_null,
3095         .parent         = &secure_32k_fck,
3096         .clkdm_name     = "wkup_clkdm",
3097         .recalc         = &followparent_recalc,
3098 };
3099
3100 /* Clocks for AM35XX */
3101 static struct clk ipss_ick = {
3102         .name           = "ipss_ick",
3103         .ops            = &clkops_am35xx_ipss_wait,
3104         .parent         = &core_l3_ick,
3105         .clkdm_name     = "core_l3_clkdm",
3106         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3107         .enable_bit     = AM35XX_EN_IPSS_SHIFT,
3108         .recalc         = &followparent_recalc,
3109 };
3110
3111 static struct clk emac_ick = {
3112         .name           = "emac_ick",
3113         .ops            = &clkops_am35xx_ipss_module_wait,
3114         .parent         = &ipss_ick,
3115         .clkdm_name     = "core_l3_clkdm",
3116         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3117         .enable_bit     = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
3118         .recalc         = &followparent_recalc,
3119 };
3120
3121 static struct clk rmii_ck = {
3122         .name           = "rmii_ck",
3123         .ops            = &clkops_null,
3124         .rate           = 50000000,
3125 };
3126
3127 static struct clk emac_fck = {
3128         .name           = "emac_fck",
3129         .ops            = &clkops_omap2_dflt,
3130         .parent         = &rmii_ck,
3131         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3132         .enable_bit     = AM35XX_CPGMAC_FCLK_SHIFT,
3133         .recalc         = &followparent_recalc,
3134 };
3135
3136 static struct clk hsotgusb_ick_am35xx = {
3137         .name           = "hsotgusb_ick",
3138         .ops            = &clkops_am35xx_ipss_module_wait,
3139         .parent         = &ipss_ick,
3140         .clkdm_name     = "core_l3_clkdm",
3141         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3142         .enable_bit     = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
3143         .recalc         = &followparent_recalc,
3144 };
3145
3146 static struct clk hsotgusb_fck_am35xx = {
3147         .name           = "hsotgusb_fck",
3148         .ops            = &clkops_omap2_dflt,
3149         .parent         = &sys_ck,
3150         .clkdm_name     = "core_l3_clkdm",
3151         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3152         .enable_bit     = AM35XX_USBOTG_FCLK_SHIFT,
3153         .recalc         = &followparent_recalc,
3154 };
3155
3156 static struct clk hecc_ck = {
3157         .name           = "hecc_ck",
3158         .ops            = &clkops_am35xx_ipss_module_wait,
3159         .parent         = &sys_ck,
3160         .clkdm_name     = "core_l3_clkdm",
3161         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3162         .enable_bit     = AM35XX_HECC_VBUSP_CLK_SHIFT,
3163         .recalc         = &followparent_recalc,
3164 };
3165
3166 static struct clk vpfe_ick = {
3167         .name           = "vpfe_ick",
3168         .ops            = &clkops_am35xx_ipss_module_wait,
3169         .parent         = &ipss_ick,
3170         .clkdm_name     = "core_l3_clkdm",
3171         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3172         .enable_bit     = AM35XX_VPFE_VBUSP_CLK_SHIFT,
3173         .recalc         = &followparent_recalc,
3174 };
3175
3176 static struct clk pclk_ck = {
3177         .name           = "pclk_ck",
3178         .ops            = &clkops_null,
3179         .rate           = 27000000,
3180 };
3181
3182 static struct clk vpfe_fck = {
3183         .name           = "vpfe_fck",
3184         .ops            = &clkops_omap2_dflt,
3185         .parent         = &pclk_ck,
3186         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3187         .enable_bit     = AM35XX_VPFE_FCLK_SHIFT,
3188         .recalc         = &followparent_recalc,
3189 };
3190
3191 /*
3192  * The UART1/2 functional clock acts as the functional clock for
3193  * UART4. No separate fclk control available.  XXX Well now we have a
3194  * uart4_fck that is apparently used as the UART4 functional clock,
3195  * but it also seems that uart1_fck or uart2_fck are still needed, at
3196  * least for UART4 softresets to complete.  This really needs
3197  * clarification.
3198  */
3199 static struct clk uart4_ick_am35xx = {
3200         .name           = "uart4_ick",
3201         .ops            = &clkops_omap2_iclk_dflt_wait,
3202         .parent         = &core_l4_ick,
3203         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3204         .enable_bit     = AM35XX_EN_UART4_SHIFT,
3205         .clkdm_name     = "core_l4_clkdm",
3206         .recalc         = &followparent_recalc,
3207 };
3208
3209 static struct clk dummy_apb_pclk = {
3210         .name           = "apb_pclk",
3211         .ops            = &clkops_null,
3212 };
3213
3214 /*
3215  * clkdev
3216  */
3217
3218 static struct omap_clk omap3xxx_clks[] = {
3219         CLK(NULL,       "apb_pclk",     &dummy_apb_pclk,        CK_3XXX),
3220         CLK(NULL,       "omap_32k_fck", &omap_32k_fck,  CK_3XXX),
3221         CLK(NULL,       "virt_12m_ck",  &virt_12m_ck,   CK_3XXX),
3222         CLK(NULL,       "virt_13m_ck",  &virt_13m_ck,   CK_3XXX),
3223         CLK(NULL,       "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX  | CK_36XX),
3224         CLK(NULL,       "virt_19200000_ck", &virt_19200000_ck, CK_3XXX),
3225         CLK(NULL,       "virt_26000000_ck",     &virt_26000000_ck,      CK_3XXX),
3226         CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
3227         CLK(NULL,       "osc_sys_ck",   &osc_sys_ck,    CK_3XXX),
3228         CLK("twl",      "fck",          &osc_sys_ck,    CK_3XXX),
3229         CLK(NULL,       "sys_ck",       &sys_ck,        CK_3XXX),
3230         CLK(NULL,       "sys_altclk",   &sys_altclk,    CK_3XXX),
3231         CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_3XXX),
3232         CLK(NULL,       "sys_clkout1",  &sys_clkout1,   CK_3XXX),
3233         CLK(NULL,       "dpll1_ck",     &dpll1_ck,      CK_3XXX),
3234         CLK(NULL,       "dpll1_x2_ck",  &dpll1_x2_ck,   CK_3XXX),
3235         CLK(NULL,       "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
3236         CLK(NULL,       "dpll2_ck",     &dpll2_ck,      CK_34XX | CK_36XX),
3237         CLK(NULL,       "dpll2_m2_ck",  &dpll2_m2_ck,   CK_34XX | CK_36XX),
3238         CLK(NULL,       "dpll3_ck",     &dpll3_ck,      CK_3XXX),
3239         CLK(NULL,       "core_ck",      &core_ck,       CK_3XXX),
3240         CLK(NULL,       "dpll3_x2_ck",  &dpll3_x2_ck,   CK_3XXX),
3241         CLK(NULL,       "dpll3_m2_ck",  &dpll3_m2_ck,   CK_3XXX),
3242         CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
3243         CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck,   CK_3XXX),
3244         CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
3245         CLK(NULL,       "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
3246         CLK("etb",      "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
3247         CLK(NULL,       "dpll4_ck",     &dpll4_ck,      CK_3XXX),
3248         CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck,   CK_3XXX),
3249         CLK(NULL,       "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
3250         CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
3251         CLK(NULL,       "omap_96m_alwon_fck_3630", &omap_96m_alwon_fck_3630, CK_36XX),
3252         CLK(NULL,       "omap_96m_fck", &omap_96m_fck,  CK_3XXX),
3253         CLK(NULL,       "cm_96m_fck",   &cm_96m_fck,    CK_3XXX),
3254         CLK(NULL,       "omap_54m_fck", &omap_54m_fck,  CK_3XXX),
3255         CLK(NULL,       "omap_48m_fck", &omap_48m_fck,  CK_3XXX),
3256         CLK(NULL,       "omap_12m_fck", &omap_12m_fck,  CK_3XXX),
3257         CLK(NULL,       "dpll4_m2_ck",  &dpll4_m2_ck,   CK_3XXX),
3258         CLK(NULL,       "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
3259         CLK(NULL,       "dpll4_m3_ck",  &dpll4_m3_ck,   CK_3XXX),
3260         CLK(NULL,       "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
3261         CLK(NULL,       "dpll4_m4_ck",  &dpll4_m4_ck,   CK_3XXX),
3262         CLK(NULL,       "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
3263         CLK(NULL,       "dpll4_m5_ck",  &dpll4_m5_ck,   CK_3XXX),
3264         CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
3265         CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck,   CK_3XXX),
3266         CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
3267         CLK(NULL,       "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
3268         CLK("etb",      "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
3269         CLK(NULL,       "dpll5_ck",     &dpll5_ck,      CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3270         CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3271         CLK(NULL,       "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
3272         CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_3XXX),
3273         CLK(NULL,       "corex2_fck",   &corex2_fck,    CK_3XXX),
3274         CLK(NULL,       "dpll1_fck",    &dpll1_fck,     CK_3XXX),
3275         CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_3XXX),
3276         CLK(NULL,       "arm_fck",      &arm_fck,       CK_3XXX),
3277         CLK(NULL,       "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
3278         CLK("etb",      "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
3279         CLK(NULL,       "dpll2_fck",    &dpll2_fck,     CK_34XX | CK_36XX),
3280         CLK(NULL,       "iva2_ck",      &iva2_ck,       CK_34XX | CK_36XX),
3281         CLK(NULL,       "l3_ick",       &l3_ick,        CK_3XXX),
3282         CLK(NULL,       "l4_ick",       &l4_ick,        CK_3XXX),
3283         CLK(NULL,       "rm_ick",       &rm_ick,        CK_3XXX),
3284         CLK(NULL,       "gfx_l3_ck",    &gfx_l3_ck,     CK_3430ES1),
3285         CLK(NULL,       "gfx_l3_fck",   &gfx_l3_fck,    CK_3430ES1),
3286         CLK(NULL,       "gfx_l3_ick",   &gfx_l3_ick,    CK_3430ES1),
3287         CLK(NULL,       "gfx_cg1_ck",   &gfx_cg1_ck,    CK_3430ES1),
3288         CLK(NULL,       "gfx_cg2_ck",   &gfx_cg2_ck,    CK_3430ES1),
3289         CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3290         CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3291         CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck,   CK_3430ES1),
3292         CLK(NULL,       "modem_fck",    &modem_fck,     CK_34XX | CK_36XX),
3293         CLK(NULL,       "sad2d_ick",    &sad2d_ick,     CK_34XX | CK_36XX),
3294         CLK(NULL,       "mad2d_ick",    &mad2d_ick,     CK_34XX | CK_36XX),
3295         CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_3XXX),
3296         CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_3XXX),
3297         CLK(NULL,       "cpefuse_fck",  &cpefuse_fck,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3298         CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3299         CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3300         CLK("usbhs_omap",       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3301         CLK("usbhs_tll",        "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3302         CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_3XXX),
3303         CLK(NULL,       "mmchs3_fck",   &mmchs3_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3304         CLK(NULL,       "mmchs2_fck",   &mmchs2_fck,    CK_3XXX),
3305         CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_34XX | CK_36XX),
3306         CLK(NULL,       "mmchs1_fck",   &mmchs1_fck,    CK_3XXX),
3307         CLK(NULL,       "i2c3_fck",     &i2c3_fck,      CK_3XXX),
3308         CLK(NULL,       "i2c2_fck",     &i2c2_fck,      CK_3XXX),
3309         CLK(NULL,       "i2c1_fck",     &i2c1_fck,      CK_3XXX),
3310         CLK(NULL,       "mcbsp5_fck",   &mcbsp5_fck,    CK_3XXX),
3311         CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck,    CK_3XXX),
3312         CLK(NULL,       "core_48m_fck", &core_48m_fck,  CK_3XXX),
3313         CLK(NULL,       "mcspi4_fck",   &mcspi4_fck,    CK_3XXX),
3314         CLK(NULL,       "mcspi3_fck",   &mcspi3_fck,    CK_3XXX),
3315         CLK(NULL,       "mcspi2_fck",   &mcspi2_fck,    CK_3XXX),
3316         CLK(NULL,       "mcspi1_fck",   &mcspi1_fck,    CK_3XXX),
3317         CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_3XXX),
3318         CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_3XXX),
3319         CLK(NULL,       "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
3320         CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_3XXX),
3321         CLK("omap_hdq.0",       "fck",  &hdq_fck,       CK_3XXX),
3322         CLK(NULL,       "hdq_fck",      &hdq_fck,       CK_3XXX),
3323         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1,   CK_3430ES1),
3324         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2,   CK_3430ES2PLUS | CK_36XX),
3325         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1,   CK_3430ES1),
3326         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es2,   CK_3430ES2PLUS | CK_36XX),
3327         CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_3XXX),
3328         CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es1,  CK_3430ES1),
3329         CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es2,  CK_3430ES2PLUS | CK_36XX),
3330         CLK(NULL,       "hsotgusb_ick", &hsotgusb_ick_3430es1,  CK_3430ES1),
3331         CLK(NULL,       "hsotgusb_ick", &hsotgusb_ick_3430es2,  CK_3430ES2PLUS | CK_36XX),
3332         CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_3XXX),
3333         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_3XXX),
3334         CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
3335         CLK(NULL,       "pka_ick",      &pka_ick,       CK_34XX | CK_36XX),
3336         CLK(NULL,       "core_l4_ick",  &core_l4_ick,   CK_3XXX),
3337         CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3338         CLK("usbhs_omap",       "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3339         CLK("usbhs_tll",        "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3340         CLK("omap_hsmmc.2",     "ick",  &mmchs3_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3341         CLK(NULL,       "mmchs3_ick",   &mmchs3_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3342         CLK(NULL,       "icr_ick",      &icr_ick,       CK_34XX | CK_36XX),
3343         CLK("omap-aes", "ick",  &aes2_ick,      CK_34XX | CK_36XX),
3344         CLK("omap-sham",        "ick",  &sha12_ick,     CK_34XX | CK_36XX),
3345         CLK(NULL,       "des2_ick",     &des2_ick,      CK_34XX | CK_36XX),
3346         CLK("omap_hsmmc.1",     "ick",  &mmchs2_ick,    CK_3XXX),
3347         CLK("omap_hsmmc.0",     "ick",  &mmchs1_ick,    CK_3XXX),
3348         CLK(NULL,       "mmchs2_ick",   &mmchs2_ick,    CK_3XXX),
3349         CLK(NULL,       "mmchs1_ick",   &mmchs1_ick,    CK_3XXX),
3350         CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_34XX | CK_36XX),
3351         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_3XXX),
3352         CLK(NULL,       "hdq_ick",      &hdq_ick,       CK_3XXX),
3353         CLK("omap2_mcspi.4", "ick",     &mcspi4_ick,    CK_3XXX),
3354         CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_3XXX),
3355         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_3XXX),
3356         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_3XXX),
3357         CLK(NULL,       "mcspi4_ick",   &mcspi4_ick,    CK_3XXX),
3358         CLK(NULL,       "mcspi3_ick",   &mcspi3_ick,    CK_3XXX),
3359         CLK(NULL,       "mcspi2_ick",   &mcspi2_ick,    CK_3XXX),
3360         CLK(NULL,       "mcspi1_ick",   &mcspi1_ick,    CK_3XXX),
3361         CLK("omap_i2c.3", "ick",        &i2c3_ick,      CK_3XXX),
3362         CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_3XXX),
3363         CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_3XXX),
3364         CLK(NULL,       "i2c3_ick",     &i2c3_ick,      CK_3XXX),
3365         CLK(NULL,       "i2c2_ick",     &i2c2_ick,      CK_3XXX),
3366         CLK(NULL,       "i2c1_ick",     &i2c1_ick,      CK_3XXX),
3367         CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_3XXX),
3368         CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_3XXX),
3369         CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_3XXX),
3370         CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_3XXX),
3371         CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_3XXX),
3372         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_3XXX),
3373         CLK(NULL,       "mcbsp5_ick",   &mcbsp5_ick,    CK_3XXX),
3374         CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick,    CK_3XXX),
3375         CLK(NULL,       "fac_ick",      &fac_ick,       CK_3430ES1),
3376         CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
3377         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_3XXX),
3378         CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_34XX | CK_36XX),
3379         CLK(NULL,       "ssi_ick",      &ssi_ick_3430es1,       CK_3430ES1),
3380         CLK(NULL,       "ssi_ick",      &ssi_ick_3430es2,       CK_3430ES2PLUS | CK_36XX),
3381         CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_3430ES1),
3382         CLK(NULL,       "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX),
3383         CLK(NULL,       "aes1_ick",     &aes1_ick,      CK_34XX | CK_36XX),
3384         CLK("omap_rng", "ick",          &rng_ick,       CK_34XX | CK_36XX),
3385         CLK(NULL,       "sha11_ick",    &sha11_ick,     CK_34XX | CK_36XX),
3386         CLK(NULL,       "des1_ick",     &des1_ick,      CK_34XX | CK_36XX),
3387         CLK(NULL,       "dss1_alwon_fck",               &dss1_alwon_fck_3430es1, CK_3430ES1),
3388         CLK(NULL,       "dss1_alwon_fck",               &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3389         CLK(NULL,       "dss_tv_fck",   &dss_tv_fck,    CK_3XXX),
3390         CLK(NULL,       "dss_96m_fck",  &dss_96m_fck,   CK_3XXX),
3391         CLK(NULL,       "dss2_alwon_fck",       &dss2_alwon_fck, CK_3XXX),
3392         CLK("omapdss_dss",      "ick",          &dss_ick_3430es1,       CK_3430ES1),
3393         CLK(NULL,       "dss_ick",              &dss_ick_3430es1,       CK_3430ES1),
3394         CLK("omapdss_dss",      "ick",          &dss_ick_3430es2,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3395         CLK(NULL,       "dss_ick",              &dss_ick_3430es2,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3396         CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_34XX | CK_36XX),
3397         CLK(NULL,       "cam_ick",      &cam_ick,       CK_34XX | CK_36XX),
3398         CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_34XX | CK_36XX),
3399         CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3400         CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3401         CLK(NULL,       "usbhost_ick",  &usbhost_ick,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3402         CLK("usbhs_omap",       "usbhost_ick",  &usbhost_ick,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3403         CLK(NULL,       "utmi_p1_gfclk",        &dummy_ck,      CK_3XXX),
3404         CLK(NULL,       "utmi_p2_gfclk",        &dummy_ck,      CK_3XXX),
3405         CLK(NULL,       "xclk60mhsp1_ck",       &dummy_ck,      CK_3XXX),
3406         CLK(NULL,       "xclk60mhsp2_ck",       &dummy_ck,      CK_3XXX),
3407         CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &dummy_ck,      CK_3XXX),
3408         CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &dummy_ck,      CK_3XXX),
3409         CLK("usbhs_omap",       "usb_tll_hs_usb_ch0_clk",       &dummy_ck,      CK_3XXX),
3410         CLK("usbhs_omap",       "usb_tll_hs_usb_ch1_clk",       &dummy_ck,      CK_3XXX),
3411         CLK("usbhs_tll",        "usb_tll_hs_usb_ch0_clk",       &dummy_ck,      CK_3XXX),
3412         CLK("usbhs_tll",        "usb_tll_hs_usb_ch1_clk",       &dummy_ck,      CK_3XXX),
3413         CLK(NULL,       "init_60m_fclk",        &dummy_ck,      CK_3XXX),
3414         CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2PLUS | CK_36XX),
3415         CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_3XXX),
3416         CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck,  CK_3XXX),
3417         CLK(NULL,       "gpio1_dbck",   &gpio1_dbck,    CK_3XXX),
3418         CLK(NULL,       "wdt2_fck",             &wdt2_fck,      CK_3XXX),
3419         CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick,   CK_34XX | CK_36XX),
3420         CLK(NULL,       "usim_ick",     &usim_ick,      CK_3430ES2PLUS | CK_36XX),
3421         CLK("omap_wdt", "ick",          &wdt2_ick,      CK_3XXX),
3422         CLK(NULL,       "wdt2_ick",     &wdt2_ick,      CK_3XXX),
3423         CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_3XXX),
3424         CLK(NULL,       "gpio1_ick",    &gpio1_ick,     CK_3XXX),
3425         CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
3426         CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_3XXX),
3427         CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_3XXX),
3428         CLK(NULL,       "per_96m_fck",  &per_96m_fck,   CK_3XXX),
3429         CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_3XXX),
3430         CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_3XXX),
3431         CLK(NULL,       "uart4_fck",    &uart4_fck,     CK_36XX),
3432         CLK(NULL,       "uart4_fck",    &uart4_fck_am35xx, CK_AM35XX),
3433         CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_3XXX),
3434         CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_3XXX),
3435         CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_3XXX),
3436         CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_3XXX),
3437         CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_3XXX),
3438         CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_3XXX),
3439         CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_3XXX),
3440         CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_3XXX),
3441         CLK(NULL,       "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
3442         CLK(NULL,       "gpio6_dbck",   &gpio6_dbck,    CK_3XXX),
3443         CLK(NULL,       "gpio5_dbck",   &gpio5_dbck,    CK_3XXX),
3444         CLK(NULL,       "gpio4_dbck",   &gpio4_dbck,    CK_3XXX),
3445         CLK(NULL,       "gpio3_dbck",   &gpio3_dbck,    CK_3XXX),
3446         CLK(NULL,       "gpio2_dbck",   &gpio2_dbck,    CK_3XXX),
3447         CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_3XXX),
3448         CLK(NULL,       "per_l4_ick",   &per_l4_ick,    CK_3XXX),
3449         CLK(NULL,       "gpio6_ick",    &gpio6_ick,     CK_3XXX),
3450         CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_3XXX),
3451         CLK(NULL,       "gpio4_ick",    &gpio4_ick,     CK_3XXX),
3452         CLK(NULL,       "gpio3_ick",    &gpio3_ick,     CK_3XXX),
3453         CLK(NULL,       "gpio2_ick",    &gpio2_ick,     CK_3XXX),
3454         CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_3XXX),
3455         CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_3XXX),
3456         CLK(NULL,       "uart4_ick",    &uart4_ick,     CK_36XX),
3457         CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_3XXX),
3458         CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_3XXX),
3459         CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_3XXX),
3460         CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_3XXX),
3461         CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_3XXX),
3462         CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_3XXX),
3463         CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_3XXX),
3464         CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_3XXX),
3465         CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_3XXX),
3466         CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_3XXX),
3467         CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_3XXX),
3468         CLK(NULL,       "mcbsp4_ick",   &mcbsp2_ick,    CK_3XXX),
3469         CLK(NULL,       "mcbsp3_ick",   &mcbsp3_ick,    CK_3XXX),
3470         CLK(NULL,       "mcbsp2_ick",   &mcbsp4_ick,    CK_3XXX),
3471         CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_3XXX),
3472         CLK(NULL,       "mcbsp3_fck",   &mcbsp3_fck,    CK_3XXX),
3473         CLK(NULL,       "mcbsp4_fck",   &mcbsp4_fck,    CK_3XXX),
3474         CLK(NULL,       "emu_src_ck",   &emu_src_ck,    CK_3XXX),
3475         CLK("etb",      "emu_src_ck",   &emu_src_ck,    CK_3XXX),
3476         CLK(NULL,       "pclk_fck",     &pclk_fck,      CK_3XXX),
3477         CLK(NULL,       "pclkx2_fck",   &pclkx2_fck,    CK_3XXX),
3478         CLK(NULL,       "atclk_fck",    &atclk_fck,     CK_3XXX),
3479         CLK(NULL,       "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
3480         CLK(NULL,       "traceclk_fck", &traceclk_fck,  CK_3XXX),
3481         CLK(NULL,       "sr1_fck",      &sr1_fck,       CK_34XX | CK_36XX),
3482         CLK(NULL,       "sr2_fck",      &sr2_fck,       CK_34XX | CK_36XX),
3483         CLK(NULL,       "sr_l4_ick",    &sr_l4_ick,     CK_34XX | CK_36XX),
3484         CLK(NULL,       "secure_32k_fck", &secure_32k_fck, CK_3XXX),
3485         CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_3XXX),
3486         CLK(NULL,       "wdt1_fck",     &wdt1_fck,      CK_3XXX),
3487         CLK(NULL,       "ipss_ick",     &ipss_ick,      CK_AM35XX),
3488         CLK(NULL,       "rmii_ck",      &rmii_ck,       CK_AM35XX),
3489         CLK(NULL,       "pclk_ck",      &pclk_ck,       CK_AM35XX),
3490         CLK(NULL,       "emac_ick",     &emac_ick,      CK_AM35XX),
3491         CLK(NULL,       "emac_fck",     &emac_fck,      CK_AM35XX),
3492         CLK("davinci_emac.0",   NULL,   &emac_ick,      CK_AM35XX),
3493         CLK("davinci_mdio.0",   NULL,   &emac_fck,      CK_AM35XX),
3494         CLK(NULL,       "vpfe_ick",     &emac_ick,      CK_AM35XX),
3495         CLK(NULL,       "vpfe_fck",     &emac_fck,      CK_AM35XX),
3496         CLK("vpfe-capture",     "master",       &vpfe_ick,      CK_AM35XX),
3497         CLK("vpfe-capture",     "slave",        &vpfe_fck,      CK_AM35XX),
3498         CLK(NULL,       "hsotgusb_ick",         &hsotgusb_ick_am35xx,   CK_AM35XX),
3499         CLK(NULL,       "hsotgusb_fck",         &hsotgusb_fck_am35xx,   CK_AM35XX),
3500         CLK(NULL,       "hecc_ck",      &hecc_ck,       CK_AM35XX),
3501         CLK(NULL,       "uart4_ick",    &uart4_ick_am35xx,      CK_AM35XX),
3502         CLK(NULL,       "timer_32k_ck", &omap_32k_fck,  CK_3XXX),
3503         CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_3XXX),
3504         CLK(NULL,       "cpufreq_ck",   &dpll1_ck,      CK_3XXX),
3505 };
3506
3507
3508 int __init omap3xxx_clk_init(void)
3509 {
3510         struct omap_clk *c;
3511         u32 cpu_clkflg = 0;
3512
3513         if (soc_is_am35xx()) {
3514                 cpu_mask = RATE_IN_34XX;
3515                 cpu_clkflg = CK_AM35XX;
3516         } else if (cpu_is_omap3630()) {
3517                 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
3518                 cpu_clkflg = CK_36XX;
3519         } else if (cpu_is_ti816x()) {
3520                 cpu_mask = RATE_IN_TI816X;
3521                 cpu_clkflg = CK_TI816X;
3522         } else if (soc_is_am33xx()) {
3523                 cpu_mask = RATE_IN_AM33XX;
3524         } else if (cpu_is_ti814x()) {
3525                 cpu_mask = RATE_IN_TI814X;
3526         } else if (cpu_is_omap34xx()) {
3527                 if (omap_rev() == OMAP3430_REV_ES1_0) {
3528                         cpu_mask = RATE_IN_3430ES1;
3529                         cpu_clkflg = CK_3430ES1;
3530                 } else {
3531                         /*
3532                          * Assume that anything that we haven't matched yet
3533                          * has 3430ES2-type clocks.
3534                          */
3535                         cpu_mask = RATE_IN_3430ES2PLUS;
3536                         cpu_clkflg = CK_3430ES2PLUS;
3537                 }
3538         } else {
3539                 WARN(1, "clock: could not identify OMAP3 variant\n");
3540         }
3541
3542         if (omap3_has_192mhz_clk())
3543                 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
3544
3545         if (cpu_is_omap3630()) {
3546                 /*
3547                  * XXX This type of dynamic rewriting of the clock tree is
3548                  * deprecated and should be revised soon.
3549                  *
3550                  * For 3630: override clkops_omap2_dflt_wait for the
3551                  * clocks affected from PWRDN reset Limitation
3552                  */
3553                 dpll3_m3x2_ck.ops =
3554                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3555                 dpll4_m2x2_ck.ops =
3556                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3557                 dpll4_m3x2_ck.ops =
3558                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3559                 dpll4_m4x2_ck.ops =
3560                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3561                 dpll4_m5x2_ck.ops =
3562                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3563                 dpll4_m6x2_ck.ops =
3564                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3565         }
3566
3567         /*
3568          * XXX This type of dynamic rewriting of the clock tree is
3569          * deprecated and should be revised soon.
3570          */
3571         if (cpu_is_omap3630())
3572                 dpll4_dd = dpll4_dd_3630;
3573         else
3574                 dpll4_dd = dpll4_dd_34xx;
3575
3576         clk_init(&omap2_clk_functions);
3577
3578         for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3579              c++)
3580                 clk_preinit(c->lk.clk);
3581
3582         for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3583              c++)
3584                 if (c->cpu & cpu_clkflg) {
3585                         clkdev_add(&c->lk);
3586                         clk_register(c->lk.clk);
3587                         omap2_init_clk_clkdm(c->lk.clk);
3588                 }
3589
3590         /* Disable autoidle on all clocks; let the PM code enable it later */
3591         omap_clk_disable_autoidle_all();
3592
3593         recalculate_root_clocks();
3594
3595         pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
3596                 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
3597                 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
3598
3599         /*
3600          * Only enable those clocks we will need, let the drivers
3601          * enable other clocks as necessary
3602          */
3603         clk_enable_init_clocks();
3604
3605         /*
3606          * Lock DPLL5 -- here only until other device init code can
3607          * handle this
3608          */
3609         if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
3610                 omap3_clk_lock_dpll5();
3611
3612         /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3613         sdrc_ick_p = clk_get(NULL, "sdrc_ick");
3614         arm_fck_p = clk_get(NULL, "arm_fck");
3615
3616         return 0;
3617 }