arch/arm/mach-omap2/clock34xx_data.c

   1 /*
   2  * OMAP3 clock data
   3  *
   4  * Copyright (C) 2007-2009 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2009 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/kernel.h>
  21 #include <linux/clk.h>
  22
  23 #include <plat/control.h>
  24 #include <plat/clkdev_omap.h>
  25
  26 #include "clock.h"
  27 #include "clock34xx.h"
  28 #include "cm.h"
  29 #include "cm-regbits-34xx.h"
  30 #include "prm.h"
  31 #include "prm-regbits-34xx.h"
  32
  33 /*
  34  * clocks
  35  */
  36
  37 #define OMAP_CM_REGADDR         OMAP34XX_CM_REGADDR
  38
  39 /* Maximum DPLL multiplier, divider values for OMAP3 */
  40 #define OMAP3_MAX_DPLL_MULT             2048
  41 #define OMAP3_MAX_DPLL_DIV              128
  42
  43 /*
  44  * DPLL1 supplies clock to the MPU.
  45  * DPLL2 supplies clock to the IVA2.
  46  * DPLL3 supplies CORE domain clocks.
  47  * DPLL4 supplies peripheral clocks.
  48  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  49  */
  50
  51 /* Forward declarations for DPLL bypass clocks */
  52 static struct clk dpll1_fck;
  53 static struct clk dpll2_fck;
  54
  55 /* PRM CLOCKS */
  56
  57 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  58 static struct clk omap_32k_fck = {
  59         .name           = "omap_32k_fck",
  60         .ops            = &clkops_null,
  61         .rate           = 32768,
  62         .flags          = RATE_FIXED,
  63 };
  64
  65 static struct clk secure_32k_fck = {
  66         .name           = "secure_32k_fck",
  67         .ops            = &clkops_null,
  68         .rate           = 32768,
  69         .flags          = RATE_FIXED,
  70 };
  71
  72 /* Virtual source clocks for osc_sys_ck */
  73 static struct clk virt_12m_ck = {
  74         .name           = "virt_12m_ck",
  75         .ops            = &clkops_null,
  76         .rate           = 12000000,
  77         .flags          = RATE_FIXED,
  78 };
  79
  80 static struct clk virt_13m_ck = {
  81         .name           = "virt_13m_ck",
  82         .ops            = &clkops_null,
  83         .rate           = 13000000,
  84         .flags          = RATE_FIXED,
  85 };
  86
  87 static struct clk virt_16_8m_ck = {
  88         .name           = "virt_16_8m_ck",
  89         .ops            = &clkops_null,
  90         .rate           = 16800000,
  91         .flags          = RATE_FIXED,
  92 };
  93
  94 static struct clk virt_19_2m_ck = {
  95         .name           = "virt_19_2m_ck",
  96         .ops            = &clkops_null,
  97         .rate           = 19200000,
  98         .flags          = RATE_FIXED,
  99 };
 100
 101 static struct clk virt_26m_ck = {
 102         .name           = "virt_26m_ck",
 103         .ops            = &clkops_null,
 104         .rate           = 26000000,
 105         .flags          = RATE_FIXED,
 106 };
 107
 108 static struct clk virt_38_4m_ck = {
 109         .name           = "virt_38_4m_ck",
 110         .ops            = &clkops_null,
 111         .rate           = 38400000,
 112         .flags          = RATE_FIXED,
 113 };
 114
 115 static const struct clksel_rate osc_sys_12m_rates[] = {
 116         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 117         { .div = 0 }
 118 };
 119
 120 static const struct clksel_rate osc_sys_13m_rates[] = {
 121         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 122         { .div = 0 }
 123 };
 124
 125 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 126         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 127         { .div = 0 }
 128 };
 129
 130 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 131         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 132         { .div = 0 }
 133 };
 134
 135 static const struct clksel_rate osc_sys_26m_rates[] = {
 136         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 137         { .div = 0 }
 138 };
 139
 140 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 141         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 142         { .div = 0 }
 143 };
 144
 145 static const struct clksel osc_sys_clksel[] = {
 146         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 147         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 148         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 149         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 150         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 151         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 152         { .parent = NULL },
 153 };
 154
 155 /* Oscillator clock */
 156 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 157 static struct clk osc_sys_ck = {
 158         .name           = "osc_sys_ck",
 159         .ops            = &clkops_null,
 160         .init           = &omap2_init_clksel_parent,
 161         .clksel_reg     = OMAP3430_PRM_CLKSEL,
 162         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 163         .clksel         = osc_sys_clksel,
 164         /* REVISIT: deal with autoextclkmode? */
 165         .flags          = RATE_FIXED,
 166         .recalc         = &omap2_clksel_recalc,
 167 };
 168
 169 static const struct clksel_rate div2_rates[] = {
 170         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 171         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 172         { .div = 0 }
 173 };
 174
 175 static const struct clksel sys_clksel[] = {
 176         { .parent = &osc_sys_ck, .rates = div2_rates },
 177         { .parent = NULL }
 178 };
 179
 180 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 181 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 182 static struct clk sys_ck = {
 183         .name           = "sys_ck",
 184         .ops            = &clkops_null,
 185         .parent         = &osc_sys_ck,
 186         .init           = &omap2_init_clksel_parent,
 187         .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
 188         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 189         .clksel         = sys_clksel,
 190         .recalc         = &omap2_clksel_recalc,
 191 };
 192
 193 static struct clk sys_altclk = {
 194         .name           = "sys_altclk",
 195         .ops            = &clkops_null,
 196 };
 197
 198 /* Optional external clock input for some McBSPs */
 199 static struct clk mcbsp_clks = {
 200         .name           = "mcbsp_clks",
 201         .ops            = &clkops_null,
 202 };
 203
 204 /* PRM EXTERNAL CLOCK OUTPUT */
 205
 206 static struct clk sys_clkout1 = {
 207         .name           = "sys_clkout1",
 208         .ops            = &clkops_omap2_dflt,
 209         .parent         = &osc_sys_ck,
 210         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
 211         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 212         .recalc         = &followparent_recalc,
 213 };
 214
 215 /* DPLLS */
 216
 217 /* CM CLOCKS */
 218
 219 static const struct clksel_rate div16_dpll_rates[] = {
 220         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 221         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 222         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 223         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 224         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 225         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 226         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 227         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 228         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 229         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 230         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 231         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 232         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 233         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 234         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 235         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 236         { .div = 0 }
 237 };
 238
 239 /* DPLL1 */
 240 /* MPU clock source */
 241 /* Type: DPLL */
 242 static struct dpll_data dpll1_dd = {
 243         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 244         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 245         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 246         .clk_bypass     = &dpll1_fck,
 247         .clk_ref        = &sys_ck,
 248         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 249         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 250         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 251         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 252         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 253         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 254         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 255         .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 256         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 257         .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 258         .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
 259         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 260         .min_divider    = 1,
 261         .max_divider    = OMAP3_MAX_DPLL_DIV,
 262         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 263 };
 264
 265 static struct clk dpll1_ck = {
 266         .name           = "dpll1_ck",
 267         .ops            = &clkops_null,
 268         .parent         = &sys_ck,
 269         .dpll_data      = &dpll1_dd,
 270         .round_rate     = &omap2_dpll_round_rate,
 271         .set_rate       = &omap3_noncore_dpll_set_rate,
 272         .clkdm_name     = "dpll1_clkdm",
 273         .recalc         = &omap3_dpll_recalc,
 274 };
 275
 276 /*
 277  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 278  * DPLL isn't bypassed.
 279  */
 280 static struct clk dpll1_x2_ck = {
 281         .name           = "dpll1_x2_ck",
 282         .ops            = &clkops_null,
 283         .parent         = &dpll1_ck,
 284         .clkdm_name     = "dpll1_clkdm",
 285         .recalc         = &omap3_clkoutx2_recalc,
 286 };
 287
 288 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 289 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 290         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 291         { .parent = NULL }
 292 };
 293
 294 /*
 295  * Does not exist in the TRM - needed to separate the M2 divider from
 296  * bypass selection in mpu_ck
 297  */
 298 static struct clk dpll1_x2m2_ck = {
 299         .name           = "dpll1_x2m2_ck",
 300         .ops            = &clkops_null,
 301         .parent         = &dpll1_x2_ck,
 302         .init           = &omap2_init_clksel_parent,
 303         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 304         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 305         .clksel         = div16_dpll1_x2m2_clksel,
 306         .clkdm_name     = "dpll1_clkdm",
 307         .recalc         = &omap2_clksel_recalc,
 308 };
 309
 310 /* DPLL2 */
 311 /* IVA2 clock source */
 312 /* Type: DPLL */
 313
 314 static struct dpll_data dpll2_dd = {
 315         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 316         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 317         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 318         .clk_bypass     = &dpll2_fck,
 319         .clk_ref        = &sys_ck,
 320         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 321         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 322         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 323         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 324                                 (1 << DPLL_LOW_POWER_BYPASS),
 325         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 326         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 327         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 328         .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 329         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 330         .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 331         .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
 332         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 333         .min_divider    = 1,
 334         .max_divider    = OMAP3_MAX_DPLL_DIV,
 335         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 336 };
 337
 338 static struct clk dpll2_ck = {
 339         .name           = "dpll2_ck",
 340         .ops            = &clkops_noncore_dpll_ops,
 341         .parent         = &sys_ck,
 342         .dpll_data      = &dpll2_dd,
 343         .round_rate     = &omap2_dpll_round_rate,
 344         .set_rate       = &omap3_noncore_dpll_set_rate,
 345         .clkdm_name     = "dpll2_clkdm",
 346         .recalc         = &omap3_dpll_recalc,
 347 };
 348
 349 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 350         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 351         { .parent = NULL }
 352 };
 353
 354 /*
 355  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 356  * or CLKOUTX2. CLKOUT seems most plausible.
 357  */
 358 static struct clk dpll2_m2_ck = {
 359         .name           = "dpll2_m2_ck",
 360         .ops            = &clkops_null,
 361         .parent         = &dpll2_ck,
 362         .init           = &omap2_init_clksel_parent,
 363         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
 364                                           OMAP3430_CM_CLKSEL2_PLL),
 365         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 366         .clksel         = div16_dpll2_m2x2_clksel,
 367         .clkdm_name     = "dpll2_clkdm",
 368         .recalc         = &omap2_clksel_recalc,
 369 };
 370
 371 /*
 372  * DPLL3
 373  * Source clock for all interfaces and for some device fclks
 374  * REVISIT: Also supports fast relock bypass - not included below
 375  */
 376 static struct dpll_data dpll3_dd = {
 377         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 378         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 379         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 380         .clk_bypass     = &sys_ck,
 381         .clk_ref        = &sys_ck,
 382         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
 383         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 384         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 385         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 386         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 387         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 388         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 389         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 390         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 391         .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
 392         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 393         .min_divider    = 1,
 394         .max_divider    = OMAP3_MAX_DPLL_DIV,
 395         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 396 };
 397
 398 static struct clk dpll3_ck = {
 399         .name           = "dpll3_ck",
 400         .ops            = &clkops_null,
 401         .parent         = &sys_ck,
 402         .dpll_data      = &dpll3_dd,
 403         .round_rate     = &omap2_dpll_round_rate,
 404         .clkdm_name     = "dpll3_clkdm",
 405         .recalc         = &omap3_dpll_recalc,
 406 };
 407
 408 /*
 409  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 410  * DPLL isn't bypassed
 411  */
 412 static struct clk dpll3_x2_ck = {
 413         .name           = "dpll3_x2_ck",
 414         .ops            = &clkops_null,
 415         .parent         = &dpll3_ck,
 416         .clkdm_name     = "dpll3_clkdm",
 417         .recalc         = &omap3_clkoutx2_recalc,
 418 };
 419
 420 static const struct clksel_rate div31_dpll3_rates[] = {
 421         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 422         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 423         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 424         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 425         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 426         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 427         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 428         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 429         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 430         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 431         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 432         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 433         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 434         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 435         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 436         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 437         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 438         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 439         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 440         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 441         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 442         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 443         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 444         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 445         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 446         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 447         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 448         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 449         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 450         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 451         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 452         { .div = 0 },
 453 };
 454
 455 static const struct clksel div31_dpll3m2_clksel[] = {
 456         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 457         { .parent = NULL }
 458 };
 459
 460 /* DPLL3 output M2 - primary control point for CORE speed */
 461 static struct clk dpll3_m2_ck = {
 462         .name           = "dpll3_m2_ck",
 463         .ops            = &clkops_null,
 464         .parent         = &dpll3_ck,
 465         .init           = &omap2_init_clksel_parent,
 466         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 467         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 468         .clksel         = div31_dpll3m2_clksel,
 469         .clkdm_name     = "dpll3_clkdm",
 470         .round_rate     = &omap2_clksel_round_rate,
 471         .set_rate       = &omap3_core_dpll_m2_set_rate,
 472         .recalc         = &omap2_clksel_recalc,
 473 };
 474
 475 static struct clk core_ck = {
 476         .name           = "core_ck",
 477         .ops            = &clkops_null,
 478         .parent         = &dpll3_m2_ck,
 479         .recalc         = &followparent_recalc,
 480 };
 481
 482 static struct clk dpll3_m2x2_ck = {
 483         .name           = "dpll3_m2x2_ck",
 484         .ops            = &clkops_null,
 485         .parent         = &dpll3_m2_ck,
 486         .clkdm_name     = "dpll3_clkdm",
 487         .recalc         = &omap3_clkoutx2_recalc,
 488 };
 489
 490 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 491 static const struct clksel div16_dpll3_clksel[] = {
 492         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 493         { .parent = NULL }
 494 };
 495
 496 /* This virtual clock is the source for dpll3_m3x2_ck */
 497 static struct clk dpll3_m3_ck = {
 498         .name           = "dpll3_m3_ck",
 499         .ops            = &clkops_null,
 500         .parent         = &dpll3_ck,
 501         .init           = &omap2_init_clksel_parent,
 502         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 503         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 504         .clksel         = div16_dpll3_clksel,
 505         .clkdm_name     = "dpll3_clkdm",
 506         .recalc         = &omap2_clksel_recalc,
 507 };
 508
 509 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 510 static struct clk dpll3_m3x2_ck = {
 511         .name           = "dpll3_m3x2_ck",
 512         .ops            = &clkops_omap2_dflt_wait,
 513         .parent         = &dpll3_m3_ck,
 514         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 515         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 516         .flags          = INVERT_ENABLE,
 517         .clkdm_name     = "dpll3_clkdm",
 518         .recalc         = &omap3_clkoutx2_recalc,
 519 };
 520
 521 static struct clk emu_core_alwon_ck = {
 522         .name           = "emu_core_alwon_ck",
 523         .ops            = &clkops_null,
 524         .parent         = &dpll3_m3x2_ck,
 525         .clkdm_name     = "dpll3_clkdm",
 526         .recalc         = &followparent_recalc,
 527 };
 528
 529 /* DPLL4 */
 530 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 531 /* Type: DPLL */
 532 static struct dpll_data dpll4_dd = {
 533         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 534         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 535         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 536         .clk_bypass     = &sys_ck,
 537         .clk_ref        = &sys_ck,
 538         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 539         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 540         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 541         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 542         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 543         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 544         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 545         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 546         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 547         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 548         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 549         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 550         .min_divider    = 1,
 551         .max_divider    = OMAP3_MAX_DPLL_DIV,
 552         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 553 };
 554
 555 static struct clk dpll4_ck = {
 556         .name           = "dpll4_ck",
 557         .ops            = &clkops_noncore_dpll_ops,
 558         .parent         = &sys_ck,
 559         .dpll_data      = &dpll4_dd,
 560         .round_rate     = &omap2_dpll_round_rate,
 561         .set_rate       = &omap3_dpll4_set_rate,
 562         .clkdm_name     = "dpll4_clkdm",
 563         .recalc         = &omap3_dpll_recalc,
 564 };
 565
 566 /*
 567  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 568  * DPLL isn't bypassed --
 569  * XXX does this serve any downstream clocks?
 570  */
 571 static struct clk dpll4_x2_ck = {
 572         .name           = "dpll4_x2_ck",
 573         .ops            = &clkops_null,
 574         .parent         = &dpll4_ck,
 575         .clkdm_name     = "dpll4_clkdm",
 576         .recalc         = &omap3_clkoutx2_recalc,
 577 };
 578
 579 static const struct clksel div16_dpll4_clksel[] = {
 580         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 581         { .parent = NULL }
 582 };
 583
 584 /* This virtual clock is the source for dpll4_m2x2_ck */
 585 static struct clk dpll4_m2_ck = {
 586         .name           = "dpll4_m2_ck",
 587         .ops            = &clkops_null,
 588         .parent         = &dpll4_ck,
 589         .init           = &omap2_init_clksel_parent,
 590         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 591         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 592         .clksel         = div16_dpll4_clksel,
 593         .clkdm_name     = "dpll4_clkdm",
 594         .recalc         = &omap2_clksel_recalc,
 595 };
 596
 597 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 598 static struct clk dpll4_m2x2_ck = {
 599         .name           = "dpll4_m2x2_ck",
 600         .ops            = &clkops_omap2_dflt_wait,
 601         .parent         = &dpll4_m2_ck,
 602         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 603         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 604         .flags          = INVERT_ENABLE,
 605         .clkdm_name     = "dpll4_clkdm",
 606         .recalc         = &omap3_clkoutx2_recalc,
 607 };
 608
 609 /*
 610  * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
 611  * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
 612  * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
 613  * CM_96K_(F)CLK.
 614  */
 615 static struct clk omap_96m_alwon_fck = {
 616         .name           = "omap_96m_alwon_fck",
 617         .ops            = &clkops_null,
 618         .parent         = &dpll4_m2x2_ck,
 619         .recalc         = &followparent_recalc,
 620 };
 621
 622 static struct clk cm_96m_fck = {
 623         .name           = "cm_96m_fck",
 624         .ops            = &clkops_null,
 625         .parent         = &omap_96m_alwon_fck,
 626         .recalc         = &followparent_recalc,
 627 };
 628
 629 static const struct clksel_rate omap_96m_dpll_rates[] = {
 630         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 631         { .div = 0 }
 632 };
 633
 634 static const struct clksel_rate omap_96m_sys_rates[] = {
 635         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 636         { .div = 0 }
 637 };
 638
 639 static const struct clksel omap_96m_fck_clksel[] = {
 640         { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
 641         { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
 642         { .parent = NULL }
 643 };
 644
 645 static struct clk omap_96m_fck = {
 646         .name           = "omap_96m_fck",
 647         .ops            = &clkops_null,
 648         .parent         = &sys_ck,
 649         .init           = &omap2_init_clksel_parent,
 650         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 651         .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
 652         .clksel         = omap_96m_fck_clksel,
 653         .recalc         = &omap2_clksel_recalc,
 654 };
 655
 656 /* This virtual clock is the source for dpll4_m3x2_ck */
 657 static struct clk dpll4_m3_ck = {
 658         .name           = "dpll4_m3_ck",
 659         .ops            = &clkops_null,
 660         .parent         = &dpll4_ck,
 661         .init           = &omap2_init_clksel_parent,
 662         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 663         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 664         .clksel         = div16_dpll4_clksel,
 665         .clkdm_name     = "dpll4_clkdm",
 666         .recalc         = &omap2_clksel_recalc,
 667 };
 668
 669 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 670 static struct clk dpll4_m3x2_ck = {
 671         .name           = "dpll4_m3x2_ck",
 672         .ops            = &clkops_omap2_dflt_wait,
 673         .parent         = &dpll4_m3_ck,
 674         .init           = &omap2_init_clksel_parent,
 675         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 676         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 677         .flags          = INVERT_ENABLE,
 678         .clkdm_name     = "dpll4_clkdm",
 679         .recalc         = &omap3_clkoutx2_recalc,
 680 };
 681
 682 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 683         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 684         { .div = 0 }
 685 };
 686
 687 static const struct clksel_rate omap_54m_alt_rates[] = {
 688         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 689         { .div = 0 }
 690 };
 691
 692 static const struct clksel omap_54m_clksel[] = {
 693         { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
 694         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 695         { .parent = NULL }
 696 };
 697
 698 static struct clk omap_54m_fck = {
 699         .name           = "omap_54m_fck",
 700         .ops            = &clkops_null,
 701         .init           = &omap2_init_clksel_parent,
 702         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 703         .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
 704         .clksel         = omap_54m_clksel,
 705         .recalc         = &omap2_clksel_recalc,
 706 };
 707
 708 static const struct clksel_rate omap_48m_cm96m_rates[] = {
 709         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 710         { .div = 0 }
 711 };
 712
 713 static const struct clksel_rate omap_48m_alt_rates[] = {
 714         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 715         { .div = 0 }
 716 };
 717
 718 static const struct clksel omap_48m_clksel[] = {
 719         { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 720         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 721         { .parent = NULL }
 722 };
 723
 724 static struct clk omap_48m_fck = {
 725         .name           = "omap_48m_fck",
 726         .ops            = &clkops_null,
 727         .init           = &omap2_init_clksel_parent,
 728         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 729         .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
 730         .clksel         = omap_48m_clksel,
 731         .recalc         = &omap2_clksel_recalc,
 732 };
 733
 734 static struct clk omap_12m_fck = {
 735         .name           = "omap_12m_fck",
 736         .ops            = &clkops_null,
 737         .parent         = &omap_48m_fck,
 738         .fixed_div      = 4,
 739         .recalc         = &omap2_fixed_divisor_recalc,
 740 };
 741
 742 /* This virstual clock is the source for dpll4_m4x2_ck */
 743 static struct clk dpll4_m4_ck = {
 744         .name           = "dpll4_m4_ck",
 745         .ops            = &clkops_null,
 746         .parent         = &dpll4_ck,
 747         .init           = &omap2_init_clksel_parent,
 748         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 749         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 750         .clksel         = div16_dpll4_clksel,
 751         .clkdm_name     = "dpll4_clkdm",
 752         .recalc         = &omap2_clksel_recalc,
 753         .set_rate       = &omap2_clksel_set_rate,
 754         .round_rate     = &omap2_clksel_round_rate,
 755 };
 756
 757 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 758 static struct clk dpll4_m4x2_ck = {
 759         .name           = "dpll4_m4x2_ck",
 760         .ops            = &clkops_omap2_dflt_wait,
 761         .parent         = &dpll4_m4_ck,
 762         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 763         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 764         .flags          = INVERT_ENABLE,
 765         .clkdm_name     = "dpll4_clkdm",
 766         .recalc         = &omap3_clkoutx2_recalc,
 767 };
 768
 769 /* This virtual clock is the source for dpll4_m5x2_ck */
 770 static struct clk dpll4_m5_ck = {
 771         .name           = "dpll4_m5_ck",
 772         .ops            = &clkops_null,
 773         .parent         = &dpll4_ck,
 774         .init           = &omap2_init_clksel_parent,
 775         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 776         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 777         .clksel         = div16_dpll4_clksel,
 778         .clkdm_name     = "dpll4_clkdm",
 779         .set_rate       = &omap2_clksel_set_rate,
 780         .round_rate     = &omap2_clksel_round_rate,
 781         .recalc         = &omap2_clksel_recalc,
 782 };
 783
 784 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 785 static struct clk dpll4_m5x2_ck = {
 786         .name           = "dpll4_m5x2_ck",
 787         .ops            = &clkops_omap2_dflt_wait,
 788         .parent         = &dpll4_m5_ck,
 789         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 790         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 791         .flags          = INVERT_ENABLE,
 792         .clkdm_name     = "dpll4_clkdm",
 793         .recalc         = &omap3_clkoutx2_recalc,
 794 };
 795
 796 /* This virtual clock is the source for dpll4_m6x2_ck */
 797 static struct clk dpll4_m6_ck = {
 798         .name           = "dpll4_m6_ck",
 799         .ops            = &clkops_null,
 800         .parent         = &dpll4_ck,
 801         .init           = &omap2_init_clksel_parent,
 802         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 803         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 804         .clksel         = div16_dpll4_clksel,
 805         .clkdm_name     = "dpll4_clkdm",
 806         .recalc         = &omap2_clksel_recalc,
 807 };
 808
 809 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 810 static struct clk dpll4_m6x2_ck = {
 811         .name           = "dpll4_m6x2_ck",
 812         .ops            = &clkops_omap2_dflt_wait,
 813         .parent         = &dpll4_m6_ck,
 814         .init           = &omap2_init_clksel_parent,
 815         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 816         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 817         .flags          = INVERT_ENABLE,
 818         .clkdm_name     = "dpll4_clkdm",
 819         .recalc         = &omap3_clkoutx2_recalc,
 820 };
 821
 822 static struct clk emu_per_alwon_ck = {
 823         .name           = "emu_per_alwon_ck",
 824         .ops            = &clkops_null,
 825         .parent         = &dpll4_m6x2_ck,
 826         .clkdm_name     = "dpll4_clkdm",
 827         .recalc         = &followparent_recalc,
 828 };
 829
 830 /* DPLL5 */
 831 /* Supplies 120MHz clock, USIM source clock */
 832 /* Type: DPLL */
 833 /* 3430ES2 only */
 834 static struct dpll_data dpll5_dd = {
 835         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 836         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 837         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 838         .clk_bypass     = &sys_ck,
 839         .clk_ref        = &sys_ck,
 840         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 841         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 842         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 843         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 844         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 845         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 846         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 847         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 848         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 849         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 850         .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 851         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 852         .min_divider    = 1,
 853         .max_divider    = OMAP3_MAX_DPLL_DIV,
 854         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 855 };
 856
 857 static struct clk dpll5_ck = {
 858         .name           = "dpll5_ck",
 859         .ops            = &clkops_noncore_dpll_ops,
 860         .parent         = &sys_ck,
 861         .dpll_data      = &dpll5_dd,
 862         .round_rate     = &omap2_dpll_round_rate,
 863         .set_rate       = &omap3_noncore_dpll_set_rate,
 864         .clkdm_name     = "dpll5_clkdm",
 865         .recalc         = &omap3_dpll_recalc,
 866 };
 867
 868 static const struct clksel div16_dpll5_clksel[] = {
 869         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 870         { .parent = NULL }
 871 };
 872
 873 static struct clk dpll5_m2_ck = {
 874         .name           = "dpll5_m2_ck",
 875         .ops            = &clkops_null,
 876         .parent         = &dpll5_ck,
 877         .init           = &omap2_init_clksel_parent,
 878         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 879         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 880         .clksel         = div16_dpll5_clksel,
 881         .clkdm_name     = "dpll5_clkdm",
 882         .recalc         = &omap2_clksel_recalc,
 883 };
 884
 885 /* CM EXTERNAL CLOCK OUTPUTS */
 886
 887 static const struct clksel_rate clkout2_src_core_rates[] = {
 888         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 889         { .div = 0 }
 890 };
 891
 892 static const struct clksel_rate clkout2_src_sys_rates[] = {
 893         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 894         { .div = 0 }
 895 };
 896
 897 static const struct clksel_rate clkout2_src_96m_rates[] = {
 898         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 899         { .div = 0 }
 900 };
 901
 902 static const struct clksel_rate clkout2_src_54m_rates[] = {
 903         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 904         { .div = 0 }
 905 };
 906
 907 static const struct clksel clkout2_src_clksel[] = {
 908         { .parent = &core_ck,           .rates = clkout2_src_core_rates },
 909         { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
 910         { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
 911         { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
 912         { .parent = NULL }
 913 };
 914
 915 static struct clk clkout2_src_ck = {
 916         .name           = "clkout2_src_ck",
 917         .ops            = &clkops_omap2_dflt,
 918         .init           = &omap2_init_clksel_parent,
 919         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
 920         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
 921         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 922         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
 923         .clksel         = clkout2_src_clksel,
 924         .clkdm_name     = "core_clkdm",
 925         .recalc         = &omap2_clksel_recalc,
 926 };
 927
 928 static const struct clksel_rate sys_clkout2_rates[] = {
 929         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 930         { .div = 2, .val = 1, .flags = RATE_IN_343X },
 931         { .div = 4, .val = 2, .flags = RATE_IN_343X },
 932         { .div = 8, .val = 3, .flags = RATE_IN_343X },
 933         { .div = 16, .val = 4, .flags = RATE_IN_343X },
 934         { .div = 0 },
 935 };
 936
 937 static const struct clksel sys_clkout2_clksel[] = {
 938         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
 939         { .parent = NULL },
 940 };
 941
 942 static struct clk sys_clkout2 = {
 943         .name           = "sys_clkout2",
 944         .ops            = &clkops_null,
 945         .init           = &omap2_init_clksel_parent,
 946         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 947         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
 948         .clksel         = sys_clkout2_clksel,
 949         .recalc         = &omap2_clksel_recalc,
 950 };
 951
 952 /* CM OUTPUT CLOCKS */
 953
 954 static struct clk corex2_fck = {
 955         .name           = "corex2_fck",
 956         .ops            = &clkops_null,
 957         .parent         = &dpll3_m2x2_ck,
 958         .recalc         = &followparent_recalc,
 959 };
 960
 961 /* DPLL power domain clock controls */
 962
 963 static const struct clksel_rate div4_rates[] = {
 964         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 965         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 966         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 967         { .div = 0 }
 968 };
 969
 970 static const struct clksel div4_core_clksel[] = {
 971         { .parent = &core_ck, .rates = div4_rates },
 972         { .parent = NULL }
 973 };
 974
 975 /*
 976  * REVISIT: Are these in DPLL power domain or CM power domain? docs
 977  * may be inconsistent here?
 978  */
 979 static struct clk dpll1_fck = {
 980         .name           = "dpll1_fck",
 981         .ops            = &clkops_null,
 982         .parent         = &core_ck,
 983         .init           = &omap2_init_clksel_parent,
 984         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 985         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
 986         .clksel         = div4_core_clksel,
 987         .recalc         = &omap2_clksel_recalc,
 988 };
 989
 990 static struct clk mpu_ck = {
 991         .name           = "mpu_ck",
 992         .ops            = &clkops_null,
 993         .parent         = &dpll1_x2m2_ck,
 994         .clkdm_name     = "mpu_clkdm",
 995         .recalc         = &followparent_recalc,
 996 };
 997
 998 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
 999 static const struct clksel_rate arm_fck_rates[] = {
1000         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1001         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1002         { .div = 0 },
1003 };
1004
1005 static const struct clksel arm_fck_clksel[] = {
1006         { .parent = &mpu_ck, .rates = arm_fck_rates },
1007         { .parent = NULL }
1008 };
1009
1010 static struct clk arm_fck = {
1011         .name           = "arm_fck",
1012         .ops            = &clkops_null,
1013         .parent         = &mpu_ck,
1014         .init           = &omap2_init_clksel_parent,
1015         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1016         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1017         .clksel         = arm_fck_clksel,
1018         .clkdm_name     = "mpu_clkdm",
1019         .recalc         = &omap2_clksel_recalc,
1020 };
1021
1022 /* XXX What about neon_clkdm ? */
1023
1024 /*
1025  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1026  * although it is referenced - so this is a guess
1027  */
1028 static struct clk emu_mpu_alwon_ck = {
1029         .name           = "emu_mpu_alwon_ck",
1030         .ops            = &clkops_null,
1031         .parent         = &mpu_ck,
1032         .recalc         = &followparent_recalc,
1033 };
1034
1035 static struct clk dpll2_fck = {
1036         .name           = "dpll2_fck",
1037         .ops            = &clkops_null,
1038         .parent         = &core_ck,
1039         .init           = &omap2_init_clksel_parent,
1040         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1041         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1042         .clksel         = div4_core_clksel,
1043         .recalc         = &omap2_clksel_recalc,
1044 };
1045
1046 static struct clk iva2_ck = {
1047         .name           = "iva2_ck",
1048         .ops            = &clkops_omap2_dflt_wait,
1049         .parent         = &dpll2_m2_ck,
1050         .init           = &omap2_init_clksel_parent,
1051         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1052         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1053         .clkdm_name     = "iva2_clkdm",
1054         .recalc         = &followparent_recalc,
1055 };
1056
1057 /* Common interface clocks */
1058
1059 static const struct clksel div2_core_clksel[] = {
1060         { .parent = &core_ck, .rates = div2_rates },
1061         { .parent = NULL }
1062 };
1063
1064 static struct clk l3_ick = {
1065         .name           = "l3_ick",
1066         .ops            = &clkops_null,
1067         .parent         = &core_ck,
1068         .init           = &omap2_init_clksel_parent,
1069         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1070         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1071         .clksel         = div2_core_clksel,
1072         .clkdm_name     = "core_l3_clkdm",
1073         .recalc         = &omap2_clksel_recalc,
1074 };
1075
1076 static const struct clksel div2_l3_clksel[] = {
1077         { .parent = &l3_ick, .rates = div2_rates },
1078         { .parent = NULL }
1079 };
1080
1081 static struct clk l4_ick = {
1082         .name           = "l4_ick",
1083         .ops            = &clkops_null,
1084         .parent         = &l3_ick,
1085         .init           = &omap2_init_clksel_parent,
1086         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1087         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1088         .clksel         = div2_l3_clksel,
1089         .clkdm_name     = "core_l4_clkdm",
1090         .recalc         = &omap2_clksel_recalc,
1091
1092 };
1093
1094 static const struct clksel div2_l4_clksel[] = {
1095         { .parent = &l4_ick, .rates = div2_rates },
1096         { .parent = NULL }
1097 };
1098
1099 static struct clk rm_ick = {
1100         .name           = "rm_ick",
1101         .ops            = &clkops_null,
1102         .parent         = &l4_ick,
1103         .init           = &omap2_init_clksel_parent,
1104         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1105         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1106         .clksel         = div2_l4_clksel,
1107         .recalc         = &omap2_clksel_recalc,
1108 };
1109
1110 /* GFX power domain */
1111
1112 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1113
1114 static const struct clksel gfx_l3_clksel[] = {
1115         { .parent = &l3_ick, .rates = gfx_l3_rates },
1116         { .parent = NULL }
1117 };
1118
1119 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1120 static struct clk gfx_l3_ck = {
1121         .name           = "gfx_l3_ck",
1122         .ops            = &clkops_omap2_dflt_wait,
1123         .parent         = &l3_ick,
1124         .init           = &omap2_init_clksel_parent,
1125         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1126         .enable_bit     = OMAP_EN_GFX_SHIFT,
1127         .recalc         = &followparent_recalc,
1128 };
1129
1130 static struct clk gfx_l3_fck = {
1131         .name           = "gfx_l3_fck",
1132         .ops            = &clkops_null,
1133         .parent         = &gfx_l3_ck,
1134         .init           = &omap2_init_clksel_parent,
1135         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1136         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1137         .clksel         = gfx_l3_clksel,
1138         .clkdm_name     = "gfx_3430es1_clkdm",
1139         .recalc         = &omap2_clksel_recalc,
1140 };
1141
1142 static struct clk gfx_l3_ick = {
1143         .name           = "gfx_l3_ick",
1144         .ops            = &clkops_null,
1145         .parent         = &gfx_l3_ck,
1146         .clkdm_name     = "gfx_3430es1_clkdm",
1147         .recalc         = &followparent_recalc,
1148 };
1149
1150 static struct clk gfx_cg1_ck = {
1151         .name           = "gfx_cg1_ck",
1152         .ops            = &clkops_omap2_dflt_wait,
1153         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1154         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1155         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1156         .clkdm_name     = "gfx_3430es1_clkdm",
1157         .recalc         = &followparent_recalc,
1158 };
1159
1160 static struct clk gfx_cg2_ck = {
1161         .name           = "gfx_cg2_ck",
1162         .ops            = &clkops_omap2_dflt_wait,
1163         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1164         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1165         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1166         .clkdm_name     = "gfx_3430es1_clkdm",
1167         .recalc         = &followparent_recalc,
1168 };
1169
1170 /* SGX power domain - 3430ES2 only */
1171
1172 static const struct clksel_rate sgx_core_rates[] = {
1173         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1174         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1175         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1176         { .div = 0 },
1177 };
1178
1179 static const struct clksel_rate sgx_96m_rates[] = {
1180         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1181         { .div = 0 },
1182 };
1183
1184 static const struct clksel sgx_clksel[] = {
1185         { .parent = &core_ck,    .rates = sgx_core_rates },
1186         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1187         { .parent = NULL },
1188 };
1189
1190 static struct clk sgx_fck = {
1191         .name           = "sgx_fck",
1192         .ops            = &clkops_omap2_dflt_wait,
1193         .init           = &omap2_init_clksel_parent,
1194         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1195         .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1196         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1197         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1198         .clksel         = sgx_clksel,
1199         .clkdm_name     = "sgx_clkdm",
1200         .recalc         = &omap2_clksel_recalc,
1201 };
1202
1203 static struct clk sgx_ick = {
1204         .name           = "sgx_ick",
1205         .ops            = &clkops_omap2_dflt_wait,
1206         .parent         = &l3_ick,
1207         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1208         .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1209         .clkdm_name     = "sgx_clkdm",
1210         .recalc         = &followparent_recalc,
1211 };
1212
1213 /* CORE power domain */
1214
1215 static struct clk d2d_26m_fck = {
1216         .name           = "d2d_26m_fck",
1217         .ops            = &clkops_omap2_dflt_wait,
1218         .parent         = &sys_ck,
1219         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1220         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1221         .clkdm_name     = "d2d_clkdm",
1222         .recalc         = &followparent_recalc,
1223 };
1224
1225 static struct clk modem_fck = {
1226         .name           = "modem_fck",
1227         .ops            = &clkops_omap2_dflt_wait,
1228         .parent         = &sys_ck,
1229         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1230         .enable_bit     = OMAP3430_EN_MODEM_SHIFT,
1231         .clkdm_name     = "d2d_clkdm",
1232         .recalc         = &followparent_recalc,
1233 };
1234
1235 static struct clk sad2d_ick = {
1236         .name           = "sad2d_ick",
1237         .ops            = &clkops_omap2_dflt_wait,
1238         .parent         = &l3_ick,
1239         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1240         .enable_bit     = OMAP3430_EN_SAD2D_SHIFT,
1241         .clkdm_name     = "d2d_clkdm",
1242         .recalc         = &followparent_recalc,
1243 };
1244
1245 static struct clk mad2d_ick = {
1246         .name           = "mad2d_ick",
1247         .ops            = &clkops_omap2_dflt_wait,
1248         .parent         = &l3_ick,
1249         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1250         .enable_bit     = OMAP3430_EN_MAD2D_SHIFT,
1251         .clkdm_name     = "d2d_clkdm",
1252         .recalc         = &followparent_recalc,
1253 };
1254
1255 static const struct clksel omap343x_gpt_clksel[] = {
1256         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1257         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1258         { .parent = NULL}
1259 };
1260
1261 static struct clk gpt10_fck = {
1262         .name           = "gpt10_fck",
1263         .ops            = &clkops_omap2_dflt_wait,
1264         .parent         = &sys_ck,
1265         .init           = &omap2_init_clksel_parent,
1266         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1267         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1268         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1269         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1270         .clksel         = omap343x_gpt_clksel,
1271         .clkdm_name     = "core_l4_clkdm",
1272         .recalc         = &omap2_clksel_recalc,
1273 };
1274
1275 static struct clk gpt11_fck = {
1276         .name           = "gpt11_fck",
1277         .ops            = &clkops_omap2_dflt_wait,
1278         .parent         = &sys_ck,
1279         .init           = &omap2_init_clksel_parent,
1280         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1281         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1282         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1283         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1284         .clksel         = omap343x_gpt_clksel,
1285         .clkdm_name     = "core_l4_clkdm",
1286         .recalc         = &omap2_clksel_recalc,
1287 };
1288
1289 static struct clk cpefuse_fck = {
1290         .name           = "cpefuse_fck",
1291         .ops            = &clkops_omap2_dflt,
1292         .parent         = &sys_ck,
1293         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1294         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1295         .recalc         = &followparent_recalc,
1296 };
1297
1298 static struct clk ts_fck = {
1299         .name           = "ts_fck",
1300         .ops            = &clkops_omap2_dflt,
1301         .parent         = &omap_32k_fck,
1302         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1303         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1304         .recalc         = &followparent_recalc,
1305 };
1306
1307 static struct clk usbtll_fck = {
1308         .name           = "usbtll_fck",
1309         .ops            = &clkops_omap2_dflt,
1310         .parent         = &dpll5_m2_ck,
1311         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1312         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1313         .recalc         = &followparent_recalc,
1314 };
1315
1316 /* CORE 96M FCLK-derived clocks */
1317
1318 static struct clk core_96m_fck = {
1319         .name           = "core_96m_fck",
1320         .ops            = &clkops_null,
1321         .parent         = &omap_96m_fck,
1322         .clkdm_name     = "core_l4_clkdm",
1323         .recalc         = &followparent_recalc,
1324 };
1325
1326 static struct clk mmchs3_fck = {
1327         .name           = "mmchs_fck",
1328         .ops            = &clkops_omap2_dflt_wait,
1329         .id             = 2,
1330         .parent         = &core_96m_fck,
1331         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1332         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1333         .clkdm_name     = "core_l4_clkdm",
1334         .recalc         = &followparent_recalc,
1335 };
1336
1337 static struct clk mmchs2_fck = {
1338         .name           = "mmchs_fck",
1339         .ops            = &clkops_omap2_dflt_wait,
1340         .id             = 1,
1341         .parent         = &core_96m_fck,
1342         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1343         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1344         .clkdm_name     = "core_l4_clkdm",
1345         .recalc         = &followparent_recalc,
1346 };
1347
1348 static struct clk mspro_fck = {
1349         .name           = "mspro_fck",
1350         .ops            = &clkops_omap2_dflt_wait,
1351         .parent         = &core_96m_fck,
1352         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1353         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1354         .clkdm_name     = "core_l4_clkdm",
1355         .recalc         = &followparent_recalc,
1356 };
1357
1358 static struct clk mmchs1_fck = {
1359         .name           = "mmchs_fck",
1360         .ops            = &clkops_omap2_dflt_wait,
1361         .parent         = &core_96m_fck,
1362         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1363         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1364         .clkdm_name     = "core_l4_clkdm",
1365         .recalc         = &followparent_recalc,
1366 };
1367
1368 static struct clk i2c3_fck = {
1369         .name           = "i2c_fck",
1370         .ops            = &clkops_omap2_dflt_wait,
1371         .id             = 3,
1372         .parent         = &core_96m_fck,
1373         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1374         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1375         .clkdm_name     = "core_l4_clkdm",
1376         .recalc         = &followparent_recalc,
1377 };
1378
1379 static struct clk i2c2_fck = {
1380         .name           = "i2c_fck",
1381         .ops            = &clkops_omap2_dflt_wait,
1382         .id             = 2,
1383         .parent         = &core_96m_fck,
1384         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1385         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1386         .clkdm_name     = "core_l4_clkdm",
1387         .recalc         = &followparent_recalc,
1388 };
1389
1390 static struct clk i2c1_fck = {
1391         .name           = "i2c_fck",
1392         .ops            = &clkops_omap2_dflt_wait,
1393         .id             = 1,
1394         .parent         = &core_96m_fck,
1395         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1396         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1397         .clkdm_name     = "core_l4_clkdm",
1398         .recalc         = &followparent_recalc,
1399 };
1400
1401 /*
1402  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1403  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1404  */
1405 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1406         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1407         { .div = 0 }
1408 };
1409
1410 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1411         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1412         { .div = 0 }
1413 };
1414
1415 static const struct clksel mcbsp_15_clksel[] = {
1416         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1417         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1418         { .parent = NULL }
1419 };
1420
1421 static struct clk mcbsp5_fck = {
1422         .name           = "mcbsp_fck",
1423         .ops            = &clkops_omap2_dflt_wait,
1424         .id             = 5,
1425         .init           = &omap2_init_clksel_parent,
1426         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1427         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1428         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1429         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1430         .clksel         = mcbsp_15_clksel,
1431         .clkdm_name     = "core_l4_clkdm",
1432         .recalc         = &omap2_clksel_recalc,
1433 };
1434
1435 static struct clk mcbsp1_fck = {
1436         .name           = "mcbsp_fck",
1437         .ops            = &clkops_omap2_dflt_wait,
1438         .id             = 1,
1439         .init           = &omap2_init_clksel_parent,
1440         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1441         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1442         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1443         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1444         .clksel         = mcbsp_15_clksel,
1445         .clkdm_name     = "core_l4_clkdm",
1446         .recalc         = &omap2_clksel_recalc,
1447 };
1448
1449 /* CORE_48M_FCK-derived clocks */
1450
1451 static struct clk core_48m_fck = {
1452         .name           = "core_48m_fck",
1453         .ops            = &clkops_null,
1454         .parent         = &omap_48m_fck,
1455         .clkdm_name     = "core_l4_clkdm",
1456         .recalc         = &followparent_recalc,
1457 };
1458
1459 static struct clk mcspi4_fck = {
1460         .name           = "mcspi_fck",
1461         .ops            = &clkops_omap2_dflt_wait,
1462         .id             = 4,
1463         .parent         = &core_48m_fck,
1464         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1465         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1466         .recalc         = &followparent_recalc,
1467 };
1468
1469 static struct clk mcspi3_fck = {
1470         .name           = "mcspi_fck",
1471         .ops            = &clkops_omap2_dflt_wait,
1472         .id             = 3,
1473         .parent         = &core_48m_fck,
1474         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1475         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1476         .recalc         = &followparent_recalc,
1477 };
1478
1479 static struct clk mcspi2_fck = {
1480         .name           = "mcspi_fck",
1481         .ops            = &clkops_omap2_dflt_wait,
1482         .id             = 2,
1483         .parent         = &core_48m_fck,
1484         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1485         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1486         .recalc         = &followparent_recalc,
1487 };
1488
1489 static struct clk mcspi1_fck = {
1490         .name           = "mcspi_fck",
1491         .ops            = &clkops_omap2_dflt_wait,
1492         .id             = 1,
1493         .parent         = &core_48m_fck,
1494         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1495         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1496         .recalc         = &followparent_recalc,
1497 };
1498
1499 static struct clk uart2_fck = {
1500         .name           = "uart2_fck",
1501         .ops            = &clkops_omap2_dflt_wait,
1502         .parent         = &core_48m_fck,
1503         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1504         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1505         .clkdm_name     = "core_l4_clkdm",
1506         .recalc         = &followparent_recalc,
1507 };
1508
1509 static struct clk uart1_fck = {
1510         .name           = "uart1_fck",
1511         .ops            = &clkops_omap2_dflt_wait,
1512         .parent         = &core_48m_fck,
1513         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1514         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1515         .clkdm_name     = "core_l4_clkdm",
1516         .recalc         = &followparent_recalc,
1517 };
1518
1519 static struct clk fshostusb_fck = {
1520         .name           = "fshostusb_fck",
1521         .ops            = &clkops_omap2_dflt_wait,
1522         .parent         = &core_48m_fck,
1523         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1524         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1525         .recalc         = &followparent_recalc,
1526 };
1527
1528 /* CORE_12M_FCK based clocks */
1529
1530 static struct clk core_12m_fck = {
1531         .name           = "core_12m_fck",
1532         .ops            = &clkops_null,
1533         .parent         = &omap_12m_fck,
1534         .clkdm_name     = "core_l4_clkdm",
1535         .recalc         = &followparent_recalc,
1536 };
1537
1538 static struct clk hdq_fck = {
1539         .name           = "hdq_fck",
1540         .ops            = &clkops_omap2_dflt_wait,
1541         .parent         = &core_12m_fck,
1542         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1543         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1544         .recalc         = &followparent_recalc,
1545 };
1546
1547 /* DPLL3-derived clock */
1548
1549 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1550         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1551         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1552         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1553         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1554         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1555         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1556         { .div = 0 }
1557 };
1558
1559 static const struct clksel ssi_ssr_clksel[] = {
1560         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1561         { .parent = NULL }
1562 };
1563
1564 static struct clk ssi_ssr_fck_3430es1 = {
1565         .name           = "ssi_ssr_fck",
1566         .ops            = &clkops_omap2_dflt,
1567         .init           = &omap2_init_clksel_parent,
1568         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1569         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1570         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1571         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1572         .clksel         = ssi_ssr_clksel,
1573         .clkdm_name     = "core_l4_clkdm",
1574         .recalc         = &omap2_clksel_recalc,
1575 };
1576
1577 static struct clk ssi_ssr_fck_3430es2 = {
1578         .name           = "ssi_ssr_fck",
1579         .ops            = &clkops_omap3430es2_ssi_wait,
1580         .init           = &omap2_init_clksel_parent,
1581         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1582         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1583         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1584         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1585         .clksel         = ssi_ssr_clksel,
1586         .clkdm_name     = "core_l4_clkdm",
1587         .recalc         = &omap2_clksel_recalc,
1588 };
1589
1590 static struct clk ssi_sst_fck_3430es1 = {
1591         .name           = "ssi_sst_fck",
1592         .ops            = &clkops_null,
1593         .parent         = &ssi_ssr_fck_3430es1,
1594         .fixed_div      = 2,
1595         .recalc         = &omap2_fixed_divisor_recalc,
1596 };
1597
1598 static struct clk ssi_sst_fck_3430es2 = {
1599         .name           = "ssi_sst_fck",
1600         .ops            = &clkops_null,
1601         .parent         = &ssi_ssr_fck_3430es2,
1602         .fixed_div      = 2,
1603         .recalc         = &omap2_fixed_divisor_recalc,
1604 };
1605
1606
1607
1608 /* CORE_L3_ICK based clocks */
1609
1610 /*
1611  * XXX must add clk_enable/clk_disable for these if standard code won't
1612  * handle it
1613  */
1614 static struct clk core_l3_ick = {
1615         .name           = "core_l3_ick",
1616         .ops            = &clkops_null,
1617         .parent         = &l3_ick,
1618         .clkdm_name     = "core_l3_clkdm",
1619         .recalc         = &followparent_recalc,
1620 };
1621
1622 static struct clk hsotgusb_ick_3430es1 = {
1623         .name           = "hsotgusb_ick",
1624         .ops            = &clkops_omap2_dflt,
1625         .parent         = &core_l3_ick,
1626         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1627         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1628         .clkdm_name     = "core_l3_clkdm",
1629         .recalc         = &followparent_recalc,
1630 };
1631
1632 static struct clk hsotgusb_ick_3430es2 = {
1633         .name           = "hsotgusb_ick",
1634         .ops            = &clkops_omap3430es2_hsotgusb_wait,
1635         .parent         = &core_l3_ick,
1636         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1637         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1638         .clkdm_name     = "core_l3_clkdm",
1639         .recalc         = &followparent_recalc,
1640 };
1641
1642 static struct clk sdrc_ick = {
1643         .name           = "sdrc_ick",
1644         .ops            = &clkops_omap2_dflt_wait,
1645         .parent         = &core_l3_ick,
1646         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1647         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1648         .flags          = ENABLE_ON_INIT,
1649         .clkdm_name     = "core_l3_clkdm",
1650         .recalc         = &followparent_recalc,
1651 };
1652
1653 static struct clk gpmc_fck = {
1654         .name           = "gpmc_fck",
1655         .ops            = &clkops_null,
1656         .parent         = &core_l3_ick,
1657         .flags          = ENABLE_ON_INIT, /* huh? */
1658         .clkdm_name     = "core_l3_clkdm",
1659         .recalc         = &followparent_recalc,
1660 };
1661
1662 /* SECURITY_L3_ICK based clocks */
1663
1664 static struct clk security_l3_ick = {
1665         .name           = "security_l3_ick",
1666         .ops            = &clkops_null,
1667         .parent         = &l3_ick,
1668         .recalc         = &followparent_recalc,
1669 };
1670
1671 static struct clk pka_ick = {
1672         .name           = "pka_ick",
1673         .ops            = &clkops_omap2_dflt_wait,
1674         .parent         = &security_l3_ick,
1675         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1676         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1677         .recalc         = &followparent_recalc,
1678 };
1679
1680 /* CORE_L4_ICK based clocks */
1681
1682 static struct clk core_l4_ick = {
1683         .name           = "core_l4_ick",
1684         .ops            = &clkops_null,
1685         .parent         = &l4_ick,
1686         .clkdm_name     = "core_l4_clkdm",
1687         .recalc         = &followparent_recalc,
1688 };
1689
1690 static struct clk usbtll_ick = {
1691         .name           = "usbtll_ick",
1692         .ops            = &clkops_omap2_dflt_wait,
1693         .parent         = &core_l4_ick,
1694         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1695         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1696         .clkdm_name     = "core_l4_clkdm",
1697         .recalc         = &followparent_recalc,
1698 };
1699
1700 static struct clk mmchs3_ick = {
1701         .name           = "mmchs_ick",
1702         .ops            = &clkops_omap2_dflt_wait,
1703         .id             = 2,
1704         .parent         = &core_l4_ick,
1705         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1706         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1707         .clkdm_name     = "core_l4_clkdm",
1708         .recalc         = &followparent_recalc,
1709 };
1710
1711 /* Intersystem Communication Registers - chassis mode only */
1712 static struct clk icr_ick = {
1713         .name           = "icr_ick",
1714         .ops            = &clkops_omap2_dflt_wait,
1715         .parent         = &core_l4_ick,
1716         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1717         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1718         .clkdm_name     = "core_l4_clkdm",
1719         .recalc         = &followparent_recalc,
1720 };
1721
1722 static struct clk aes2_ick = {
1723         .name           = "aes2_ick",
1724         .ops            = &clkops_omap2_dflt_wait,
1725         .parent         = &core_l4_ick,
1726         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1727         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1728         .clkdm_name     = "core_l4_clkdm",
1729         .recalc         = &followparent_recalc,
1730 };
1731
1732 static struct clk sha12_ick = {
1733         .name           = "sha12_ick",
1734         .ops            = &clkops_omap2_dflt_wait,
1735         .parent         = &core_l4_ick,
1736         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1737         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1738         .clkdm_name     = "core_l4_clkdm",
1739         .recalc         = &followparent_recalc,
1740 };
1741
1742 static struct clk des2_ick = {
1743         .name           = "des2_ick",
1744         .ops            = &clkops_omap2_dflt_wait,
1745         .parent         = &core_l4_ick,
1746         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1747         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1748         .clkdm_name     = "core_l4_clkdm",
1749         .recalc         = &followparent_recalc,
1750 };
1751
1752 static struct clk mmchs2_ick = {
1753         .name           = "mmchs_ick",
1754         .ops            = &clkops_omap2_dflt_wait,
1755         .id             = 1,
1756         .parent         = &core_l4_ick,
1757         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1758         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1759         .clkdm_name     = "core_l4_clkdm",
1760         .recalc         = &followparent_recalc,
1761 };
1762
1763 static struct clk mmchs1_ick = {
1764         .name           = "mmchs_ick",
1765         .ops            = &clkops_omap2_dflt_wait,
1766         .parent         = &core_l4_ick,
1767         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1768         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1769         .clkdm_name     = "core_l4_clkdm",
1770         .recalc         = &followparent_recalc,
1771 };
1772
1773 static struct clk mspro_ick = {
1774         .name           = "mspro_ick",
1775         .ops            = &clkops_omap2_dflt_wait,
1776         .parent         = &core_l4_ick,
1777         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1778         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1779         .clkdm_name     = "core_l4_clkdm",
1780         .recalc         = &followparent_recalc,
1781 };
1782
1783 static struct clk hdq_ick = {
1784         .name           = "hdq_ick",
1785         .ops            = &clkops_omap2_dflt_wait,
1786         .parent         = &core_l4_ick,
1787         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1788         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1789         .clkdm_name     = "core_l4_clkdm",
1790         .recalc         = &followparent_recalc,
1791 };
1792
1793 static struct clk mcspi4_ick = {
1794         .name           = "mcspi_ick",
1795         .ops            = &clkops_omap2_dflt_wait,
1796         .id             = 4,
1797         .parent         = &core_l4_ick,
1798         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1799         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1800         .clkdm_name     = "core_l4_clkdm",
1801         .recalc         = &followparent_recalc,
1802 };
1803
1804 static struct clk mcspi3_ick = {
1805         .name           = "mcspi_ick",
1806         .ops            = &clkops_omap2_dflt_wait,
1807         .id             = 3,
1808         .parent         = &core_l4_ick,
1809         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1810         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1811         .clkdm_name     = "core_l4_clkdm",
1812         .recalc         = &followparent_recalc,
1813 };
1814
1815 static struct clk mcspi2_ick = {
1816         .name           = "mcspi_ick",
1817         .ops            = &clkops_omap2_dflt_wait,
1818         .id             = 2,
1819         .parent         = &core_l4_ick,
1820         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1821         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1822         .clkdm_name     = "core_l4_clkdm",
1823         .recalc         = &followparent_recalc,
1824 };
1825
1826 static struct clk mcspi1_ick = {
1827         .name           = "mcspi_ick",
1828         .ops            = &clkops_omap2_dflt_wait,
1829         .id             = 1,
1830         .parent         = &core_l4_ick,
1831         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1832         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1833         .clkdm_name     = "core_l4_clkdm",
1834         .recalc         = &followparent_recalc,
1835 };
1836
1837 static struct clk i2c3_ick = {
1838         .name           = "i2c_ick",
1839         .ops            = &clkops_omap2_dflt_wait,
1840         .id             = 3,
1841         .parent         = &core_l4_ick,
1842         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1843         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1844         .clkdm_name     = "core_l4_clkdm",
1845         .recalc         = &followparent_recalc,
1846 };
1847
1848 static struct clk i2c2_ick = {
1849         .name           = "i2c_ick",
1850         .ops            = &clkops_omap2_dflt_wait,
1851         .id             = 2,
1852         .parent         = &core_l4_ick,
1853         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1854         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1855         .clkdm_name     = "core_l4_clkdm",
1856         .recalc         = &followparent_recalc,
1857 };
1858
1859 static struct clk i2c1_ick = {
1860         .name           = "i2c_ick",
1861         .ops            = &clkops_omap2_dflt_wait,
1862         .id             = 1,
1863         .parent         = &core_l4_ick,
1864         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1865         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1866         .clkdm_name     = "core_l4_clkdm",
1867         .recalc         = &followparent_recalc,
1868 };
1869
1870 static struct clk uart2_ick = {
1871         .name           = "uart2_ick",
1872         .ops            = &clkops_omap2_dflt_wait,
1873         .parent         = &core_l4_ick,
1874         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1875         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1876         .clkdm_name     = "core_l4_clkdm",
1877         .recalc         = &followparent_recalc,
1878 };
1879
1880 static struct clk uart1_ick = {
1881         .name           = "uart1_ick",
1882         .ops            = &clkops_omap2_dflt_wait,
1883         .parent         = &core_l4_ick,
1884         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1885         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1886         .clkdm_name     = "core_l4_clkdm",
1887         .recalc         = &followparent_recalc,
1888 };
1889
1890 static struct clk gpt11_ick = {
1891         .name           = "gpt11_ick",
1892         .ops            = &clkops_omap2_dflt_wait,
1893         .parent         = &core_l4_ick,
1894         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1895         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1896         .clkdm_name     = "core_l4_clkdm",
1897         .recalc         = &followparent_recalc,
1898 };
1899
1900 static struct clk gpt10_ick = {
1901         .name           = "gpt10_ick",
1902         .ops            = &clkops_omap2_dflt_wait,
1903         .parent         = &core_l4_ick,
1904         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1905         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1906         .clkdm_name     = "core_l4_clkdm",
1907         .recalc         = &followparent_recalc,
1908 };
1909
1910 static struct clk mcbsp5_ick = {
1911         .name           = "mcbsp_ick",
1912         .ops            = &clkops_omap2_dflt_wait,
1913         .id             = 5,
1914         .parent         = &core_l4_ick,
1915         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1916         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1917         .clkdm_name     = "core_l4_clkdm",
1918         .recalc         = &followparent_recalc,
1919 };
1920
1921 static struct clk mcbsp1_ick = {
1922         .name           = "mcbsp_ick",
1923         .ops            = &clkops_omap2_dflt_wait,
1924         .id             = 1,
1925         .parent         = &core_l4_ick,
1926         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1927         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1928         .clkdm_name     = "core_l4_clkdm",
1929         .recalc         = &followparent_recalc,
1930 };
1931
1932 static struct clk fac_ick = {
1933         .name           = "fac_ick",
1934         .ops            = &clkops_omap2_dflt_wait,
1935         .parent         = &core_l4_ick,
1936         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1937         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
1938         .clkdm_name     = "core_l4_clkdm",
1939         .recalc         = &followparent_recalc,
1940 };
1941
1942 static struct clk mailboxes_ick = {
1943         .name           = "mailboxes_ick",
1944         .ops            = &clkops_omap2_dflt_wait,
1945         .parent         = &core_l4_ick,
1946         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1947         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
1948         .clkdm_name     = "core_l4_clkdm",
1949         .recalc         = &followparent_recalc,
1950 };
1951
1952 static struct clk omapctrl_ick = {
1953         .name           = "omapctrl_ick",
1954         .ops            = &clkops_omap2_dflt_wait,
1955         .parent         = &core_l4_ick,
1956         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1957         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
1958         .flags          = ENABLE_ON_INIT,
1959         .recalc         = &followparent_recalc,
1960 };
1961
1962 /* SSI_L4_ICK based clocks */
1963
1964 static struct clk ssi_l4_ick = {
1965         .name           = "ssi_l4_ick",
1966         .ops            = &clkops_null,
1967         .parent         = &l4_ick,
1968         .clkdm_name     = "core_l4_clkdm",
1969         .recalc         = &followparent_recalc,
1970 };
1971
1972 static struct clk ssi_ick_3430es1 = {
1973         .name           = "ssi_ick",
1974         .ops            = &clkops_omap2_dflt,
1975         .parent         = &ssi_l4_ick,
1976         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1977         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1978         .clkdm_name     = "core_l4_clkdm",
1979         .recalc         = &followparent_recalc,
1980 };
1981
1982 static struct clk ssi_ick_3430es2 = {
1983         .name           = "ssi_ick",
1984         .ops            = &clkops_omap3430es2_ssi_wait,
1985         .parent         = &ssi_l4_ick,
1986         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1987         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1988         .clkdm_name     = "core_l4_clkdm",
1989         .recalc         = &followparent_recalc,
1990 };
1991
1992 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
1993  * but l4_ick makes more sense to me */
1994
1995 static const struct clksel usb_l4_clksel[] = {
1996         { .parent = &l4_ick, .rates = div2_rates },
1997         { .parent = NULL },
1998 };
1999
2000 static struct clk usb_l4_ick = {
2001         .name           = "usb_l4_ick",
2002         .ops            = &clkops_omap2_dflt_wait,
2003         .parent         = &l4_ick,
2004         .init           = &omap2_init_clksel_parent,
2005         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2006         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2007         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2008         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2009         .clksel         = usb_l4_clksel,
2010         .recalc         = &omap2_clksel_recalc,
2011 };
2012
2013 /* SECURITY_L4_ICK2 based clocks */
2014
2015 static struct clk security_l4_ick2 = {
2016         .name           = "security_l4_ick2",
2017         .ops            = &clkops_null,
2018         .parent         = &l4_ick,
2019         .recalc         = &followparent_recalc,
2020 };
2021
2022 static struct clk aes1_ick = {
2023         .name           = "aes1_ick",
2024         .ops            = &clkops_omap2_dflt_wait,
2025         .parent         = &security_l4_ick2,
2026         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2027         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2028         .recalc         = &followparent_recalc,
2029 };
2030
2031 static struct clk rng_ick = {
2032         .name           = "rng_ick",
2033         .ops            = &clkops_omap2_dflt_wait,
2034         .parent         = &security_l4_ick2,
2035         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2036         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2037         .recalc         = &followparent_recalc,
2038 };
2039
2040 static struct clk sha11_ick = {
2041         .name           = "sha11_ick",
2042         .ops            = &clkops_omap2_dflt_wait,
2043         .parent         = &security_l4_ick2,
2044         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2045         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2046         .recalc         = &followparent_recalc,
2047 };
2048
2049 static struct clk des1_ick = {
2050         .name           = "des1_ick",
2051         .ops            = &clkops_omap2_dflt_wait,
2052         .parent         = &security_l4_ick2,
2053         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2054         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2055         .recalc         = &followparent_recalc,
2056 };
2057
2058 /* DSS */
2059 static struct clk dss1_alwon_fck_3430es1 = {
2060         .name           = "dss1_alwon_fck",
2061         .ops            = &clkops_omap2_dflt,
2062         .parent         = &dpll4_m4x2_ck,
2063         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2064         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2065         .clkdm_name     = "dss_clkdm",
2066         .recalc         = &followparent_recalc,
2067 };
2068
2069 static struct clk dss1_alwon_fck_3430es2 = {
2070         .name           = "dss1_alwon_fck",
2071         .ops            = &clkops_omap3430es2_dss_usbhost_wait,
2072         .parent         = &dpll4_m4x2_ck,
2073         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2074         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2075         .clkdm_name     = "dss_clkdm",
2076         .recalc         = &followparent_recalc,
2077 };
2078
2079 static struct clk dss_tv_fck = {
2080         .name           = "dss_tv_fck",
2081         .ops            = &clkops_omap2_dflt,
2082         .parent         = &omap_54m_fck,
2083         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2084         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2085         .clkdm_name     = "dss_clkdm",
2086         .recalc         = &followparent_recalc,
2087 };
2088
2089 static struct clk dss_96m_fck = {
2090         .name           = "dss_96m_fck",
2091         .ops            = &clkops_omap2_dflt,
2092         .parent         = &omap_96m_fck,
2093         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2094         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2095         .clkdm_name     = "dss_clkdm",
2096         .recalc         = &followparent_recalc,
2097 };
2098
2099 static struct clk dss2_alwon_fck = {
2100         .name           = "dss2_alwon_fck",
2101         .ops            = &clkops_omap2_dflt,
2102         .parent         = &sys_ck,
2103         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2104         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2105         .clkdm_name     = "dss_clkdm",
2106         .recalc         = &followparent_recalc,
2107 };
2108
2109 static struct clk dss_ick_3430es1 = {
2110         /* Handles both L3 and L4 clocks */
2111         .name           = "dss_ick",
2112         .ops            = &clkops_omap2_dflt,
2113         .parent         = &l4_ick,
2114         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2115         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2116         .clkdm_name     = "dss_clkdm",
2117         .recalc         = &followparent_recalc,
2118 };
2119
2120 static struct clk dss_ick_3430es2 = {
2121         /* Handles both L3 and L4 clocks */
2122         .name           = "dss_ick",
2123         .ops            = &clkops_omap3430es2_dss_usbhost_wait,
2124         .parent         = &l4_ick,
2125         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2126         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2127         .clkdm_name     = "dss_clkdm",
2128         .recalc         = &followparent_recalc,
2129 };
2130
2131 /* CAM */
2132
2133 static struct clk cam_mclk = {
2134         .name           = "cam_mclk",
2135         .ops            = &clkops_omap2_dflt,
2136         .parent         = &dpll4_m5x2_ck,
2137         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2138         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2139         .clkdm_name     = "cam_clkdm",
2140         .recalc         = &followparent_recalc,
2141 };
2142
2143 static struct clk cam_ick = {
2144         /* Handles both L3 and L4 clocks */
2145         .name           = "cam_ick",
2146         .ops            = &clkops_omap2_dflt,
2147         .parent         = &l4_ick,
2148         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2149         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2150         .clkdm_name     = "cam_clkdm",
2151         .recalc         = &followparent_recalc,
2152 };
2153
2154 static struct clk csi2_96m_fck = {
2155         .name           = "csi2_96m_fck",
2156         .ops            = &clkops_omap2_dflt,
2157         .parent         = &core_96m_fck,
2158         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2159         .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
2160         .clkdm_name     = "cam_clkdm",
2161         .recalc         = &followparent_recalc,
2162 };
2163
2164 /* USBHOST - 3430ES2 only */
2165
2166 static struct clk usbhost_120m_fck = {
2167         .name           = "usbhost_120m_fck",
2168         .ops            = &clkops_omap2_dflt,
2169         .parent         = &dpll5_m2_ck,
2170         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2171         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2172         .clkdm_name     = "usbhost_clkdm",
2173         .recalc         = &followparent_recalc,
2174 };
2175
2176 static struct clk usbhost_48m_fck = {
2177         .name           = "usbhost_48m_fck",
2178         .ops            = &clkops_omap3430es2_dss_usbhost_wait,
2179         .parent         = &omap_48m_fck,
2180         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2181         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2182         .clkdm_name     = "usbhost_clkdm",
2183         .recalc         = &followparent_recalc,
2184 };
2185
2186 static struct clk usbhost_ick = {
2187         /* Handles both L3 and L4 clocks */
2188         .name           = "usbhost_ick",
2189         .ops            = &clkops_omap3430es2_dss_usbhost_wait,
2190         .parent         = &l4_ick,
2191         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2192         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2193         .clkdm_name     = "usbhost_clkdm",
2194         .recalc         = &followparent_recalc,
2195 };
2196
2197 /* WKUP */
2198
2199 static const struct clksel_rate usim_96m_rates[] = {
2200         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2201         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2202         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2203         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2204         { .div = 0 },
2205 };
2206
2207 static const struct clksel_rate usim_120m_rates[] = {
2208         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2209         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2210         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2211         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2212         { .div = 0 },
2213 };
2214
2215 static const struct clksel usim_clksel[] = {
2216         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2217         { .parent = &dpll5_m2_ck,       .rates = usim_120m_rates },
2218         { .parent = &sys_ck,            .rates = div2_rates },
2219         { .parent = NULL },
2220 };
2221
2222 /* 3430ES2 only */
2223 static struct clk usim_fck = {
2224         .name           = "usim_fck",
2225         .ops            = &clkops_omap2_dflt_wait,
2226         .init           = &omap2_init_clksel_parent,
2227         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2228         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2229         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2230         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2231         .clksel         = usim_clksel,
2232         .recalc         = &omap2_clksel_recalc,
2233 };
2234
2235 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2236 static struct clk gpt1_fck = {
2237         .name           = "gpt1_fck",
2238         .ops            = &clkops_omap2_dflt_wait,
2239         .init           = &omap2_init_clksel_parent,
2240         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2241         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2242         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2243         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2244         .clksel         = omap343x_gpt_clksel,
2245         .clkdm_name     = "wkup_clkdm",
2246         .recalc         = &omap2_clksel_recalc,
2247 };
2248
2249 static struct clk wkup_32k_fck = {
2250         .name           = "wkup_32k_fck",
2251         .ops            = &clkops_null,
2252         .parent         = &omap_32k_fck,
2253         .clkdm_name     = "wkup_clkdm",
2254         .recalc         = &followparent_recalc,
2255 };
2256
2257 static struct clk gpio1_dbck = {
2258         .name           = "gpio1_dbck",
2259         .ops            = &clkops_omap2_dflt,
2260         .parent         = &wkup_32k_fck,
2261         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2262         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2263         .clkdm_name     = "wkup_clkdm",
2264         .recalc         = &followparent_recalc,
2265 };
2266
2267 static struct clk wdt2_fck = {
2268         .name           = "wdt2_fck",
2269         .ops            = &clkops_omap2_dflt_wait,
2270         .parent         = &wkup_32k_fck,
2271         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2272         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2273         .clkdm_name     = "wkup_clkdm",
2274         .recalc         = &followparent_recalc,
2275 };
2276
2277 static struct clk wkup_l4_ick = {
2278         .name           = "wkup_l4_ick",
2279         .ops            = &clkops_null,
2280         .parent         = &sys_ck,
2281         .clkdm_name     = "wkup_clkdm",
2282         .recalc         = &followparent_recalc,
2283 };
2284
2285 /* 3430ES2 only */
2286 /* Never specifically named in the TRM, so we have to infer a likely name */
2287 static struct clk usim_ick = {
2288         .name           = "usim_ick",
2289         .ops            = &clkops_omap2_dflt_wait,
2290         .parent         = &wkup_l4_ick,
2291         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2292         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2293         .clkdm_name     = "wkup_clkdm",
2294         .recalc         = &followparent_recalc,
2295 };
2296
2297 static struct clk wdt2_ick = {
2298         .name           = "wdt2_ick",
2299         .ops            = &clkops_omap2_dflt_wait,
2300         .parent         = &wkup_l4_ick,
2301         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2302         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2303         .clkdm_name     = "wkup_clkdm",
2304         .recalc         = &followparent_recalc,
2305 };
2306
2307 static struct clk wdt1_ick = {
2308         .name           = "wdt1_ick",
2309         .ops            = &clkops_omap2_dflt_wait,
2310         .parent         = &wkup_l4_ick,
2311         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2312         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2313         .clkdm_name     = "wkup_clkdm",
2314         .recalc         = &followparent_recalc,
2315 };
2316
2317 static struct clk gpio1_ick = {
2318         .name           = "gpio1_ick",
2319         .ops            = &clkops_omap2_dflt_wait,
2320         .parent         = &wkup_l4_ick,
2321         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2322         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2323         .clkdm_name     = "wkup_clkdm",
2324         .recalc         = &followparent_recalc,
2325 };
2326
2327 static struct clk omap_32ksync_ick = {
2328         .name           = "omap_32ksync_ick",
2329         .ops            = &clkops_omap2_dflt_wait,
2330         .parent         = &wkup_l4_ick,
2331         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2332         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2333         .clkdm_name     = "wkup_clkdm",
2334         .recalc         = &followparent_recalc,
2335 };
2336
2337 /* XXX This clock no longer exists in 3430 TRM rev F */
2338 static struct clk gpt12_ick = {
2339         .name           = "gpt12_ick",
2340         .ops            = &clkops_omap2_dflt_wait,
2341         .parent         = &wkup_l4_ick,
2342         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2343         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2344         .clkdm_name     = "wkup_clkdm",
2345         .recalc         = &followparent_recalc,
2346 };
2347
2348 static struct clk gpt1_ick = {
2349         .name           = "gpt1_ick",
2350         .ops            = &clkops_omap2_dflt_wait,
2351         .parent         = &wkup_l4_ick,
2352         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2353         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2354         .clkdm_name     = "wkup_clkdm",
2355         .recalc         = &followparent_recalc,
2356 };
2357
2358
2359
2360 /* PER clock domain */
2361
2362 static struct clk per_96m_fck = {
2363         .name           = "per_96m_fck",
2364         .ops            = &clkops_null,
2365         .parent         = &omap_96m_alwon_fck,
2366         .clkdm_name     = "per_clkdm",
2367         .recalc         = &followparent_recalc,
2368 };
2369
2370 static struct clk per_48m_fck = {
2371         .name           = "per_48m_fck",
2372         .ops            = &clkops_null,
2373         .parent         = &omap_48m_fck,
2374         .clkdm_name     = "per_clkdm",
2375         .recalc         = &followparent_recalc,
2376 };
2377
2378 static struct clk uart3_fck = {
2379         .name           = "uart3_fck",
2380         .ops            = &clkops_omap2_dflt_wait,
2381         .parent         = &per_48m_fck,
2382         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2383         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2384         .clkdm_name     = "per_clkdm",
2385         .recalc         = &followparent_recalc,
2386 };
2387
2388 static struct clk gpt2_fck = {
2389         .name           = "gpt2_fck",
2390         .ops            = &clkops_omap2_dflt_wait,
2391         .init           = &omap2_init_clksel_parent,
2392         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2393         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2394         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2395         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2396         .clksel         = omap343x_gpt_clksel,
2397         .clkdm_name     = "per_clkdm",
2398         .recalc         = &omap2_clksel_recalc,
2399 };
2400
2401 static struct clk gpt3_fck = {
2402         .name           = "gpt3_fck",
2403         .ops            = &clkops_omap2_dflt_wait,
2404         .init           = &omap2_init_clksel_parent,
2405         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2406         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2407         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2408         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2409         .clksel         = omap343x_gpt_clksel,
2410         .clkdm_name     = "per_clkdm",
2411         .recalc         = &omap2_clksel_recalc,
2412 };
2413
2414 static struct clk gpt4_fck = {
2415         .name           = "gpt4_fck",
2416         .ops            = &clkops_omap2_dflt_wait,
2417         .init           = &omap2_init_clksel_parent,
2418         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2419         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2420         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2421         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2422         .clksel         = omap343x_gpt_clksel,
2423         .clkdm_name     = "per_clkdm",
2424         .recalc         = &omap2_clksel_recalc,
2425 };
2426
2427 static struct clk gpt5_fck = {
2428         .name           = "gpt5_fck",
2429         .ops            = &clkops_omap2_dflt_wait,
2430         .init           = &omap2_init_clksel_parent,
2431         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2432         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2433         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2434         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2435         .clksel         = omap343x_gpt_clksel,
2436         .clkdm_name     = "per_clkdm",
2437         .recalc         = &omap2_clksel_recalc,
2438 };
2439
2440 static struct clk gpt6_fck = {
2441         .name           = "gpt6_fck",
2442         .ops            = &clkops_omap2_dflt_wait,
2443         .init           = &omap2_init_clksel_parent,
2444         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2445         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2446         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2447         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2448         .clksel         = omap343x_gpt_clksel,
2449         .clkdm_name     = "per_clkdm",
2450         .recalc         = &omap2_clksel_recalc,
2451 };
2452
2453 static struct clk gpt7_fck = {
2454         .name           = "gpt7_fck",
2455         .ops            = &clkops_omap2_dflt_wait,
2456         .init           = &omap2_init_clksel_parent,
2457         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2458         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2459         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2460         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2461         .clksel         = omap343x_gpt_clksel,
2462         .clkdm_name     = "per_clkdm",
2463         .recalc         = &omap2_clksel_recalc,
2464 };
2465
2466 static struct clk gpt8_fck = {
2467         .name           = "gpt8_fck",
2468         .ops            = &clkops_omap2_dflt_wait,
2469         .init           = &omap2_init_clksel_parent,
2470         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2471         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2472         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2473         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2474         .clksel         = omap343x_gpt_clksel,
2475         .clkdm_name     = "per_clkdm",
2476         .recalc         = &omap2_clksel_recalc,
2477 };
2478
2479 static struct clk gpt9_fck = {
2480         .name           = "gpt9_fck",
2481         .ops            = &clkops_omap2_dflt_wait,
2482         .init           = &omap2_init_clksel_parent,
2483         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2484         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2485         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2486         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2487         .clksel         = omap343x_gpt_clksel,
2488         .clkdm_name     = "per_clkdm",
2489         .recalc         = &omap2_clksel_recalc,
2490 };
2491
2492 static struct clk per_32k_alwon_fck = {
2493         .name           = "per_32k_alwon_fck",
2494         .ops            = &clkops_null,
2495         .parent         = &omap_32k_fck,
2496         .clkdm_name     = "per_clkdm",
2497         .recalc         = &followparent_recalc,
2498 };
2499
2500 static struct clk gpio6_dbck = {
2501         .name           = "gpio6_dbck",
2502         .ops            = &clkops_omap2_dflt,
2503         .parent         = &per_32k_alwon_fck,
2504         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2505         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2506         .clkdm_name     = "per_clkdm",
2507         .recalc         = &followparent_recalc,
2508 };
2509
2510 static struct clk gpio5_dbck = {
2511         .name           = "gpio5_dbck",
2512         .ops            = &clkops_omap2_dflt,
2513         .parent         = &per_32k_alwon_fck,
2514         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2515         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2516         .clkdm_name     = "per_clkdm",
2517         .recalc         = &followparent_recalc,
2518 };
2519
2520 static struct clk gpio4_dbck = {
2521         .name           = "gpio4_dbck",
2522         .ops            = &clkops_omap2_dflt,
2523         .parent         = &per_32k_alwon_fck,
2524         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2525         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2526         .clkdm_name     = "per_clkdm",
2527         .recalc         = &followparent_recalc,
2528 };
2529
2530 static struct clk gpio3_dbck = {
2531         .name           = "gpio3_dbck",
2532         .ops            = &clkops_omap2_dflt,
2533         .parent         = &per_32k_alwon_fck,
2534         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2535         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2536         .clkdm_name     = "per_clkdm",
2537         .recalc         = &followparent_recalc,
2538 };
2539
2540 static struct clk gpio2_dbck = {
2541         .name           = "gpio2_dbck",
2542         .ops            = &clkops_omap2_dflt,
2543         .parent         = &per_32k_alwon_fck,
2544         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2545         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2546         .clkdm_name     = "per_clkdm",
2547         .recalc         = &followparent_recalc,
2548 };
2549
2550 static struct clk wdt3_fck = {
2551         .name           = "wdt3_fck",
2552         .ops            = &clkops_omap2_dflt_wait,
2553         .parent         = &per_32k_alwon_fck,
2554         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2555         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2556         .clkdm_name     = "per_clkdm",
2557         .recalc         = &followparent_recalc,
2558 };
2559
2560 static struct clk per_l4_ick = {
2561         .name           = "per_l4_ick",
2562         .ops            = &clkops_null,
2563         .parent         = &l4_ick,
2564         .clkdm_name     = "per_clkdm",
2565         .recalc         = &followparent_recalc,
2566 };
2567
2568 static struct clk gpio6_ick = {
2569         .name           = "gpio6_ick",
2570         .ops            = &clkops_omap2_dflt_wait,
2571         .parent         = &per_l4_ick,
2572         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2573         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2574         .clkdm_name     = "per_clkdm",
2575         .recalc         = &followparent_recalc,
2576 };
2577
2578 static struct clk gpio5_ick = {
2579         .name           = "gpio5_ick",
2580         .ops            = &clkops_omap2_dflt_wait,
2581         .parent         = &per_l4_ick,
2582         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2583         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2584         .clkdm_name     = "per_clkdm",
2585         .recalc         = &followparent_recalc,
2586 };
2587
2588 static struct clk gpio4_ick = {
2589         .name           = "gpio4_ick",
2590         .ops            = &clkops_omap2_dflt_wait,
2591         .parent         = &per_l4_ick,
2592         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2593         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2594         .clkdm_name     = "per_clkdm",
2595         .recalc         = &followparent_recalc,
2596 };
2597
2598 static struct clk gpio3_ick = {
2599         .name           = "gpio3_ick",
2600         .ops            = &clkops_omap2_dflt_wait,
2601         .parent         = &per_l4_ick,
2602         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2603         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2604         .clkdm_name     = "per_clkdm",
2605         .recalc         = &followparent_recalc,
2606 };
2607
2608 static struct clk gpio2_ick = {
2609         .name           = "gpio2_ick",
2610         .ops            = &clkops_omap2_dflt_wait,
2611         .parent         = &per_l4_ick,
2612         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2613         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2614         .clkdm_name     = "per_clkdm",
2615         .recalc         = &followparent_recalc,
2616 };
2617
2618 static struct clk wdt3_ick = {
2619         .name           = "wdt3_ick",
2620         .ops            = &clkops_omap2_dflt_wait,
2621         .parent         = &per_l4_ick,
2622         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2623         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2624         .clkdm_name     = "per_clkdm",
2625         .recalc         = &followparent_recalc,
2626 };
2627
2628 static struct clk uart3_ick = {
2629         .name           = "uart3_ick",
2630         .ops            = &clkops_omap2_dflt_wait,
2631         .parent         = &per_l4_ick,
2632         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2633         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2634         .clkdm_name     = "per_clkdm",
2635         .recalc         = &followparent_recalc,
2636 };
2637
2638 static struct clk gpt9_ick = {
2639         .name           = "gpt9_ick",
2640         .ops            = &clkops_omap2_dflt_wait,
2641         .parent         = &per_l4_ick,
2642         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2643         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2644         .clkdm_name     = "per_clkdm",
2645         .recalc         = &followparent_recalc,
2646 };
2647
2648 static struct clk gpt8_ick = {
2649         .name           = "gpt8_ick",
2650         .ops            = &clkops_omap2_dflt_wait,
2651         .parent         = &per_l4_ick,
2652         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2653         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2654         .clkdm_name     = "per_clkdm",
2655         .recalc         = &followparent_recalc,
2656 };
2657
2658 static struct clk gpt7_ick = {
2659         .name           = "gpt7_ick",
2660         .ops            = &clkops_omap2_dflt_wait,
2661         .parent         = &per_l4_ick,
2662         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2663         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2664         .clkdm_name     = "per_clkdm",
2665         .recalc         = &followparent_recalc,
2666 };
2667
2668 static struct clk gpt6_ick = {
2669         .name           = "gpt6_ick",
2670         .ops            = &clkops_omap2_dflt_wait,
2671         .parent         = &per_l4_ick,
2672         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2673         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2674         .clkdm_name     = "per_clkdm",
2675         .recalc         = &followparent_recalc,
2676 };
2677
2678 static struct clk gpt5_ick = {
2679         .name           = "gpt5_ick",
2680         .ops            = &clkops_omap2_dflt_wait,
2681         .parent         = &per_l4_ick,
2682         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2683         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2684         .clkdm_name     = "per_clkdm",
2685         .recalc         = &followparent_recalc,
2686 };
2687
2688 static struct clk gpt4_ick = {
2689         .name           = "gpt4_ick",
2690         .ops            = &clkops_omap2_dflt_wait,
2691         .parent         = &per_l4_ick,
2692         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2693         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2694         .clkdm_name     = "per_clkdm",
2695         .recalc         = &followparent_recalc,
2696 };
2697
2698 static struct clk gpt3_ick = {
2699         .name           = "gpt3_ick",
2700         .ops            = &clkops_omap2_dflt_wait,
2701         .parent         = &per_l4_ick,
2702         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2703         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2704         .clkdm_name     = "per_clkdm",
2705         .recalc         = &followparent_recalc,
2706 };
2707
2708 static struct clk gpt2_ick = {
2709         .name           = "gpt2_ick",
2710         .ops            = &clkops_omap2_dflt_wait,
2711         .parent         = &per_l4_ick,
2712         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2713         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2714         .clkdm_name     = "per_clkdm",
2715         .recalc         = &followparent_recalc,
2716 };
2717
2718 static struct clk mcbsp2_ick = {
2719         .name           = "mcbsp_ick",
2720         .ops            = &clkops_omap2_dflt_wait,
2721         .id             = 2,
2722         .parent         = &per_l4_ick,
2723         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2724         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2725         .clkdm_name     = "per_clkdm",
2726         .recalc         = &followparent_recalc,
2727 };
2728
2729 static struct clk mcbsp3_ick = {
2730         .name           = "mcbsp_ick",
2731         .ops            = &clkops_omap2_dflt_wait,
2732         .id             = 3,
2733         .parent         = &per_l4_ick,
2734         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2735         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2736         .clkdm_name     = "per_clkdm",
2737         .recalc         = &followparent_recalc,
2738 };
2739
2740 static struct clk mcbsp4_ick = {
2741         .name           = "mcbsp_ick",
2742         .ops            = &clkops_omap2_dflt_wait,
2743         .id             = 4,
2744         .parent         = &per_l4_ick,
2745         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2746         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2747         .clkdm_name     = "per_clkdm",
2748         .recalc         = &followparent_recalc,
2749 };
2750
2751 static const struct clksel mcbsp_234_clksel[] = {
2752         { .parent = &per_96m_fck,  .rates = common_mcbsp_96m_rates },
2753         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
2754         { .parent = NULL }
2755 };
2756
2757 static struct clk mcbsp2_fck = {
2758         .name           = "mcbsp_fck",
2759         .ops            = &clkops_omap2_dflt_wait,
2760         .id             = 2,
2761         .init           = &omap2_init_clksel_parent,
2762         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2763         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2764         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2765         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2766         .clksel         = mcbsp_234_clksel,
2767         .clkdm_name     = "per_clkdm",
2768         .recalc         = &omap2_clksel_recalc,
2769 };
2770
2771 static struct clk mcbsp3_fck = {
2772         .name           = "mcbsp_fck",
2773         .ops            = &clkops_omap2_dflt_wait,
2774         .id             = 3,
2775         .init           = &omap2_init_clksel_parent,
2776         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2777         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2778         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2779         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2780         .clksel         = mcbsp_234_clksel,
2781         .clkdm_name     = "per_clkdm",
2782         .recalc         = &omap2_clksel_recalc,
2783 };
2784
2785 static struct clk mcbsp4_fck = {
2786         .name           = "mcbsp_fck",
2787         .ops            = &clkops_omap2_dflt_wait,
2788         .id             = 4,
2789         .init           = &omap2_init_clksel_parent,
2790         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2791         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2792         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2793         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2794         .clksel         = mcbsp_234_clksel,
2795         .clkdm_name     = "per_clkdm",
2796         .recalc         = &omap2_clksel_recalc,
2797 };
2798
2799 /* EMU clocks */
2800
2801 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2802
2803 static const struct clksel_rate emu_src_sys_rates[] = {
2804         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2805         { .div = 0 },
2806 };
2807
2808 static const struct clksel_rate emu_src_core_rates[] = {
2809         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2810         { .div = 0 },
2811 };
2812
2813 static const struct clksel_rate emu_src_per_rates[] = {
2814         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2815         { .div = 0 },
2816 };
2817
2818 static const struct clksel_rate emu_src_mpu_rates[] = {
2819         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2820         { .div = 0 },
2821 };
2822
2823 static const struct clksel emu_src_clksel[] = {
2824         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2825         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2826         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2827         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2828         { .parent = NULL },
2829 };
2830
2831 /*
2832  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2833  * to switch the source of some of the EMU clocks.
2834  * XXX Are there CLKEN bits for these EMU clks?
2835  */
2836 static struct clk emu_src_ck = {
2837         .name           = "emu_src_ck",
2838         .ops            = &clkops_null,
2839         .init           = &omap2_init_clksel_parent,
2840         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2841         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2842         .clksel         = emu_src_clksel,
2843         .clkdm_name     = "emu_clkdm",
2844         .recalc         = &omap2_clksel_recalc,
2845 };
2846
2847 static const struct clksel_rate pclk_emu_rates[] = {
2848         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2849         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2850         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2851         { .div = 6, .val = 6, .flags = RATE_IN_343X },
2852         { .div = 0 },
2853 };
2854
2855 static const struct clksel pclk_emu_clksel[] = {
2856         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2857         { .parent = NULL },
2858 };
2859
2860 static struct clk pclk_fck = {
2861         .name           = "pclk_fck",
2862         .ops            = &clkops_null,
2863         .init           = &omap2_init_clksel_parent,
2864         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2865         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
2866         .clksel         = pclk_emu_clksel,
2867         .clkdm_name     = "emu_clkdm",
2868         .recalc         = &omap2_clksel_recalc,
2869 };
2870
2871 static const struct clksel_rate pclkx2_emu_rates[] = {
2872         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2873         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2874         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2875         { .div = 0 },
2876 };
2877
2878 static const struct clksel pclkx2_emu_clksel[] = {
2879         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2880         { .parent = NULL },
2881 };
2882
2883 static struct clk pclkx2_fck = {
2884         .name           = "pclkx2_fck",
2885         .ops            = &clkops_null,
2886         .init           = &omap2_init_clksel_parent,
2887         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2888         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
2889         .clksel         = pclkx2_emu_clksel,
2890         .clkdm_name     = "emu_clkdm",
2891         .recalc         = &omap2_clksel_recalc,
2892 };
2893
2894 static const struct clksel atclk_emu_clksel[] = {
2895         { .parent = &emu_src_ck, .rates = div2_rates },
2896         { .parent = NULL },
2897 };
2898
2899 static struct clk atclk_fck = {
2900         .name           = "atclk_fck",
2901         .ops            = &clkops_null,
2902         .init           = &omap2_init_clksel_parent,
2903         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2904         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
2905         .clksel         = atclk_emu_clksel,
2906         .clkdm_name     = "emu_clkdm",
2907         .recalc         = &omap2_clksel_recalc,
2908 };
2909
2910 static struct clk traceclk_src_fck = {
2911         .name           = "traceclk_src_fck",
2912         .ops            = &clkops_null,
2913         .init           = &omap2_init_clksel_parent,
2914         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2915         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
2916         .clksel         = emu_src_clksel,
2917         .clkdm_name     = "emu_clkdm",
2918         .recalc         = &omap2_clksel_recalc,
2919 };
2920
2921 static const struct clksel_rate traceclk_rates[] = {
2922         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2923         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2924         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2925         { .div = 0 },
2926 };
2927
2928 static const struct clksel traceclk_clksel[] = {
2929         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2930         { .parent = NULL },
2931 };
2932
2933 static struct clk traceclk_fck = {
2934         .name           = "traceclk_fck",
2935         .ops            = &clkops_null,
2936         .init           = &omap2_init_clksel_parent,
2937         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2938         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
2939         .clksel         = traceclk_clksel,
2940         .clkdm_name     = "emu_clkdm",
2941         .recalc         = &omap2_clksel_recalc,
2942 };
2943
2944 /* SR clocks */
2945
2946 /* SmartReflex fclk (VDD1) */
2947 static struct clk sr1_fck = {
2948         .name           = "sr1_fck",
2949         .ops            = &clkops_omap2_dflt_wait,
2950         .parent         = &sys_ck,
2951         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2952         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
2953         .recalc         = &followparent_recalc,
2954 };
2955
2956 /* SmartReflex fclk (VDD2) */
2957 static struct clk sr2_fck = {
2958         .name           = "sr2_fck",
2959         .ops            = &clkops_omap2_dflt_wait,
2960         .parent         = &sys_ck,
2961         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2962         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
2963         .recalc         = &followparent_recalc,
2964 };
2965
2966 static struct clk sr_l4_ick = {
2967         .name           = "sr_l4_ick",
2968         .ops            = &clkops_null, /* RMK: missing? */
2969         .parent         = &l4_ick,
2970         .clkdm_name     = "core_l4_clkdm",
2971         .recalc         = &followparent_recalc,
2972 };
2973
2974 /* SECURE_32K_FCK clocks */
2975
2976 static struct clk gpt12_fck = {
2977         .name           = "gpt12_fck",
2978         .ops            = &clkops_null,
2979         .parent         = &secure_32k_fck,
2980         .recalc         = &followparent_recalc,
2981 };
2982
2983 static struct clk wdt1_fck = {
2984         .name           = "wdt1_fck",
2985         .ops            = &clkops_null,
2986         .parent         = &secure_32k_fck,
2987         .recalc         = &followparent_recalc,
2988 };
2989
2990
2991 /*
2992  * clkdev
2993  */
2994
2995 static struct omap_clk omap34xx_clks[] = {
2996         CLK(NULL,       "omap_32k_fck", &omap_32k_fck,  CK_343X),
2997         CLK(NULL,       "virt_12m_ck",  &virt_12m_ck,   CK_343X),
2998         CLK(NULL,       "virt_13m_ck",  &virt_13m_ck,   CK_343X),
2999         CLK(NULL,       "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2),
3000         CLK(NULL,       "virt_19_2m_ck", &virt_19_2m_ck, CK_343X),
3001         CLK(NULL,       "virt_26m_ck",  &virt_26m_ck,   CK_343X),
3002         CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck, CK_343X),
3003         CLK(NULL,       "osc_sys_ck",   &osc_sys_ck,    CK_343X),
3004         CLK(NULL,       "sys_ck",       &sys_ck,        CK_343X),
3005         CLK(NULL,       "sys_altclk",   &sys_altclk,    CK_343X),
3006         CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_343X),
3007         CLK(NULL,       "sys_clkout1",  &sys_clkout1,   CK_343X),
3008         CLK(NULL,       "dpll1_ck",     &dpll1_ck,      CK_343X),
3009         CLK(NULL,       "dpll1_x2_ck",  &dpll1_x2_ck,   CK_343X),
3010         CLK(NULL,       "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X),
3011         CLK(NULL,       "dpll2_ck",     &dpll2_ck,      CK_343X),
3012         CLK(NULL,       "dpll2_m2_ck",  &dpll2_m2_ck,   CK_343X),
3013         CLK(NULL,       "dpll3_ck",     &dpll3_ck,      CK_343X),
3014         CLK(NULL,       "core_ck",      &core_ck,       CK_343X),
3015         CLK(NULL,       "dpll3_x2_ck",  &dpll3_x2_ck,   CK_343X),
3016         CLK(NULL,       "dpll3_m2_ck",  &dpll3_m2_ck,   CK_343X),
3017         CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X),
3018         CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck,   CK_343X),
3019         CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X),
3020         CLK("etb",      "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X),
3021         CLK(NULL,       "dpll4_ck",     &dpll4_ck,      CK_343X),
3022         CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck,   CK_343X),
3023         CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X),
3024         CLK(NULL,       "omap_96m_fck", &omap_96m_fck,  CK_343X),
3025         CLK(NULL,       "cm_96m_fck",   &cm_96m_fck,    CK_343X),
3026         CLK(NULL,       "omap_54m_fck", &omap_54m_fck,  CK_343X),
3027         CLK(NULL,       "omap_48m_fck", &omap_48m_fck,  CK_343X),
3028         CLK(NULL,       "omap_12m_fck", &omap_12m_fck,  CK_343X),
3029         CLK(NULL,       "dpll4_m2_ck",  &dpll4_m2_ck,   CK_343X),
3030         CLK(NULL,       "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X),
3031         CLK(NULL,       "dpll4_m3_ck",  &dpll4_m3_ck,   CK_343X),
3032         CLK(NULL,       "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X),
3033         CLK(NULL,       "dpll4_m4_ck",  &dpll4_m4_ck,   CK_343X),
3034         CLK(NULL,       "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X),
3035         CLK(NULL,       "dpll4_m5_ck",  &dpll4_m5_ck,   CK_343X),
3036         CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X),
3037         CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck,   CK_343X),
3038         CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X),
3039         CLK("etb",      "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X),
3040         CLK(NULL,       "dpll5_ck",     &dpll5_ck,      CK_3430ES2),
3041         CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck,   CK_3430ES2),
3042         CLK(NULL,       "clkout2_src_ck", &clkout2_src_ck, CK_343X),
3043         CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_343X),
3044         CLK(NULL,       "corex2_fck",   &corex2_fck,    CK_343X),
3045         CLK(NULL,       "dpll1_fck",    &dpll1_fck,     CK_343X),
3046         CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_343X),
3047         CLK(NULL,       "arm_fck",      &arm_fck,       CK_343X),
3048         CLK("etb",      "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X),
3049         CLK(NULL,       "dpll2_fck",    &dpll2_fck,     CK_343X),
3050         CLK(NULL,       "iva2_ck",      &iva2_ck,       CK_343X),
3051         CLK(NULL,       "l3_ick",       &l3_ick,        CK_343X),
3052         CLK(NULL,       "l4_ick",       &l4_ick,        CK_343X),
3053         CLK(NULL,       "rm_ick",       &rm_ick,        CK_343X),
3054         CLK(NULL,       "gfx_l3_ck",    &gfx_l3_ck,     CK_3430ES1),
3055         CLK(NULL,       "gfx_l3_fck",   &gfx_l3_fck,    CK_3430ES1),
3056         CLK(NULL,       "gfx_l3_ick",   &gfx_l3_ick,    CK_3430ES1),
3057         CLK(NULL,       "gfx_cg1_ck",   &gfx_cg1_ck,    CK_3430ES1),
3058         CLK(NULL,       "gfx_cg2_ck",   &gfx_cg2_ck,    CK_3430ES1),
3059         CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2),
3060         CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2),
3061         CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck,   CK_3430ES1),
3062         CLK(NULL,       "modem_fck",    &modem_fck,     CK_343X),
3063         CLK(NULL,       "sad2d_ick",    &sad2d_ick,     CK_343X),
3064         CLK(NULL,       "mad2d_ick",    &mad2d_ick,     CK_343X),
3065         CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_343X),
3066         CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_343X),
3067         CLK(NULL,       "cpefuse_fck",  &cpefuse_fck,   CK_3430ES2),
3068         CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2),
3069         CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2),
3070         CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_343X),
3071         CLK("mmci-omap-hs.2",   "fck",  &mmchs3_fck,    CK_3430ES2),
3072         CLK("mmci-omap-hs.1",   "fck",  &mmchs2_fck,    CK_343X),
3073         CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_343X),
3074         CLK("mmci-omap-hs.0",   "fck",  &mmchs1_fck,    CK_343X),
3075         CLK("i2c_omap.3", "fck",        &i2c3_fck,      CK_343X),
3076         CLK("i2c_omap.2", "fck",        &i2c2_fck,      CK_343X),
3077         CLK("i2c_omap.1", "fck",        &i2c1_fck,      CK_343X),
3078         CLK("omap-mcbsp.5", "fck",      &mcbsp5_fck,    CK_343X),
3079         CLK("omap-mcbsp.1", "fck",      &mcbsp1_fck,    CK_343X),
3080         CLK(NULL,       "core_48m_fck", &core_48m_fck,  CK_343X),
3081         CLK("omap2_mcspi.4", "fck",     &mcspi4_fck,    CK_343X),
3082         CLK("omap2_mcspi.3", "fck",     &mcspi3_fck,    CK_343X),
3083         CLK("omap2_mcspi.2", "fck",     &mcspi2_fck,    CK_343X),
3084         CLK("omap2_mcspi.1", "fck",     &mcspi1_fck,    CK_343X),
3085         CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_343X),
3086         CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_343X),
3087         CLK(NULL,       "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
3088         CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_343X),
3089         CLK("omap_hdq.0", "fck",        &hdq_fck,       CK_343X),
3090         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1,   CK_3430ES1),
3091         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2,   CK_3430ES2),
3092         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1,   CK_3430ES1),
3093         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es2,   CK_3430ES2),
3094         CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_343X),
3095         CLK("musb_hdrc",        "ick",  &hsotgusb_ick_3430es1,  CK_3430ES1),
3096         CLK("musb_hdrc",        "ick",  &hsotgusb_ick_3430es2,  CK_3430ES2),
3097         CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_343X),
3098         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_343X),
3099         CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_343X),
3100         CLK(NULL,       "pka_ick",      &pka_ick,       CK_343X),
3101         CLK(NULL,       "core_l4_ick",  &core_l4_ick,   CK_343X),
3102         CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2),
3103         CLK("mmci-omap-hs.2",   "ick",  &mmchs3_ick,    CK_3430ES2),
3104         CLK(NULL,       "icr_ick",      &icr_ick,       CK_343X),
3105         CLK(NULL,       "aes2_ick",     &aes2_ick,      CK_343X),
3106         CLK(NULL,       "sha12_ick",    &sha12_ick,     CK_343X),
3107         CLK(NULL,       "des2_ick",     &des2_ick,      CK_343X),
3108         CLK("mmci-omap-hs.1",   "ick",  &mmchs2_ick,    CK_343X),
3109         CLK("mmci-omap-hs.0",   "ick",  &mmchs1_ick,    CK_343X),
3110         CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_343X),
3111         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_343X),
3112         CLK("omap2_mcspi.4", "ick",     &mcspi4_ick,    CK_343X),
3113         CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_343X),
3114         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_343X),
3115         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_343X),
3116         CLK("i2c_omap.3", "ick",        &i2c3_ick,      CK_343X),
3117         CLK("i2c_omap.2", "ick",        &i2c2_ick,      CK_343X),
3118         CLK("i2c_omap.1", "ick",        &i2c1_ick,      CK_343X),
3119         CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_343X),
3120         CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_343X),
3121         CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_343X),
3122         CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_343X),
3123         CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_343X),
3124         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_343X),
3125         CLK(NULL,       "fac_ick",      &fac_ick,       CK_3430ES1),
3126         CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_343X),
3127         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_343X),
3128         CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_343X),
3129         CLK(NULL,       "ssi_ick",      &ssi_ick_3430es1,       CK_3430ES1),
3130         CLK(NULL,       "ssi_ick",      &ssi_ick_3430es2,       CK_3430ES2),
3131         CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_3430ES1),
3132         CLK(NULL,       "security_l4_ick2", &security_l4_ick2, CK_343X),
3133         CLK(NULL,       "aes1_ick",     &aes1_ick,      CK_343X),
3134         CLK("omap_rng", "ick",          &rng_ick,       CK_343X),
3135         CLK(NULL,       "sha11_ick",    &sha11_ick,     CK_343X),
3136         CLK(NULL,       "des1_ick",     &des1_ick,      CK_343X),
3137         CLK("omapdss",  "dss1_fck",     &dss1_alwon_fck_3430es1, CK_3430ES1),
3138         CLK("omapdss",  "dss1_fck",     &dss1_alwon_fck_3430es2, CK_3430ES2),
3139         CLK("omapdss",  "tv_fck",       &dss_tv_fck,    CK_343X),
3140         CLK("omapdss",  "video_fck",    &dss_96m_fck,   CK_343X),
3141         CLK("omapdss",  "dss2_fck",     &dss2_alwon_fck, CK_343X),
3142         CLK("omapdss",  "ick",          &dss_ick_3430es1,       CK_3430ES1),
3143         CLK("omapdss",  "ick",          &dss_ick_3430es2,       CK_3430ES2),
3144         CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_343X),
3145         CLK(NULL,       "cam_ick",      &cam_ick,       CK_343X),
3146         CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_343X),
3147         CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2),
3148         CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2),
3149         CLK(NULL,       "usbhost_ick",  &usbhost_ick,   CK_3430ES2),
3150         CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2),
3151         CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_343X),
3152         CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck,  CK_343X),
3153         CLK(NULL,       "gpio1_dbck",   &gpio1_dbck,    CK_343X),
3154         CLK("omap_wdt", "fck",          &wdt2_fck,      CK_343X),
3155         CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick,   CK_343X),
3156         CLK(NULL,       "usim_ick",     &usim_ick,      CK_3430ES2),
3157         CLK("omap_wdt", "ick",          &wdt2_ick,      CK_343X),
3158         CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_343X),
3159         CLK(NULL,       "gpio1_ick",    &gpio1_ick,     CK_343X),
3160         CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick, CK_343X),
3161         CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_343X),
3162         CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_343X),
3163         CLK(NULL,       "per_96m_fck",  &per_96m_fck,   CK_343X),
3164         CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_343X),
3165         CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_343X),
3166         CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_343X),
3167         CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_343X),
3168         CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_343X),
3169         CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_343X),
3170         CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_343X),
3171         CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_343X),
3172         CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_343X),
3173         CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_343X),
3174         CLK(NULL,       "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X),
3175         CLK(NULL,       "gpio6_dbck",   &gpio6_dbck,    CK_343X),
3176         CLK(NULL,       "gpio5_dbck",   &gpio5_dbck,    CK_343X),
3177         CLK(NULL,       "gpio4_dbck",   &gpio4_dbck,    CK_343X),
3178         CLK(NULL,       "gpio3_dbck",   &gpio3_dbck,    CK_343X),
3179         CLK(NULL,       "gpio2_dbck",   &gpio2_dbck,    CK_343X),
3180         CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_343X),
3181         CLK(NULL,       "per_l4_ick",   &per_l4_ick,    CK_343X),
3182         CLK(NULL,       "gpio6_ick",    &gpio6_ick,     CK_343X),
3183         CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_343X),
3184         CLK(NULL,       "gpio4_ick",    &gpio4_ick,     CK_343X),
3185         CLK(NULL,       "gpio3_ick",    &gpio3_ick,     CK_343X),
3186         CLK(NULL,       "gpio2_ick",    &gpio2_ick,     CK_343X),
3187         CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_343X),
3188         CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_343X),
3189         CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_343X),
3190         CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_343X),
3191         CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_343X),
3192         CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_343X),
3193         CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_343X),
3194         CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_343X),
3195         CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_343X),
3196         CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_343X),
3197         CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_343X),
3198         CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_343X),
3199         CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_343X),
3200         CLK("omap-mcbsp.2", "fck",      &mcbsp2_fck,    CK_343X),
3201         CLK("omap-mcbsp.3", "fck",      &mcbsp3_fck,    CK_343X),
3202         CLK("omap-mcbsp.4", "fck",      &mcbsp4_fck,    CK_343X),
3203         CLK("etb",      "emu_src_ck",   &emu_src_ck,    CK_343X),
3204         CLK(NULL,       "pclk_fck",     &pclk_fck,      CK_343X),
3205         CLK(NULL,       "pclkx2_fck",   &pclkx2_fck,    CK_343X),
3206         CLK(NULL,       "atclk_fck",    &atclk_fck,     CK_343X),
3207         CLK(NULL,       "traceclk_src_fck", &traceclk_src_fck, CK_343X),
3208         CLK(NULL,       "traceclk_fck", &traceclk_fck,  CK_343X),
3209         CLK(NULL,       "sr1_fck",      &sr1_fck,       CK_343X),
3210         CLK(NULL,       "sr2_fck",      &sr2_fck,       CK_343X),
3211         CLK(NULL,       "sr_l4_ick",    &sr_l4_ick,     CK_343X),
3212         CLK(NULL,       "secure_32k_fck", &secure_32k_fck, CK_343X),
3213         CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_343X),
3214         CLK(NULL,       "wdt1_fck",     &wdt1_fck,      CK_343X),
3215 };
3216
3217
3218 int __init omap2_clk_init(void)
3219 {
3220         /* struct prcm_config *prcm; */
3221         struct omap_clk *c;
3222         /* u32 clkrate; */
3223         u32 cpu_clkflg;
3224
3225         if (cpu_is_omap34xx()) {
3226                 cpu_mask = RATE_IN_343X;
3227                 cpu_clkflg = CK_343X;
3228
3229                 /*
3230                  * Update this if there are further clock changes between ES2
3231                  * and production parts
3232                  */
3233                 if (omap_rev() == OMAP3430_REV_ES1_0) {
3234                         /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
3235                         cpu_clkflg |= CK_3430ES1;
3236                 } else {
3237                         cpu_mask |= RATE_IN_3430ES2;
3238                         cpu_clkflg |= CK_3430ES2;
3239                 }
3240         }
3241
3242         clk_init(&omap2_clk_functions);
3243
3244         for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
3245                 clk_preinit(c->lk.clk);
3246
3247         for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
3248                 if (c->cpu & cpu_clkflg) {
3249                         clkdev_add(&c->lk);
3250                         clk_register(c->lk.clk);
3251                         omap2_init_clk_clkdm(c->lk.clk);
3252                 }
3253
3254         /* REVISIT: Not yet ready for OMAP3 */
3255 #if 0
3256         /* Check the MPU rate set by bootloader */
3257         clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
3258         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
3259                 if (!(prcm->flags & cpu_mask))
3260                         continue;
3261                 if (prcm->xtal_speed != sys_ck.rate)
3262                         continue;
3263                 if (prcm->dpll_speed <= clkrate)
3264                         break;
3265         }
3266         curr_prcm_set = prcm;
3267 #endif
3268
3269         recalculate_root_clocks();
3270
3271         printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): "
3272                "%ld.%01ld/%ld/%ld MHz\n",
3273                (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
3274                (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
3275
3276         /*
3277          * Only enable those clocks we will need, let the drivers
3278          * enable other clocks as necessary
3279          */
3280         clk_enable_init_clocks();
3281
3282         /*
3283          * Lock DPLL5 and put it in autoidle.
3284          */
3285         if (omap_rev() >= OMAP3430_REV_ES2_0)
3286                 omap3_clk_lock_dpll5();
3287
3288         /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3289         sdrc_ick_p = clk_get(NULL, "sdrc_ick");
3290         arm_fck_p = clk_get(NULL, "arm_fck");
3291
3292         return 0;
3293 }