arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  21
  22 #include <mach/control.h>
  23
  24 #include "clock.h"
  25 #include "cm.h"
  26 #include "cm-regbits-34xx.h"
  27 #include "prm.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 static void omap3_dpll_recalc(struct clk *clk);
  31 static void omap3_clkoutx2_recalc(struct clk *clk);
  32 static void omap3_dpll_allow_idle(struct clk *clk);
  33 static void omap3_dpll_deny_idle(struct clk *clk);
  34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
  35 static int omap3_noncore_dpll_enable(struct clk *clk);
  36 static void omap3_noncore_dpll_disable(struct clk *clk);
  37
  38 /* Maximum DPLL multiplier, divider values for OMAP3 */
  39 #define OMAP3_MAX_DPLL_MULT             2048
  40 #define OMAP3_MAX_DPLL_DIV              128
  41
  42 /*
  43  * DPLL1 supplies clock to the MPU.
  44  * DPLL2 supplies clock to the IVA2.
  45  * DPLL3 supplies CORE domain clocks.
  46  * DPLL4 supplies peripheral clocks.
  47  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  48  */
  49
  50 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  51 #define DPLL_LOW_POWER_STOP             0x1
  52 #define DPLL_LOW_POWER_BYPASS           0x5
  53 #define DPLL_LOCKED                     0x7
  54
  55 /* PRM CLOCKS */
  56
  57 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  58 static struct clk omap_32k_fck = {
  59         .name           = "omap_32k_fck",
  60         .rate           = 32768,
  61         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  62                                 ALWAYS_ENABLED,
  63         .recalc         = &propagate_rate,
  64 };
  65
  66 static struct clk secure_32k_fck = {
  67         .name           = "secure_32k_fck",
  68         .rate           = 32768,
  69         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  70                                 ALWAYS_ENABLED,
  71         .recalc         = &propagate_rate,
  72 };
  73
  74 /* Virtual source clocks for osc_sys_ck */
  75 static struct clk virt_12m_ck = {
  76         .name           = "virt_12m_ck",
  77         .rate           = 12000000,
  78         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  79                                 ALWAYS_ENABLED,
  80         .recalc         = &propagate_rate,
  81 };
  82
  83 static struct clk virt_13m_ck = {
  84         .name           = "virt_13m_ck",
  85         .rate           = 13000000,
  86         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  87                                 ALWAYS_ENABLED,
  88         .recalc         = &propagate_rate,
  89 };
  90
  91 static struct clk virt_16_8m_ck = {
  92         .name           = "virt_16_8m_ck",
  93         .rate           = 16800000,
  94         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
  95                                 ALWAYS_ENABLED,
  96         .recalc         = &propagate_rate,
  97 };
  98
  99 static struct clk virt_19_2m_ck = {
 100         .name           = "virt_19_2m_ck",
 101         .rate           = 19200000,
 102         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 103                                 ALWAYS_ENABLED,
 104         .recalc         = &propagate_rate,
 105 };
 106
 107 static struct clk virt_26m_ck = {
 108         .name           = "virt_26m_ck",
 109         .rate           = 26000000,
 110         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 111                                 ALWAYS_ENABLED,
 112         .recalc         = &propagate_rate,
 113 };
 114
 115 static struct clk virt_38_4m_ck = {
 116         .name           = "virt_38_4m_ck",
 117         .rate           = 38400000,
 118         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 119                                 ALWAYS_ENABLED,
 120         .recalc         = &propagate_rate,
 121 };
 122
 123 static const struct clksel_rate osc_sys_12m_rates[] = {
 124         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 125         { .div = 0 }
 126 };
 127
 128 static const struct clksel_rate osc_sys_13m_rates[] = {
 129         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 130         { .div = 0 }
 131 };
 132
 133 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 134         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 135         { .div = 0 }
 136 };
 137
 138 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 139         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 140         { .div = 0 }
 141 };
 142
 143 static const struct clksel_rate osc_sys_26m_rates[] = {
 144         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 145         { .div = 0 }
 146 };
 147
 148 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 149         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 150         { .div = 0 }
 151 };
 152
 153 static const struct clksel osc_sys_clksel[] = {
 154         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 155         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 156         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 157         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 158         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 159         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 160         { .parent = NULL },
 161 };
 162
 163 /* Oscillator clock */
 164 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 165 static struct clk osc_sys_ck = {
 166         .name           = "osc_sys_ck",
 167         .init           = &omap2_init_clksel_parent,
 168         .clksel_reg     = OMAP3430_PRM_CLKSEL,
 169         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 170         .clksel         = osc_sys_clksel,
 171         /* REVISIT: deal with autoextclkmode? */
 172         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 173                                 ALWAYS_ENABLED,
 174         .recalc         = &omap2_clksel_recalc,
 175 };
 176
 177 static const struct clksel_rate div2_rates[] = {
 178         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 179         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 180         { .div = 0 }
 181 };
 182
 183 static const struct clksel sys_clksel[] = {
 184         { .parent = &osc_sys_ck, .rates = div2_rates },
 185         { .parent = NULL }
 186 };
 187
 188 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 189 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 190 static struct clk sys_ck = {
 191         .name           = "sys_ck",
 192         .parent         = &osc_sys_ck,
 193         .init           = &omap2_init_clksel_parent,
 194         .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
 195         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 196         .clksel         = sys_clksel,
 197         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 198         .recalc         = &omap2_clksel_recalc,
 199 };
 200
 201 static struct clk sys_altclk = {
 202         .name           = "sys_altclk",
 203         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 204         .recalc         = &propagate_rate,
 205 };
 206
 207 /* Optional external clock input for some McBSPs */
 208 static struct clk mcbsp_clks = {
 209         .name           = "mcbsp_clks",
 210         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 211         .recalc         = &propagate_rate,
 212 };
 213
 214 /* PRM EXTERNAL CLOCK OUTPUT */
 215
 216 static struct clk sys_clkout1 = {
 217         .name           = "sys_clkout1",
 218         .parent         = &osc_sys_ck,
 219         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
 220         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 221         .flags          = CLOCK_IN_OMAP343X,
 222         .recalc         = &followparent_recalc,
 223 };
 224
 225 /* DPLLS */
 226
 227 /* CM CLOCKS */
 228
 229 static const struct clksel_rate dpll_bypass_rates[] = {
 230         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 231         { .div = 0 }
 232 };
 233
 234 static const struct clksel_rate dpll_locked_rates[] = {
 235         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 236         { .div = 0 }
 237 };
 238
 239 static const struct clksel_rate div16_dpll_rates[] = {
 240         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 241         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 242         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 243         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 244         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 245         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 246         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 247         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 248         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 249         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 250         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 251         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 252         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 253         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 254         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 255         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 256         { .div = 0 }
 257 };
 258
 259 /* DPLL1 */
 260 /* MPU clock source */
 261 /* Type: DPLL */
 262 static struct dpll_data dpll1_dd = {
 263         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 264         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 265         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 266         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 267         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 268         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 269         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 270         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 271         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 272         .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 273         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 274         .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 275         .idlest_bit     = OMAP3430_ST_MPU_CLK_SHIFT,
 276         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 277         .max_divider    = OMAP3_MAX_DPLL_DIV,
 278         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 279 };
 280
 281 static struct clk dpll1_ck = {
 282         .name           = "dpll1_ck",
 283         .parent         = &sys_ck,
 284         .dpll_data      = &dpll1_dd,
 285         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 286         .round_rate     = &omap2_dpll_round_rate,
 287         .recalc         = &omap3_dpll_recalc,
 288 };
 289
 290 /*
 291  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 292  * DPLL isn't bypassed.
 293  */
 294 static struct clk dpll1_x2_ck = {
 295         .name           = "dpll1_x2_ck",
 296         .parent         = &dpll1_ck,
 297         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 298                                 PARENT_CONTROLS_CLOCK,
 299         .recalc         = &omap3_clkoutx2_recalc,
 300 };
 301
 302 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 303 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 304         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 305         { .parent = NULL }
 306 };
 307
 308 /*
 309  * Does not exist in the TRM - needed to separate the M2 divider from
 310  * bypass selection in mpu_ck
 311  */
 312 static struct clk dpll1_x2m2_ck = {
 313         .name           = "dpll1_x2m2_ck",
 314         .parent         = &dpll1_x2_ck,
 315         .init           = &omap2_init_clksel_parent,
 316         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 317         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 318         .clksel         = div16_dpll1_x2m2_clksel,
 319         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 320                                 PARENT_CONTROLS_CLOCK,
 321         .recalc         = &omap2_clksel_recalc,
 322 };
 323
 324 /* DPLL2 */
 325 /* IVA2 clock source */
 326 /* Type: DPLL */
 327
 328 static struct dpll_data dpll2_dd = {
 329         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 330         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 331         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 332         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 333         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 334         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 335                                 (1 << DPLL_LOW_POWER_BYPASS),
 336         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 337         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 338         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 339         .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 340         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 341         .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 342         .idlest_bit     = OMAP3430_ST_IVA2_CLK_SHIFT,
 343         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 344         .max_divider    = OMAP3_MAX_DPLL_DIV,
 345         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 346 };
 347
 348 static struct clk dpll2_ck = {
 349         .name           = "dpll2_ck",
 350         .parent         = &sys_ck,
 351         .dpll_data      = &dpll2_dd,
 352         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 353         .enable         = &omap3_noncore_dpll_enable,
 354         .disable        = &omap3_noncore_dpll_disable,
 355         .round_rate     = &omap2_dpll_round_rate,
 356         .recalc         = &omap3_dpll_recalc,
 357 };
 358
 359 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 360         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 361         { .parent = NULL }
 362 };
 363
 364 /*
 365  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 366  * or CLKOUTX2. CLKOUT seems most plausible.
 367  */
 368 static struct clk dpll2_m2_ck = {
 369         .name           = "dpll2_m2_ck",
 370         .parent         = &dpll2_ck,
 371         .init           = &omap2_init_clksel_parent,
 372         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
 373                                           OMAP3430_CM_CLKSEL2_PLL),
 374         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 375         .clksel         = div16_dpll2_m2x2_clksel,
 376         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 377                                 PARENT_CONTROLS_CLOCK,
 378         .recalc         = &omap2_clksel_recalc,
 379 };
 380
 381 /*
 382  * DPLL3
 383  * Source clock for all interfaces and for some device fclks
 384  * REVISIT: Also supports fast relock bypass - not included below
 385  */
 386 static struct dpll_data dpll3_dd = {
 387         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 388         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 389         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 390         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 391         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 392         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 393         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 394         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 395         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 396         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 397         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 398         .max_divider    = OMAP3_MAX_DPLL_DIV,
 399         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 400 };
 401
 402 static struct clk dpll3_ck = {
 403         .name           = "dpll3_ck",
 404         .parent         = &sys_ck,
 405         .dpll_data      = &dpll3_dd,
 406         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 407         .round_rate     = &omap2_dpll_round_rate,
 408         .recalc         = &omap3_dpll_recalc,
 409 };
 410
 411 /*
 412  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 413  * DPLL isn't bypassed
 414  */
 415 static struct clk dpll3_x2_ck = {
 416         .name           = "dpll3_x2_ck",
 417         .parent         = &dpll3_ck,
 418         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 419                                 PARENT_CONTROLS_CLOCK,
 420         .recalc         = &omap3_clkoutx2_recalc,
 421 };
 422
 423 static const struct clksel_rate div31_dpll3_rates[] = {
 424         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 425         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 426         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 427         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 428         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 429         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 430         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 431         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 432         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 433         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 434         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 435         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 436         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 437         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 438         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 439         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 440         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 441         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 442         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 443         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 444         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 445         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 446         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 447         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 448         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 449         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 450         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 451         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 452         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 453         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 454         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 455         { .div = 0 },
 456 };
 457
 458 static const struct clksel div31_dpll3m2_clksel[] = {
 459         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 460         { .parent = NULL }
 461 };
 462
 463 /*
 464  * DPLL3 output M2
 465  * REVISIT: This DPLL output divider must be changed in SRAM, so until
 466  * that code is ready, this should remain a 'read-only' clksel clock.
 467  */
 468 static struct clk dpll3_m2_ck = {
 469         .name           = "dpll3_m2_ck",
 470         .parent         = &dpll3_ck,
 471         .init           = &omap2_init_clksel_parent,
 472         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 473         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 474         .clksel         = div31_dpll3m2_clksel,
 475         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 476                                 PARENT_CONTROLS_CLOCK,
 477         .recalc         = &omap2_clksel_recalc,
 478 };
 479
 480 static const struct clksel core_ck_clksel[] = {
 481         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 482         { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
 483         { .parent = NULL }
 484 };
 485
 486 static struct clk core_ck = {
 487         .name           = "core_ck",
 488         .init           = &omap2_init_clksel_parent,
 489         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 490         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 491         .clksel         = core_ck_clksel,
 492         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 493                                 PARENT_CONTROLS_CLOCK,
 494         .recalc         = &omap2_clksel_recalc,
 495 };
 496
 497 static const struct clksel dpll3_m2x2_ck_clksel[] = {
 498         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 499         { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
 500         { .parent = NULL }
 501 };
 502
 503 static struct clk dpll3_m2x2_ck = {
 504         .name           = "dpll3_m2x2_ck",
 505         .init           = &omap2_init_clksel_parent,
 506         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 507         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 508         .clksel         = dpll3_m2x2_ck_clksel,
 509         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 510                                 PARENT_CONTROLS_CLOCK,
 511         .recalc         = &omap2_clksel_recalc,
 512 };
 513
 514 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 515 static const struct clksel div16_dpll3_clksel[] = {
 516         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 517         { .parent = NULL }
 518 };
 519
 520 /* This virtual clock is the source for dpll3_m3x2_ck */
 521 static struct clk dpll3_m3_ck = {
 522         .name           = "dpll3_m3_ck",
 523         .parent         = &dpll3_ck,
 524         .init           = &omap2_init_clksel_parent,
 525         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 526         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 527         .clksel         = div16_dpll3_clksel,
 528         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 529                                 PARENT_CONTROLS_CLOCK,
 530         .recalc         = &omap2_clksel_recalc,
 531 };
 532
 533 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 534 static struct clk dpll3_m3x2_ck = {
 535         .name           = "dpll3_m3x2_ck",
 536         .parent         = &dpll3_m3_ck,
 537         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 538         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 539         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 540         .recalc         = &omap3_clkoutx2_recalc,
 541 };
 542
 543 static const struct clksel emu_core_alwon_ck_clksel[] = {
 544         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 545         { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
 546         { .parent = NULL }
 547 };
 548
 549 static struct clk emu_core_alwon_ck = {
 550         .name           = "emu_core_alwon_ck",
 551         .parent         = &dpll3_m3x2_ck,
 552         .init           = &omap2_init_clksel_parent,
 553         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 554         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 555         .clksel         = emu_core_alwon_ck_clksel,
 556         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 557                                 PARENT_CONTROLS_CLOCK,
 558         .recalc         = &omap2_clksel_recalc,
 559 };
 560
 561 /* DPLL4 */
 562 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 563 /* Type: DPLL */
 564 static struct dpll_data dpll4_dd = {
 565         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 566         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 567         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 568         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 569         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 570         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 571         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 572         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 573         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 574         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 575         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 576         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 577         .idlest_bit     = OMAP3430_ST_PERIPH_CLK_SHIFT,
 578         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 579         .max_divider    = OMAP3_MAX_DPLL_DIV,
 580         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 581 };
 582
 583 static struct clk dpll4_ck = {
 584         .name           = "dpll4_ck",
 585         .parent         = &sys_ck,
 586         .dpll_data      = &dpll4_dd,
 587         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 588         .enable         = &omap3_noncore_dpll_enable,
 589         .disable        = &omap3_noncore_dpll_disable,
 590         .round_rate     = &omap2_dpll_round_rate,
 591         .recalc         = &omap3_dpll_recalc,
 592 };
 593
 594 /*
 595  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 596  * DPLL isn't bypassed --
 597  * XXX does this serve any downstream clocks?
 598  */
 599 static struct clk dpll4_x2_ck = {
 600         .name           = "dpll4_x2_ck",
 601         .parent         = &dpll4_ck,
 602         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 603                                 PARENT_CONTROLS_CLOCK,
 604         .recalc         = &omap3_clkoutx2_recalc,
 605 };
 606
 607 static const struct clksel div16_dpll4_clksel[] = {
 608         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 609         { .parent = NULL }
 610 };
 611
 612 /* This virtual clock is the source for dpll4_m2x2_ck */
 613 static struct clk dpll4_m2_ck = {
 614         .name           = "dpll4_m2_ck",
 615         .parent         = &dpll4_ck,
 616         .init           = &omap2_init_clksel_parent,
 617         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 618         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 619         .clksel         = div16_dpll4_clksel,
 620         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 621                                 PARENT_CONTROLS_CLOCK,
 622         .recalc         = &omap2_clksel_recalc,
 623 };
 624
 625 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 626 static struct clk dpll4_m2x2_ck = {
 627         .name           = "dpll4_m2x2_ck",
 628         .parent         = &dpll4_m2_ck,
 629         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 630         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 631         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 632         .recalc         = &omap3_clkoutx2_recalc,
 633 };
 634
 635 static const struct clksel omap_96m_alwon_fck_clksel[] = {
 636         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 637         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 638         { .parent = NULL }
 639 };
 640
 641 static struct clk omap_96m_alwon_fck = {
 642         .name           = "omap_96m_alwon_fck",
 643         .parent         = &dpll4_m2x2_ck,
 644         .init           = &omap2_init_clksel_parent,
 645         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 646         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 647         .clksel         = omap_96m_alwon_fck_clksel,
 648         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 649                                  PARENT_CONTROLS_CLOCK,
 650         .recalc         = &omap2_clksel_recalc,
 651 };
 652
 653 static struct clk omap_96m_fck = {
 654         .name           = "omap_96m_fck",
 655         .parent         = &omap_96m_alwon_fck,
 656         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 657                                 PARENT_CONTROLS_CLOCK,
 658         .recalc         = &followparent_recalc,
 659 };
 660
 661 static const struct clksel cm_96m_fck_clksel[] = {
 662         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 663         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 664         { .parent = NULL }
 665 };
 666
 667 static struct clk cm_96m_fck = {
 668         .name           = "cm_96m_fck",
 669         .parent         = &dpll4_m2x2_ck,
 670         .init           = &omap2_init_clksel_parent,
 671         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 672         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 673         .clksel         = cm_96m_fck_clksel,
 674         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 675                                 PARENT_CONTROLS_CLOCK,
 676         .recalc         = &omap2_clksel_recalc,
 677 };
 678
 679 /* This virtual clock is the source for dpll4_m3x2_ck */
 680 static struct clk dpll4_m3_ck = {
 681         .name           = "dpll4_m3_ck",
 682         .parent         = &dpll4_ck,
 683         .init           = &omap2_init_clksel_parent,
 684         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 685         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 686         .clksel         = div16_dpll4_clksel,
 687         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 688                                 PARENT_CONTROLS_CLOCK,
 689         .recalc         = &omap2_clksel_recalc,
 690 };
 691
 692 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 693 static struct clk dpll4_m3x2_ck = {
 694         .name           = "dpll4_m3x2_ck",
 695         .parent         = &dpll4_m3_ck,
 696         .init           = &omap2_init_clksel_parent,
 697         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 698         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 699         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 700         .recalc         = &omap3_clkoutx2_recalc,
 701 };
 702
 703 static const struct clksel virt_omap_54m_fck_clksel[] = {
 704         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 705         { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
 706         { .parent = NULL }
 707 };
 708
 709 static struct clk virt_omap_54m_fck = {
 710         .name           = "virt_omap_54m_fck",
 711         .parent         = &dpll4_m3x2_ck,
 712         .init           = &omap2_init_clksel_parent,
 713         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 714         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 715         .clksel         = virt_omap_54m_fck_clksel,
 716         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 717                                 PARENT_CONTROLS_CLOCK,
 718         .recalc         = &omap2_clksel_recalc,
 719 };
 720
 721 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 722         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 723         { .div = 0 }
 724 };
 725
 726 static const struct clksel_rate omap_54m_alt_rates[] = {
 727         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 728         { .div = 0 }
 729 };
 730
 731 static const struct clksel omap_54m_clksel[] = {
 732         { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
 733         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 734         { .parent = NULL }
 735 };
 736
 737 static struct clk omap_54m_fck = {
 738         .name           = "omap_54m_fck",
 739         .init           = &omap2_init_clksel_parent,
 740         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 741         .clksel_mask    = OMAP3430_SOURCE_54M,
 742         .clksel         = omap_54m_clksel,
 743         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 744                                 PARENT_CONTROLS_CLOCK,
 745         .recalc         = &omap2_clksel_recalc,
 746 };
 747
 748 static const struct clksel_rate omap_48m_96md2_rates[] = {
 749         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 750         { .div = 0 }
 751 };
 752
 753 static const struct clksel_rate omap_48m_alt_rates[] = {
 754         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 755         { .div = 0 }
 756 };
 757
 758 static const struct clksel omap_48m_clksel[] = {
 759         { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates },
 760         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 761         { .parent = NULL }
 762 };
 763
 764 static struct clk omap_48m_fck = {
 765         .name           = "omap_48m_fck",
 766         .init           = &omap2_init_clksel_parent,
 767         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 768         .clksel_mask    = OMAP3430_SOURCE_48M,
 769         .clksel         = omap_48m_clksel,
 770         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 771                                 PARENT_CONTROLS_CLOCK,
 772         .recalc         = &omap2_clksel_recalc,
 773 };
 774
 775 static struct clk omap_12m_fck = {
 776         .name           = "omap_12m_fck",
 777         .parent         = &omap_48m_fck,
 778         .fixed_div      = 4,
 779         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 780                                 PARENT_CONTROLS_CLOCK,
 781         .recalc         = &omap2_fixed_divisor_recalc,
 782 };
 783
 784 /* This virstual clock is the source for dpll4_m4x2_ck */
 785 static struct clk dpll4_m4_ck = {
 786         .name           = "dpll4_m4_ck",
 787         .parent         = &dpll4_ck,
 788         .init           = &omap2_init_clksel_parent,
 789         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 790         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 791         .clksel         = div16_dpll4_clksel,
 792         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 793                                 PARENT_CONTROLS_CLOCK,
 794         .recalc         = &omap2_clksel_recalc,
 795 };
 796
 797 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 798 static struct clk dpll4_m4x2_ck = {
 799         .name           = "dpll4_m4x2_ck",
 800         .parent         = &dpll4_m4_ck,
 801         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 802         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 803         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 804         .recalc         = &omap3_clkoutx2_recalc,
 805 };
 806
 807 /* This virtual clock is the source for dpll4_m5x2_ck */
 808 static struct clk dpll4_m5_ck = {
 809         .name           = "dpll4_m5_ck",
 810         .parent         = &dpll4_ck,
 811         .init           = &omap2_init_clksel_parent,
 812         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 813         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 814         .clksel         = div16_dpll4_clksel,
 815         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 816                                 PARENT_CONTROLS_CLOCK,
 817         .recalc         = &omap2_clksel_recalc,
 818 };
 819
 820 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 821 static struct clk dpll4_m5x2_ck = {
 822         .name           = "dpll4_m5x2_ck",
 823         .parent         = &dpll4_m5_ck,
 824         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 825         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 826         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 827         .recalc         = &omap3_clkoutx2_recalc,
 828 };
 829
 830 /* This virtual clock is the source for dpll4_m6x2_ck */
 831 static struct clk dpll4_m6_ck = {
 832         .name           = "dpll4_m6_ck",
 833         .parent         = &dpll4_ck,
 834         .init           = &omap2_init_clksel_parent,
 835         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 836         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 837         .clksel         = div16_dpll4_clksel,
 838         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 839                                 PARENT_CONTROLS_CLOCK,
 840         .recalc         = &omap2_clksel_recalc,
 841 };
 842
 843 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 844 static struct clk dpll4_m6x2_ck = {
 845         .name           = "dpll4_m6x2_ck",
 846         .parent         = &dpll4_m6_ck,
 847         .init           = &omap2_init_clksel_parent,
 848         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 849         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 850         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 851         .recalc         = &omap3_clkoutx2_recalc,
 852 };
 853
 854 static struct clk emu_per_alwon_ck = {
 855         .name           = "emu_per_alwon_ck",
 856         .parent         = &dpll4_m6x2_ck,
 857         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 858                                 PARENT_CONTROLS_CLOCK,
 859         .recalc         = &followparent_recalc,
 860 };
 861
 862 /* DPLL5 */
 863 /* Supplies 120MHz clock, USIM source clock */
 864 /* Type: DPLL */
 865 /* 3430ES2 only */
 866 static struct dpll_data dpll5_dd = {
 867         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 868         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 869         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 870         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 871         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 872         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 873         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 874         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 875         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 876         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 877         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 878         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 879         .idlest_bit     = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT,
 880         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 881         .max_divider    = OMAP3_MAX_DPLL_DIV,
 882         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 883 };
 884
 885 static struct clk dpll5_ck = {
 886         .name           = "dpll5_ck",
 887         .parent         = &sys_ck,
 888         .dpll_data      = &dpll5_dd,
 889         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
 890         .enable         = &omap3_noncore_dpll_enable,
 891         .disable        = &omap3_noncore_dpll_disable,
 892         .round_rate     = &omap2_dpll_round_rate,
 893         .recalc         = &omap3_dpll_recalc,
 894 };
 895
 896 static const struct clksel div16_dpll5_clksel[] = {
 897         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 898         { .parent = NULL }
 899 };
 900
 901 static struct clk dpll5_m2_ck = {
 902         .name           = "dpll5_m2_ck",
 903         .parent         = &dpll5_ck,
 904         .init           = &omap2_init_clksel_parent,
 905         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 906         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 907         .clksel         = div16_dpll5_clksel,
 908         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
 909                                 PARENT_CONTROLS_CLOCK,
 910         .recalc         = &omap2_clksel_recalc,
 911 };
 912
 913 static const struct clksel omap_120m_fck_clksel[] = {
 914         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 915         { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
 916         { .parent = NULL }
 917 };
 918
 919 static struct clk omap_120m_fck = {
 920         .name           = "omap_120m_fck",
 921         .parent         = &dpll5_m2_ck,
 922         .init           = &omap2_init_clksel_parent,
 923         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 924         .clksel_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 925         .clksel         = omap_120m_fck_clksel,
 926         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
 927                                 PARENT_CONTROLS_CLOCK,
 928         .recalc         = &omap2_clksel_recalc,
 929 };
 930
 931 /* CM EXTERNAL CLOCK OUTPUTS */
 932
 933 static const struct clksel_rate clkout2_src_core_rates[] = {
 934         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 935         { .div = 0 }
 936 };
 937
 938 static const struct clksel_rate clkout2_src_sys_rates[] = {
 939         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 940         { .div = 0 }
 941 };
 942
 943 static const struct clksel_rate clkout2_src_96m_rates[] = {
 944         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 945         { .div = 0 }
 946 };
 947
 948 static const struct clksel_rate clkout2_src_54m_rates[] = {
 949         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 950         { .div = 0 }
 951 };
 952
 953 static const struct clksel clkout2_src_clksel[] = {
 954         { .parent = &core_ck,             .rates = clkout2_src_core_rates },
 955         { .parent = &sys_ck,              .rates = clkout2_src_sys_rates },
 956         { .parent = &omap_96m_alwon_fck,  .rates = clkout2_src_96m_rates },
 957         { .parent = &omap_54m_fck,        .rates = clkout2_src_54m_rates },
 958         { .parent = NULL }
 959 };
 960
 961 static struct clk clkout2_src_ck = {
 962         .name           = "clkout2_src_ck",
 963         .init           = &omap2_init_clksel_parent,
 964         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
 965         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
 966         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 967         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
 968         .clksel         = clkout2_src_clksel,
 969         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 970         .recalc         = &omap2_clksel_recalc,
 971 };
 972
 973 static const struct clksel_rate sys_clkout2_rates[] = {
 974         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 975         { .div = 2, .val = 1, .flags = RATE_IN_343X },
 976         { .div = 4, .val = 2, .flags = RATE_IN_343X },
 977         { .div = 8, .val = 3, .flags = RATE_IN_343X },
 978         { .div = 16, .val = 4, .flags = RATE_IN_343X },
 979         { .div = 0 },
 980 };
 981
 982 static const struct clksel sys_clkout2_clksel[] = {
 983         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
 984         { .parent = NULL },
 985 };
 986
 987 static struct clk sys_clkout2 = {
 988         .name           = "sys_clkout2",
 989         .init           = &omap2_init_clksel_parent,
 990         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 991         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
 992         .clksel         = sys_clkout2_clksel,
 993         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 994         .recalc         = &omap2_clksel_recalc,
 995 };
 996
 997 /* CM OUTPUT CLOCKS */
 998
 999 static struct clk corex2_fck = {
1000         .name           = "corex2_fck",
1001         .parent         = &dpll3_m2x2_ck,
1002         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1003                                 PARENT_CONTROLS_CLOCK,
1004         .recalc         = &followparent_recalc,
1005 };
1006
1007 /* DPLL power domain clock controls */
1008
1009 static const struct clksel div2_core_clksel[] = {
1010         { .parent = &core_ck, .rates = div2_rates },
1011         { .parent = NULL }
1012 };
1013
1014 /*
1015  * REVISIT: Are these in DPLL power domain or CM power domain? docs
1016  * may be inconsistent here?
1017  */
1018 static struct clk dpll1_fck = {
1019         .name           = "dpll1_fck",
1020         .parent         = &core_ck,
1021         .init           = &omap2_init_clksel_parent,
1022         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1023         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1024         .clksel         = div2_core_clksel,
1025         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1026                                 PARENT_CONTROLS_CLOCK,
1027         .recalc         = &omap2_clksel_recalc,
1028 };
1029
1030 /*
1031  * MPU clksel:
1032  * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
1033  * derives from the high-frequency bypass clock originating from DPLL3,
1034  * called 'dpll1_fck'
1035  */
1036 static const struct clksel mpu_clksel[] = {
1037         { .parent = &dpll1_fck,     .rates = dpll_bypass_rates },
1038         { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1039         { .parent = NULL }
1040 };
1041
1042 static struct clk mpu_ck = {
1043         .name           = "mpu_ck",
1044         .parent         = &dpll1_x2m2_ck,
1045         .init           = &omap2_init_clksel_parent,
1046         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1047         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1048         .clksel         = mpu_clksel,
1049         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1050                                 PARENT_CONTROLS_CLOCK,
1051         .clkdm_name     = "mpu_clkdm",
1052         .recalc         = &omap2_clksel_recalc,
1053 };
1054
1055 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1056 static const struct clksel_rate arm_fck_rates[] = {
1057         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1058         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1059         { .div = 0 },
1060 };
1061
1062 static const struct clksel arm_fck_clksel[] = {
1063         { .parent = &mpu_ck, .rates = arm_fck_rates },
1064         { .parent = NULL }
1065 };
1066
1067 static struct clk arm_fck = {
1068         .name           = "arm_fck",
1069         .parent         = &mpu_ck,
1070         .init           = &omap2_init_clksel_parent,
1071         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1072         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1073         .clksel         = arm_fck_clksel,
1074         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1075                                 PARENT_CONTROLS_CLOCK,
1076         .recalc         = &omap2_clksel_recalc,
1077 };
1078
1079 /* XXX What about neon_clkdm ? */
1080
1081 /*
1082  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1083  * although it is referenced - so this is a guess
1084  */
1085 static struct clk emu_mpu_alwon_ck = {
1086         .name           = "emu_mpu_alwon_ck",
1087         .parent         = &mpu_ck,
1088         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1089                                 PARENT_CONTROLS_CLOCK,
1090         .recalc         = &followparent_recalc,
1091 };
1092
1093 static struct clk dpll2_fck = {
1094         .name           = "dpll2_fck",
1095         .parent         = &core_ck,
1096         .init           = &omap2_init_clksel_parent,
1097         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1098         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1099         .clksel         = div2_core_clksel,
1100         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1101                                 PARENT_CONTROLS_CLOCK,
1102         .recalc         = &omap2_clksel_recalc,
1103 };
1104
1105 /*
1106  * IVA2 clksel:
1107  * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1108  * derives from the high-frequency bypass clock originating from DPLL3,
1109  * called 'dpll2_fck'
1110  */
1111
1112 static const struct clksel iva2_clksel[] = {
1113         { .parent = &dpll2_fck,   .rates = dpll_bypass_rates },
1114         { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1115         { .parent = NULL }
1116 };
1117
1118 static struct clk iva2_ck = {
1119         .name           = "iva2_ck",
1120         .parent         = &dpll2_m2_ck,
1121         .init           = &omap2_init_clksel_parent,
1122         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1123         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1124         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
1125                                           OMAP3430_CM_IDLEST_PLL),
1126         .clksel_mask    = OMAP3430_ST_IVA2_CLK_MASK,
1127         .clksel         = iva2_clksel,
1128         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1129         .clkdm_name     = "iva2_clkdm",
1130         .recalc         = &omap2_clksel_recalc,
1131 };
1132
1133 /* Common interface clocks */
1134
1135 static struct clk l3_ick = {
1136         .name           = "l3_ick",
1137         .parent         = &core_ck,
1138         .init           = &omap2_init_clksel_parent,
1139         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1140         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1141         .clksel         = div2_core_clksel,
1142         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1143                                 PARENT_CONTROLS_CLOCK,
1144         .clkdm_name     = "core_l3_clkdm",
1145         .recalc         = &omap2_clksel_recalc,
1146 };
1147
1148 static const struct clksel div2_l3_clksel[] = {
1149         { .parent = &l3_ick, .rates = div2_rates },
1150         { .parent = NULL }
1151 };
1152
1153 static struct clk l4_ick = {
1154         .name           = "l4_ick",
1155         .parent         = &l3_ick,
1156         .init           = &omap2_init_clksel_parent,
1157         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1158         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1159         .clksel         = div2_l3_clksel,
1160         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1161                                 PARENT_CONTROLS_CLOCK,
1162         .clkdm_name     = "core_l4_clkdm",
1163         .recalc         = &omap2_clksel_recalc,
1164
1165 };
1166
1167 static const struct clksel div2_l4_clksel[] = {
1168         { .parent = &l4_ick, .rates = div2_rates },
1169         { .parent = NULL }
1170 };
1171
1172 static struct clk rm_ick = {
1173         .name           = "rm_ick",
1174         .parent         = &l4_ick,
1175         .init           = &omap2_init_clksel_parent,
1176         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1177         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1178         .clksel         = div2_l4_clksel,
1179         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1180         .recalc         = &omap2_clksel_recalc,
1181 };
1182
1183 /* GFX power domain */
1184
1185 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1186
1187 static const struct clksel gfx_l3_clksel[] = {
1188         { .parent = &l3_ick, .rates = gfx_l3_rates },
1189         { .parent = NULL }
1190 };
1191
1192 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1193 static struct clk gfx_l3_ck = {
1194         .name           = "gfx_l3_ck",
1195         .parent         = &l3_ick,
1196         .init           = &omap2_init_clksel_parent,
1197         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1198         .enable_bit     = OMAP_EN_GFX_SHIFT,
1199         .flags          = CLOCK_IN_OMAP3430ES1,
1200         .recalc         = &followparent_recalc,
1201 };
1202
1203 static struct clk gfx_l3_fck = {
1204         .name           = "gfx_l3_fck",
1205         .parent         = &gfx_l3_ck,
1206         .init           = &omap2_init_clksel_parent,
1207         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1208         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1209         .clksel         = gfx_l3_clksel,
1210         .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
1211                                 PARENT_CONTROLS_CLOCK,
1212         .clkdm_name     = "gfx_3430es1_clkdm",
1213         .recalc         = &omap2_clksel_recalc,
1214 };
1215
1216 static struct clk gfx_l3_ick = {
1217         .name           = "gfx_l3_ick",
1218         .parent         = &gfx_l3_ck,
1219         .flags          = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1220         .clkdm_name     = "gfx_3430es1_clkdm",
1221         .recalc         = &followparent_recalc,
1222 };
1223
1224 static struct clk gfx_cg1_ck = {
1225         .name           = "gfx_cg1_ck",
1226         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1227         .init           = &omap2_init_clk_clkdm,
1228         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1229         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1230         .flags          = CLOCK_IN_OMAP3430ES1,
1231         .clkdm_name     = "gfx_3430es1_clkdm",
1232         .recalc         = &followparent_recalc,
1233 };
1234
1235 static struct clk gfx_cg2_ck = {
1236         .name           = "gfx_cg2_ck",
1237         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1238         .init           = &omap2_init_clk_clkdm,
1239         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1240         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1241         .flags          = CLOCK_IN_OMAP3430ES1,
1242         .clkdm_name     = "gfx_3430es1_clkdm",
1243         .recalc         = &followparent_recalc,
1244 };
1245
1246 /* SGX power domain - 3430ES2 only */
1247
1248 static const struct clksel_rate sgx_core_rates[] = {
1249         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1250         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1251         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1252         { .div = 0 },
1253 };
1254
1255 static const struct clksel_rate sgx_96m_rates[] = {
1256         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1257         { .div = 0 },
1258 };
1259
1260 static const struct clksel sgx_clksel[] = {
1261         { .parent = &core_ck,    .rates = sgx_core_rates },
1262         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1263         { .parent = NULL },
1264 };
1265
1266 static struct clk sgx_fck = {
1267         .name           = "sgx_fck",
1268         .init           = &omap2_init_clksel_parent,
1269         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1270         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1271         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1272         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1273         .clksel         = sgx_clksel,
1274         .flags          = CLOCK_IN_OMAP3430ES2,
1275         .clkdm_name     = "sgx_clkdm",
1276         .recalc         = &omap2_clksel_recalc,
1277 };
1278
1279 static struct clk sgx_ick = {
1280         .name           = "sgx_ick",
1281         .parent         = &l3_ick,
1282         .init           = &omap2_init_clk_clkdm,
1283         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1284         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1285         .flags          = CLOCK_IN_OMAP3430ES2,
1286         .clkdm_name     = "sgx_clkdm",
1287         .recalc         = &followparent_recalc,
1288 };
1289
1290 /* CORE power domain */
1291
1292 static struct clk d2d_26m_fck = {
1293         .name           = "d2d_26m_fck",
1294         .parent         = &sys_ck,
1295         .init           = &omap2_init_clk_clkdm,
1296         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1297         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1298         .flags          = CLOCK_IN_OMAP3430ES1,
1299         .clkdm_name     = "d2d_clkdm",
1300         .recalc         = &followparent_recalc,
1301 };
1302
1303 static const struct clksel omap343x_gpt_clksel[] = {
1304         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1305         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1306         { .parent = NULL}
1307 };
1308
1309 static struct clk gpt10_fck = {
1310         .name           = "gpt10_fck",
1311         .parent         = &sys_ck,
1312         .init           = &omap2_init_clksel_parent,
1313         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1314         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1315         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1316         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1317         .clksel         = omap343x_gpt_clksel,
1318         .flags          = CLOCK_IN_OMAP343X,
1319         .clkdm_name     = "core_l4_clkdm",
1320         .recalc         = &omap2_clksel_recalc,
1321 };
1322
1323 static struct clk gpt11_fck = {
1324         .name           = "gpt11_fck",
1325         .parent         = &sys_ck,
1326         .init           = &omap2_init_clksel_parent,
1327         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1328         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1329         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1330         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1331         .clksel         = omap343x_gpt_clksel,
1332         .flags          = CLOCK_IN_OMAP343X,
1333         .clkdm_name     = "core_l4_clkdm",
1334         .recalc         = &omap2_clksel_recalc,
1335 };
1336
1337 static struct clk cpefuse_fck = {
1338         .name           = "cpefuse_fck",
1339         .parent         = &sys_ck,
1340         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1341         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1342         .flags          = CLOCK_IN_OMAP3430ES2,
1343         .recalc         = &followparent_recalc,
1344 };
1345
1346 static struct clk ts_fck = {
1347         .name           = "ts_fck",
1348         .parent         = &omap_32k_fck,
1349         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1350         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1351         .flags          = CLOCK_IN_OMAP3430ES2,
1352         .recalc         = &followparent_recalc,
1353 };
1354
1355 static struct clk usbtll_fck = {
1356         .name           = "usbtll_fck",
1357         .parent         = &omap_120m_fck,
1358         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1359         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1360         .flags          = CLOCK_IN_OMAP3430ES2,
1361         .recalc         = &followparent_recalc,
1362 };
1363
1364 /* CORE 96M FCLK-derived clocks */
1365
1366 static struct clk core_96m_fck = {
1367         .name           = "core_96m_fck",
1368         .parent         = &omap_96m_fck,
1369         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1370                                 PARENT_CONTROLS_CLOCK,
1371         .clkdm_name     = "core_l4_clkdm",
1372         .recalc         = &followparent_recalc,
1373 };
1374
1375 static struct clk mmchs3_fck = {
1376         .name           = "mmchs_fck",
1377         .id             = 3,
1378         .parent         = &core_96m_fck,
1379         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1380         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1381         .flags          = CLOCK_IN_OMAP3430ES2,
1382         .clkdm_name     = "core_l4_clkdm",
1383         .recalc         = &followparent_recalc,
1384 };
1385
1386 static struct clk mmchs2_fck = {
1387         .name           = "mmchs_fck",
1388         .id             = 2,
1389         .parent         = &core_96m_fck,
1390         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1391         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1392         .flags          = CLOCK_IN_OMAP343X,
1393         .clkdm_name     = "core_l4_clkdm",
1394         .recalc         = &followparent_recalc,
1395 };
1396
1397 static struct clk mspro_fck = {
1398         .name           = "mspro_fck",
1399         .parent         = &core_96m_fck,
1400         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1401         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1402         .flags          = CLOCK_IN_OMAP343X,
1403         .clkdm_name     = "core_l4_clkdm",
1404         .recalc         = &followparent_recalc,
1405 };
1406
1407 static struct clk mmchs1_fck = {
1408         .name           = "mmchs_fck",
1409         .id             = 1,
1410         .parent         = &core_96m_fck,
1411         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1412         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1413         .flags          = CLOCK_IN_OMAP343X,
1414         .clkdm_name     = "core_l4_clkdm",
1415         .recalc         = &followparent_recalc,
1416 };
1417
1418 static struct clk i2c3_fck = {
1419         .name           = "i2c_fck",
1420         .id             = 3,
1421         .parent         = &core_96m_fck,
1422         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1423         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1424         .flags          = CLOCK_IN_OMAP343X,
1425         .clkdm_name     = "core_l4_clkdm",
1426         .recalc         = &followparent_recalc,
1427 };
1428
1429 static struct clk i2c2_fck = {
1430         .name           = "i2c_fck",
1431         .id             = 2,
1432         .parent         = &core_96m_fck,
1433         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1434         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1435         .flags          = CLOCK_IN_OMAP343X,
1436         .clkdm_name     = "core_l4_clkdm",
1437         .recalc         = &followparent_recalc,
1438 };
1439
1440 static struct clk i2c1_fck = {
1441         .name           = "i2c_fck",
1442         .id             = 1,
1443         .parent         = &core_96m_fck,
1444         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1445         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1446         .flags          = CLOCK_IN_OMAP343X,
1447         .clkdm_name     = "core_l4_clkdm",
1448         .recalc         = &followparent_recalc,
1449 };
1450
1451 /*
1452  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1453  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1454  */
1455 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1456         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1457         { .div = 0 }
1458 };
1459
1460 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1461         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1462         { .div = 0 }
1463 };
1464
1465 static const struct clksel mcbsp_15_clksel[] = {
1466         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1467         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1468         { .parent = NULL }
1469 };
1470
1471 static struct clk mcbsp5_fck = {
1472         .name           = "mcbsp_fck",
1473         .id             = 5,
1474         .init           = &omap2_init_clksel_parent,
1475         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1476         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1477         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1478         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1479         .clksel         = mcbsp_15_clksel,
1480         .flags          = CLOCK_IN_OMAP343X,
1481         .clkdm_name     = "core_l4_clkdm",
1482         .recalc         = &omap2_clksel_recalc,
1483 };
1484
1485 static struct clk mcbsp1_fck = {
1486         .name           = "mcbsp_fck",
1487         .id             = 1,
1488         .init           = &omap2_init_clksel_parent,
1489         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1490         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1491         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1492         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1493         .clksel         = mcbsp_15_clksel,
1494         .flags          = CLOCK_IN_OMAP343X,
1495         .clkdm_name     = "core_l4_clkdm",
1496         .recalc         = &omap2_clksel_recalc,
1497 };
1498
1499 /* CORE_48M_FCK-derived clocks */
1500
1501 static struct clk core_48m_fck = {
1502         .name           = "core_48m_fck",
1503         .parent         = &omap_48m_fck,
1504         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1505                                 PARENT_CONTROLS_CLOCK,
1506         .clkdm_name     = "core_l4_clkdm",
1507         .recalc         = &followparent_recalc,
1508 };
1509
1510 static struct clk mcspi4_fck = {
1511         .name           = "mcspi_fck",
1512         .id             = 4,
1513         .parent         = &core_48m_fck,
1514         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1515         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1516         .flags          = CLOCK_IN_OMAP343X,
1517         .recalc         = &followparent_recalc,
1518 };
1519
1520 static struct clk mcspi3_fck = {
1521         .name           = "mcspi_fck",
1522         .id             = 3,
1523         .parent         = &core_48m_fck,
1524         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1525         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1526         .flags          = CLOCK_IN_OMAP343X,
1527         .recalc         = &followparent_recalc,
1528 };
1529
1530 static struct clk mcspi2_fck = {
1531         .name           = "mcspi_fck",
1532         .id             = 2,
1533         .parent         = &core_48m_fck,
1534         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1535         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1536         .flags          = CLOCK_IN_OMAP343X,
1537         .recalc         = &followparent_recalc,
1538 };
1539
1540 static struct clk mcspi1_fck = {
1541         .name           = "mcspi_fck",
1542         .id             = 1,
1543         .parent         = &core_48m_fck,
1544         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1545         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1546         .flags          = CLOCK_IN_OMAP343X,
1547         .recalc         = &followparent_recalc,
1548 };
1549
1550 static struct clk uart2_fck = {
1551         .name           = "uart2_fck",
1552         .parent         = &core_48m_fck,
1553         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1554         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1555         .flags          = CLOCK_IN_OMAP343X,
1556         .recalc         = &followparent_recalc,
1557 };
1558
1559 static struct clk uart1_fck = {
1560         .name           = "uart1_fck",
1561         .parent         = &core_48m_fck,
1562         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1563         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1564         .flags          = CLOCK_IN_OMAP343X,
1565         .recalc         = &followparent_recalc,
1566 };
1567
1568 static struct clk fshostusb_fck = {
1569         .name           = "fshostusb_fck",
1570         .parent         = &core_48m_fck,
1571         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1572         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1573         .flags          = CLOCK_IN_OMAP3430ES1,
1574         .recalc         = &followparent_recalc,
1575 };
1576
1577 /* CORE_12M_FCK based clocks */
1578
1579 static struct clk core_12m_fck = {
1580         .name           = "core_12m_fck",
1581         .parent         = &omap_12m_fck,
1582         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1583                                 PARENT_CONTROLS_CLOCK,
1584         .clkdm_name     = "core_l4_clkdm",
1585         .recalc         = &followparent_recalc,
1586 };
1587
1588 static struct clk hdq_fck = {
1589         .name           = "hdq_fck",
1590         .parent         = &core_12m_fck,
1591         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1592         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1593         .flags          = CLOCK_IN_OMAP343X,
1594         .recalc         = &followparent_recalc,
1595 };
1596
1597 /* DPLL3-derived clock */
1598
1599 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1600         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1601         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1602         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1603         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1604         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1605         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1606         { .div = 0 }
1607 };
1608
1609 static const struct clksel ssi_ssr_clksel[] = {
1610         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1611         { .parent = NULL }
1612 };
1613
1614 static struct clk ssi_ssr_fck = {
1615         .name           = "ssi_ssr_fck",
1616         .init           = &omap2_init_clksel_parent,
1617         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1618         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1619         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1620         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1621         .clksel         = ssi_ssr_clksel,
1622         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1623         .clkdm_name     = "core_l4_clkdm",
1624         .recalc         = &omap2_clksel_recalc,
1625 };
1626
1627 static struct clk ssi_sst_fck = {
1628         .name           = "ssi_sst_fck",
1629         .parent         = &ssi_ssr_fck,
1630         .fixed_div      = 2,
1631         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1632         .recalc         = &omap2_fixed_divisor_recalc,
1633 };
1634
1635
1636
1637 /* CORE_L3_ICK based clocks */
1638
1639 /*
1640  * XXX must add clk_enable/clk_disable for these if standard code won't
1641  * handle it
1642  */
1643 static struct clk core_l3_ick = {
1644         .name           = "core_l3_ick",
1645         .parent         = &l3_ick,
1646         .init           = &omap2_init_clk_clkdm,
1647         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1648                                 PARENT_CONTROLS_CLOCK,
1649         .clkdm_name     = "core_l3_clkdm",
1650         .recalc         = &followparent_recalc,
1651 };
1652
1653 static struct clk hsotgusb_ick = {
1654         .name           = "hsotgusb_ick",
1655         .parent         = &core_l3_ick,
1656         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1657         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1658         .flags          = CLOCK_IN_OMAP343X,
1659         .clkdm_name     = "core_l3_clkdm",
1660         .recalc         = &followparent_recalc,
1661 };
1662
1663 static struct clk sdrc_ick = {
1664         .name           = "sdrc_ick",
1665         .parent         = &core_l3_ick,
1666         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1667         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1668         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1669         .clkdm_name     = "core_l3_clkdm",
1670         .recalc         = &followparent_recalc,
1671 };
1672
1673 static struct clk gpmc_fck = {
1674         .name           = "gpmc_fck",
1675         .parent         = &core_l3_ick,
1676         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1677                                 ENABLE_ON_INIT,
1678         .clkdm_name     = "core_l3_clkdm",
1679         .recalc         = &followparent_recalc,
1680 };
1681
1682 /* SECURITY_L3_ICK based clocks */
1683
1684 static struct clk security_l3_ick = {
1685         .name           = "security_l3_ick",
1686         .parent         = &l3_ick,
1687         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1688                                 PARENT_CONTROLS_CLOCK,
1689         .recalc         = &followparent_recalc,
1690 };
1691
1692 static struct clk pka_ick = {
1693         .name           = "pka_ick",
1694         .parent         = &security_l3_ick,
1695         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1696         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1697         .flags          = CLOCK_IN_OMAP343X,
1698         .recalc         = &followparent_recalc,
1699 };
1700
1701 /* CORE_L4_ICK based clocks */
1702
1703 static struct clk core_l4_ick = {
1704         .name           = "core_l4_ick",
1705         .parent         = &l4_ick,
1706         .init           = &omap2_init_clk_clkdm,
1707         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1708                                 PARENT_CONTROLS_CLOCK,
1709         .clkdm_name     = "core_l4_clkdm",
1710         .recalc         = &followparent_recalc,
1711 };
1712
1713 static struct clk usbtll_ick = {
1714         .name           = "usbtll_ick",
1715         .parent         = &core_l4_ick,
1716         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1717         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1718         .flags          = CLOCK_IN_OMAP3430ES2,
1719         .clkdm_name     = "core_l4_clkdm",
1720         .recalc         = &followparent_recalc,
1721 };
1722
1723 static struct clk mmchs3_ick = {
1724         .name           = "mmchs_ick",
1725         .id             = 3,
1726         .parent         = &core_l4_ick,
1727         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1728         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1729         .flags          = CLOCK_IN_OMAP3430ES2,
1730         .clkdm_name     = "core_l4_clkdm",
1731         .recalc         = &followparent_recalc,
1732 };
1733
1734 /* Intersystem Communication Registers - chassis mode only */
1735 static struct clk icr_ick = {
1736         .name           = "icr_ick",
1737         .parent         = &core_l4_ick,
1738         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1739         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1740         .flags          = CLOCK_IN_OMAP343X,
1741         .clkdm_name     = "core_l4_clkdm",
1742         .recalc         = &followparent_recalc,
1743 };
1744
1745 static struct clk aes2_ick = {
1746         .name           = "aes2_ick",
1747         .parent         = &core_l4_ick,
1748         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1749         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1750         .flags          = CLOCK_IN_OMAP343X,
1751         .clkdm_name     = "core_l4_clkdm",
1752         .recalc         = &followparent_recalc,
1753 };
1754
1755 static struct clk sha12_ick = {
1756         .name           = "sha12_ick",
1757         .parent         = &core_l4_ick,
1758         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1759         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1760         .flags          = CLOCK_IN_OMAP343X,
1761         .clkdm_name     = "core_l4_clkdm",
1762         .recalc         = &followparent_recalc,
1763 };
1764
1765 static struct clk des2_ick = {
1766         .name           = "des2_ick",
1767         .parent         = &core_l4_ick,
1768         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1769         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1770         .flags          = CLOCK_IN_OMAP343X,
1771         .clkdm_name     = "core_l4_clkdm",
1772         .recalc         = &followparent_recalc,
1773 };
1774
1775 static struct clk mmchs2_ick = {
1776         .name           = "mmchs_ick",
1777         .id             = 2,
1778         .parent         = &core_l4_ick,
1779         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1780         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1781         .flags          = CLOCK_IN_OMAP343X,
1782         .clkdm_name     = "core_l4_clkdm",
1783         .recalc         = &followparent_recalc,
1784 };
1785
1786 static struct clk mmchs1_ick = {
1787         .name           = "mmchs_ick",
1788         .id             = 1,
1789         .parent         = &core_l4_ick,
1790         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1791         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1792         .flags          = CLOCK_IN_OMAP343X,
1793         .clkdm_name     = "core_l4_clkdm",
1794         .recalc         = &followparent_recalc,
1795 };
1796
1797 static struct clk mspro_ick = {
1798         .name           = "mspro_ick",
1799         .parent         = &core_l4_ick,
1800         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1801         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1802         .flags          = CLOCK_IN_OMAP343X,
1803         .clkdm_name     = "core_l4_clkdm",
1804         .recalc         = &followparent_recalc,
1805 };
1806
1807 static struct clk hdq_ick = {
1808         .name           = "hdq_ick",
1809         .parent         = &core_l4_ick,
1810         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1811         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1812         .flags          = CLOCK_IN_OMAP343X,
1813         .clkdm_name     = "core_l4_clkdm",
1814         .recalc         = &followparent_recalc,
1815 };
1816
1817 static struct clk mcspi4_ick = {
1818         .name           = "mcspi_ick",
1819         .id             = 4,
1820         .parent         = &core_l4_ick,
1821         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1822         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1823         .flags          = CLOCK_IN_OMAP343X,
1824         .clkdm_name     = "core_l4_clkdm",
1825         .recalc         = &followparent_recalc,
1826 };
1827
1828 static struct clk mcspi3_ick = {
1829         .name           = "mcspi_ick",
1830         .id             = 3,
1831         .parent         = &core_l4_ick,
1832         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1833         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1834         .flags          = CLOCK_IN_OMAP343X,
1835         .clkdm_name     = "core_l4_clkdm",
1836         .recalc         = &followparent_recalc,
1837 };
1838
1839 static struct clk mcspi2_ick = {
1840         .name           = "mcspi_ick",
1841         .id             = 2,
1842         .parent         = &core_l4_ick,
1843         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1844         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1845         .flags          = CLOCK_IN_OMAP343X,
1846         .clkdm_name     = "core_l4_clkdm",
1847         .recalc         = &followparent_recalc,
1848 };
1849
1850 static struct clk mcspi1_ick = {
1851         .name           = "mcspi_ick",
1852         .id             = 1,
1853         .parent         = &core_l4_ick,
1854         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1855         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1856         .flags          = CLOCK_IN_OMAP343X,
1857         .clkdm_name     = "core_l4_clkdm",
1858         .recalc         = &followparent_recalc,
1859 };
1860
1861 static struct clk i2c3_ick = {
1862         .name           = "i2c_ick",
1863         .id             = 3,
1864         .parent         = &core_l4_ick,
1865         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1866         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1867         .flags          = CLOCK_IN_OMAP343X,
1868         .clkdm_name     = "core_l4_clkdm",
1869         .recalc         = &followparent_recalc,
1870 };
1871
1872 static struct clk i2c2_ick = {
1873         .name           = "i2c_ick",
1874         .id             = 2,
1875         .parent         = &core_l4_ick,
1876         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1877         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1878         .flags          = CLOCK_IN_OMAP343X,
1879         .clkdm_name     = "core_l4_clkdm",
1880         .recalc         = &followparent_recalc,
1881 };
1882
1883 static struct clk i2c1_ick = {
1884         .name           = "i2c_ick",
1885         .id             = 1,
1886         .parent         = &core_l4_ick,
1887         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1888         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1889         .flags          = CLOCK_IN_OMAP343X,
1890         .clkdm_name     = "core_l4_clkdm",
1891         .recalc         = &followparent_recalc,
1892 };
1893
1894 static struct clk uart2_ick = {
1895         .name           = "uart2_ick",
1896         .parent         = &core_l4_ick,
1897         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1898         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1899         .flags          = CLOCK_IN_OMAP343X,
1900         .clkdm_name     = "core_l4_clkdm",
1901         .recalc         = &followparent_recalc,
1902 };
1903
1904 static struct clk uart1_ick = {
1905         .name           = "uart1_ick",
1906         .parent         = &core_l4_ick,
1907         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1908         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1909         .flags          = CLOCK_IN_OMAP343X,
1910         .clkdm_name     = "core_l4_clkdm",
1911         .recalc         = &followparent_recalc,
1912 };
1913
1914 static struct clk gpt11_ick = {
1915         .name           = "gpt11_ick",
1916         .parent         = &core_l4_ick,
1917         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1918         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1919         .flags          = CLOCK_IN_OMAP343X,
1920         .clkdm_name     = "core_l4_clkdm",
1921         .recalc         = &followparent_recalc,
1922 };
1923
1924 static struct clk gpt10_ick = {
1925         .name           = "gpt10_ick",
1926         .parent         = &core_l4_ick,
1927         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1928         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1929         .flags          = CLOCK_IN_OMAP343X,
1930         .clkdm_name     = "core_l4_clkdm",
1931         .recalc         = &followparent_recalc,
1932 };
1933
1934 static struct clk mcbsp5_ick = {
1935         .name           = "mcbsp_ick",
1936         .id             = 5,
1937         .parent         = &core_l4_ick,
1938         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1939         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1940         .flags          = CLOCK_IN_OMAP343X,
1941         .clkdm_name     = "core_l4_clkdm",
1942         .recalc         = &followparent_recalc,
1943 };
1944
1945 static struct clk mcbsp1_ick = {
1946         .name           = "mcbsp_ick",
1947         .id             = 1,
1948         .parent         = &core_l4_ick,
1949         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1950         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1951         .flags          = CLOCK_IN_OMAP343X,
1952         .clkdm_name     = "core_l4_clkdm",
1953         .recalc         = &followparent_recalc,
1954 };
1955
1956 static struct clk fac_ick = {
1957         .name           = "fac_ick",
1958         .parent         = &core_l4_ick,
1959         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1960         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
1961         .flags          = CLOCK_IN_OMAP3430ES1,
1962         .clkdm_name     = "core_l4_clkdm",
1963         .recalc         = &followparent_recalc,
1964 };
1965
1966 static struct clk mailboxes_ick = {
1967         .name           = "mailboxes_ick",
1968         .parent         = &core_l4_ick,
1969         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1970         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
1971         .flags          = CLOCK_IN_OMAP343X,
1972         .clkdm_name     = "core_l4_clkdm",
1973         .recalc         = &followparent_recalc,
1974 };
1975
1976 static struct clk omapctrl_ick = {
1977         .name           = "omapctrl_ick",
1978         .parent         = &core_l4_ick,
1979         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1980         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
1981         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1982         .recalc         = &followparent_recalc,
1983 };
1984
1985 /* SSI_L4_ICK based clocks */
1986
1987 static struct clk ssi_l4_ick = {
1988         .name           = "ssi_l4_ick",
1989         .parent         = &l4_ick,
1990         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1991                                 PARENT_CONTROLS_CLOCK,
1992         .clkdm_name     = "core_l4_clkdm",
1993         .recalc         = &followparent_recalc,
1994 };
1995
1996 static struct clk ssi_ick = {
1997         .name           = "ssi_ick",
1998         .parent         = &ssi_l4_ick,
1999         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2000         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2001         .flags          = CLOCK_IN_OMAP343X,
2002         .clkdm_name     = "core_l4_clkdm",
2003         .recalc         = &followparent_recalc,
2004 };
2005
2006 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2007  * but l4_ick makes more sense to me */
2008
2009 static const struct clksel usb_l4_clksel[] = {
2010         { .parent = &l4_ick, .rates = div2_rates },
2011         { .parent = NULL },
2012 };
2013
2014 static struct clk usb_l4_ick = {
2015         .name           = "usb_l4_ick",
2016         .parent         = &l4_ick,
2017         .init           = &omap2_init_clksel_parent,
2018         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2019         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2020         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2021         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2022         .clksel         = usb_l4_clksel,
2023         .flags          = CLOCK_IN_OMAP3430ES1,
2024         .recalc         = &omap2_clksel_recalc,
2025 };
2026
2027 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2028
2029 /* SECURITY_L4_ICK2 based clocks */
2030
2031 static struct clk security_l4_ick2 = {
2032         .name           = "security_l4_ick2",
2033         .parent         = &l4_ick,
2034         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2035                                 PARENT_CONTROLS_CLOCK,
2036         .recalc         = &followparent_recalc,
2037 };
2038
2039 static struct clk aes1_ick = {
2040         .name           = "aes1_ick",
2041         .parent         = &security_l4_ick2,
2042         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2043         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2044         .flags          = CLOCK_IN_OMAP343X,
2045         .recalc         = &followparent_recalc,
2046 };
2047
2048 static struct clk rng_ick = {
2049         .name           = "rng_ick",
2050         .parent         = &security_l4_ick2,
2051         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2052         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2053         .flags          = CLOCK_IN_OMAP343X,
2054         .recalc         = &followparent_recalc,
2055 };
2056
2057 static struct clk sha11_ick = {
2058         .name           = "sha11_ick",
2059         .parent         = &security_l4_ick2,
2060         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2061         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2062         .flags          = CLOCK_IN_OMAP343X,
2063         .recalc         = &followparent_recalc,
2064 };
2065
2066 static struct clk des1_ick = {
2067         .name           = "des1_ick",
2068         .parent         = &security_l4_ick2,
2069         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2070         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2071         .flags          = CLOCK_IN_OMAP343X,
2072         .recalc         = &followparent_recalc,
2073 };
2074
2075 /* DSS */
2076 static const struct clksel dss1_alwon_fck_clksel[] = {
2077         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2078         { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2079         { .parent = NULL }
2080 };
2081
2082 static struct clk dss1_alwon_fck = {
2083         .name           = "dss1_alwon_fck",
2084         .parent         = &dpll4_m4x2_ck,
2085         .init           = &omap2_init_clksel_parent,
2086         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2087         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2088         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2089         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2090         .clksel         = dss1_alwon_fck_clksel,
2091         .flags          = CLOCK_IN_OMAP343X,
2092         .clkdm_name     = "dss_clkdm",
2093         .recalc         = &omap2_clksel_recalc,
2094 };
2095
2096 static struct clk dss_tv_fck = {
2097         .name           = "dss_tv_fck",
2098         .parent         = &omap_54m_fck,
2099         .init           = &omap2_init_clk_clkdm,
2100         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2101         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2102         .flags          = CLOCK_IN_OMAP343X,
2103         .clkdm_name     = "dss_clkdm",
2104         .recalc         = &followparent_recalc,
2105 };
2106
2107 static struct clk dss_96m_fck = {
2108         .name           = "dss_96m_fck",
2109         .parent         = &omap_96m_fck,
2110         .init           = &omap2_init_clk_clkdm,
2111         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2112         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2113         .flags          = CLOCK_IN_OMAP343X,
2114         .clkdm_name     = "dss_clkdm",
2115         .recalc         = &followparent_recalc,
2116 };
2117
2118 static struct clk dss2_alwon_fck = {
2119         .name           = "dss2_alwon_fck",
2120         .parent         = &sys_ck,
2121         .init           = &omap2_init_clk_clkdm,
2122         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2123         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2124         .flags          = CLOCK_IN_OMAP343X,
2125         .clkdm_name     = "dss_clkdm",
2126         .recalc         = &followparent_recalc,
2127 };
2128
2129 static struct clk dss_ick = {
2130         /* Handles both L3 and L4 clocks */
2131         .name           = "dss_ick",
2132         .parent         = &l4_ick,
2133         .init           = &omap2_init_clk_clkdm,
2134         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2135         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2136         .flags          = CLOCK_IN_OMAP343X,
2137         .clkdm_name     = "dss_clkdm",
2138         .recalc         = &followparent_recalc,
2139 };
2140
2141 /* CAM */
2142
2143 static const struct clksel cam_mclk_clksel[] = {
2144         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2145         { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2146         { .parent = NULL }
2147 };
2148
2149 static struct clk cam_mclk = {
2150         .name           = "cam_mclk",
2151         .parent         = &dpll4_m5x2_ck,
2152         .init           = &omap2_init_clksel_parent,
2153         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2154         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2155         .clksel         = cam_mclk_clksel,
2156         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2157         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2158         .flags          = CLOCK_IN_OMAP343X,
2159         .clkdm_name     = "cam_clkdm",
2160         .recalc         = &omap2_clksel_recalc,
2161 };
2162
2163 static struct clk cam_ick = {
2164         /* Handles both L3 and L4 clocks */
2165         .name           = "cam_ick",
2166         .parent         = &l4_ick,
2167         .init           = &omap2_init_clk_clkdm,
2168         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2169         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2170         .flags          = CLOCK_IN_OMAP343X,
2171         .clkdm_name     = "cam_clkdm",
2172         .recalc         = &followparent_recalc,
2173 };
2174
2175 /* USBHOST - 3430ES2 only */
2176
2177 static struct clk usbhost_120m_fck = {
2178         .name           = "usbhost_120m_fck",
2179         .parent         = &omap_120m_fck,
2180         .init           = &omap2_init_clk_clkdm,
2181         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2182         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2183         .flags          = CLOCK_IN_OMAP3430ES2,
2184         .clkdm_name     = "usbhost_clkdm",
2185         .recalc         = &followparent_recalc,
2186 };
2187
2188 static struct clk usbhost_48m_fck = {
2189         .name           = "usbhost_48m_fck",
2190         .parent         = &omap_48m_fck,
2191         .init           = &omap2_init_clk_clkdm,
2192         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2193         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2194         .flags          = CLOCK_IN_OMAP3430ES2,
2195         .clkdm_name     = "usbhost_clkdm",
2196         .recalc         = &followparent_recalc,
2197 };
2198
2199 static struct clk usbhost_ick = {
2200         /* Handles both L3 and L4 clocks */
2201         .name           = "usbhost_ick",
2202         .parent         = &l4_ick,
2203         .init           = &omap2_init_clk_clkdm,
2204         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2205         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2206         .flags          = CLOCK_IN_OMAP3430ES2,
2207         .clkdm_name     = "usbhost_clkdm",
2208         .recalc         = &followparent_recalc,
2209 };
2210
2211 static struct clk usbhost_sar_fck = {
2212         .name           = "usbhost_sar_fck",
2213         .parent         = &osc_sys_ck,
2214         .init           = &omap2_init_clk_clkdm,
2215         .enable_reg     = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL),
2216         .enable_bit     = OMAP3430ES2_SAVEANDRESTORE_SHIFT,
2217         .flags          = CLOCK_IN_OMAP3430ES2,
2218         .clkdm_name     = "usbhost_clkdm",
2219         .recalc         = &followparent_recalc,
2220 };
2221
2222 /* WKUP */
2223
2224 static const struct clksel_rate usim_96m_rates[] = {
2225         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2226         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2227         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2228         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2229         { .div = 0 },
2230 };
2231
2232 static const struct clksel_rate usim_120m_rates[] = {
2233         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2234         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2235         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2236         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2237         { .div = 0 },
2238 };
2239
2240 static const struct clksel usim_clksel[] = {
2241         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2242         { .parent = &omap_120m_fck,     .rates = usim_120m_rates },
2243         { .parent = &sys_ck,            .rates = div2_rates },
2244         { .parent = NULL },
2245 };
2246
2247 /* 3430ES2 only */
2248 static struct clk usim_fck = {
2249         .name           = "usim_fck",
2250         .init           = &omap2_init_clksel_parent,
2251         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2252         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2253         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2254         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2255         .clksel         = usim_clksel,
2256         .flags          = CLOCK_IN_OMAP3430ES2,
2257         .recalc         = &omap2_clksel_recalc,
2258 };
2259
2260 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2261 static struct clk gpt1_fck = {
2262         .name           = "gpt1_fck",
2263         .init           = &omap2_init_clksel_parent,
2264         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2265         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2266         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2267         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2268         .clksel         = omap343x_gpt_clksel,
2269         .flags          = CLOCK_IN_OMAP343X,
2270         .clkdm_name     = "wkup_clkdm",
2271         .recalc         = &omap2_clksel_recalc,
2272 };
2273
2274 static struct clk wkup_32k_fck = {
2275         .name           = "wkup_32k_fck",
2276         .init           = &omap2_init_clk_clkdm,
2277         .parent         = &omap_32k_fck,
2278         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2279         .clkdm_name     = "wkup_clkdm",
2280         .recalc         = &followparent_recalc,
2281 };
2282
2283 static struct clk gpio1_fck = {
2284         .name           = "gpio1_fck",
2285         .parent         = &wkup_32k_fck,
2286         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2287         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2288         .flags          = CLOCK_IN_OMAP343X,
2289         .clkdm_name     = "wkup_clkdm",
2290         .recalc         = &followparent_recalc,
2291 };
2292
2293 static struct clk wdt2_fck = {
2294         .name           = "wdt2_fck",
2295         .parent         = &wkup_32k_fck,
2296         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2297         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2298         .flags          = CLOCK_IN_OMAP343X,
2299         .clkdm_name     = "wkup_clkdm",
2300         .recalc         = &followparent_recalc,
2301 };
2302
2303 static struct clk wkup_l4_ick = {
2304         .name           = "wkup_l4_ick",
2305         .parent         = &sys_ck,
2306         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2307         .clkdm_name     = "wkup_clkdm",
2308         .recalc         = &followparent_recalc,
2309 };
2310
2311 /* 3430ES2 only */
2312 /* Never specifically named in the TRM, so we have to infer a likely name */
2313 static struct clk usim_ick = {
2314         .name           = "usim_ick",
2315         .parent         = &wkup_l4_ick,
2316         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2317         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2318         .flags          = CLOCK_IN_OMAP3430ES2,
2319         .clkdm_name     = "wkup_clkdm",
2320         .recalc         = &followparent_recalc,
2321 };
2322
2323 static struct clk wdt2_ick = {
2324         .name           = "wdt2_ick",
2325         .parent         = &wkup_l4_ick,
2326         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2327         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2328         .flags          = CLOCK_IN_OMAP343X,
2329         .clkdm_name     = "wkup_clkdm",
2330         .recalc         = &followparent_recalc,
2331 };
2332
2333 static struct clk wdt1_ick = {
2334         .name           = "wdt1_ick",
2335         .parent         = &wkup_l4_ick,
2336         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2337         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2338         .flags          = CLOCK_IN_OMAP343X,
2339         .clkdm_name     = "wkup_clkdm",
2340         .recalc         = &followparent_recalc,
2341 };
2342
2343 static struct clk gpio1_ick = {
2344         .name           = "gpio1_ick",
2345         .parent         = &wkup_l4_ick,
2346         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2347         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2348         .flags          = CLOCK_IN_OMAP343X,
2349         .clkdm_name     = "wkup_clkdm",
2350         .recalc         = &followparent_recalc,
2351 };
2352
2353 static struct clk omap_32ksync_ick = {
2354         .name           = "omap_32ksync_ick",
2355         .parent         = &wkup_l4_ick,
2356         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2357         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2358         .flags          = CLOCK_IN_OMAP343X,
2359         .clkdm_name     = "wkup_clkdm",
2360         .recalc         = &followparent_recalc,
2361 };
2362
2363 /* XXX This clock no longer exists in 3430 TRM rev F */
2364 static struct clk gpt12_ick = {
2365         .name           = "gpt12_ick",
2366         .parent         = &wkup_l4_ick,
2367         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2368         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2369         .flags          = CLOCK_IN_OMAP343X,
2370         .clkdm_name     = "wkup_clkdm",
2371         .recalc         = &followparent_recalc,
2372 };
2373
2374 static struct clk gpt1_ick = {
2375         .name           = "gpt1_ick",
2376         .parent         = &wkup_l4_ick,
2377         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2378         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2379         .flags          = CLOCK_IN_OMAP343X,
2380         .clkdm_name     = "wkup_clkdm",
2381         .recalc         = &followparent_recalc,
2382 };
2383
2384
2385
2386 /* PER clock domain */
2387
2388 static struct clk per_96m_fck = {
2389         .name           = "per_96m_fck",
2390         .parent         = &omap_96m_alwon_fck,
2391         .init           = &omap2_init_clk_clkdm,
2392         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2393                                 PARENT_CONTROLS_CLOCK,
2394         .clkdm_name     = "per_clkdm",
2395         .recalc         = &followparent_recalc,
2396 };
2397
2398 static struct clk per_48m_fck = {
2399         .name           = "per_48m_fck",
2400         .parent         = &omap_48m_fck,
2401         .init           = &omap2_init_clk_clkdm,
2402         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2403                                 PARENT_CONTROLS_CLOCK,
2404         .clkdm_name     = "per_clkdm",
2405         .recalc         = &followparent_recalc,
2406 };
2407
2408 static struct clk uart3_fck = {
2409         .name           = "uart3_fck",
2410         .parent         = &per_48m_fck,
2411         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2412         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2413         .flags          = CLOCK_IN_OMAP343X,
2414         .clkdm_name     = "per_clkdm",
2415         .recalc         = &followparent_recalc,
2416 };
2417
2418 static struct clk gpt2_fck = {
2419         .name           = "gpt2_fck",
2420         .init           = &omap2_init_clksel_parent,
2421         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2422         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2423         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2424         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2425         .clksel         = omap343x_gpt_clksel,
2426         .flags          = CLOCK_IN_OMAP343X,
2427         .clkdm_name     = "per_clkdm",
2428         .recalc         = &omap2_clksel_recalc,
2429 };
2430
2431 static struct clk gpt3_fck = {
2432         .name           = "gpt3_fck",
2433         .init           = &omap2_init_clksel_parent,
2434         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2435         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2436         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2437         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2438         .clksel         = omap343x_gpt_clksel,
2439         .flags          = CLOCK_IN_OMAP343X,
2440         .clkdm_name     = "per_clkdm",
2441         .recalc         = &omap2_clksel_recalc,
2442 };
2443
2444 static struct clk gpt4_fck = {
2445         .name           = "gpt4_fck",
2446         .init           = &omap2_init_clksel_parent,
2447         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2448         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2449         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2450         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2451         .clksel         = omap343x_gpt_clksel,
2452         .flags          = CLOCK_IN_OMAP343X,
2453         .clkdm_name     = "per_clkdm",
2454         .recalc         = &omap2_clksel_recalc,
2455 };
2456
2457 static struct clk gpt5_fck = {
2458         .name           = "gpt5_fck",
2459         .init           = &omap2_init_clksel_parent,
2460         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2461         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2462         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2463         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2464         .clksel         = omap343x_gpt_clksel,
2465         .flags          = CLOCK_IN_OMAP343X,
2466         .clkdm_name     = "per_clkdm",
2467         .recalc         = &omap2_clksel_recalc,
2468 };
2469
2470 static struct clk gpt6_fck = {
2471         .name           = "gpt6_fck",
2472         .init           = &omap2_init_clksel_parent,
2473         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2474         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2475         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2476         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2477         .clksel         = omap343x_gpt_clksel,
2478         .flags          = CLOCK_IN_OMAP343X,
2479         .clkdm_name     = "per_clkdm",
2480         .recalc         = &omap2_clksel_recalc,
2481 };
2482
2483 static struct clk gpt7_fck = {
2484         .name           = "gpt7_fck",
2485         .init           = &omap2_init_clksel_parent,
2486         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2487         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2488         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2489         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2490         .clksel         = omap343x_gpt_clksel,
2491         .flags          = CLOCK_IN_OMAP343X,
2492         .clkdm_name     = "per_clkdm",
2493         .recalc         = &omap2_clksel_recalc,
2494 };
2495
2496 static struct clk gpt8_fck = {
2497         .name           = "gpt8_fck",
2498         .init           = &omap2_init_clksel_parent,
2499         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2500         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2501         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2502         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2503         .clksel         = omap343x_gpt_clksel,
2504         .flags          = CLOCK_IN_OMAP343X,
2505         .clkdm_name     = "per_clkdm",
2506         .recalc         = &omap2_clksel_recalc,
2507 };
2508
2509 static struct clk gpt9_fck = {
2510         .name           = "gpt9_fck",
2511         .init           = &omap2_init_clksel_parent,
2512         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2513         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2514         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2515         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2516         .clksel         = omap343x_gpt_clksel,
2517         .flags          = CLOCK_IN_OMAP343X,
2518         .clkdm_name     = "per_clkdm",
2519         .recalc         = &omap2_clksel_recalc,
2520 };
2521
2522 static struct clk per_32k_alwon_fck = {
2523         .name           = "per_32k_alwon_fck",
2524         .parent         = &omap_32k_fck,
2525         .clkdm_name     = "per_clkdm",
2526         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2527         .recalc         = &followparent_recalc,
2528 };
2529
2530 static struct clk gpio6_fck = {
2531         .name           = "gpio6_fck",
2532         .parent         = &per_32k_alwon_fck,
2533         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2534         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2535         .flags          = CLOCK_IN_OMAP343X,
2536         .clkdm_name     = "per_clkdm",
2537         .recalc         = &followparent_recalc,
2538 };
2539
2540 static struct clk gpio5_fck = {
2541         .name           = "gpio5_fck",
2542         .parent         = &per_32k_alwon_fck,
2543         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2544         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2545         .flags          = CLOCK_IN_OMAP343X,
2546         .clkdm_name     = "per_clkdm",
2547         .recalc         = &followparent_recalc,
2548 };
2549
2550 static struct clk gpio4_fck = {
2551         .name           = "gpio4_fck",
2552         .parent         = &per_32k_alwon_fck,
2553         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2554         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2555         .flags          = CLOCK_IN_OMAP343X,
2556         .clkdm_name     = "per_clkdm",
2557         .recalc         = &followparent_recalc,
2558 };
2559
2560 static struct clk gpio3_fck = {
2561         .name           = "gpio3_fck",
2562         .parent         = &per_32k_alwon_fck,
2563         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2564         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2565         .flags          = CLOCK_IN_OMAP343X,
2566         .clkdm_name     = "per_clkdm",
2567         .recalc         = &followparent_recalc,
2568 };
2569
2570 static struct clk gpio2_fck = {
2571         .name           = "gpio2_fck",
2572         .parent         = &per_32k_alwon_fck,
2573         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2574         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2575         .flags          = CLOCK_IN_OMAP343X,
2576         .clkdm_name     = "per_clkdm",
2577         .recalc         = &followparent_recalc,
2578 };
2579
2580 static struct clk wdt3_fck = {
2581         .name           = "wdt3_fck",
2582         .parent         = &per_32k_alwon_fck,
2583         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2584         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2585         .flags          = CLOCK_IN_OMAP343X,
2586         .clkdm_name     = "per_clkdm",
2587         .recalc         = &followparent_recalc,
2588 };
2589
2590 static struct clk per_l4_ick = {
2591         .name           = "per_l4_ick",
2592         .parent         = &l4_ick,
2593         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2594                                 PARENT_CONTROLS_CLOCK,
2595         .clkdm_name     = "per_clkdm",
2596         .recalc         = &followparent_recalc,
2597 };
2598
2599 static struct clk gpio6_ick = {
2600         .name           = "gpio6_ick",
2601         .parent         = &per_l4_ick,
2602         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2603         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2604         .flags          = CLOCK_IN_OMAP343X,
2605         .clkdm_name     = "per_clkdm",
2606         .recalc         = &followparent_recalc,
2607 };
2608
2609 static struct clk gpio5_ick = {
2610         .name           = "gpio5_ick",
2611         .parent         = &per_l4_ick,
2612         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2613         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2614         .flags          = CLOCK_IN_OMAP343X,
2615         .clkdm_name     = "per_clkdm",
2616         .recalc         = &followparent_recalc,
2617 };
2618
2619 static struct clk gpio4_ick = {
2620         .name           = "gpio4_ick",
2621         .parent         = &per_l4_ick,
2622         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2623         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2624         .flags          = CLOCK_IN_OMAP343X,
2625         .clkdm_name     = "per_clkdm",
2626         .recalc         = &followparent_recalc,
2627 };
2628
2629 static struct clk gpio3_ick = {
2630         .name           = "gpio3_ick",
2631         .parent         = &per_l4_ick,
2632         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2633         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2634         .flags          = CLOCK_IN_OMAP343X,
2635         .clkdm_name     = "per_clkdm",
2636         .recalc         = &followparent_recalc,
2637 };
2638
2639 static struct clk gpio2_ick = {
2640         .name           = "gpio2_ick",
2641         .parent         = &per_l4_ick,
2642         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2643         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2644         .flags          = CLOCK_IN_OMAP343X,
2645         .clkdm_name     = "per_clkdm",
2646         .recalc         = &followparent_recalc,
2647 };
2648
2649 static struct clk wdt3_ick = {
2650         .name           = "wdt3_ick",
2651         .parent         = &per_l4_ick,
2652         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2653         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2654         .flags          = CLOCK_IN_OMAP343X,
2655         .clkdm_name     = "per_clkdm",
2656         .recalc         = &followparent_recalc,
2657 };
2658
2659 static struct clk uart3_ick = {
2660         .name           = "uart3_ick",
2661         .parent         = &per_l4_ick,
2662         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2663         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2664         .flags          = CLOCK_IN_OMAP343X,
2665         .clkdm_name     = "per_clkdm",
2666         .recalc         = &followparent_recalc,
2667 };
2668
2669 static struct clk gpt9_ick = {
2670         .name           = "gpt9_ick",
2671         .parent         = &per_l4_ick,
2672         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2673         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2674         .flags          = CLOCK_IN_OMAP343X,
2675         .clkdm_name     = "per_clkdm",
2676         .recalc         = &followparent_recalc,
2677 };
2678
2679 static struct clk gpt8_ick = {
2680         .name           = "gpt8_ick",
2681         .parent         = &per_l4_ick,
2682         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2683         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2684         .flags          = CLOCK_IN_OMAP343X,
2685         .clkdm_name     = "per_clkdm",
2686         .recalc         = &followparent_recalc,
2687 };
2688
2689 static struct clk gpt7_ick = {
2690         .name           = "gpt7_ick",
2691         .parent         = &per_l4_ick,
2692         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2693         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2694         .flags          = CLOCK_IN_OMAP343X,
2695         .clkdm_name     = "per_clkdm",
2696         .recalc         = &followparent_recalc,
2697 };
2698
2699 static struct clk gpt6_ick = {
2700         .name           = "gpt6_ick",
2701         .parent         = &per_l4_ick,
2702         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2703         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2704         .flags          = CLOCK_IN_OMAP343X,
2705         .clkdm_name     = "per_clkdm",
2706         .recalc         = &followparent_recalc,
2707 };
2708
2709 static struct clk gpt5_ick = {
2710         .name           = "gpt5_ick",
2711         .parent         = &per_l4_ick,
2712         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2713         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2714         .flags          = CLOCK_IN_OMAP343X,
2715         .clkdm_name     = "per_clkdm",
2716         .recalc         = &followparent_recalc,
2717 };
2718
2719 static struct clk gpt4_ick = {
2720         .name           = "gpt4_ick",
2721         .parent         = &per_l4_ick,
2722         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2723         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2724         .flags          = CLOCK_IN_OMAP343X,
2725         .clkdm_name     = "per_clkdm",
2726         .recalc         = &followparent_recalc,
2727 };
2728
2729 static struct clk gpt3_ick = {
2730         .name           = "gpt3_ick",
2731         .parent         = &per_l4_ick,
2732         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2733         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2734         .flags          = CLOCK_IN_OMAP343X,
2735         .clkdm_name     = "per_clkdm",
2736         .recalc         = &followparent_recalc,
2737 };
2738
2739 static struct clk gpt2_ick = {
2740         .name           = "gpt2_ick",
2741         .parent         = &per_l4_ick,
2742         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2743         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2744         .flags          = CLOCK_IN_OMAP343X,
2745         .clkdm_name     = "per_clkdm",
2746         .recalc         = &followparent_recalc,
2747 };
2748
2749 static struct clk mcbsp2_ick = {
2750         .name           = "mcbsp_ick",
2751         .id             = 2,
2752         .parent         = &per_l4_ick,
2753         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2754         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2755         .flags          = CLOCK_IN_OMAP343X,
2756         .clkdm_name     = "per_clkdm",
2757         .recalc         = &followparent_recalc,
2758 };
2759
2760 static struct clk mcbsp3_ick = {
2761         .name           = "mcbsp_ick",
2762         .id             = 3,
2763         .parent         = &per_l4_ick,
2764         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2765         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2766         .flags          = CLOCK_IN_OMAP343X,
2767         .clkdm_name     = "per_clkdm",
2768         .recalc         = &followparent_recalc,
2769 };
2770
2771 static struct clk mcbsp4_ick = {
2772         .name           = "mcbsp_ick",
2773         .id             = 4,
2774         .parent         = &per_l4_ick,
2775         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2776         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2777         .flags          = CLOCK_IN_OMAP343X,
2778         .clkdm_name     = "per_clkdm",
2779         .recalc         = &followparent_recalc,
2780 };
2781
2782 static const struct clksel mcbsp_234_clksel[] = {
2783         { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2784         { .parent = &mcbsp_clks,  .rates = common_mcbsp_mcbsp_rates },
2785         { .parent = NULL }
2786 };
2787
2788 static struct clk mcbsp2_fck = {
2789         .name           = "mcbsp_fck",
2790         .id             = 2,
2791         .init           = &omap2_init_clksel_parent,
2792         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2793         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2794         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2795         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2796         .clksel         = mcbsp_234_clksel,
2797         .flags          = CLOCK_IN_OMAP343X,
2798         .clkdm_name     = "per_clkdm",
2799         .recalc         = &omap2_clksel_recalc,
2800 };
2801
2802 static struct clk mcbsp3_fck = {
2803         .name           = "mcbsp_fck",
2804         .id             = 3,
2805         .init           = &omap2_init_clksel_parent,
2806         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2807         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2808         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2809         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2810         .clksel         = mcbsp_234_clksel,
2811         .flags          = CLOCK_IN_OMAP343X,
2812         .clkdm_name     = "per_clkdm",
2813         .recalc         = &omap2_clksel_recalc,
2814 };
2815
2816 static struct clk mcbsp4_fck = {
2817         .name           = "mcbsp_fck",
2818         .id             = 4,
2819         .init           = &omap2_init_clksel_parent,
2820         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2821         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2822         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2823         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2824         .clksel         = mcbsp_234_clksel,
2825         .flags          = CLOCK_IN_OMAP343X,
2826         .clkdm_name     = "per_clkdm",
2827         .recalc         = &omap2_clksel_recalc,
2828 };
2829
2830 /* EMU clocks */
2831
2832 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2833
2834 static const struct clksel_rate emu_src_sys_rates[] = {
2835         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2836         { .div = 0 },
2837 };
2838
2839 static const struct clksel_rate emu_src_core_rates[] = {
2840         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2841         { .div = 0 },
2842 };
2843
2844 static const struct clksel_rate emu_src_per_rates[] = {
2845         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2846         { .div = 0 },
2847 };
2848
2849 static const struct clksel_rate emu_src_mpu_rates[] = {
2850         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2851         { .div = 0 },
2852 };
2853
2854 static const struct clksel emu_src_clksel[] = {
2855         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2856         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2857         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2858         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2859         { .parent = NULL },
2860 };
2861
2862 /*
2863  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2864  * to switch the source of some of the EMU clocks.
2865  * XXX Are there CLKEN bits for these EMU clks?
2866  */
2867 static struct clk emu_src_ck = {
2868         .name           = "emu_src_ck",
2869         .init           = &omap2_init_clksel_parent,
2870         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2871         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2872         .clksel         = emu_src_clksel,
2873         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2874         .clkdm_name     = "emu_clkdm",
2875         .recalc         = &omap2_clksel_recalc,
2876 };
2877
2878 static const struct clksel_rate pclk_emu_rates[] = {
2879         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2880         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2881         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2882         { .div = 6, .val = 6, .flags = RATE_IN_343X },
2883         { .div = 0 },
2884 };
2885
2886 static const struct clksel pclk_emu_clksel[] = {
2887         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2888         { .parent = NULL },
2889 };
2890
2891 static struct clk pclk_fck = {
2892         .name           = "pclk_fck",
2893         .init           = &omap2_init_clksel_parent,
2894         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2895         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
2896         .clksel         = pclk_emu_clksel,
2897         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2898         .clkdm_name     = "emu_clkdm",
2899         .recalc         = &omap2_clksel_recalc,
2900 };
2901
2902 static const struct clksel_rate pclkx2_emu_rates[] = {
2903         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2904         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2905         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2906         { .div = 0 },
2907 };
2908
2909 static const struct clksel pclkx2_emu_clksel[] = {
2910         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2911         { .parent = NULL },
2912 };
2913
2914 static struct clk pclkx2_fck = {
2915         .name           = "pclkx2_fck",
2916         .init           = &omap2_init_clksel_parent,
2917         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2918         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
2919         .clksel         = pclkx2_emu_clksel,
2920         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2921         .clkdm_name     = "emu_clkdm",
2922         .recalc         = &omap2_clksel_recalc,
2923 };
2924
2925 static const struct clksel atclk_emu_clksel[] = {
2926         { .parent = &emu_src_ck, .rates = div2_rates },
2927         { .parent = NULL },
2928 };
2929
2930 static struct clk atclk_fck = {
2931         .name           = "atclk_fck",
2932         .init           = &omap2_init_clksel_parent,
2933         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2934         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
2935         .clksel         = atclk_emu_clksel,
2936         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2937         .clkdm_name     = "emu_clkdm",
2938         .recalc         = &omap2_clksel_recalc,
2939 };
2940
2941 static struct clk traceclk_src_fck = {
2942         .name           = "traceclk_src_fck",
2943         .init           = &omap2_init_clksel_parent,
2944         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2945         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
2946         .clksel         = emu_src_clksel,
2947         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2948         .clkdm_name     = "emu_clkdm",
2949         .recalc         = &omap2_clksel_recalc,
2950 };
2951
2952 static const struct clksel_rate traceclk_rates[] = {
2953         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2954         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2955         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2956         { .div = 0 },
2957 };
2958
2959 static const struct clksel traceclk_clksel[] = {
2960         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2961         { .parent = NULL },
2962 };
2963
2964 static struct clk traceclk_fck = {
2965         .name           = "traceclk_fck",
2966         .init           = &omap2_init_clksel_parent,
2967         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2968         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
2969         .clksel         = traceclk_clksel,
2970         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2971         .clkdm_name     = "emu_clkdm",
2972         .recalc         = &omap2_clksel_recalc,
2973 };
2974
2975 /* SR clocks */
2976
2977 /* SmartReflex fclk (VDD1) */
2978 static struct clk sr1_fck = {
2979         .name           = "sr1_fck",
2980         .parent         = &sys_ck,
2981         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2982         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
2983         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2984         .recalc         = &followparent_recalc,
2985 };
2986
2987 /* SmartReflex fclk (VDD2) */
2988 static struct clk sr2_fck = {
2989         .name           = "sr2_fck",
2990         .parent         = &sys_ck,
2991         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2992         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
2993         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2994         .recalc         = &followparent_recalc,
2995 };
2996
2997 static struct clk sr_l4_ick = {
2998         .name           = "sr_l4_ick",
2999         .parent         = &l4_ick,
3000         .flags          = CLOCK_IN_OMAP343X,
3001         .clkdm_name     = "core_l4_clkdm",
3002         .recalc         = &followparent_recalc,
3003 };
3004
3005 /* SECURE_32K_FCK clocks */
3006
3007 /* XXX This clock no longer exists in 3430 TRM rev F */
3008 static struct clk gpt12_fck = {
3009         .name           = "gpt12_fck",
3010         .parent         = &secure_32k_fck,
3011         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3012         .recalc         = &followparent_recalc,
3013 };
3014
3015 static struct clk wdt1_fck = {
3016         .name           = "wdt1_fck",
3017         .parent         = &secure_32k_fck,
3018         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3019         .recalc         = &followparent_recalc,
3020 };
3021
3022 static struct clk *onchip_34xx_clks[] __initdata = {
3023         &omap_32k_fck,
3024         &virt_12m_ck,
3025         &virt_13m_ck,
3026         &virt_16_8m_ck,
3027         &virt_19_2m_ck,
3028         &virt_26m_ck,
3029         &virt_38_4m_ck,
3030         &osc_sys_ck,
3031         &sys_ck,
3032         &sys_altclk,
3033         &mcbsp_clks,
3034         &sys_clkout1,
3035         &dpll1_ck,
3036         &dpll1_x2_ck,
3037         &dpll1_x2m2_ck,
3038         &dpll2_ck,
3039         &dpll2_m2_ck,
3040         &dpll3_ck,
3041         &core_ck,
3042         &dpll3_x2_ck,
3043         &dpll3_m2_ck,
3044         &dpll3_m2x2_ck,
3045         &dpll3_m3_ck,
3046         &dpll3_m3x2_ck,
3047         &emu_core_alwon_ck,
3048         &dpll4_ck,
3049         &dpll4_x2_ck,
3050         &omap_96m_alwon_fck,
3051         &omap_96m_fck,
3052         &cm_96m_fck,
3053         &virt_omap_54m_fck,
3054         &omap_54m_fck,
3055         &omap_48m_fck,
3056         &omap_12m_fck,
3057         &dpll4_m2_ck,
3058         &dpll4_m2x2_ck,
3059         &dpll4_m3_ck,
3060         &dpll4_m3x2_ck,
3061         &dpll4_m4_ck,
3062         &dpll4_m4x2_ck,
3063         &dpll4_m5_ck,
3064         &dpll4_m5x2_ck,
3065         &dpll4_m6_ck,
3066         &dpll4_m6x2_ck,
3067         &emu_per_alwon_ck,
3068         &dpll5_ck,
3069         &dpll5_m2_ck,
3070         &omap_120m_fck,
3071         &clkout2_src_ck,
3072         &sys_clkout2,
3073         &corex2_fck,
3074         &dpll1_fck,
3075         &mpu_ck,
3076         &arm_fck,
3077         &emu_mpu_alwon_ck,
3078         &dpll2_fck,
3079         &iva2_ck,
3080         &l3_ick,
3081         &l4_ick,
3082         &rm_ick,
3083         &gfx_l3_ck,
3084         &gfx_l3_fck,
3085         &gfx_l3_ick,
3086         &gfx_cg1_ck,
3087         &gfx_cg2_ck,
3088         &sgx_fck,
3089         &sgx_ick,
3090         &d2d_26m_fck,
3091         &gpt10_fck,
3092         &gpt11_fck,
3093         &cpefuse_fck,
3094         &ts_fck,
3095         &usbtll_fck,
3096         &core_96m_fck,
3097         &mmchs3_fck,
3098         &mmchs2_fck,
3099         &mspro_fck,
3100         &mmchs1_fck,
3101         &i2c3_fck,
3102         &i2c2_fck,
3103         &i2c1_fck,
3104         &mcbsp5_fck,
3105         &mcbsp1_fck,
3106         &core_48m_fck,
3107         &mcspi4_fck,
3108         &mcspi3_fck,
3109         &mcspi2_fck,
3110         &mcspi1_fck,
3111         &uart2_fck,
3112         &uart1_fck,
3113         &fshostusb_fck,
3114         &core_12m_fck,
3115         &hdq_fck,
3116         &ssi_ssr_fck,
3117         &ssi_sst_fck,
3118         &core_l3_ick,
3119         &hsotgusb_ick,
3120         &sdrc_ick,
3121         &gpmc_fck,
3122         &security_l3_ick,
3123         &pka_ick,
3124         &core_l4_ick,
3125         &usbtll_ick,
3126         &mmchs3_ick,
3127         &icr_ick,
3128         &aes2_ick,
3129         &sha12_ick,
3130         &des2_ick,
3131         &mmchs2_ick,
3132         &mmchs1_ick,
3133         &mspro_ick,
3134         &hdq_ick,
3135         &mcspi4_ick,
3136         &mcspi3_ick,
3137         &mcspi2_ick,
3138         &mcspi1_ick,
3139         &i2c3_ick,
3140         &i2c2_ick,
3141         &i2c1_ick,
3142         &uart2_ick,
3143         &uart1_ick,
3144         &gpt11_ick,
3145         &gpt10_ick,
3146         &mcbsp5_ick,
3147         &mcbsp1_ick,
3148         &fac_ick,
3149         &mailboxes_ick,
3150         &omapctrl_ick,
3151         &ssi_l4_ick,
3152         &ssi_ick,
3153         &usb_l4_ick,
3154         &security_l4_ick2,
3155         &aes1_ick,
3156         &rng_ick,
3157         &sha11_ick,
3158         &des1_ick,
3159         &dss1_alwon_fck,
3160         &dss_tv_fck,
3161         &dss_96m_fck,
3162         &dss2_alwon_fck,
3163         &dss_ick,
3164         &cam_mclk,
3165         &cam_ick,
3166         &usbhost_120m_fck,
3167         &usbhost_48m_fck,
3168         &usbhost_ick,
3169         &usbhost_sar_fck,
3170         &usim_fck,
3171         &gpt1_fck,
3172         &wkup_32k_fck,
3173         &gpio1_fck,
3174         &wdt2_fck,
3175         &wkup_l4_ick,
3176         &usim_ick,
3177         &wdt2_ick,
3178         &wdt1_ick,
3179         &gpio1_ick,
3180         &omap_32ksync_ick,
3181         &gpt12_ick,
3182         &gpt1_ick,
3183         &per_96m_fck,
3184         &per_48m_fck,
3185         &uart3_fck,
3186         &gpt2_fck,
3187         &gpt3_fck,
3188         &gpt4_fck,
3189         &gpt5_fck,
3190         &gpt6_fck,
3191         &gpt7_fck,
3192         &gpt8_fck,
3193         &gpt9_fck,
3194         &per_32k_alwon_fck,
3195         &gpio6_fck,
3196         &gpio5_fck,
3197         &gpio4_fck,
3198         &gpio3_fck,
3199         &gpio2_fck,
3200         &wdt3_fck,
3201         &per_l4_ick,
3202         &gpio6_ick,
3203         &gpio5_ick,
3204         &gpio4_ick,
3205         &gpio3_ick,
3206         &gpio2_ick,
3207         &wdt3_ick,
3208         &uart3_ick,
3209         &gpt9_ick,
3210         &gpt8_ick,
3211         &gpt7_ick,
3212         &gpt6_ick,
3213         &gpt5_ick,
3214         &gpt4_ick,
3215         &gpt3_ick,
3216         &gpt2_ick,
3217         &mcbsp2_ick,
3218         &mcbsp3_ick,
3219         &mcbsp4_ick,
3220         &mcbsp2_fck,
3221         &mcbsp3_fck,
3222         &mcbsp4_fck,
3223         &emu_src_ck,
3224         &pclk_fck,
3225         &pclkx2_fck,
3226         &atclk_fck,
3227         &traceclk_src_fck,
3228         &traceclk_fck,
3229         &sr1_fck,
3230         &sr2_fck,
3231         &sr_l4_ick,
3232         &secure_32k_fck,
3233         &gpt12_fck,
3234         &wdt1_fck,
3235 };
3236
3237 #endif