arch/arm/mach-omap1/pm.c

   1 /*
   2  * linux/arch/arm/mach-omap1/pm.c
   3  *
   4  * OMAP Power Management Routines
   5  *
   6  * Original code for the SA11x0:
   7  * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
   8  *
   9  * Modified for the PXA250 by Nicolas Pitre:
  10  * Copyright (c) 2002 Monta Vista Software, Inc.
  11  *
  12  * Modified for the OMAP1510 by David Singleton:
  13  * Copyright (c) 2002 Monta Vista Software, Inc.
  14  *
  15  * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
  16  *
  17  * This program is free software; you can redistribute it and/or modify it
  18  * under the terms of the GNU General Public License as published by the
  19  * Free Software Foundation; either version 2 of the License, or (at your
  20  * option) any later version.
  21  *
  22  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  23  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  24  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  25  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  29  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * You should have received a copy of the GNU General Public License along
  34  * with this program; if not, write to the Free Software Foundation, Inc.,
  35  * 675 Mass Ave, Cambridge, MA 02139, USA.
  36  */
  37
  38 #include <linux/suspend.h>
  39 #include <linux/sched.h>
  40 #include <linux/debugfs.h>
  41 #include <linux/seq_file.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/sysfs.h>
  44 #include <linux/module.h>
  45 #include <linux/io.h>
  46 #include <linux/atomic.h>
  47 #include <linux/cpu.h>
  48
  49 #include <asm/fncpy.h>
  50 #include <asm/system_misc.h>
  51 #include <asm/irq.h>
  52 #include <asm/mach/time.h>
  53 #include <asm/mach/irq.h>
  54
  55 #include <mach/tc.h>
  56 #include <mach/mux.h>
  57 #include <linux/omap-dma.h>
  58 #include <plat/dmtimer.h>
  59
  60 #include <mach/irqs.h>
  61
  62 #include "iomap.h"
  63 #include "clock.h"
  64 #include "pm.h"
  65 #include "sram.h"
  66
  67 static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
  68 static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
  69 static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
  70 static unsigned int mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_SIZE];
  71 static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
  72 static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
  73
  74 #ifndef CONFIG_OMAP_32K_TIMER
  75
  76 static unsigned short enable_dyn_sleep = 0;
  77
  78 #else
  79
  80 static unsigned short enable_dyn_sleep = 1;
  81
  82 static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
  83                          char *buf)
  84 {
  85         return sprintf(buf, "%hu\n", enable_dyn_sleep);
  86 }
  87
  88 static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
  89                           const char * buf, size_t n)
  90 {
  91         unsigned short value;
  92         if (sscanf(buf, "%hu", &value) != 1 ||
  93             (value != 0 && value != 1)) {
  94                 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
  95                 return -EINVAL;
  96         }
  97         enable_dyn_sleep = value;
  98         return n;
  99 }
 100
 101 static struct kobj_attribute sleep_while_idle_attr =
 102         __ATTR(sleep_while_idle, 0644, idle_show, idle_store);
 103
 104 #endif
 105
 106 static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
 107
 108 /*
 109  * Let's power down on idle, but only if we are really
 110  * idle, because once we start down the path of
 111  * going idle we continue to do idle even if we get
 112  * a clock tick interrupt . .
 113  */
 114 void omap1_pm_idle(void)
 115 {
 116         extern __u32 arm_idlect1_mask;
 117         __u32 use_idlect1 = arm_idlect1_mask;
 118         int do_sleep = 0;
 119
 120         local_fiq_disable();
 121
 122 #if defined(CONFIG_OMAP_MPU_TIMER) && !defined(CONFIG_OMAP_DM_TIMER)
 123 #warning Enable 32kHz OS timer in order to allow sleep states in idle
 124         use_idlect1 = use_idlect1 & ~(1 << 9);
 125 #else
 126         if (enable_dyn_sleep)
 127                 do_sleep = 1;
 128 #endif
 129
 130 #ifdef CONFIG_OMAP_DM_TIMER
 131         use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1);
 132 #endif
 133
 134         if (omap_dma_running())
 135                 use_idlect1 &= ~(1 << 6);
 136
 137         /* We should be able to remove the do_sleep variable and multiple
 138          * tests above as soon as drivers, timer and DMA code have been fixed.
 139          * Even the sleep block count should become obsolete. */
 140         if ((use_idlect1 != ~0) || !do_sleep) {
 141
 142                 __u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
 143                 if (cpu_is_omap15xx())
 144                         use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST;
 145                 else
 146                         use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL;
 147                 omap_writel(use_idlect1, ARM_IDLECT1);
 148                 __asm__ volatile ("mcr  p15, 0, r0, c7, c0, 4");
 149                 omap_writel(saved_idlect1, ARM_IDLECT1);
 150
 151                 local_fiq_enable();
 152                 return;
 153         }
 154         omap_sram_suspend(omap_readl(ARM_IDLECT1),
 155                           omap_readl(ARM_IDLECT2));
 156
 157         local_fiq_enable();
 158 }
 159
 160 /*
 161  * Configuration of the wakeup event is board specific. For the
 162  * moment we put it into this helper function. Later it may move
 163  * to board specific files.
 164  */
 165 static void omap_pm_wakeup_setup(void)
 166 {
 167         u32 level1_wake = 0;
 168         u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
 169
 170         /*
 171          * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
 172          * and the L2 wakeup interrupts: keypad and UART2. Note that the
 173          * drivers must still separately call omap_set_gpio_wakeup() to
 174          * wake up to a GPIO interrupt.
 175          */
 176         if (cpu_is_omap7xx())
 177                 level1_wake = OMAP_IRQ_BIT(INT_7XX_GPIO_BANK1) |
 178                         OMAP_IRQ_BIT(INT_7XX_IH2_IRQ);
 179         else if (cpu_is_omap15xx())
 180                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
 181                         OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
 182         else if (cpu_is_omap16xx())
 183                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
 184                         OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
 185
 186         omap_writel(~level1_wake, OMAP_IH1_MIR);
 187
 188         if (cpu_is_omap7xx()) {
 189                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
 190                 omap_writel(~(OMAP_IRQ_BIT(INT_7XX_WAKE_UP_REQ) |
 191                                 OMAP_IRQ_BIT(INT_7XX_MPUIO_KEYPAD)),
 192                                 OMAP_IH2_1_MIR);
 193         } else if (cpu_is_omap15xx()) {
 194                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
 195                 omap_writel(~level2_wake,  OMAP_IH2_MIR);
 196         } else if (cpu_is_omap16xx()) {
 197                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
 198                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
 199
 200                 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
 201                 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ),
 202                             OMAP_IH2_1_MIR);
 203                 omap_writel(~0x0, OMAP_IH2_2_MIR);
 204                 omap_writel(~0x0, OMAP_IH2_3_MIR);
 205         }
 206
 207         /*  New IRQ agreement, recalculate in cascade order */
 208         omap_writel(1, OMAP_IH2_CONTROL);
 209         omap_writel(1, OMAP_IH1_CONTROL);
 210 }
 211
 212 #define EN_DSPCK        13      /* ARM_CKCTL */
 213 #define EN_APICK        6       /* ARM_IDLECT2 */
 214 #define DSP_EN          1       /* ARM_RSTCT1 */
 215
 216 void omap1_pm_suspend(void)
 217 {
 218         unsigned long arg0 = 0, arg1 = 0;
 219
 220         printk(KERN_INFO "PM: OMAP%x is trying to enter deep sleep...\n",
 221                 omap_rev());
 222
 223         omap_serial_wake_trigger(1);
 224
 225         if (!cpu_is_omap15xx())
 226                 omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
 227
 228         /*
 229          * Step 1: turn off interrupts (FIXME: NOTE: already disabled)
 230          */
 231
 232         local_irq_disable();
 233         local_fiq_disable();
 234
 235         /*
 236          * Step 2: save registers
 237          *
 238          * The omap is a strange/beautiful device. The caches, memory
 239          * and register state are preserved across power saves.
 240          * We have to save and restore very little register state to
 241          * idle the omap.
 242          *
 243          * Save interrupt, MPUI, ARM and UPLD control registers.
 244          */
 245
 246         if (cpu_is_omap7xx()) {
 247                 MPUI7XX_SAVE(OMAP_IH1_MIR);
 248                 MPUI7XX_SAVE(OMAP_IH2_0_MIR);
 249                 MPUI7XX_SAVE(OMAP_IH2_1_MIR);
 250                 MPUI7XX_SAVE(MPUI_CTRL);
 251                 MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
 252                 MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
 253                 MPUI7XX_SAVE(EMIFS_CONFIG);
 254                 MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
 255
 256         } else if (cpu_is_omap15xx()) {
 257                 MPUI1510_SAVE(OMAP_IH1_MIR);
 258                 MPUI1510_SAVE(OMAP_IH2_MIR);
 259                 MPUI1510_SAVE(MPUI_CTRL);
 260                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
 261                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
 262                 MPUI1510_SAVE(EMIFS_CONFIG);
 263                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
 264         } else if (cpu_is_omap16xx()) {
 265                 MPUI1610_SAVE(OMAP_IH1_MIR);
 266                 MPUI1610_SAVE(OMAP_IH2_0_MIR);
 267                 MPUI1610_SAVE(OMAP_IH2_1_MIR);
 268                 MPUI1610_SAVE(OMAP_IH2_2_MIR);
 269                 MPUI1610_SAVE(OMAP_IH2_3_MIR);
 270                 MPUI1610_SAVE(MPUI_CTRL);
 271                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
 272                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
 273                 MPUI1610_SAVE(EMIFS_CONFIG);
 274                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
 275         }
 276
 277         ARM_SAVE(ARM_CKCTL);
 278         ARM_SAVE(ARM_IDLECT1);
 279         ARM_SAVE(ARM_IDLECT2);
 280         if (!(cpu_is_omap15xx()))
 281                 ARM_SAVE(ARM_IDLECT3);
 282         ARM_SAVE(ARM_EWUPCT);
 283         ARM_SAVE(ARM_RSTCT1);
 284         ARM_SAVE(ARM_RSTCT2);
 285         ARM_SAVE(ARM_SYSST);
 286         ULPD_SAVE(ULPD_CLOCK_CTRL);
 287         ULPD_SAVE(ULPD_STATUS_REQ);
 288
 289         /* (Step 3 removed - we now allow deep sleep by default) */
 290
 291         /*
 292          * Step 4: OMAP DSP Shutdown
 293          */
 294
 295         /* stop DSP */
 296         omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1);
 297
 298                 /* shut down dsp_ck */
 299         if (!cpu_is_omap7xx())
 300                 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
 301
 302         /* temporarily enabling api_ck to access DSP registers */
 303         omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
 304
 305         /* save DSP registers */
 306         DSP_SAVE(DSP_IDLECT2);
 307
 308         /* Stop all DSP domain clocks */
 309         __raw_writew(0, DSP_IDLECT2);
 310
 311         /*
 312          * Step 5: Wakeup Event Setup
 313          */
 314
 315         omap_pm_wakeup_setup();
 316
 317         /*
 318          * Step 6: ARM and Traffic controller shutdown
 319          */
 320
 321         /* disable ARM watchdog */
 322         omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
 323         omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
 324
 325         /*
 326          * Step 6b: ARM and Traffic controller shutdown
 327          *
 328          * Step 6 continues here. Prepare jump to power management
 329          * assembly code in internal SRAM.
 330          *
 331          * Since the omap_cpu_suspend routine has been copied to
 332          * SRAM, we'll do an indirect procedure call to it and pass the
 333          * contents of arm_idlect1 and arm_idlect2 so it can restore
 334          * them when it wakes up and it will return.
 335          */
 336
 337         arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
 338         arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
 339
 340         /*
 341          * Step 6c: ARM and Traffic controller shutdown
 342          *
 343          * Jump to assembly code. The processor will stay there
 344          * until wake up.
 345          */
 346         omap_sram_suspend(arg0, arg1);
 347
 348         /*
 349          * If we are here, processor is woken up!
 350          */
 351
 352         /*
 353          * Restore DSP clocks
 354          */
 355
 356         /* again temporarily enabling api_ck to access DSP registers */
 357         omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
 358
 359         /* Restore DSP domain clocks */
 360         DSP_RESTORE(DSP_IDLECT2);
 361
 362         /*
 363          * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
 364          */
 365
 366         if (!(cpu_is_omap15xx()))
 367                 ARM_RESTORE(ARM_IDLECT3);
 368         ARM_RESTORE(ARM_CKCTL);
 369         ARM_RESTORE(ARM_EWUPCT);
 370         ARM_RESTORE(ARM_RSTCT1);
 371         ARM_RESTORE(ARM_RSTCT2);
 372         ARM_RESTORE(ARM_SYSST);
 373         ULPD_RESTORE(ULPD_CLOCK_CTRL);
 374         ULPD_RESTORE(ULPD_STATUS_REQ);
 375
 376         if (cpu_is_omap7xx()) {
 377                 MPUI7XX_RESTORE(EMIFS_CONFIG);
 378                 MPUI7XX_RESTORE(EMIFF_SDRAM_CONFIG);
 379                 MPUI7XX_RESTORE(OMAP_IH1_MIR);
 380                 MPUI7XX_RESTORE(OMAP_IH2_0_MIR);
 381                 MPUI7XX_RESTORE(OMAP_IH2_1_MIR);
 382         } else if (cpu_is_omap15xx()) {
 383                 MPUI1510_RESTORE(MPUI_CTRL);
 384                 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
 385                 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
 386                 MPUI1510_RESTORE(EMIFS_CONFIG);
 387                 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
 388                 MPUI1510_RESTORE(OMAP_IH1_MIR);
 389                 MPUI1510_RESTORE(OMAP_IH2_MIR);
 390         } else if (cpu_is_omap16xx()) {
 391                 MPUI1610_RESTORE(MPUI_CTRL);
 392                 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
 393                 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
 394                 MPUI1610_RESTORE(EMIFS_CONFIG);
 395                 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
 396
 397                 MPUI1610_RESTORE(OMAP_IH1_MIR);
 398                 MPUI1610_RESTORE(OMAP_IH2_0_MIR);
 399                 MPUI1610_RESTORE(OMAP_IH2_1_MIR);
 400                 MPUI1610_RESTORE(OMAP_IH2_2_MIR);
 401                 MPUI1610_RESTORE(OMAP_IH2_3_MIR);
 402         }
 403
 404         if (!cpu_is_omap15xx())
 405                 omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
 406
 407         /*
 408          * Re-enable interrupts
 409          */
 410
 411         local_irq_enable();
 412         local_fiq_enable();
 413
 414         omap_serial_wake_trigger(0);
 415
 416         printk(KERN_INFO "PM: OMAP%x is re-starting from deep sleep...\n",
 417                 omap_rev());
 418 }
 419
 420 #ifdef CONFIG_DEBUG_FS
 421 /*
 422  * Read system PM registers for debugging
 423  */
 424 static int omap_pm_debug_show(struct seq_file *m, void *v)
 425 {
 426         ARM_SAVE(ARM_CKCTL);
 427         ARM_SAVE(ARM_IDLECT1);
 428         ARM_SAVE(ARM_IDLECT2);
 429         if (!(cpu_is_omap15xx()))
 430                 ARM_SAVE(ARM_IDLECT3);
 431         ARM_SAVE(ARM_EWUPCT);
 432         ARM_SAVE(ARM_RSTCT1);
 433         ARM_SAVE(ARM_RSTCT2);
 434         ARM_SAVE(ARM_SYSST);
 435
 436         ULPD_SAVE(ULPD_IT_STATUS);
 437         ULPD_SAVE(ULPD_CLOCK_CTRL);
 438         ULPD_SAVE(ULPD_SOFT_REQ);
 439         ULPD_SAVE(ULPD_STATUS_REQ);
 440         ULPD_SAVE(ULPD_DPLL_CTRL);
 441         ULPD_SAVE(ULPD_POWER_CTRL);
 442
 443         if (cpu_is_omap7xx()) {
 444                 MPUI7XX_SAVE(MPUI_CTRL);
 445                 MPUI7XX_SAVE(MPUI_DSP_STATUS);
 446                 MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
 447                 MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
 448                 MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
 449                 MPUI7XX_SAVE(EMIFS_CONFIG);
 450         } else if (cpu_is_omap15xx()) {
 451                 MPUI1510_SAVE(MPUI_CTRL);
 452                 MPUI1510_SAVE(MPUI_DSP_STATUS);
 453                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
 454                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
 455                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
 456                 MPUI1510_SAVE(EMIFS_CONFIG);
 457         } else if (cpu_is_omap16xx()) {
 458                 MPUI1610_SAVE(MPUI_CTRL);
 459                 MPUI1610_SAVE(MPUI_DSP_STATUS);
 460                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
 461                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
 462                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
 463                 MPUI1610_SAVE(EMIFS_CONFIG);
 464         }
 465
 466         seq_printf(m,
 467                    "ARM_CKCTL_REG:            0x%-8x     \n"
 468                    "ARM_IDLECT1_REG:          0x%-8x     \n"
 469                    "ARM_IDLECT2_REG:          0x%-8x     \n"
 470                    "ARM_IDLECT3_REG:          0x%-8x     \n"
 471                    "ARM_EWUPCT_REG:           0x%-8x     \n"
 472                    "ARM_RSTCT1_REG:           0x%-8x     \n"
 473                    "ARM_RSTCT2_REG:           0x%-8x     \n"
 474                    "ARM_SYSST_REG:            0x%-8x     \n"
 475                    "ULPD_IT_STATUS_REG:       0x%-4x     \n"
 476                    "ULPD_CLOCK_CTRL_REG:      0x%-4x     \n"
 477                    "ULPD_SOFT_REQ_REG:        0x%-4x     \n"
 478                    "ULPD_DPLL_CTRL_REG:       0x%-4x     \n"
 479                    "ULPD_STATUS_REQ_REG:      0x%-4x     \n"
 480                    "ULPD_POWER_CTRL_REG:      0x%-4x     \n",
 481                    ARM_SHOW(ARM_CKCTL),
 482                    ARM_SHOW(ARM_IDLECT1),
 483                    ARM_SHOW(ARM_IDLECT2),
 484                    ARM_SHOW(ARM_IDLECT3),
 485                    ARM_SHOW(ARM_EWUPCT),
 486                    ARM_SHOW(ARM_RSTCT1),
 487                    ARM_SHOW(ARM_RSTCT2),
 488                    ARM_SHOW(ARM_SYSST),
 489                    ULPD_SHOW(ULPD_IT_STATUS),
 490                    ULPD_SHOW(ULPD_CLOCK_CTRL),
 491                    ULPD_SHOW(ULPD_SOFT_REQ),
 492                    ULPD_SHOW(ULPD_DPLL_CTRL),
 493                    ULPD_SHOW(ULPD_STATUS_REQ),
 494                    ULPD_SHOW(ULPD_POWER_CTRL));
 495
 496         if (cpu_is_omap7xx()) {
 497                 seq_printf(m,
 498                            "MPUI7XX_CTRL_REG         0x%-8x \n"
 499                            "MPUI7XX_DSP_STATUS_REG:      0x%-8x \n"
 500                            "MPUI7XX_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 501                            "MPUI7XX_DSP_API_CONFIG_REG:  0x%-8x \n"
 502                            "MPUI7XX_SDRAM_CONFIG_REG:    0x%-8x \n"
 503                            "MPUI7XX_EMIFS_CONFIG_REG:    0x%-8x \n",
 504                            MPUI7XX_SHOW(MPUI_CTRL),
 505                            MPUI7XX_SHOW(MPUI_DSP_STATUS),
 506                            MPUI7XX_SHOW(MPUI_DSP_BOOT_CONFIG),
 507                            MPUI7XX_SHOW(MPUI_DSP_API_CONFIG),
 508                            MPUI7XX_SHOW(EMIFF_SDRAM_CONFIG),
 509                            MPUI7XX_SHOW(EMIFS_CONFIG));
 510         } else if (cpu_is_omap15xx()) {
 511                 seq_printf(m,
 512                            "MPUI1510_CTRL_REG             0x%-8x \n"
 513                            "MPUI1510_DSP_STATUS_REG:      0x%-8x \n"
 514                            "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 515                            "MPUI1510_DSP_API_CONFIG_REG:  0x%-8x \n"
 516                            "MPUI1510_SDRAM_CONFIG_REG:    0x%-8x \n"
 517                            "MPUI1510_EMIFS_CONFIG_REG:    0x%-8x \n",
 518                            MPUI1510_SHOW(MPUI_CTRL),
 519                            MPUI1510_SHOW(MPUI_DSP_STATUS),
 520                            MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
 521                            MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
 522                            MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
 523                            MPUI1510_SHOW(EMIFS_CONFIG));
 524         } else if (cpu_is_omap16xx()) {
 525                 seq_printf(m,
 526                            "MPUI1610_CTRL_REG             0x%-8x \n"
 527                            "MPUI1610_DSP_STATUS_REG:      0x%-8x \n"
 528                            "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 529                            "MPUI1610_DSP_API_CONFIG_REG:  0x%-8x \n"
 530                            "MPUI1610_SDRAM_CONFIG_REG:    0x%-8x \n"
 531                            "MPUI1610_EMIFS_CONFIG_REG:    0x%-8x \n",
 532                            MPUI1610_SHOW(MPUI_CTRL),
 533                            MPUI1610_SHOW(MPUI_DSP_STATUS),
 534                            MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
 535                            MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
 536                            MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
 537                            MPUI1610_SHOW(EMIFS_CONFIG));
 538         }
 539
 540         return 0;
 541 }
 542
 543 static int omap_pm_debug_open(struct inode *inode, struct file *file)
 544 {
 545         return single_open(file, omap_pm_debug_show,
 546                                 &inode->i_private);
 547 }
 548
 549 static const struct file_operations omap_pm_debug_fops = {
 550         .open           = omap_pm_debug_open,
 551         .read           = seq_read,
 552         .llseek         = seq_lseek,
 553         .release        = single_release,
 554 };
 555
 556 static void omap_pm_init_debugfs(void)
 557 {
 558         struct dentry *d;
 559
 560         d = debugfs_create_dir("pm_debug", NULL);
 561         if (!d)
 562                 return;
 563
 564         (void) debugfs_create_file("omap_pm", S_IWUSR | S_IRUGO,
 565                                         d, NULL, &omap_pm_debug_fops);
 566 }
 567
 568 #endif /* CONFIG_DEBUG_FS */
 569
 570 /*
 571  *      omap_pm_prepare - Do preliminary suspend work.
 572  *
 573  */
 574 static int omap_pm_prepare(void)
 575 {
 576         /* We cannot sleep in idle until we have resumed */
 577         cpu_idle_poll_ctrl(true);
 578         return 0;
 579 }
 580
 581
 582 /*
 583  *      omap_pm_enter - Actually enter a sleep state.
 584  *      @state:         State we're entering.
 585  *
 586  */
 587
 588 static int omap_pm_enter(suspend_state_t state)
 589 {
 590         switch (state)
 591         {
 592         case PM_SUSPEND_STANDBY:
 593         case PM_SUSPEND_MEM:
 594                 omap1_pm_suspend();
 595                 break;
 596         default:
 597                 return -EINVAL;
 598         }
 599
 600         return 0;
 601 }
 602
 603
 604 /**
 605  *      omap_pm_finish - Finish up suspend sequence.
 606  *
 607  *      This is called after we wake back up (or if entering the sleep state
 608  *      failed).
 609  */
 610
 611 static void omap_pm_finish(void)
 612 {
 613         cpu_idle_poll_ctrl(false);
 614 }
 615
 616
 617 static irqreturn_t omap_wakeup_interrupt(int irq, void *dev)
 618 {
 619         return IRQ_HANDLED;
 620 }
 621
 622 static struct irqaction omap_wakeup_irq = {
 623         .name           = "peripheral wakeup",
 624         .handler        = omap_wakeup_interrupt
 625 };
 626
 627
 628
 629 static const struct platform_suspend_ops omap_pm_ops = {
 630         .prepare        = omap_pm_prepare,
 631         .enter          = omap_pm_enter,
 632         .finish         = omap_pm_finish,
 633         .valid          = suspend_valid_only_mem,
 634 };
 635
 636 static int __init omap_pm_init(void)
 637 {
 638
 639 #ifdef CONFIG_OMAP_32K_TIMER
 640         int error;
 641 #endif
 642
 643         if (!cpu_class_is_omap1())
 644                 return -ENODEV;
 645
 646         printk("Power Management for TI OMAP.\n");
 647
 648         /*
 649          * We copy the assembler sleep/wakeup routines to SRAM.
 650          * These routines need to be in SRAM as that's the only
 651          * memory the MPU can see when it wakes up.
 652          */
 653         if (cpu_is_omap7xx()) {
 654                 omap_sram_suspend = omap_sram_push(omap7xx_cpu_suspend,
 655                                                    omap7xx_cpu_suspend_sz);
 656         } else if (cpu_is_omap15xx()) {
 657                 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
 658                                                    omap1510_cpu_suspend_sz);
 659         } else if (cpu_is_omap16xx()) {
 660                 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
 661                                                    omap1610_cpu_suspend_sz);
 662         }
 663
 664         if (omap_sram_suspend == NULL) {
 665                 printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
 666                 return -ENODEV;
 667         }
 668
 669         arm_pm_idle = omap1_pm_idle;
 670
 671         if (cpu_is_omap7xx())
 672                 setup_irq(INT_7XX_WAKE_UP_REQ, &omap_wakeup_irq);
 673         else if (cpu_is_omap16xx())
 674                 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
 675
 676         /* Program new power ramp-up time
 677          * (0 for most boards since we don't lower voltage when in deep sleep)
 678          */
 679         omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
 680
 681         /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
 682         omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
 683
 684         /* Configure IDLECT3 */
 685         if (cpu_is_omap7xx())
 686                 omap_writel(OMAP7XX_IDLECT3_VAL, OMAP7XX_IDLECT3);
 687         else if (cpu_is_omap16xx())
 688                 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
 689
 690         suspend_set_ops(&omap_pm_ops);
 691
 692 #ifdef CONFIG_DEBUG_FS
 693         omap_pm_init_debugfs();
 694 #endif
 695
 696 #ifdef CONFIG_OMAP_32K_TIMER
 697         error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr);
 698         if (error)
 699                 printk(KERN_ERR "sysfs_create_file failed: %d\n", error);
 700 #endif
 701
 702         if (cpu_is_omap16xx()) {
 703                 /* configure LOW_PWR pin */
 704                 omap_cfg_reg(T20_1610_LOW_PWR);
 705         }
 706
 707         return 0;
 708 }
 709 __initcall(omap_pm_init);