arch/arm/mach-omap1/board-h3.c

   1 /*
   2  * linux/arch/arm/mach-omap1/board-h3.c
   3  *
   4  * This file contains OMAP1710 H3 specific code.
   5  *
   6  * Copyright (C) 2004 Texas Instruments, Inc.
   7  * Copyright (C) 2002 MontaVista Software, Inc.
   8  * Copyright (C) 2001 RidgeRun, Inc.
   9  * Author: RidgeRun, Inc.
  10  *         Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #include <linux/types.h>
  18 #include <linux/init.h>
  19 #include <linux/major.h>
  20 #include <linux/kernel.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/errno.h>
  23 #include <linux/workqueue.h>
  24 #include <linux/i2c.h>
  25 #include <linux/mtd/mtd.h>
  26 #include <linux/mtd/nand.h>
  27 #include <linux/mtd/partitions.h>
  28 #include <linux/input.h>
  29 #include <linux/spi/spi.h>
  30 #include <linux/i2c/tps65010.h>
  31
  32 #include <asm/setup.h>
  33 #include <asm/page.h>
  34 #include <mach/hardware.h>
  35 #include <asm/gpio.h>
  36
  37 #include <asm/mach-types.h>
  38 #include <asm/mach/arch.h>
  39 #include <asm/mach/flash.h>
  40 #include <asm/mach/map.h>
  41
  42 #include <mach/gpioexpander.h>
  43 #include <mach/irqs.h>
  44 #include <mach/mux.h>
  45 #include <mach/tc.h>
  46 #include <mach/nand.h>
  47 #include <mach/irda.h>
  48 #include <mach/usb.h>
  49 #include <mach/keypad.h>
  50 #include <mach/dma.h>
  51 #include <mach/common.h>
  52 #include <mach/mcbsp.h>
  53 #include <mach/omap-alsa.h>
  54
  55 #define H3_TS_GPIO      48
  56
  57 static int h3_keymap[] = {
  58         KEY(0, 0, KEY_LEFT),
  59         KEY(0, 1, KEY_RIGHT),
  60         KEY(0, 2, KEY_3),
  61         KEY(0, 3, KEY_F10),
  62         KEY(0, 4, KEY_F5),
  63         KEY(0, 5, KEY_9),
  64         KEY(1, 0, KEY_DOWN),
  65         KEY(1, 1, KEY_UP),
  66         KEY(1, 2, KEY_2),
  67         KEY(1, 3, KEY_F9),
  68         KEY(1, 4, KEY_F7),
  69         KEY(1, 5, KEY_0),
  70         KEY(2, 0, KEY_ENTER),
  71         KEY(2, 1, KEY_6),
  72         KEY(2, 2, KEY_1),
  73         KEY(2, 3, KEY_F2),
  74         KEY(2, 4, KEY_F6),
  75         KEY(2, 5, KEY_HOME),
  76         KEY(3, 0, KEY_8),
  77         KEY(3, 1, KEY_5),
  78         KEY(3, 2, KEY_F12),
  79         KEY(3, 3, KEY_F3),
  80         KEY(3, 4, KEY_F8),
  81         KEY(3, 5, KEY_END),
  82         KEY(4, 0, KEY_7),
  83         KEY(4, 1, KEY_4),
  84         KEY(4, 2, KEY_F11),
  85         KEY(4, 3, KEY_F1),
  86         KEY(4, 4, KEY_F4),
  87         KEY(4, 5, KEY_ESC),
  88         KEY(5, 0, KEY_F13),
  89         KEY(5, 1, KEY_F14),
  90         KEY(5, 2, KEY_F15),
  91         KEY(5, 3, KEY_F16),
  92         KEY(5, 4, KEY_SLEEP),
  93         0
  94 };
  95
  96
  97 static struct mtd_partition nor_partitions[] = {
  98         /* bootloader (U-Boot, etc) in first sector */
  99         {
 100               .name             = "bootloader",
 101               .offset           = 0,
 102               .size             = SZ_128K,
 103               .mask_flags       = MTD_WRITEABLE, /* force read-only */
 104         },
 105         /* bootloader params in the next sector */
 106         {
 107               .name             = "params",
 108               .offset           = MTDPART_OFS_APPEND,
 109               .size             = SZ_128K,
 110               .mask_flags       = 0,
 111         },
 112         /* kernel */
 113         {
 114               .name             = "kernel",
 115               .offset           = MTDPART_OFS_APPEND,
 116               .size             = SZ_2M,
 117               .mask_flags       = 0
 118         },
 119         /* file system */
 120         {
 121               .name             = "filesystem",
 122               .offset           = MTDPART_OFS_APPEND,
 123               .size             = MTDPART_SIZ_FULL,
 124               .mask_flags       = 0
 125         }
 126 };
 127
 128 static struct flash_platform_data nor_data = {
 129         .map_name       = "cfi_probe",
 130         .width          = 2,
 131         .parts          = nor_partitions,
 132         .nr_parts       = ARRAY_SIZE(nor_partitions),
 133 };
 134
 135 static struct resource nor_resource = {
 136         /* This is on CS3, wherever it's mapped */
 137         .flags          = IORESOURCE_MEM,
 138 };
 139
 140 static struct platform_device nor_device = {
 141         .name           = "omapflash",
 142         .id             = 0,
 143         .dev            = {
 144                 .platform_data  = &nor_data,
 145         },
 146         .num_resources  = 1,
 147         .resource       = &nor_resource,
 148 };
 149
 150 static struct mtd_partition nand_partitions[] = {
 151 #if 0
 152         /* REVISIT: enable these partitions if you make NAND BOOT work */
 153         {
 154                 .name           = "xloader",
 155                 .offset         = 0,
 156                 .size           = 64 * 1024,
 157                 .mask_flags     = MTD_WRITEABLE,        /* force read-only */
 158         },
 159         {
 160                 .name           = "bootloader",
 161                 .offset         = MTDPART_OFS_APPEND,
 162                 .size           = 256 * 1024,
 163                 .mask_flags     = MTD_WRITEABLE,        /* force read-only */
 164         },
 165         {
 166                 .name           = "params",
 167                 .offset         = MTDPART_OFS_APPEND,
 168                 .size           = 192 * 1024,
 169         },
 170         {
 171                 .name           = "kernel",
 172                 .offset         = MTDPART_OFS_APPEND,
 173                 .size           = 2 * SZ_1M,
 174         },
 175 #endif
 176         {
 177                 .name           = "filesystem",
 178                 .size           = MTDPART_SIZ_FULL,
 179                 .offset         = MTDPART_OFS_APPEND,
 180         },
 181 };
 182
 183 /* dip switches control NAND chip access:  8 bit, 16 bit, or neither */
 184 static struct omap_nand_platform_data nand_data = {
 185         .options        = NAND_SAMSUNG_LP_OPTIONS,
 186         .parts          = nand_partitions,
 187         .nr_parts       = ARRAY_SIZE(nand_partitions),
 188 };
 189
 190 static struct resource nand_resource = {
 191         .flags          = IORESOURCE_MEM,
 192 };
 193
 194 static struct platform_device nand_device = {
 195         .name           = "omapnand",
 196         .id             = 0,
 197         .dev            = {
 198                 .platform_data  = &nand_data,
 199         },
 200         .num_resources  = 1,
 201         .resource       = &nand_resource,
 202 };
 203
 204 static struct resource smc91x_resources[] = {
 205         [0] = {
 206                 .start  = OMAP1710_ETHR_START,          /* Physical */
 207                 .end    = OMAP1710_ETHR_START + 0xf,
 208                 .flags  = IORESOURCE_MEM,
 209         },
 210         [1] = {
 211                 .start  = OMAP_GPIO_IRQ(40),
 212                 .end    = OMAP_GPIO_IRQ(40),
 213                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
 214         },
 215 };
 216
 217 static struct platform_device smc91x_device = {
 218         .name           = "smc91x",
 219         .id             = 0,
 220         .num_resources  = ARRAY_SIZE(smc91x_resources),
 221         .resource       = smc91x_resources,
 222 };
 223
 224 #define GPTIMER_BASE            0xFFFB1400
 225 #define GPTIMER_REGS(x) (0xFFFB1400 + (x * 0x800))
 226 #define GPTIMER_REGS_SIZE       0x46
 227
 228 static struct resource intlat_resources[] = {
 229         [0] = {
 230                 .start  = GPTIMER_REGS(0),            /* Physical */
 231                 .end    = GPTIMER_REGS(0) + GPTIMER_REGS_SIZE,
 232                 .flags  = IORESOURCE_MEM,
 233         },
 234         [1] = {
 235                 .start  = INT_1610_GPTIMER1,
 236                 .end    = INT_1610_GPTIMER1,
 237                 .flags  = IORESOURCE_IRQ,
 238         },
 239 };
 240
 241 static struct platform_device intlat_device = {
 242         .name      = "omap_intlat",
 243         .id          = 0,
 244         .num_resources  = ARRAY_SIZE(intlat_resources),
 245         .resource       = intlat_resources,
 246 };
 247
 248 static struct resource h3_kp_resources[] = {
 249         [0] = {
 250                 .start  = INT_KEYBOARD,
 251                 .end    = INT_KEYBOARD,
 252                 .flags  = IORESOURCE_IRQ,
 253         },
 254 };
 255
 256 static struct omap_kp_platform_data h3_kp_data = {
 257         .rows           = 8,
 258         .cols           = 8,
 259         .keymap         = h3_keymap,
 260         .keymapsize     = ARRAY_SIZE(h3_keymap),
 261         .rep            = 1,
 262         .delay          = 9,
 263         .dbounce        = 1,
 264 };
 265
 266 static struct platform_device h3_kp_device = {
 267         .name           = "omap-keypad",
 268         .id             = -1,
 269         .dev            = {
 270                 .platform_data = &h3_kp_data,
 271         },
 272         .num_resources  = ARRAY_SIZE(h3_kp_resources),
 273         .resource       = h3_kp_resources,
 274 };
 275
 276
 277 /* Select between the IrDA and aGPS module
 278  */
 279 static int h3_select_irda(struct device *dev, int state)
 280 {
 281         unsigned char expa;
 282         int err = 0;
 283
 284         if ((err = read_gpio_expa(&expa, 0x26))) {
 285                 printk(KERN_ERR "Error reading from I/O EXPANDER \n");
 286                 return err;
 287         }
 288
 289         /* 'P6' enable/disable IRDA_TX and IRDA_RX */
 290         if (state & IR_SEL) { /* IrDA */
 291                 if ((err = write_gpio_expa(expa | 0x40, 0x26))) {
 292                         printk(KERN_ERR "Error writing to I/O EXPANDER \n");
 293                         return err;
 294                 }
 295         } else {
 296                 if ((err = write_gpio_expa(expa & ~0x40, 0x26))) {
 297                         printk(KERN_ERR "Error writing to I/O EXPANDER \n");
 298                         return err;
 299                 }
 300         }
 301         return err;
 302 }
 303
 304 static void set_trans_mode(struct work_struct *work)
 305 {
 306         struct omap_irda_config *irda_config =
 307                 container_of(work, struct omap_irda_config, gpio_expa.work);
 308         int mode = irda_config->mode;
 309         unsigned char expa;
 310         int err = 0;
 311
 312         if ((err = read_gpio_expa(&expa, 0x27)) != 0) {
 313                 printk(KERN_ERR "Error reading from I/O expander\n");
 314         }
 315
 316         expa &= ~0x03;
 317
 318         if (mode & IR_SIRMODE) {
 319                 expa |= 0x01;
 320         } else { /* MIR/FIR */
 321                 expa |= 0x03;
 322         }
 323
 324         if ((err = write_gpio_expa(expa, 0x27)) != 0) {
 325                 printk(KERN_ERR "Error writing to I/O expander\n");
 326         }
 327 }
 328
 329 static int h3_transceiver_mode(struct device *dev, int mode)
 330 {
 331         struct omap_irda_config *irda_config = dev->platform_data;
 332
 333         irda_config->mode = mode;
 334         cancel_delayed_work(&irda_config->gpio_expa);
 335         PREPARE_DELAYED_WORK(&irda_config->gpio_expa, set_trans_mode);
 336         schedule_delayed_work(&irda_config->gpio_expa, 0);
 337
 338         return 0;
 339 }
 340
 341 static struct omap_irda_config h3_irda_data = {
 342         .transceiver_cap        = IR_SIRMODE | IR_MIRMODE | IR_FIRMODE,
 343         .transceiver_mode       = h3_transceiver_mode,
 344         .select_irda            = h3_select_irda,
 345         .rx_channel             = OMAP_DMA_UART3_RX,
 346         .tx_channel             = OMAP_DMA_UART3_TX,
 347         .dest_start             = UART3_THR,
 348         .src_start              = UART3_RHR,
 349         .tx_trigger             = 0,
 350         .rx_trigger             = 0,
 351 };
 352
 353 static struct resource h3_irda_resources[] = {
 354         [0] = {
 355                 .start  = INT_UART3,
 356                 .end    = INT_UART3,
 357                 .flags  = IORESOURCE_IRQ,
 358         },
 359 };
 360
 361 static u64 irda_dmamask = 0xffffffff;
 362
 363 static struct platform_device h3_irda_device = {
 364         .name           = "omapirda",
 365         .id             = 0,
 366         .dev            = {
 367                 .platform_data  = &h3_irda_data,
 368                 .dma_mask       = &irda_dmamask,
 369         },
 370         .num_resources  = ARRAY_SIZE(h3_irda_resources),
 371         .resource       = h3_irda_resources,
 372 };
 373
 374 static struct platform_device h3_lcd_device = {
 375         .name           = "lcd_h3",
 376         .id             = -1,
 377 };
 378
 379 static struct spi_board_info h3_spi_board_info[] __initdata = {
 380         [0] = {
 381                 .modalias       = "tsc2101",
 382                 .bus_num        = 2,
 383                 .chip_select    = 0,
 384                 .irq            = OMAP_GPIO_IRQ(H3_TS_GPIO),
 385                 .max_speed_hz   = 16000000,
 386                 /* .platform_data       = &tsc_platform_data, */
 387         },
 388 };
 389
 390 static struct omap_mcbsp_reg_cfg mcbsp_regs = {
 391         .spcr2 = FREE | FRST | GRST | XRST | XINTM(3),
 392         .spcr1 = RINTM(3) | RRST,
 393         .rcr2  = RPHASE | RFRLEN2(OMAP_MCBSP_WORD_8) |
 394                 RWDLEN2(OMAP_MCBSP_WORD_16) | RDATDLY(1),
 395         .rcr1  = RFRLEN1(OMAP_MCBSP_WORD_8) | RWDLEN1(OMAP_MCBSP_WORD_16),
 396         .xcr2  = XPHASE | XFRLEN2(OMAP_MCBSP_WORD_8) |
 397                 XWDLEN2(OMAP_MCBSP_WORD_16) | XDATDLY(1) | XFIG,
 398         .xcr1  = XFRLEN1(OMAP_MCBSP_WORD_8) | XWDLEN1(OMAP_MCBSP_WORD_16),
 399         .srgr1 = FWID(15),
 400         .srgr2 = GSYNC | CLKSP | FSGM | FPER(31),
 401
 402         .pcr0  = CLKRM | SCLKME | FSXP | FSRP | CLKXP | CLKRP,
 403         /*.pcr0 = CLKXP | CLKRP,*/        /* mcbsp: slave */
 404 };
 405
 406 static struct omap_alsa_codec_config alsa_config = {
 407         .name                   = "H3 TSC2101",
 408         .mcbsp_regs_alsa        = &mcbsp_regs,
 409         .codec_configure_dev    = NULL, /* tsc2101_configure, */
 410         .codec_set_samplerate   = NULL, /* tsc2101_set_samplerate, */
 411         .codec_clock_setup      = NULL, /* tsc2101_clock_setup, */
 412         .codec_clock_on         = NULL, /* tsc2101_clock_on, */
 413         .codec_clock_off        = NULL, /* tsc2101_clock_off, */
 414         .get_default_samplerate = NULL, /* tsc2101_get_default_samplerate, */
 415 };
 416
 417 static struct platform_device h3_mcbsp1_device = {
 418         .name   = "omap_alsa_mcbsp",
 419         .id     = 1,
 420         .dev = {
 421                 .platform_data  = &alsa_config,
 422         },
 423 };
 424
 425 static struct platform_device *devices[] __initdata = {
 426         &nor_device,
 427         &nand_device,
 428         &smc91x_device,
 429         &intlat_device,
 430         &h3_irda_device,
 431         &h3_kp_device,
 432         &h3_lcd_device,
 433         &h3_mcbsp1_device,
 434 };
 435
 436 static struct omap_usb_config h3_usb_config __initdata = {
 437         /* usb1 has a Mini-AB port and external isp1301 transceiver */
 438         .otg        = 2,
 439
 440 #ifdef CONFIG_USB_GADGET_OMAP
 441         .hmc_mode       = 19,   /* 0:host(off) 1:dev|otg 2:disabled */
 442 #elif  defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
 443         /* NONSTANDARD CABLE NEEDED (B-to-Mini-B) */
 444         .hmc_mode       = 20,   /* 1:dev|otg(off) 1:host 2:disabled */
 445 #endif
 446
 447         .pins[1]        = 3,
 448 };
 449
 450 static struct omap_uart_config h3_uart_config __initdata = {
 451         .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
 452 };
 453
 454 static struct omap_lcd_config h3_lcd_config __initdata = {
 455         .ctrl_name      = "internal",
 456 };
 457
 458 static struct omap_board_config_kernel h3_config[] __initdata = {
 459         { OMAP_TAG_USB,         &h3_usb_config },
 460         { OMAP_TAG_UART,        &h3_uart_config },
 461         { OMAP_TAG_LCD,         &h3_lcd_config },
 462 };
 463
 464 static struct i2c_board_info __initdata h3_i2c_board_info[] = {
 465        {
 466                 I2C_BOARD_INFO("tps65013", 0x48),
 467                /* .irq         = OMAP_GPIO_IRQ(??), */
 468        },
 469         {
 470                 I2C_BOARD_INFO("isp1301_omap", 0x2d),
 471                 .irq            = OMAP_GPIO_IRQ(14),
 472         },
 473 };
 474
 475 static struct omap_gpio_switch h3_gpio_switches[] __initdata = {
 476         {
 477                 .name                   = "mmc_slot",
 478                 .gpio                   = OMAP_MPUIO(1),
 479                 .type                   = OMAP_GPIO_SWITCH_TYPE_COVER,
 480                 .debounce_rising        = 100,
 481                 .debounce_falling       = 0,
 482                 .notify                 = h3_mmc_slot_cover_handler,
 483                 .notify_data            = NULL,
 484         },
 485 };
 486
 487 #define H3_NAND_RB_GPIO_PIN     10
 488
 489 static int nand_dev_ready(struct omap_nand_platform_data *data)
 490 {
 491         return gpio_get_value(H3_NAND_RB_GPIO_PIN);
 492 }
 493
 494 static void __init h3_init(void)
 495 {
 496         /* Here we assume the NOR boot config:  NOR on CS3 (possibly swapped
 497          * to address 0 by a dip switch), NAND on CS2B.  The NAND driver will
 498          * notice whether a NAND chip is enabled at probe time.
 499          *
 500          * H3 support NAND-boot, with a dip switch to put NOR on CS2B and NAND
 501          * (which on H2 may be 16bit) on CS3.  Try detecting that in code here,
 502          * to avoid probing every possible flash configuration...
 503          */
 504         nor_resource.end = nor_resource.start = omap_cs3_phys();
 505         nor_resource.end += SZ_32M - 1;
 506
 507         nand_resource.end = nand_resource.start = OMAP_CS2B_PHYS;
 508         nand_resource.end += SZ_4K - 1;
 509         if (gpio_request(H3_NAND_RB_GPIO_PIN, "NAND ready") < 0)
 510                 BUG();
 511         nand_data.dev_ready = nand_dev_ready;
 512
 513         /* GPIO10 Func_MUX_CTRL reg bit 29:27, Configure V2 to mode1 as GPIO */
 514         /* GPIO10 pullup/down register, Enable pullup on GPIO10 */
 515         omap_cfg_reg(V2_1710_GPIO10);
 516
 517         platform_add_devices(devices, ARRAY_SIZE(devices));
 518         spi_register_board_info(h3_spi_board_info,
 519                                 ARRAY_SIZE(h3_spi_board_info));
 520         omap_board_config = h3_config;
 521         omap_board_config_size = ARRAY_SIZE(h3_config);
 522         omap_serial_init();
 523         omap_register_i2c_bus(1, 100, h3_i2c_board_info,
 524                               ARRAY_SIZE(h3_i2c_board_info));
 525         h3_mmc_init();
 526 }
 527
 528 static void __init h3_init_smc91x(void)
 529 {
 530         omap_cfg_reg(W15_1710_GPIO40);
 531         if (gpio_request(40, "SMC91x irq") < 0) {
 532                 printk("Error requesting gpio 40 for smc91x irq\n");
 533                 return;
 534         }
 535 }
 536
 537 static void __init h3_init_irq(void)
 538 {
 539         omap1_init_common_hw();
 540         omap_init_irq();
 541         omap_gpio_init();
 542         h3_init_smc91x();
 543 }
 544
 545 static void __init h3_map_io(void)
 546 {
 547         omap1_map_common_io();
 548 }
 549
 550 MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
 551         /* Maintainer: Texas Instruments, Inc. */
 552         .phys_io        = 0xfff00000,
 553         .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
 554         .boot_params    = 0x10000100,
 555         .map_io         = h3_map_io,
 556         .init_irq       = h3_init_irq,
 557         .init_machine   = h3_init,
 558         .timer          = &omap_timer,
 559 MACHINE_END