Merge branch 'for-rmk' of git://git.pengutronix.de/git/imx/linux-2.6 into devel-stable
[sfrench/cifs-2.6.git] / arch / arm / mach-mx5 / clock-mx51.c
1 /*
2  * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3  * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
4  *
5  * The code contained herein is licensed under the GNU General Public
6  * License. You may obtain a copy of the GNU General Public License
7  * Version 2 or later at the following locations:
8  *
9  * http://www.opensource.org/licenses/gpl-license.html
10  * http://www.gnu.org/copyleft/gpl.html
11  */
12
13 #include <linux/mm.h>
14 #include <linux/delay.h>
15 #include <linux/clk.h>
16 #include <linux/io.h>
17
18 #include <asm/clkdev.h>
19 #include <asm/div64.h>
20
21 #include <mach/hardware.h>
22 #include <mach/common.h>
23 #include <mach/clock.h>
24
25 #include "crm_regs.h"
26
27 /* External clock values passed-in by the board code */
28 static unsigned long external_high_reference, external_low_reference;
29 static unsigned long oscillator_reference, ckih2_reference;
30
31 static struct clk osc_clk;
32 static struct clk pll1_main_clk;
33 static struct clk pll1_sw_clk;
34 static struct clk pll2_sw_clk;
35 static struct clk pll3_sw_clk;
36 static struct clk lp_apm_clk;
37 static struct clk periph_apm_clk;
38 static struct clk ahb_clk;
39 static struct clk ipg_clk;
40 static struct clk usboh3_clk;
41
42 #define MAX_DPLL_WAIT_TRIES     1000 /* 1000 * udelay(1) = 1ms */
43
44 static int _clk_ccgr_enable(struct clk *clk)
45 {
46         u32 reg;
47
48         reg = __raw_readl(clk->enable_reg);
49         reg |= MXC_CCM_CCGRx_MOD_ON << clk->enable_shift;
50         __raw_writel(reg, clk->enable_reg);
51
52         return 0;
53 }
54
55 static void _clk_ccgr_disable(struct clk *clk)
56 {
57         u32 reg;
58         reg = __raw_readl(clk->enable_reg);
59         reg &= ~(MXC_CCM_CCGRx_MOD_OFF << clk->enable_shift);
60         __raw_writel(reg, clk->enable_reg);
61
62 }
63
64 static void _clk_ccgr_disable_inwait(struct clk *clk)
65 {
66         u32 reg;
67
68         reg = __raw_readl(clk->enable_reg);
69         reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
70         reg |= MXC_CCM_CCGRx_MOD_IDLE << clk->enable_shift;
71         __raw_writel(reg, clk->enable_reg);
72 }
73
74 /*
75  * For the 4-to-1 muxed input clock
76  */
77 static inline u32 _get_mux(struct clk *parent, struct clk *m0,
78                            struct clk *m1, struct clk *m2, struct clk *m3)
79 {
80         if (parent == m0)
81                 return 0;
82         else if (parent == m1)
83                 return 1;
84         else if (parent == m2)
85                 return 2;
86         else if (parent == m3)
87                 return 3;
88         else
89                 BUG();
90
91         return -EINVAL;
92 }
93
94 static inline void __iomem *_get_pll_base(struct clk *pll)
95 {
96         if (pll == &pll1_main_clk)
97                 return MX51_DPLL1_BASE;
98         else if (pll == &pll2_sw_clk)
99                 return MX51_DPLL2_BASE;
100         else if (pll == &pll3_sw_clk)
101                 return MX51_DPLL3_BASE;
102         else
103                 BUG();
104
105         return NULL;
106 }
107
108 static unsigned long clk_pll_get_rate(struct clk *clk)
109 {
110         long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
111         unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
112         void __iomem *pllbase;
113         s64 temp;
114         unsigned long parent_rate;
115
116         parent_rate = clk_get_rate(clk->parent);
117
118         pllbase = _get_pll_base(clk);
119
120         dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
121         pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
122         dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
123
124         if (pll_hfsm == 0) {
125                 dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
126                 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
127                 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
128         } else {
129                 dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
130                 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
131                 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
132         }
133         pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
134         mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
135         mfi = (mfi <= 5) ? 5 : mfi;
136         mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
137         mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK;
138         /* Sign extend to 32-bits */
139         if (mfn >= 0x04000000) {
140                 mfn |= 0xFC000000;
141                 mfn_abs = -mfn;
142         }
143
144         ref_clk = 2 * parent_rate;
145         if (dbl != 0)
146                 ref_clk *= 2;
147
148         ref_clk /= (pdf + 1);
149         temp = (u64) ref_clk * mfn_abs;
150         do_div(temp, mfd + 1);
151         if (mfn < 0)
152                 temp = -temp;
153         temp = (ref_clk * mfi) + temp;
154
155         return temp;
156 }
157
158 static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
159 {
160         u32 reg;
161         void __iomem *pllbase;
162
163         long mfi, pdf, mfn, mfd = 999999;
164         s64 temp64;
165         unsigned long quad_parent_rate;
166         unsigned long pll_hfsm, dp_ctl;
167         unsigned long parent_rate;
168
169         parent_rate = clk_get_rate(clk->parent);
170
171         pllbase = _get_pll_base(clk);
172
173         quad_parent_rate = 4 * parent_rate;
174         pdf = mfi = -1;
175         while (++pdf < 16 && mfi < 5)
176                 mfi = rate * (pdf+1) / quad_parent_rate;
177         if (mfi > 15)
178                 return -EINVAL;
179         pdf--;
180
181         temp64 = rate * (pdf+1) - quad_parent_rate * mfi;
182         do_div(temp64, quad_parent_rate/1000000);
183         mfn = (long)temp64;
184
185         dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
186         /* use dpdck0_2 */
187         __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
188         pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
189         if (pll_hfsm == 0) {
190                 reg = mfi << 4 | pdf;
191                 __raw_writel(reg, pllbase + MXC_PLL_DP_OP);
192                 __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD);
193                 __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN);
194         } else {
195                 reg = mfi << 4 | pdf;
196                 __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP);
197                 __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD);
198                 __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN);
199         }
200
201         return 0;
202 }
203
204 static int _clk_pll_enable(struct clk *clk)
205 {
206         u32 reg;
207         void __iomem *pllbase;
208         int i = 0;
209
210         pllbase = _get_pll_base(clk);
211         reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN;
212         __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
213
214         /* Wait for lock */
215         do {
216                 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
217                 if (reg & MXC_PLL_DP_CTL_LRF)
218                         break;
219
220                 udelay(1);
221         } while (++i < MAX_DPLL_WAIT_TRIES);
222
223         if (i == MAX_DPLL_WAIT_TRIES) {
224                 pr_err("MX5: pll locking failed\n");
225                 return -EINVAL;
226         }
227
228         return 0;
229 }
230
231 static void _clk_pll_disable(struct clk *clk)
232 {
233         u32 reg;
234         void __iomem *pllbase;
235
236         pllbase = _get_pll_base(clk);
237         reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;
238         __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
239 }
240
241 static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)
242 {
243         u32 reg, step;
244
245         reg = __raw_readl(MXC_CCM_CCSR);
246
247         /* When switching from pll_main_clk to a bypass clock, first select a
248          * multiplexed clock in 'step_sel', then shift the glitchless mux
249          * 'pll1_sw_clk_sel'.
250          *
251          * When switching back, do it in reverse order
252          */
253         if (parent == &pll1_main_clk) {
254                 /* Switch to pll1_main_clk */
255                 reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
256                 __raw_writel(reg, MXC_CCM_CCSR);
257                 /* step_clk mux switched to lp_apm, to save power. */
258                 reg = __raw_readl(MXC_CCM_CCSR);
259                 reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
260                 reg |= (MXC_CCM_CCSR_STEP_SEL_LP_APM <<
261                                 MXC_CCM_CCSR_STEP_SEL_OFFSET);
262         } else {
263                 if (parent == &lp_apm_clk) {
264                         step = MXC_CCM_CCSR_STEP_SEL_LP_APM;
265                 } else  if (parent == &pll2_sw_clk) {
266                         step = MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED;
267                 } else  if (parent == &pll3_sw_clk) {
268                         step = MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED;
269                 } else
270                         return -EINVAL;
271
272                 reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
273                 reg |= (step << MXC_CCM_CCSR_STEP_SEL_OFFSET);
274
275                 __raw_writel(reg, MXC_CCM_CCSR);
276                 /* Switch to step_clk */
277                 reg = __raw_readl(MXC_CCM_CCSR);
278                 reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
279         }
280         __raw_writel(reg, MXC_CCM_CCSR);
281         return 0;
282 }
283
284 static unsigned long clk_pll1_sw_get_rate(struct clk *clk)
285 {
286         u32 reg, div;
287         unsigned long parent_rate;
288
289         parent_rate = clk_get_rate(clk->parent);
290
291         reg = __raw_readl(MXC_CCM_CCSR);
292
293         if (clk->parent == &pll2_sw_clk) {
294                 div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >>
295                        MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1;
296         } else if (clk->parent == &pll3_sw_clk) {
297                 div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >>
298                        MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1;
299         } else
300                 div = 1;
301         return parent_rate / div;
302 }
303
304 static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent)
305 {
306         u32 reg;
307
308         reg = __raw_readl(MXC_CCM_CCSR);
309
310         if (parent == &pll2_sw_clk)
311                 reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
312         else
313                 reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
314
315         __raw_writel(reg, MXC_CCM_CCSR);
316         return 0;
317 }
318
319 static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent)
320 {
321         u32 reg;
322
323         if (parent == &osc_clk)
324                 reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL;
325         else
326                 return -EINVAL;
327
328         __raw_writel(reg, MXC_CCM_CCSR);
329
330         return 0;
331 }
332
333 static unsigned long clk_arm_get_rate(struct clk *clk)
334 {
335         u32 cacrr, div;
336         unsigned long parent_rate;
337
338         parent_rate = clk_get_rate(clk->parent);
339         cacrr = __raw_readl(MXC_CCM_CACRR);
340         div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1;
341
342         return parent_rate / div;
343 }
344
345 static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent)
346 {
347         u32 reg, mux;
348         int i = 0;
349
350         mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL);
351
352         reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK;
353         reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET;
354         __raw_writel(reg, MXC_CCM_CBCMR);
355
356         /* Wait for lock */
357         do {
358                 reg = __raw_readl(MXC_CCM_CDHIPR);
359                 if (!(reg &  MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY))
360                         break;
361
362                 udelay(1);
363         } while (++i < MAX_DPLL_WAIT_TRIES);
364
365         if (i == MAX_DPLL_WAIT_TRIES) {
366                 pr_err("MX5: Set parent for periph_apm clock failed\n");
367                 return -EINVAL;
368         }
369
370         return 0;
371 }
372
373 static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent)
374 {
375         u32 reg;
376
377         reg = __raw_readl(MXC_CCM_CBCDR);
378
379         if (parent == &pll2_sw_clk)
380                 reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
381         else if (parent == &periph_apm_clk)
382                 reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL;
383         else
384                 return -EINVAL;
385
386         __raw_writel(reg, MXC_CCM_CBCDR);
387
388         return 0;
389 }
390
391 static struct clk main_bus_clk = {
392         .parent = &pll2_sw_clk,
393         .set_parent = _clk_main_bus_set_parent,
394 };
395
396 static unsigned long clk_ahb_get_rate(struct clk *clk)
397 {
398         u32 reg, div;
399         unsigned long parent_rate;
400
401         parent_rate = clk_get_rate(clk->parent);
402
403         reg = __raw_readl(MXC_CCM_CBCDR);
404         div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
405                MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
406         return parent_rate / div;
407 }
408
409
410 static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
411 {
412         u32 reg, div;
413         unsigned long parent_rate;
414         int i = 0;
415
416         parent_rate = clk_get_rate(clk->parent);
417
418         div = parent_rate / rate;
419         if (div > 8 || div < 1 || ((parent_rate / div) != rate))
420                 return -EINVAL;
421
422         reg = __raw_readl(MXC_CCM_CBCDR);
423         reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
424         reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;
425         __raw_writel(reg, MXC_CCM_CBCDR);
426
427         /* Wait for lock */
428         do {
429                 reg = __raw_readl(MXC_CCM_CDHIPR);
430                 if (!(reg & MXC_CCM_CDHIPR_AHB_PODF_BUSY))
431                         break;
432
433                 udelay(1);
434         } while (++i < MAX_DPLL_WAIT_TRIES);
435
436         if (i == MAX_DPLL_WAIT_TRIES) {
437                 pr_err("MX5: clk_ahb_set_rate failed\n");
438                 return -EINVAL;
439         }
440
441         return 0;
442 }
443
444 static unsigned long _clk_ahb_round_rate(struct clk *clk,
445                                                 unsigned long rate)
446 {
447         u32 div;
448         unsigned long parent_rate;
449
450         parent_rate = clk_get_rate(clk->parent);
451
452         div = parent_rate / rate;
453         if (div > 8)
454                 div = 8;
455         else if (div == 0)
456                 div++;
457         return parent_rate / div;
458 }
459
460
461 static int _clk_max_enable(struct clk *clk)
462 {
463         u32 reg;
464
465         _clk_ccgr_enable(clk);
466
467         /* Handshake with MAX when LPM is entered. */
468         reg = __raw_readl(MXC_CCM_CLPCR);
469         reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS;
470         __raw_writel(reg, MXC_CCM_CLPCR);
471
472         return 0;
473 }
474
475 static void _clk_max_disable(struct clk *clk)
476 {
477         u32 reg;
478
479         _clk_ccgr_disable_inwait(clk);
480
481         /* No Handshake with MAX when LPM is entered as its disabled. */
482         reg = __raw_readl(MXC_CCM_CLPCR);
483         reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS;
484         __raw_writel(reg, MXC_CCM_CLPCR);
485 }
486
487 static unsigned long clk_ipg_get_rate(struct clk *clk)
488 {
489         u32 reg, div;
490         unsigned long parent_rate;
491
492         parent_rate = clk_get_rate(clk->parent);
493
494         reg = __raw_readl(MXC_CCM_CBCDR);
495         div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
496                MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
497
498         return parent_rate / div;
499 }
500
501 static unsigned long clk_ipg_per_get_rate(struct clk *clk)
502 {
503         u32 reg, prediv1, prediv2, podf;
504         unsigned long parent_rate;
505
506         parent_rate = clk_get_rate(clk->parent);
507
508         if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) {
509                 /* the main_bus_clk is the one before the DVFS engine */
510                 reg = __raw_readl(MXC_CCM_CBCDR);
511                 prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
512                            MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1;
513                 prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
514                            MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1;
515                 podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
516                         MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1;
517                 return parent_rate / (prediv1 * prediv2 * podf);
518         } else if (clk->parent == &ipg_clk)
519                 return parent_rate;
520         else
521                 BUG();
522 }
523
524 static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent)
525 {
526         u32 reg;
527
528         reg = __raw_readl(MXC_CCM_CBCMR);
529
530         reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
531         reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
532
533         if (parent == &ipg_clk)
534                 reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
535         else if (parent == &lp_apm_clk)
536                 reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
537         else if (parent != &main_bus_clk)
538                 return -EINVAL;
539
540         __raw_writel(reg, MXC_CCM_CBCMR);
541
542         return 0;
543 }
544
545 static unsigned long clk_uart_get_rate(struct clk *clk)
546 {
547         u32 reg, prediv, podf;
548         unsigned long parent_rate;
549
550         parent_rate = clk_get_rate(clk->parent);
551
552         reg = __raw_readl(MXC_CCM_CSCDR1);
553         prediv = ((reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
554                   MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1;
555         podf = ((reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
556                 MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
557
558         return parent_rate / (prediv * podf);
559 }
560
561 static int _clk_uart_set_parent(struct clk *clk, struct clk *parent)
562 {
563         u32 reg, mux;
564
565         mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
566                        &lp_apm_clk);
567         reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_UART_CLK_SEL_MASK;
568         reg |= mux << MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET;
569         __raw_writel(reg, MXC_CCM_CSCMR1);
570
571         return 0;
572 }
573
574 static unsigned long clk_usboh3_get_rate(struct clk *clk)
575 {
576         u32 reg, prediv, podf;
577         unsigned long parent_rate;
578
579         parent_rate = clk_get_rate(clk->parent);
580
581         reg = __raw_readl(MXC_CCM_CSCDR1);
582         prediv = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK) >>
583                   MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET) + 1;
584         podf = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK) >>
585                 MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET) + 1;
586
587         return parent_rate / (prediv * podf);
588 }
589
590 static int _clk_usboh3_set_parent(struct clk *clk, struct clk *parent)
591 {
592         u32 reg, mux;
593
594         mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
595                        &lp_apm_clk);
596         reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK;
597         reg |= mux << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET;
598         __raw_writel(reg, MXC_CCM_CSCMR1);
599
600         return 0;
601 }
602
603 static unsigned long get_high_reference_clock_rate(struct clk *clk)
604 {
605         return external_high_reference;
606 }
607
608 static unsigned long get_low_reference_clock_rate(struct clk *clk)
609 {
610         return external_low_reference;
611 }
612
613 static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
614 {
615         return oscillator_reference;
616 }
617
618 static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
619 {
620         return ckih2_reference;
621 }
622
623 /* External high frequency clock */
624 static struct clk ckih_clk = {
625         .get_rate = get_high_reference_clock_rate,
626 };
627
628 static struct clk ckih2_clk = {
629         .get_rate = get_ckih2_reference_clock_rate,
630 };
631
632 static struct clk osc_clk = {
633         .get_rate = get_oscillator_reference_clock_rate,
634 };
635
636 /* External low frequency (32kHz) clock */
637 static struct clk ckil_clk = {
638         .get_rate = get_low_reference_clock_rate,
639 };
640
641 static struct clk pll1_main_clk = {
642         .parent = &osc_clk,
643         .get_rate = clk_pll_get_rate,
644         .enable = _clk_pll_enable,
645         .disable = _clk_pll_disable,
646 };
647
648 /* Clock tree block diagram (WIP):
649  *      CCM: Clock Controller Module
650  *
651  * PLL output -> |
652  *               | CCM Switcher -> CCM_CLK_ROOT_GEN ->
653  * PLL bypass -> |
654  *
655  */
656
657 /* PLL1 SW supplies to ARM core */
658 static struct clk pll1_sw_clk = {
659         .parent = &pll1_main_clk,
660         .set_parent = _clk_pll1_sw_set_parent,
661         .get_rate = clk_pll1_sw_get_rate,
662 };
663
664 /* PLL2 SW supplies to AXI/AHB/IP buses */
665 static struct clk pll2_sw_clk = {
666         .parent = &osc_clk,
667         .get_rate = clk_pll_get_rate,
668         .set_rate = _clk_pll_set_rate,
669         .set_parent = _clk_pll2_sw_set_parent,
670         .enable = _clk_pll_enable,
671         .disable = _clk_pll_disable,
672 };
673
674 /* PLL3 SW supplies to serial clocks like USB, SSI, etc. */
675 static struct clk pll3_sw_clk = {
676         .parent = &osc_clk,
677         .set_rate = _clk_pll_set_rate,
678         .get_rate = clk_pll_get_rate,
679         .enable = _clk_pll_enable,
680         .disable = _clk_pll_disable,
681 };
682
683 /* Low-power Audio Playback Mode clock */
684 static struct clk lp_apm_clk = {
685         .parent = &osc_clk,
686         .set_parent = _clk_lp_apm_set_parent,
687 };
688
689 static struct clk periph_apm_clk = {
690         .parent = &pll1_sw_clk,
691         .set_parent = _clk_periph_apm_set_parent,
692 };
693
694 static struct clk cpu_clk = {
695         .parent = &pll1_sw_clk,
696         .get_rate = clk_arm_get_rate,
697 };
698
699 static struct clk ahb_clk = {
700         .parent = &main_bus_clk,
701         .get_rate = clk_ahb_get_rate,
702         .set_rate = _clk_ahb_set_rate,
703         .round_rate = _clk_ahb_round_rate,
704 };
705
706 /* Main IP interface clock for access to registers */
707 static struct clk ipg_clk = {
708         .parent = &ahb_clk,
709         .get_rate = clk_ipg_get_rate,
710 };
711
712 static struct clk ipg_perclk = {
713         .parent = &lp_apm_clk,
714         .get_rate = clk_ipg_per_get_rate,
715         .set_parent = _clk_ipg_per_set_parent,
716 };
717
718 static struct clk uart_root_clk = {
719         .parent = &pll2_sw_clk,
720         .get_rate = clk_uart_get_rate,
721         .set_parent = _clk_uart_set_parent,
722 };
723
724 static struct clk usboh3_clk = {
725         .parent = &pll2_sw_clk,
726         .get_rate = clk_usboh3_get_rate,
727         .set_parent = _clk_usboh3_set_parent,
728 };
729
730 static struct clk ahb_max_clk = {
731         .parent = &ahb_clk,
732         .enable_reg = MXC_CCM_CCGR0,
733         .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
734         .enable = _clk_max_enable,
735         .disable = _clk_max_disable,
736 };
737
738 static struct clk aips_tz1_clk = {
739         .parent = &ahb_clk,
740         .secondary = &ahb_max_clk,
741         .enable_reg = MXC_CCM_CCGR0,
742         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
743         .enable = _clk_ccgr_enable,
744         .disable = _clk_ccgr_disable_inwait,
745 };
746
747 static struct clk aips_tz2_clk = {
748         .parent = &ahb_clk,
749         .secondary = &ahb_max_clk,
750         .enable_reg = MXC_CCM_CCGR0,
751         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
752         .enable = _clk_ccgr_enable,
753         .disable = _clk_ccgr_disable_inwait,
754 };
755
756 static struct clk gpt_32k_clk = {
757         .id = 0,
758         .parent = &ckil_clk,
759 };
760
761 #define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)     \
762         static struct clk name = {                      \
763                 .id             = i,                    \
764                 .enable_reg     = er,                   \
765                 .enable_shift   = es,                   \
766                 .get_rate       = gr,                   \
767                 .set_rate       = sr,                   \
768                 .enable         = _clk_ccgr_enable,     \
769                 .disable        = _clk_ccgr_disable,    \
770                 .parent         = p,                    \
771                 .secondary      = s,                    \
772         }
773
774 /* DEFINE_CLOCK(name, id, enable_reg, enable_shift,
775    get_rate, set_rate, parent, secondary); */
776
777 /* Shared peripheral bus arbiter */
778 DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET,
779         NULL,  NULL, &ipg_clk, NULL);
780
781 /* UART */
782 DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET,
783         NULL,  NULL, &uart_root_clk, NULL);
784 DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET,
785         NULL,  NULL, &uart_root_clk, NULL);
786 DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET,
787         NULL,  NULL, &uart_root_clk, NULL);
788 DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET,
789         NULL,  NULL, &ipg_clk, &aips_tz1_clk);
790 DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET,
791         NULL,  NULL, &ipg_clk, &aips_tz1_clk);
792 DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET,
793         NULL,  NULL, &ipg_clk, &spba_clk);
794
795 /* GPT */
796 DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
797         NULL,  NULL, &ipg_clk, NULL);
798 DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
799         NULL,  NULL, &ipg_clk, NULL);
800
801 /* FEC */
802 DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
803         NULL,  NULL, &ipg_clk, NULL);
804
805 #define _REGISTER_CLOCK(d, n, c) \
806        { \
807                 .dev_id = d, \
808                 .con_id = n, \
809                 .clk = &c,   \
810        },
811
812 static struct clk_lookup lookups[] = {
813         _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
814         _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
815         _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
816         _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
817         _REGISTER_CLOCK("fec.0", NULL, fec_clk)
818         _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk)
819         _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", ahb_clk)
820         _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk)
821         _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk)
822         _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
823         _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
824 };
825
826 static void clk_tree_init(void)
827 {
828         u32 reg;
829
830         ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk);
831
832         /*
833          * Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at
834          * 8MHz, its derived from lp_apm.
835          *
836          * FIXME: Verify if true for all boards
837          */
838         reg = __raw_readl(MXC_CCM_CBCDR);
839         reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK;
840         reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK;
841         reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK;
842         reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET);
843         __raw_writel(reg, MXC_CCM_CBCDR);
844 }
845
846 int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
847                         unsigned long ckih1, unsigned long ckih2)
848 {
849         int i;
850
851         external_low_reference = ckil;
852         external_high_reference = ckih1;
853         ckih2_reference = ckih2;
854         oscillator_reference = osc;
855
856         for (i = 0; i < ARRAY_SIZE(lookups); i++)
857                 clkdev_add(&lookups[i]);
858
859         clk_tree_init();
860
861         clk_enable(&cpu_clk);
862         clk_enable(&main_bus_clk);
863
864         /* set the usboh3_clk parent to pll2_sw_clk */
865         clk_set_parent(&usboh3_clk, &pll2_sw_clk);
866
867         /* System timer */
868         mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
869                 MX51_MXC_INT_GPT);
870         return 0;
871 }