arch/arm/mach-mx3/mach-mx31ads.c

   1 /*
   2  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   3  *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
   4  *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/types.h>
  18 #include <linux/init.h>
  19 #include <linux/clk.h>
  20 #include <linux/serial_8250.h>
  21 #include <linux/gpio.h>
  22 #include <linux/i2c.h>
  23 #include <linux/irq.h>
  24
  25 #include <mach/hardware.h>
  26 #include <asm/mach-types.h>
  27 #include <asm/mach/arch.h>
  28 #include <asm/mach/time.h>
  29 #include <asm/memory.h>
  30 #include <asm/mach/map.h>
  31 #include <mach/common.h>
  32 #include <mach/iomux-mx3.h>
  33
  34 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
  35 #include <linux/mfd/wm8350/audio.h>
  36 #include <linux/mfd/wm8350/core.h>
  37 #include <linux/mfd/wm8350/pmic.h>
  38 #endif
  39
  40 #include "devices-imx31.h"
  41 #include "devices.h"
  42
  43 /* Base address of PBC controller */
  44 #define PBC_BASE_ADDRESS        MX31_CS4_BASE_ADDR_VIRT
  45 /* Offsets for the PBC Controller register */
  46
  47 /* PBC Board interrupt status register */
  48 #define PBC_INTSTATUS           0x000016
  49
  50 /* PBC Board interrupt current status register */
  51 #define PBC_INTCURR_STATUS      0x000018
  52
  53 /* PBC Interrupt mask register set address */
  54 #define PBC_INTMASK_SET         0x00001A
  55
  56 /* PBC Interrupt mask register clear address */
  57 #define PBC_INTMASK_CLEAR       0x00001C
  58
  59 /* External UART A */
  60 #define PBC_SC16C652_UARTA      0x010000
  61
  62 /* External UART B */
  63 #define PBC_SC16C652_UARTB      0x010010
  64
  65 #define PBC_INTSTATUS_REG       (PBC_INTSTATUS + PBC_BASE_ADDRESS)
  66 #define PBC_INTMASK_SET_REG     (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
  67 #define PBC_INTMASK_CLEAR_REG   (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
  68 #define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
  69
  70 #define MXC_EXP_IO_BASE         (MXC_BOARD_IRQ_START)
  71 #define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_EXP_IO_BASE)
  72
  73 #define EXPIO_INT_XUART_INTA    (MXC_EXP_IO_BASE + 10)
  74 #define EXPIO_INT_XUART_INTB    (MXC_EXP_IO_BASE + 11)
  75
  76 #define MXC_MAX_EXP_IO_LINES    16
  77 /*
  78  * This file contains the board-specific initialization routines.
  79  */
  80
  81 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
  82 /*!
  83  * The serial port definition structure.
  84  */
  85 static struct plat_serial8250_port serial_platform_data[] = {
  86         {
  87                 .membase  = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
  88                 .mapbase  = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA),
  89                 .irq      = EXPIO_INT_XUART_INTA,
  90                 .uartclk  = 14745600,
  91                 .regshift = 0,
  92                 .iotype   = UPIO_MEM,
  93                 .flags    = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
  94         }, {
  95                 .membase  = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
  96                 .mapbase  = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB),
  97                 .irq      = EXPIO_INT_XUART_INTB,
  98                 .uartclk  = 14745600,
  99                 .regshift = 0,
 100                 .iotype   = UPIO_MEM,
 101                 .flags    = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
 102         },
 103         {},
 104 };
 105
 106 static struct platform_device serial_device = {
 107         .name   = "serial8250",
 108         .id     = 0,
 109         .dev    = {
 110                 .platform_data = serial_platform_data,
 111         },
 112 };
 113
 114 static int __init mxc_init_extuart(void)
 115 {
 116         return platform_device_register(&serial_device);
 117 }
 118 #else
 119 static inline int mxc_init_extuart(void)
 120 {
 121         return 0;
 122 }
 123 #endif
 124
 125 #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
 126 static const struct imxuart_platform_data uart_pdata __initconst = {
 127         .flags = IMXUART_HAVE_RTSCTS,
 128 };
 129
 130 static unsigned int uart_pins[] = {
 131         MX31_PIN_CTS1__CTS1,
 132         MX31_PIN_RTS1__RTS1,
 133         MX31_PIN_TXD1__TXD1,
 134         MX31_PIN_RXD1__RXD1
 135 };
 136
 137 static inline void mxc_init_imx_uart(void)
 138 {
 139         mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
 140         imx31_add_imx_uart0(&uart_pdata);
 141 }
 142 #else /* !SERIAL_IMX */
 143 static inline void mxc_init_imx_uart(void)
 144 {
 145 }
 146 #endif /* !SERIAL_IMX */
 147
 148 static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
 149 {
 150         u32 imr_val;
 151         u32 int_valid;
 152         u32 expio_irq;
 153
 154         imr_val = __raw_readw(PBC_INTMASK_SET_REG);
 155         int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val;
 156
 157         expio_irq = MXC_EXP_IO_BASE;
 158         for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
 159                 if ((int_valid & 1) == 0)
 160                         continue;
 161
 162                 generic_handle_irq(expio_irq);
 163         }
 164 }
 165
 166 /*
 167  * Disable an expio pin's interrupt by setting the bit in the imr.
 168  * @param irq           an expio virtual irq number
 169  */
 170 static void expio_mask_irq(u32 irq)
 171 {
 172         u32 expio = MXC_IRQ_TO_EXPIO(irq);
 173         /* mask the interrupt */
 174         __raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
 175         __raw_readw(PBC_INTMASK_CLEAR_REG);
 176 }
 177
 178 /*
 179  * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
 180  * @param irq           an expanded io virtual irq number
 181  */
 182 static void expio_ack_irq(u32 irq)
 183 {
 184         u32 expio = MXC_IRQ_TO_EXPIO(irq);
 185         /* clear the interrupt status */
 186         __raw_writew(1 << expio, PBC_INTSTATUS_REG);
 187 }
 188
 189 /*
 190  * Enable a expio pin's interrupt by clearing the bit in the imr.
 191  * @param irq           a expio virtual irq number
 192  */
 193 static void expio_unmask_irq(u32 irq)
 194 {
 195         u32 expio = MXC_IRQ_TO_EXPIO(irq);
 196         /* unmask the interrupt */
 197         __raw_writew(1 << expio, PBC_INTMASK_SET_REG);
 198 }
 199
 200 static struct irq_chip expio_irq_chip = {
 201         .name = "EXPIO(CPLD)",
 202         .ack = expio_ack_irq,
 203         .mask = expio_mask_irq,
 204         .unmask = expio_unmask_irq,
 205 };
 206
 207 static void __init mx31ads_init_expio(void)
 208 {
 209         int i;
 210
 211         printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");
 212
 213         /*
 214          * Configure INT line as GPIO input
 215          */
 216         mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");
 217
 218         /* disable the interrupt and clear the status */
 219         __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
 220         __raw_writew(0xFFFF, PBC_INTSTATUS_REG);
 221         for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
 222              i++) {
 223                 set_irq_chip(i, &expio_irq_chip);
 224                 set_irq_handler(i, handle_level_irq);
 225                 set_irq_flags(i, IRQF_VALID);
 226         }
 227         set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
 228         set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
 229 }
 230
 231 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
 232 /* This section defines setup for the Wolfson Microelectronics
 233  * 1133-EV1 PMU/audio board.  When other PMU boards are supported the
 234  * regulator definitions may be shared with them, but for now they can
 235  * only be used with this board so would generate warnings about
 236  * unused statics and some of the configuration is specific to this
 237  * module.
 238  */
 239
 240 /* CPU */
 241 static struct regulator_consumer_supply sw1a_consumers[] = {
 242         {
 243                 .supply = "cpu_vcc",
 244         }
 245 };
 246
 247 static struct regulator_init_data sw1a_data = {
 248         .constraints = {
 249                 .name = "SW1A",
 250                 .min_uV = 1275000,
 251                 .max_uV = 1600000,
 252                 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
 253                                   REGULATOR_CHANGE_MODE,
 254                 .valid_modes_mask = REGULATOR_MODE_NORMAL |
 255                                     REGULATOR_MODE_FAST,
 256                 .state_mem = {
 257                          .uV = 1400000,
 258                          .mode = REGULATOR_MODE_NORMAL,
 259                          .enabled = 1,
 260                  },
 261                 .initial_state = PM_SUSPEND_MEM,
 262                 .always_on = 1,
 263                 .boot_on = 1,
 264         },
 265         .num_consumer_supplies = ARRAY_SIZE(sw1a_consumers),
 266         .consumer_supplies = sw1a_consumers,
 267 };
 268
 269 /* System IO - High */
 270 static struct regulator_init_data viohi_data = {
 271         .constraints = {
 272                 .name = "VIOHO",
 273                 .min_uV = 2800000,
 274                 .max_uV = 2800000,
 275                 .state_mem = {
 276                          .uV = 2800000,
 277                          .mode = REGULATOR_MODE_NORMAL,
 278                          .enabled = 1,
 279                  },
 280                 .initial_state = PM_SUSPEND_MEM,
 281                 .always_on = 1,
 282                 .boot_on = 1,
 283         },
 284 };
 285
 286 /* System IO - Low */
 287 static struct regulator_init_data violo_data = {
 288         .constraints = {
 289                 .name = "VIOLO",
 290                 .min_uV = 1800000,
 291                 .max_uV = 1800000,
 292                 .state_mem = {
 293                          .uV = 1800000,
 294                          .mode = REGULATOR_MODE_NORMAL,
 295                          .enabled = 1,
 296                  },
 297                 .initial_state = PM_SUSPEND_MEM,
 298                 .always_on = 1,
 299                 .boot_on = 1,
 300         },
 301 };
 302
 303 /* DDR RAM */
 304 static struct regulator_init_data sw2a_data = {
 305         .constraints = {
 306                 .name = "SW2A",
 307                 .min_uV = 1800000,
 308                 .max_uV = 1800000,
 309                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
 310                 .state_mem = {
 311                          .uV = 1800000,
 312                          .mode = REGULATOR_MODE_NORMAL,
 313                          .enabled = 1,
 314                  },
 315                 .state_disk = {
 316                          .mode = REGULATOR_MODE_NORMAL,
 317                          .enabled = 0,
 318                  },
 319                 .always_on = 1,
 320                 .boot_on = 1,
 321                 .initial_state = PM_SUSPEND_MEM,
 322         },
 323 };
 324
 325 static struct regulator_init_data ldo1_data = {
 326         .constraints = {
 327                 .name = "VCAM/VMMC1/VMMC2",
 328                 .min_uV = 2800000,
 329                 .max_uV = 2800000,
 330                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
 331                 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
 332                 .apply_uV = 1,
 333         },
 334 };
 335
 336 static struct regulator_consumer_supply ldo2_consumers[] = {
 337         { .supply = "AVDD", .dev_name = "1-001a" },
 338         { .supply = "HPVDD", .dev_name = "1-001a" },
 339 };
 340
 341 /* CODEC and SIM */
 342 static struct regulator_init_data ldo2_data = {
 343         .constraints = {
 344                 .name = "VESIM/VSIM/AVDD",
 345                 .min_uV = 3300000,
 346                 .max_uV = 3300000,
 347                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
 348                 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
 349                 .apply_uV = 1,
 350         },
 351         .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
 352         .consumer_supplies = ldo2_consumers,
 353 };
 354
 355 /* General */
 356 static struct regulator_init_data vdig_data = {
 357         .constraints = {
 358                 .name = "VDIG",
 359                 .min_uV = 1500000,
 360                 .max_uV = 1500000,
 361                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
 362                 .apply_uV = 1,
 363                 .always_on = 1,
 364                 .boot_on = 1,
 365         },
 366 };
 367
 368 /* Tranceivers */
 369 static struct regulator_init_data ldo4_data = {
 370         .constraints = {
 371                 .name = "VRF1/CVDD_2.775",
 372                 .min_uV = 2500000,
 373                 .max_uV = 2500000,
 374                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
 375                 .apply_uV = 1,
 376                 .always_on = 1,
 377                 .boot_on = 1,
 378         },
 379 };
 380
 381 static struct wm8350_led_platform_data wm8350_led_data = {
 382         .name            = "wm8350:white",
 383         .default_trigger = "heartbeat",
 384         .max_uA          = 27899,
 385 };
 386
 387 static struct wm8350_audio_platform_data imx32ads_wm8350_setup = {
 388         .vmid_discharge_msecs = 1000,
 389         .drain_msecs = 30,
 390         .cap_discharge_msecs = 700,
 391         .vmid_charge_msecs = 700,
 392         .vmid_s_curve = WM8350_S_CURVE_SLOW,
 393         .dis_out4 = WM8350_DISCHARGE_SLOW,
 394         .dis_out3 = WM8350_DISCHARGE_SLOW,
 395         .dis_out2 = WM8350_DISCHARGE_SLOW,
 396         .dis_out1 = WM8350_DISCHARGE_SLOW,
 397         .vroi_out4 = WM8350_TIE_OFF_500R,
 398         .vroi_out3 = WM8350_TIE_OFF_500R,
 399         .vroi_out2 = WM8350_TIE_OFF_500R,
 400         .vroi_out1 = WM8350_TIE_OFF_500R,
 401         .vroi_enable = 0,
 402         .codec_current_on = WM8350_CODEC_ISEL_1_0,
 403         .codec_current_standby = WM8350_CODEC_ISEL_0_5,
 404         .codec_current_charge = WM8350_CODEC_ISEL_1_5,
 405 };
 406
 407 static int mx31_wm8350_init(struct wm8350 *wm8350)
 408 {
 409         wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN,
 410                            WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW,
 411                            WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF,
 412                            WM8350_GPIO_DEBOUNCE_ON);
 413
 414         wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN,
 415                            WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH,
 416                            WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
 417                            WM8350_GPIO_DEBOUNCE_ON);
 418
 419         wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN,
 420                            WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH,
 421                            WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
 422                            WM8350_GPIO_DEBOUNCE_OFF);
 423
 424         wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN,
 425                            WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH,
 426                            WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
 427                            WM8350_GPIO_DEBOUNCE_OFF);
 428
 429         wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT,
 430                            WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH,
 431                            WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
 432                            WM8350_GPIO_DEBOUNCE_OFF);
 433
 434         wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT,
 435                            WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
 436                            WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
 437                            WM8350_GPIO_DEBOUNCE_OFF);
 438
 439         wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT,
 440                            WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
 441                            WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
 442                            WM8350_GPIO_DEBOUNCE_OFF);
 443
 444         wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data);
 445         wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data);
 446         wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data);
 447         wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data);
 448         wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data);
 449         wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data);
 450         wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data);
 451         wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data);
 452
 453         /* LEDs */
 454         wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1,
 455                              WM8350_DC5_ERRACT_SHUTDOWN_CONV);
 456         wm8350_isink_set_flash(wm8350, WM8350_ISINK_A,
 457                                WM8350_ISINK_FLASH_DISABLE,
 458                                WM8350_ISINK_FLASH_TRIG_BIT,
 459                                WM8350_ISINK_FLASH_DUR_32MS,
 460                                WM8350_ISINK_FLASH_ON_INSTANT,
 461                                WM8350_ISINK_FLASH_OFF_INSTANT,
 462                                WM8350_ISINK_FLASH_MODE_EN);
 463         wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5,
 464                                WM8350_ISINK_MODE_BOOST,
 465                                WM8350_ISINK_ILIM_NORMAL,
 466                                WM8350_DC5_RMP_20V,
 467                                WM8350_DC5_FBSRC_ISINKA);
 468         wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A,
 469                             &wm8350_led_data);
 470
 471         wm8350->codec.platform_data = &imx32ads_wm8350_setup;
 472
 473         regulator_has_full_constraints();
 474
 475         return 0;
 476 }
 477
 478 static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
 479         .init = mx31_wm8350_init,
 480         .irq_base = MXC_BOARD_IRQ_START + MXC_MAX_EXP_IO_LINES,
 481 };
 482 #endif
 483
 484 #if defined(CONFIG_I2C_IMX) || defined(CONFIG_I2C_IMX_MODULE)
 485 static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
 486 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
 487         {
 488                 I2C_BOARD_INFO("wm8350", 0x1a),
 489                 .platform_data = &mx31_wm8350_pdata,
 490                 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
 491         },
 492 #endif
 493 };
 494
 495 static void mxc_init_i2c(void)
 496 {
 497         i2c_register_board_info(1, mx31ads_i2c1_devices,
 498                                 ARRAY_SIZE(mx31ads_i2c1_devices));
 499
 500         mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
 501         mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));
 502
 503         imx31_add_imx_i2c1(NULL);
 504 }
 505 #else
 506 static void mxc_init_i2c(void)
 507 {
 508 }
 509 #endif
 510
 511 static unsigned int ssi_pins[] = {
 512         MX31_PIN_SFS5__SFS5,
 513         MX31_PIN_SCK5__SCK5,
 514         MX31_PIN_SRXD5__SRXD5,
 515         MX31_PIN_STXD5__STXD5,
 516 };
 517
 518 static void mxc_init_audio(void)
 519 {
 520         mxc_register_device(&imx_ssi_device0, NULL);
 521         mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
 522 }
 523
 524 /*!
 525  * This structure defines static mappings for the i.MX31ADS board.
 526  */
 527 static struct map_desc mx31ads_io_desc[] __initdata = {
 528         {
 529                 .virtual        = MX31_CS4_BASE_ADDR_VIRT,
 530                 .pfn            = __phys_to_pfn(MX31_CS4_BASE_ADDR),
 531                 .length         = MX31_CS4_SIZE / 2,
 532                 .type           = MT_DEVICE
 533         },
 534 };
 535
 536 /*!
 537  * Set up static virtual mappings.
 538  */
 539 static void __init mx31ads_map_io(void)
 540 {
 541         mx31_map_io();
 542         iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
 543 }
 544
 545 static void __init mx31ads_init_irq(void)
 546 {
 547         mx31_init_irq();
 548         mx31ads_init_expio();
 549 }
 550
 551 /*!
 552  * Board specific initialization.
 553  */
 554 static void __init mxc_board_init(void)
 555 {
 556         mxc_init_extuart();
 557         mxc_init_imx_uart();
 558         mxc_init_i2c();
 559         mxc_init_audio();
 560 }
 561
 562 static void __init mx31ads_timer_init(void)
 563 {
 564         mx31_clocks_init(26000000);
 565 }
 566
 567 static struct sys_timer mx31ads_timer = {
 568         .init   = mx31ads_timer_init,
 569 };
 570
 571 /*
 572  * The following uses standard kernel macros defined in arch.h in order to
 573  * initialize __mach_desc_MX31ADS data structure.
 574  */
 575 MACHINE_START(MX31ADS, "Freescale MX31ADS")
 576         /* Maintainer: Freescale Semiconductor, Inc. */
 577         .phys_io        = MX31_AIPS1_BASE_ADDR,
 578         .io_pg_offst    = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
 579         .boot_params    = MX3x_PHYS_OFFSET + 0x100,
 580         .map_io         = mx31ads_map_io,
 581         .init_irq       = mx31ads_init_irq,
 582         .init_machine   = mxc_board_init,
 583         .timer          = &mx31ads_timer,
 584 MACHINE_END