2 * arch/arm/mach-ixp4xx/common.c
4 * Generic code shared across all IXP4XX platforms
6 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
8 * Copyright 2002 (c) Intel Corporation
9 * Copyright 2003-2004 (c) MontaVista, Software, Inc.
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
16 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/serial.h>
20 #include <linux/tty.h>
21 #include <linux/platform_device.h>
22 #include <linux/serial_core.h>
23 #include <linux/interrupt.h>
24 #include <linux/bitops.h>
25 #include <linux/time.h>
26 #include <linux/clocksource.h>
27 #include <linux/clockchips.h>
29 #include <linux/export.h>
30 #include <linux/cpu.h>
31 #include <linux/pci.h>
32 #include <linux/sched_clock.h>
33 #include <linux/bitops.h>
34 #include <linux/irqchip/irq-ixp4xx.h>
36 #include <mach/hardware.h>
38 #include <linux/uaccess.h>
39 #include <asm/pgtable.h>
41 #include <asm/exception.h>
43 #include <asm/system_misc.h>
44 #include <asm/mach/map.h>
45 #include <asm/mach/irq.h>
46 #include <asm/mach/time.h>
50 #define IXP4XX_TIMER_FREQ 66666000
53 * The timer register doesn't allow to specify the two least significant bits of
54 * the timeout value and assumes them being zero. So make sure IXP4XX_LATCH is
55 * the best value with the two least significant bits unset.
57 #define IXP4XX_LATCH DIV_ROUND_CLOSEST(IXP4XX_TIMER_FREQ, \
58 (IXP4XX_OST_RELOAD_MASK + 1) * HZ) * \
59 (IXP4XX_OST_RELOAD_MASK + 1)
61 static void __init ixp4xx_clocksource_init(void);
62 static void __init ixp4xx_clockevent_init(void);
63 static struct clock_event_device clockevent_ixp4xx;
65 /*************************************************************************
66 * IXP4xx chipset I/O mapping
67 *************************************************************************/
68 static struct map_desc ixp4xx_io_desc[] __initdata = {
69 { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
70 .virtual = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT,
71 .pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
72 .length = IXP4XX_PERIPHERAL_REGION_SIZE,
74 }, { /* Expansion Bus Config Registers */
75 .virtual = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT,
76 .pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
77 .length = IXP4XX_EXP_CFG_REGION_SIZE,
79 }, { /* PCI Registers */
80 .virtual = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT,
81 .pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
82 .length = IXP4XX_PCI_CFG_REGION_SIZE,
84 }, { /* Queue Manager */
85 .virtual = (unsigned long)IXP4XX_QMGR_BASE_VIRT,
86 .pfn = __phys_to_pfn(IXP4XX_QMGR_BASE_PHYS),
87 .length = IXP4XX_QMGR_REGION_SIZE,
92 void __init ixp4xx_map_io(void)
94 iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
97 void __init ixp4xx_init_irq(void)
100 * ixp4xx does not implement the XScale PWRMODE register
101 * so it must not call cpu_do_idle().
103 cpu_idle_poll_ctrl(true);
105 ixp4xx_irq_init(IXP4XX_INTC_BASE_PHYS,
106 (cpu_is_ixp46x() || cpu_is_ixp43x()));
109 /*************************************************************************
111 * We use OS timer1 on the CPU for the timer tick and the timestamp
112 * counter as a source of real clock ticks to account for missed jiffies.
113 *************************************************************************/
115 static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
117 struct clock_event_device *evt = dev_id;
119 /* Clear Pending Interrupt by writing '1' to it */
120 *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
122 evt->event_handler(evt);
127 void __init ixp4xx_timer_init(void)
129 /* Reset/disable counter */
132 /* Clear Pending Interrupt by writing '1' to it */
133 *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
135 /* Reset time-stamp counter */
138 ixp4xx_clocksource_init();
139 ixp4xx_clockevent_init();
142 static struct pxa2xx_udc_mach_info ixp4xx_udc_info;
144 void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info)
146 memcpy(&ixp4xx_udc_info, info, sizeof *info);
149 static struct resource ixp4xx_udc_resources[] = {
153 .flags = IORESOURCE_MEM,
156 .start = IRQ_IXP4XX_USB,
157 .end = IRQ_IXP4XX_USB,
158 .flags = IORESOURCE_IRQ,
162 static struct resource ixp4xx_gpio_resource[] = {
164 .start = IXP4XX_GPIO_BASE_PHYS,
165 .end = IXP4XX_GPIO_BASE_PHYS + 0xfff,
166 .flags = IORESOURCE_MEM,
170 static struct platform_device ixp4xx_gpio_device = {
171 .name = "ixp4xx-gpio",
174 .coherent_dma_mask = DMA_BIT_MASK(32),
176 .resource = ixp4xx_gpio_resource,
177 .num_resources = ARRAY_SIZE(ixp4xx_gpio_resource),
181 * USB device controller. The IXP4xx uses the same controller as PXA25X,
182 * so we just use the same device.
184 static struct platform_device ixp4xx_udc_device = {
185 .name = "pxa25x-udc",
188 .resource = ixp4xx_udc_resources,
190 .platform_data = &ixp4xx_udc_info,
194 static struct platform_device *ixp4xx_devices[] __initdata = {
199 static struct resource ixp46x_i2c_resources[] = {
203 .flags = IORESOURCE_MEM,
206 .start = IRQ_IXP4XX_I2C,
207 .end = IRQ_IXP4XX_I2C,
208 .flags = IORESOURCE_IRQ
213 * I2C controller. The IXP46x uses the same block as the IOP3xx, so
214 * we just use the same device name.
216 static struct platform_device ixp46x_i2c_controller = {
217 .name = "IOP3xx-I2C",
220 .resource = ixp46x_i2c_resources
223 static struct platform_device *ixp46x_devices[] __initdata = {
224 &ixp46x_i2c_controller
227 unsigned long ixp4xx_exp_bus_size;
228 EXPORT_SYMBOL(ixp4xx_exp_bus_size);
230 void __init ixp4xx_sys_init(void)
232 ixp4xx_exp_bus_size = SZ_16M;
234 platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
236 if (cpu_is_ixp46x()) {
239 platform_add_devices(ixp46x_devices,
240 ARRAY_SIZE(ixp46x_devices));
242 for (region = 0; region < 7; region++) {
243 if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) {
244 ixp4xx_exp_bus_size = SZ_32M;
250 printk("IXP4xx: Using %luMiB expansion bus window size\n",
251 ixp4xx_exp_bus_size >> 20);
257 static u64 notrace ixp4xx_read_sched_clock(void)
266 static u64 ixp4xx_clocksource_read(struct clocksource *c)
271 unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;
272 EXPORT_SYMBOL(ixp4xx_timer_freq);
273 static void __init ixp4xx_clocksource_init(void)
275 sched_clock_register(ixp4xx_read_sched_clock, 32, ixp4xx_timer_freq);
277 clocksource_mmio_init(NULL, "OSTS", ixp4xx_timer_freq, 200, 32,
278 ixp4xx_clocksource_read);
284 static int ixp4xx_set_next_event(unsigned long evt,
285 struct clock_event_device *unused)
287 unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
289 *IXP4XX_OSRT1 = (evt & ~IXP4XX_OST_RELOAD_MASK) | opts;
294 static int ixp4xx_shutdown(struct clock_event_device *evt)
296 unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
297 unsigned long osrt = *IXP4XX_OSRT1 & ~IXP4XX_OST_RELOAD_MASK;
299 opts &= ~IXP4XX_OST_ENABLE;
300 *IXP4XX_OSRT1 = osrt | opts;
304 static int ixp4xx_set_oneshot(struct clock_event_device *evt)
306 unsigned long opts = IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT;
307 unsigned long osrt = 0;
309 /* period set by 'set next_event' */
310 *IXP4XX_OSRT1 = osrt | opts;
314 static int ixp4xx_set_periodic(struct clock_event_device *evt)
316 unsigned long opts = IXP4XX_OST_ENABLE;
317 unsigned long osrt = IXP4XX_LATCH & ~IXP4XX_OST_RELOAD_MASK;
319 *IXP4XX_OSRT1 = osrt | opts;
323 static int ixp4xx_resume(struct clock_event_device *evt)
325 unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
326 unsigned long osrt = *IXP4XX_OSRT1 & ~IXP4XX_OST_RELOAD_MASK;
328 opts |= IXP4XX_OST_ENABLE;
329 *IXP4XX_OSRT1 = osrt | opts;
333 static struct clock_event_device clockevent_ixp4xx = {
334 .name = "ixp4xx timer1",
335 .features = CLOCK_EVT_FEAT_PERIODIC |
336 CLOCK_EVT_FEAT_ONESHOT,
338 .set_state_shutdown = ixp4xx_shutdown,
339 .set_state_periodic = ixp4xx_set_periodic,
340 .set_state_oneshot = ixp4xx_set_oneshot,
341 .tick_resume = ixp4xx_resume,
342 .set_next_event = ixp4xx_set_next_event,
345 static void __init ixp4xx_clockevent_init(void)
349 clockevent_ixp4xx.cpumask = cpumask_of(0);
350 clockevent_ixp4xx.irq = IRQ_IXP4XX_TIMER1;
351 ret = request_irq(IRQ_IXP4XX_TIMER1, ixp4xx_timer_interrupt,
352 IRQF_TIMER, "IXP4XX-TIMER1", &clockevent_ixp4xx);
354 pr_crit("no timer IRQ\n");
357 clockevents_config_and_register(&clockevent_ixp4xx, IXP4XX_TIMER_FREQ,
361 void ixp4xx_restart(enum reboot_mode mode, const char *cmd)
363 if (mode == REBOOT_SOFT) {
364 /* Jump into ROM at address 0 */
367 /* Use on-chip reset capability */
369 /* set the "key" register to enable access to
370 * "timer" and "enable" registers
372 *IXP4XX_OSWK = IXP4XX_WDT_KEY;
374 /* write 0 to the timer register for an immediate reset */
377 *IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;
382 static int ixp4xx_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
384 return (dma_addr + size) > SZ_64M;
387 static int ixp4xx_platform_notify_remove(struct device *dev)
390 dmabounce_unregister_dev(dev);
397 * Setup DMA mask to 64MB on PCI devices and 4 GB on all other things.
399 static int ixp4xx_platform_notify(struct device *dev)
401 dev->dma_mask = &dev->coherent_dma_mask;
404 if (dev_is_pci(dev)) {
405 dev->coherent_dma_mask = DMA_BIT_MASK(28); /* 64 MB */
406 dmabounce_register_dev(dev, 2048, 4096, ixp4xx_needs_bounce);
411 dev->coherent_dma_mask = DMA_BIT_MASK(32);
415 int dma_set_coherent_mask(struct device *dev, u64 mask)
418 mask &= DMA_BIT_MASK(28); /* 64 MB */
420 if ((mask & DMA_BIT_MASK(28)) == DMA_BIT_MASK(28)) {
421 dev->coherent_dma_mask = mask;
425 return -EIO; /* device wanted sub-64MB mask */
427 EXPORT_SYMBOL(dma_set_coherent_mask);
429 #ifdef CONFIG_IXP4XX_INDIRECT_PCI
431 * In the case of using indirect PCI, we simply return the actual PCI
432 * address and our read/write implementation use that to drive the
433 * access registers. If something outside of PCI is ioremap'd, we
434 * fallback to the default.
437 static void __iomem *ixp4xx_ioremap_caller(phys_addr_t addr, size_t size,
438 unsigned int mtype, void *caller)
440 if (!is_pci_memory(addr))
441 return __arm_ioremap_caller(addr, size, mtype, caller);
443 return (void __iomem *)addr;
446 static void ixp4xx_iounmap(volatile void __iomem *addr)
448 if (!is_pci_memory((__force u32)addr))
453 void __init ixp4xx_init_early(void)
455 platform_notify = ixp4xx_platform_notify;
457 platform_notify_remove = ixp4xx_platform_notify_remove;
459 #ifdef CONFIG_IXP4XX_INDIRECT_PCI
460 arch_ioremap_caller = ixp4xx_ioremap_caller;
461 arch_iounmap = ixp4xx_iounmap;