arch/arm/mach-ixp23xx/core.c

   1 /*
   2  * arch/arm/mach-ixp23xx/core.c
   3  *
   4  * Core routines for IXP23xx chips
   5  *
   6  * Author: Deepak Saxena <dsaxena@plexity.net>
   7  *
   8  * Copyright 2005 (c) MontaVista Software, Inc.
   9  *
  10  * Based on 2.4 code Copyright 2004 (c) Intel Corporation
  11  *
  12  * This file is licensed under the terms of the GNU General Public
  13  * License version 2. This program is licensed "as is" without any
  14  * warranty of any kind, whether express or implied.
  15  */
  16
  17 #include <linux/config.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/sched.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/serial.h>
  24 #include <linux/tty.h>
  25 #include <linux/bitops.h>
  26 #include <linux/serial.h>
  27 #include <linux/serial_8250.h>
  28 #include <linux/serial_core.h>
  29 #include <linux/device.h>
  30 #include <linux/mm.h>
  31 #include <linux/time.h>
  32 #include <linux/timex.h>
  33
  34 #include <asm/types.h>
  35 #include <asm/setup.h>
  36 #include <asm/memory.h>
  37 #include <asm/hardware.h>
  38 #include <asm/mach-types.h>
  39 #include <asm/irq.h>
  40 #include <asm/system.h>
  41 #include <asm/tlbflush.h>
  42 #include <asm/pgtable.h>
  43
  44 #include <asm/mach/map.h>
  45 #include <asm/mach/time.h>
  46 #include <asm/mach/irq.h>
  47 #include <asm/mach/arch.h>
  48
  49
  50 /*************************************************************************
  51  * Chip specific mappings shared by all IXP23xx systems
  52  *************************************************************************/
  53 static struct map_desc ixp23xx_io_desc[] __initdata = {
  54         { /* XSI-CPP CSRs */
  55                 .virtual        = IXP23XX_XSI2CPP_CSR_VIRT,
  56                 .pfn            = __phys_to_pfn(IXP23XX_XSI2CPP_CSR_PHYS),
  57                 .length         = IXP23XX_XSI2CPP_CSR_SIZE,
  58                 .type           = MT_DEVICE,
  59         }, { /* Expansion Bus Config */
  60                 .virtual        = IXP23XX_EXP_CFG_VIRT,
  61                 .pfn            = __phys_to_pfn(IXP23XX_EXP_CFG_PHYS),
  62                 .length         = IXP23XX_EXP_CFG_SIZE,
  63                 .type           = MT_DEVICE,
  64         }, { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACS,.... */
  65                 .virtual        = IXP23XX_PERIPHERAL_VIRT,
  66                 .pfn            = __phys_to_pfn(IXP23XX_PERIPHERAL_PHYS),
  67                 .length         = IXP23XX_PERIPHERAL_SIZE,
  68                 .type           = MT_DEVICE,
  69         }, { /* CAP CSRs */
  70                 .virtual        = IXP23XX_CAP_CSR_VIRT,
  71                 .pfn            = __phys_to_pfn(IXP23XX_CAP_CSR_PHYS),
  72                 .length         = IXP23XX_CAP_CSR_SIZE,
  73                 .type           = MT_DEVICE,
  74         }, { /* MSF CSRs */
  75                 .virtual        = IXP23XX_MSF_CSR_VIRT,
  76                 .pfn            = __phys_to_pfn(IXP23XX_MSF_CSR_PHYS),
  77                 .length         = IXP23XX_MSF_CSR_SIZE,
  78                 .type           = MT_DEVICE,
  79         }, { /* PCI I/O Space */
  80                 .virtual        = IXP23XX_PCI_IO_VIRT,
  81                 .pfn            = __phys_to_pfn(IXP23XX_PCI_IO_PHYS),
  82                 .length         = IXP23XX_PCI_IO_SIZE,
  83                 .type           = MT_DEVICE,
  84         }, { /* PCI Config Space */
  85                 .virtual        = IXP23XX_PCI_CFG_VIRT,
  86                 .pfn            = __phys_to_pfn(IXP23XX_PCI_CFG_PHYS),
  87                 .length         = IXP23XX_PCI_CFG_SIZE,
  88                 .type           = MT_DEVICE,
  89         }, { /* PCI local CFG CSRs */
  90                 .virtual        = IXP23XX_PCI_CREG_VIRT,
  91                 .pfn            = __phys_to_pfn(IXP23XX_PCI_CREG_PHYS),
  92                 .length         = IXP23XX_PCI_CREG_SIZE,
  93                 .type           = MT_DEVICE,
  94         }, { /* PCI MEM Space */
  95                 .virtual        = IXP23XX_PCI_MEM_VIRT,
  96                 .pfn            = __phys_to_pfn(IXP23XX_PCI_MEM_PHYS),
  97                 .length         = IXP23XX_PCI_MEM_SIZE,
  98                 .type           = MT_DEVICE,
  99         }
 100 };
 101
 102 void __init ixp23xx_map_io(void)
 103 {
 104         iotable_init(ixp23xx_io_desc, ARRAY_SIZE(ixp23xx_io_desc));
 105 }
 106
 107
 108 /***************************************************************************
 109  * IXP23xx Interrupt Handling
 110  ***************************************************************************/
 111 enum ixp23xx_irq_type {
 112         IXP23XX_IRQ_LEVEL, IXP23XX_IRQ_EDGE
 113 };
 114
 115 static void ixp23xx_config_irq(unsigned int, enum ixp23xx_irq_type);
 116
 117 static int ixp23xx_irq_set_type(unsigned int irq, unsigned int type)
 118 {
 119         int line = irq - IRQ_IXP23XX_GPIO6 + 6;
 120         u32 int_style;
 121         enum ixp23xx_irq_type irq_type;
 122         volatile u32 *int_reg;
 123
 124         /*
 125          * Only GPIOs 6-15 are wired to interrupts on IXP23xx
 126          */
 127         if (line < 6 || line > 15)
 128                 return -EINVAL;
 129
 130         switch (type) {
 131         case IRQT_BOTHEDGE:
 132                 int_style = IXP23XX_GPIO_STYLE_TRANSITIONAL;
 133                 irq_type = IXP23XX_IRQ_EDGE;
 134                 break;
 135         case IRQT_RISING:
 136                 int_style = IXP23XX_GPIO_STYLE_RISING_EDGE;
 137                 irq_type = IXP23XX_IRQ_EDGE;
 138                 break;
 139         case IRQT_FALLING:
 140                 int_style = IXP23XX_GPIO_STYLE_FALLING_EDGE;
 141                 irq_type = IXP23XX_IRQ_EDGE;
 142                 break;
 143         case IRQT_HIGH:
 144                 int_style = IXP23XX_GPIO_STYLE_ACTIVE_HIGH;
 145                 irq_type = IXP23XX_IRQ_LEVEL;
 146                 break;
 147         case IRQT_LOW:
 148                 int_style = IXP23XX_GPIO_STYLE_ACTIVE_LOW;
 149                 irq_type = IXP23XX_IRQ_LEVEL;
 150                 break;
 151         default:
 152                 return -EINVAL;
 153         }
 154
 155         ixp23xx_config_irq(irq, irq_type);
 156
 157         if (line >= 8) {        /* pins 8-15 */
 158                 line -= 8;
 159                 int_reg = (volatile u32 *)IXP23XX_GPIO_GPIT2R;
 160         } else {                /* pins 0-7 */
 161                 int_reg = (volatile u32 *)IXP23XX_GPIO_GPIT1R;
 162         }
 163
 164         /*
 165          * Clear pending interrupts
 166          */
 167         *IXP23XX_GPIO_GPISR = (1 << line);
 168
 169         /* Clear the style for the appropriate pin */
 170         *int_reg &= ~(IXP23XX_GPIO_STYLE_MASK <<
 171                         (line * IXP23XX_GPIO_STYLE_SIZE));
 172
 173         /* Set the new style */
 174         *int_reg |= (int_style << (line * IXP23XX_GPIO_STYLE_SIZE));
 175
 176         return 0;
 177 }
 178
 179 static void ixp23xx_irq_mask(unsigned int irq)
 180 {
 181         volatile unsigned long *intr_reg;
 182
 183         if (irq >= 56)
 184                 irq += 8;
 185
 186         intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
 187         *intr_reg &= ~(1 << (irq % 32));
 188 }
 189
 190 static void ixp23xx_irq_ack(unsigned int irq)
 191 {
 192         int line = irq - IRQ_IXP23XX_GPIO6 + 6;
 193
 194         if ((line < 6) || (line > 15))
 195                 return;
 196
 197         *IXP23XX_GPIO_GPISR = (1 << line);
 198 }
 199
 200 /*
 201  * Level triggered interrupts on GPIO lines can only be cleared when the
 202  * interrupt condition disappears.
 203  */
 204 static void ixp23xx_irq_level_unmask(unsigned int irq)
 205 {
 206         volatile unsigned long *intr_reg;
 207
 208         ixp23xx_irq_ack(irq);
 209
 210         if (irq >= 56)
 211                 irq += 8;
 212
 213         intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
 214         *intr_reg |= (1 << (irq % 32));
 215 }
 216
 217 static void ixp23xx_irq_edge_unmask(unsigned int irq)
 218 {
 219         volatile unsigned long *intr_reg;
 220
 221         if (irq >= 56)
 222                 irq += 8;
 223
 224         intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
 225         *intr_reg |= (1 << (irq % 32));
 226 }
 227
 228 static struct irqchip ixp23xx_irq_level_chip = {
 229         .ack            = ixp23xx_irq_mask,
 230         .mask           = ixp23xx_irq_mask,
 231         .unmask         = ixp23xx_irq_level_unmask,
 232         .set_type       = ixp23xx_irq_set_type
 233 };
 234
 235 static struct irqchip ixp23xx_irq_edge_chip = {
 236         .ack            = ixp23xx_irq_ack,
 237         .mask           = ixp23xx_irq_mask,
 238         .unmask         = ixp23xx_irq_edge_unmask,
 239         .set_type       = ixp23xx_irq_set_type
 240 };
 241
 242 static void ixp23xx_pci_irq_mask(unsigned int irq)
 243 {
 244         *IXP23XX_PCI_XSCALE_INT_ENABLE &= ~(1 << (IRQ_IXP23XX_INTA + 27 - irq));
 245 }
 246
 247 static void ixp23xx_pci_irq_unmask(unsigned int irq)
 248 {
 249         *IXP23XX_PCI_XSCALE_INT_ENABLE |= (1 << (IRQ_IXP23XX_INTA + 27 - irq));
 250 }
 251
 252 /*
 253  * TODO: Should this just be done at ASM level?
 254  */
 255 static void pci_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
 256 {
 257         u32 pci_interrupt;
 258         unsigned int irqno;
 259         struct irqdesc *int_desc;
 260
 261         pci_interrupt = *IXP23XX_PCI_XSCALE_INT_STATUS;
 262
 263         desc->chip->ack(irq);
 264
 265         /* See which PCI_INTA, or PCI_INTB interrupted */
 266         if (pci_interrupt & (1 << 26)) {
 267                 irqno = IRQ_IXP23XX_INTB;
 268         } else if (pci_interrupt & (1 << 27)) {
 269                 irqno = IRQ_IXP23XX_INTA;
 270         } else {
 271                 BUG();
 272         }
 273
 274         int_desc = irq_desc + irqno;
 275         int_desc->handle(irqno, int_desc, regs);
 276
 277         desc->chip->unmask(irq);
 278 }
 279
 280 static struct irqchip ixp23xx_pci_irq_chip = {
 281         .ack    = ixp23xx_pci_irq_mask,
 282         .mask   = ixp23xx_pci_irq_mask,
 283         .unmask = ixp23xx_pci_irq_unmask
 284 };
 285
 286 static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type)
 287 {
 288         switch (type) {
 289         case IXP23XX_IRQ_LEVEL:
 290                 set_irq_chip(irq, &ixp23xx_irq_level_chip);
 291                 set_irq_handler(irq, do_level_IRQ);
 292                 break;
 293         case IXP23XX_IRQ_EDGE:
 294                 set_irq_chip(irq, &ixp23xx_irq_edge_chip);
 295                 set_irq_handler(irq, do_edge_IRQ);
 296                 break;
 297         }
 298         set_irq_flags(irq, IRQF_VALID);
 299 }
 300
 301 void __init ixp23xx_init_irq(void)
 302 {
 303         int irq;
 304
 305         /* Route everything to IRQ */
 306         *IXP23XX_INTR_SEL1 = 0x0;
 307         *IXP23XX_INTR_SEL2 = 0x0;
 308         *IXP23XX_INTR_SEL3 = 0x0;
 309         *IXP23XX_INTR_SEL4 = 0x0;
 310
 311         /* Mask all sources */
 312         *IXP23XX_INTR_EN1 = 0x0;
 313         *IXP23XX_INTR_EN2 = 0x0;
 314         *IXP23XX_INTR_EN3 = 0x0;
 315         *IXP23XX_INTR_EN4 = 0x0;
 316
 317         /*
 318          * Configure all IRQs for level-sensitive operation
 319          */
 320         for (irq = 0; irq <= NUM_IXP23XX_RAW_IRQS; irq++) {
 321                 ixp23xx_config_irq(irq, IXP23XX_IRQ_LEVEL);
 322         }
 323
 324         for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) {
 325                 set_irq_chip(irq, &ixp23xx_pci_irq_chip);
 326                 set_irq_handler(irq, do_level_IRQ);
 327                 set_irq_flags(irq, IRQF_VALID);
 328         }
 329
 330         set_irq_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler);
 331 }
 332
 333
 334 /*************************************************************************
 335  * Timer-tick functions for IXP23xx
 336  *************************************************************************/
 337 #define CLOCK_TICKS_PER_USEC    CLOCK_TICK_RATE / (USEC_PER_SEC)
 338
 339 static unsigned long next_jiffy_time;
 340
 341 static unsigned long
 342 ixp23xx_gettimeoffset(void)
 343 {
 344         unsigned long elapsed;
 345
 346         elapsed = *IXP23XX_TIMER_CONT - (next_jiffy_time - LATCH);
 347
 348         return elapsed / CLOCK_TICKS_PER_USEC;
 349 }
 350
 351 static irqreturn_t
 352 ixp23xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 353 {
 354         /* Clear Pending Interrupt by writing '1' to it */
 355         *IXP23XX_TIMER_STATUS = IXP23XX_TIMER1_INT_PEND;
 356         while ((*IXP23XX_TIMER_CONT - next_jiffy_time) > LATCH) {
 357                 timer_tick(regs);
 358                 next_jiffy_time += LATCH;
 359         }
 360
 361         return IRQ_HANDLED;
 362 }
 363
 364 static struct irqaction ixp23xx_timer_irq = {
 365         .name           = "IXP23xx Timer Tick",
 366         .handler        = ixp23xx_timer_interrupt,
 367         .flags          = SA_INTERRUPT | SA_TIMER,
 368 };
 369
 370 void __init ixp23xx_init_timer(void)
 371 {
 372         /* Clear Pending Interrupt by writing '1' to it */
 373         *IXP23XX_TIMER_STATUS = IXP23XX_TIMER1_INT_PEND;
 374
 375         /* Setup the Timer counter value */
 376         *IXP23XX_TIMER1_RELOAD =
 377                 (LATCH & ~IXP23XX_TIMER_RELOAD_MASK) | IXP23XX_TIMER_ENABLE;
 378
 379         *IXP23XX_TIMER_CONT = 0;
 380         next_jiffy_time = LATCH;
 381
 382         /* Connect the interrupt handler and enable the interrupt */
 383         setup_irq(IRQ_IXP23XX_TIMER1, &ixp23xx_timer_irq);
 384 }
 385
 386 struct sys_timer ixp23xx_timer = {
 387         .init           = ixp23xx_init_timer,
 388         .offset         = ixp23xx_gettimeoffset,
 389 };
 390
 391
 392 /*************************************************************************
 393  * IXP23xx Platform Initializaion
 394  *************************************************************************/
 395 static struct resource ixp23xx_uart_resources[] = {
 396         {
 397                 .start          = IXP23XX_UART1_PHYS,
 398                 .end            = IXP23XX_UART1_PHYS + 0x0fff,
 399                 .flags          = IORESOURCE_MEM
 400         }, {
 401                 .start          = IXP23XX_UART2_PHYS,
 402                 .end            = IXP23XX_UART2_PHYS + 0x0fff,
 403                 .flags          = IORESOURCE_MEM
 404         }
 405 };
 406
 407 static struct plat_serial8250_port ixp23xx_uart_data[] = {
 408         {
 409                 .mapbase        = IXP23XX_UART1_PHYS,
 410                 .membase        = (char *)(IXP23XX_UART1_VIRT + 3),
 411                 .irq            = IRQ_IXP23XX_UART1,
 412                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 413                 .iotype         = UPIO_MEM,
 414                 .regshift       = 2,
 415                 .uartclk        = IXP23XX_UART_XTAL,
 416         }, {
 417                 .mapbase        = IXP23XX_UART2_PHYS,
 418                 .membase        = (char *)(IXP23XX_UART2_VIRT + 3),
 419                 .irq            = IRQ_IXP23XX_UART2,
 420                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 421                 .iotype         = UPIO_MEM,
 422                 .regshift       = 2,
 423                 .uartclk        = IXP23XX_UART_XTAL,
 424         },
 425         { },
 426 };
 427
 428 static struct platform_device ixp23xx_uart = {
 429         .name                   = "serial8250",
 430         .id                     = 0,
 431         .dev.platform_data      = ixp23xx_uart_data,
 432         .num_resources          = 2,
 433         .resource               = ixp23xx_uart_resources,
 434 };
 435
 436 static struct platform_device *ixp23xx_devices[] __initdata = {
 437         &ixp23xx_uart,
 438 };
 439
 440 void __init ixp23xx_sys_init(void)
 441 {
 442         platform_add_devices(ixp23xx_devices, ARRAY_SIZE(ixp23xx_devices));
 443 }