arch/arm/mach-iop13xx/setup.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * iop13xx platform Initialization
   4  * Copyright (c) 2005-2006, Intel Corporation.
   5  */
   6
   7 #include <linux/dma-mapping.h>
   8 #include <linux/serial_8250.h>
   9 #include <linux/io.h>
  10 #include <linux/reboot.h>
  11 #ifdef CONFIG_MTD_PHYSMAP
  12 #include <linux/mtd/physmap.h>
  13 #endif
  14 #include <asm/mach/map.h>
  15 #include <mach/hardware.h>
  16 #include <asm/irq.h>
  17 #include <asm/hardware/iop_adma.h>
  18 #include <mach/irqs.h>
  19
  20 #define IOP13XX_UART_XTAL 33334000
  21 #define IOP13XX_SETUP_DEBUG 0
  22 #define PRINTK(x...) ((void)(IOP13XX_SETUP_DEBUG && printk(x)))
  23
  24 /* Standard IO mapping for all IOP13XX based systems
  25  */
  26 static struct map_desc iop13xx_std_desc[] __initdata = {
  27         {    /* mem mapped registers */
  28                 .virtual = (unsigned long)IOP13XX_PMMR_VIRT_MEM_BASE,
  29                 .pfn     = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE),
  30                 .length  = IOP13XX_PMMR_SIZE,
  31                 .type    = MT_DEVICE,
  32         },
  33 };
  34
  35 static struct resource iop13xx_uart0_resources[] = {
  36         [0] = {
  37                 .start = IOP13XX_UART0_PHYS,
  38                 .end = IOP13XX_UART0_PHYS + 0x3f,
  39                 .flags = IORESOURCE_MEM,
  40         },
  41         [1] = {
  42                 .start = IRQ_IOP13XX_UART0,
  43                 .end = IRQ_IOP13XX_UART0,
  44                 .flags = IORESOURCE_IRQ
  45         }
  46 };
  47
  48 static struct resource iop13xx_uart1_resources[] = {
  49         [0] = {
  50                 .start = IOP13XX_UART1_PHYS,
  51                 .end = IOP13XX_UART1_PHYS + 0x3f,
  52                 .flags = IORESOURCE_MEM,
  53         },
  54         [1] = {
  55                 .start = IRQ_IOP13XX_UART1,
  56                 .end = IRQ_IOP13XX_UART1,
  57                 .flags = IORESOURCE_IRQ
  58         }
  59 };
  60
  61 static struct plat_serial8250_port iop13xx_uart0_data[] = {
  62         {
  63        .membase     = IOP13XX_UART0_VIRT,
  64        .mapbase     = IOP13XX_UART0_PHYS,
  65        .irq         = IRQ_IOP13XX_UART0,
  66        .uartclk     = IOP13XX_UART_XTAL,
  67        .regshift    = 2,
  68        .iotype      = UPIO_MEM,
  69        .flags       = UPF_SKIP_TEST,
  70         },
  71         {  },
  72 };
  73
  74 static struct plat_serial8250_port iop13xx_uart1_data[] = {
  75         {
  76        .membase     = IOP13XX_UART1_VIRT,
  77        .mapbase     = IOP13XX_UART1_PHYS,
  78        .irq         = IRQ_IOP13XX_UART1,
  79        .uartclk     = IOP13XX_UART_XTAL,
  80        .regshift    = 2,
  81        .iotype      = UPIO_MEM,
  82        .flags       = UPF_SKIP_TEST,
  83         },
  84         {  },
  85 };
  86
  87 /* The ids are fixed up later in iop13xx_platform_init */
  88 static struct platform_device iop13xx_uart0 = {
  89        .name = "serial8250",
  90        .id = 0,
  91        .dev.platform_data = iop13xx_uart0_data,
  92        .num_resources = 2,
  93        .resource = iop13xx_uart0_resources,
  94 };
  95
  96 static struct platform_device iop13xx_uart1 = {
  97        .name = "serial8250",
  98        .id = 0,
  99        .dev.platform_data = iop13xx_uart1_data,
 100        .num_resources = 2,
 101        .resource = iop13xx_uart1_resources
 102 };
 103
 104 static struct resource iop13xx_i2c_0_resources[] = {
 105         [0] = {
 106                 .start = IOP13XX_I2C0_PHYS,
 107                 .end = IOP13XX_I2C0_PHYS + 0x18,
 108                 .flags = IORESOURCE_MEM,
 109         },
 110         [1] = {
 111                 .start = IRQ_IOP13XX_I2C_0,
 112                 .end = IRQ_IOP13XX_I2C_0,
 113                 .flags = IORESOURCE_IRQ
 114         }
 115 };
 116
 117 static struct resource iop13xx_i2c_1_resources[] = {
 118         [0] = {
 119                 .start = IOP13XX_I2C1_PHYS,
 120                 .end = IOP13XX_I2C1_PHYS + 0x18,
 121                 .flags = IORESOURCE_MEM,
 122         },
 123         [1] = {
 124                 .start = IRQ_IOP13XX_I2C_1,
 125                 .end = IRQ_IOP13XX_I2C_1,
 126                 .flags = IORESOURCE_IRQ
 127         }
 128 };
 129
 130 static struct resource iop13xx_i2c_2_resources[] = {
 131         [0] = {
 132                 .start = IOP13XX_I2C2_PHYS,
 133                 .end = IOP13XX_I2C2_PHYS + 0x18,
 134                 .flags = IORESOURCE_MEM,
 135         },
 136         [1] = {
 137                 .start = IRQ_IOP13XX_I2C_2,
 138                 .end = IRQ_IOP13XX_I2C_2,
 139                 .flags = IORESOURCE_IRQ
 140         }
 141 };
 142
 143 /* I2C controllers. The IOP13XX uses the same block as the IOP3xx, so
 144  * we just use the same device name.
 145  */
 146
 147 /* The ids are fixed up later in iop13xx_platform_init */
 148 static struct platform_device iop13xx_i2c_0_controller = {
 149         .name = "IOP3xx-I2C",
 150         .id = 0,
 151         .num_resources = 2,
 152         .resource = iop13xx_i2c_0_resources
 153 };
 154
 155 static struct platform_device iop13xx_i2c_1_controller = {
 156         .name = "IOP3xx-I2C",
 157         .id = 0,
 158         .num_resources = 2,
 159         .resource = iop13xx_i2c_1_resources
 160 };
 161
 162 static struct platform_device iop13xx_i2c_2_controller = {
 163         .name = "IOP3xx-I2C",
 164         .id = 0,
 165         .num_resources = 2,
 166         .resource = iop13xx_i2c_2_resources
 167 };
 168
 169 #ifdef CONFIG_MTD_PHYSMAP
 170 /* PBI Flash Device
 171  */
 172 static struct physmap_flash_data iq8134x_flash_data = {
 173         .width = 2,
 174 };
 175
 176 static struct resource iq8134x_flash_resource = {
 177         .start = IQ81340_FLASHBASE,
 178         .end   = 0,
 179         .flags = IORESOURCE_MEM,
 180 };
 181
 182 static struct platform_device iq8134x_flash = {
 183         .name           = "physmap-flash",
 184         .id             = 0,
 185         .dev            = { .platform_data  = &iq8134x_flash_data, },
 186         .num_resources  = 1,
 187         .resource       = &iq8134x_flash_resource,
 188 };
 189
 190 static unsigned long iq8134x_probe_flash_size(void)
 191 {
 192         uint8_t __iomem *flash_addr = ioremap(IQ81340_FLASHBASE, PAGE_SIZE);
 193         int i;
 194         char query[3];
 195         unsigned long size = 0;
 196         int width = iq8134x_flash_data.width;
 197
 198         if (flash_addr) {
 199                 /* send CFI 'query' command */
 200                 writew(0x98, flash_addr);
 201
 202                 /* check for CFI compliance */
 203                 for (i = 0; i < 3 * width; i += width)
 204                         query[i / width] = readb(flash_addr + (0x10 * width) + i);
 205
 206                 /* read the size */
 207                 if (memcmp(query, "QRY", 3) == 0)
 208                         size = 1 << readb(flash_addr + (0x27 * width));
 209
 210                 /* send CFI 'read array' command */
 211                 writew(0xff, flash_addr);
 212
 213                 iounmap(flash_addr);
 214         }
 215
 216         return size;
 217 }
 218 #endif
 219
 220 /* ADMA Channels */
 221 static struct resource iop13xx_adma_0_resources[] = {
 222         [0] = {
 223                 .start = IOP13XX_ADMA_PHYS_BASE(0),
 224                 .end = IOP13XX_ADMA_UPPER_PA(0),
 225                 .flags = IORESOURCE_MEM,
 226         },
 227         [1] = {
 228                 .start = IRQ_IOP13XX_ADMA0_EOT,
 229                 .end = IRQ_IOP13XX_ADMA0_EOT,
 230                 .flags = IORESOURCE_IRQ
 231         },
 232         [2] = {
 233                 .start = IRQ_IOP13XX_ADMA0_EOC,
 234                 .end = IRQ_IOP13XX_ADMA0_EOC,
 235                 .flags = IORESOURCE_IRQ
 236         },
 237         [3] = {
 238                 .start = IRQ_IOP13XX_ADMA0_ERR,
 239                 .end = IRQ_IOP13XX_ADMA0_ERR,
 240                 .flags = IORESOURCE_IRQ
 241         }
 242 };
 243
 244 static struct resource iop13xx_adma_1_resources[] = {
 245         [0] = {
 246                 .start = IOP13XX_ADMA_PHYS_BASE(1),
 247                 .end = IOP13XX_ADMA_UPPER_PA(1),
 248                 .flags = IORESOURCE_MEM,
 249         },
 250         [1] = {
 251                 .start = IRQ_IOP13XX_ADMA1_EOT,
 252                 .end = IRQ_IOP13XX_ADMA1_EOT,
 253                 .flags = IORESOURCE_IRQ
 254         },
 255         [2] = {
 256                 .start = IRQ_IOP13XX_ADMA1_EOC,
 257                 .end = IRQ_IOP13XX_ADMA1_EOC,
 258                 .flags = IORESOURCE_IRQ
 259         },
 260         [3] = {
 261                 .start = IRQ_IOP13XX_ADMA1_ERR,
 262                 .end = IRQ_IOP13XX_ADMA1_ERR,
 263                 .flags = IORESOURCE_IRQ
 264         }
 265 };
 266
 267 static struct resource iop13xx_adma_2_resources[] = {
 268         [0] = {
 269                 .start = IOP13XX_ADMA_PHYS_BASE(2),
 270                 .end = IOP13XX_ADMA_UPPER_PA(2),
 271                 .flags = IORESOURCE_MEM,
 272         },
 273         [1] = {
 274                 .start = IRQ_IOP13XX_ADMA2_EOT,
 275                 .end = IRQ_IOP13XX_ADMA2_EOT,
 276                 .flags = IORESOURCE_IRQ
 277         },
 278         [2] = {
 279                 .start = IRQ_IOP13XX_ADMA2_EOC,
 280                 .end = IRQ_IOP13XX_ADMA2_EOC,
 281                 .flags = IORESOURCE_IRQ
 282         },
 283         [3] = {
 284                 .start = IRQ_IOP13XX_ADMA2_ERR,
 285                 .end = IRQ_IOP13XX_ADMA2_ERR,
 286                 .flags = IORESOURCE_IRQ
 287         }
 288 };
 289
 290 static u64 iop13xx_adma_dmamask = DMA_BIT_MASK(32);
 291 static struct iop_adma_platform_data iop13xx_adma_0_data = {
 292         .hw_id = 0,
 293         .pool_size = PAGE_SIZE,
 294 };
 295
 296 static struct iop_adma_platform_data iop13xx_adma_1_data = {
 297         .hw_id = 1,
 298         .pool_size = PAGE_SIZE,
 299 };
 300
 301 static struct iop_adma_platform_data iop13xx_adma_2_data = {
 302         .hw_id = 2,
 303         .pool_size = PAGE_SIZE,
 304 };
 305
 306 /* The ids are fixed up later in iop13xx_platform_init */
 307 static struct platform_device iop13xx_adma_0_channel = {
 308         .name = "iop-adma",
 309         .id = 0,
 310         .num_resources = 4,
 311         .resource = iop13xx_adma_0_resources,
 312         .dev = {
 313                 .dma_mask = &iop13xx_adma_dmamask,
 314                 .coherent_dma_mask = DMA_BIT_MASK(32),
 315                 .platform_data = (void *) &iop13xx_adma_0_data,
 316         },
 317 };
 318
 319 static struct platform_device iop13xx_adma_1_channel = {
 320         .name = "iop-adma",
 321         .id = 0,
 322         .num_resources = 4,
 323         .resource = iop13xx_adma_1_resources,
 324         .dev = {
 325                 .dma_mask = &iop13xx_adma_dmamask,
 326                 .coherent_dma_mask = DMA_BIT_MASK(32),
 327                 .platform_data = (void *) &iop13xx_adma_1_data,
 328         },
 329 };
 330
 331 static struct platform_device iop13xx_adma_2_channel = {
 332         .name = "iop-adma",
 333         .id = 0,
 334         .num_resources = 4,
 335         .resource = iop13xx_adma_2_resources,
 336         .dev = {
 337                 .dma_mask = &iop13xx_adma_dmamask,
 338                 .coherent_dma_mask = DMA_BIT_MASK(32),
 339                 .platform_data = (void *) &iop13xx_adma_2_data,
 340         },
 341 };
 342
 343 void __init iop13xx_map_io(void)
 344 {
 345         /* Initialize the Static Page Table maps */
 346         iotable_init(iop13xx_std_desc, ARRAY_SIZE(iop13xx_std_desc));
 347 }
 348
 349 static int init_uart;
 350 static int init_i2c;
 351 static int init_adma;
 352
 353 void __init iop13xx_platform_init(void)
 354 {
 355         int i;
 356         u32 uart_idx, i2c_idx, adma_idx, plat_idx;
 357         struct platform_device *iop13xx_devices[IQ81340_MAX_PLAT_DEVICES];
 358
 359         /* set the bases so we can read the device id */
 360         iop13xx_set_atu_mmr_bases();
 361
 362         memset(iop13xx_devices, 0, sizeof(iop13xx_devices));
 363
 364         if (init_uart == IOP13XX_INIT_UART_DEFAULT) {
 365                 switch (iop13xx_dev_id()) {
 366                 /* enable both uarts on iop341 */
 367                 case 0x3380:
 368                 case 0x3384:
 369                 case 0x3388:
 370                 case 0x338c:
 371                         init_uart |= IOP13XX_INIT_UART_0;
 372                         init_uart |= IOP13XX_INIT_UART_1;
 373                         break;
 374                 /* only enable uart 1 */
 375                 default:
 376                         init_uart |= IOP13XX_INIT_UART_1;
 377                 }
 378         }
 379
 380         if (init_i2c == IOP13XX_INIT_I2C_DEFAULT) {
 381                 switch (iop13xx_dev_id()) {
 382                 /* enable all i2c units on iop341 and iop342 */
 383                 case 0x3380:
 384                 case 0x3384:
 385                 case 0x3388:
 386                 case 0x338c:
 387                 case 0x3382:
 388                 case 0x3386:
 389                 case 0x338a:
 390                 case 0x338e:
 391                         init_i2c |= IOP13XX_INIT_I2C_0;
 392                         init_i2c |= IOP13XX_INIT_I2C_1;
 393                         init_i2c |= IOP13XX_INIT_I2C_2;
 394                         break;
 395                 /* only enable i2c 1 and 2 */
 396                 default:
 397                         init_i2c |= IOP13XX_INIT_I2C_1;
 398                         init_i2c |= IOP13XX_INIT_I2C_2;
 399                 }
 400         }
 401
 402         if (init_adma == IOP13XX_INIT_ADMA_DEFAULT) {
 403                 init_adma |= IOP13XX_INIT_ADMA_0;
 404                 init_adma |= IOP13XX_INIT_ADMA_1;
 405                 init_adma |= IOP13XX_INIT_ADMA_2;
 406         }
 407
 408         plat_idx = 0;
 409         uart_idx = 0;
 410         i2c_idx = 0;
 411
 412         /* uart 1 (if enabled) is ttyS0 */
 413         if (init_uart & IOP13XX_INIT_UART_1) {
 414                 PRINTK("Adding uart1 to platform device list\n");
 415                 iop13xx_uart1.id = uart_idx++;
 416                 iop13xx_devices[plat_idx++] = &iop13xx_uart1;
 417         }
 418         if (init_uart & IOP13XX_INIT_UART_0) {
 419                 PRINTK("Adding uart0 to platform device list\n");
 420                 iop13xx_uart0.id = uart_idx++;
 421                 iop13xx_devices[plat_idx++] = &iop13xx_uart0;
 422         }
 423
 424         for(i = 0; i < IQ81340_NUM_I2C; i++) {
 425                 if ((init_i2c & (1 << i)) && IOP13XX_SETUP_DEBUG)
 426                         printk("Adding i2c%d to platform device list\n", i);
 427                 switch(init_i2c & (1 << i)) {
 428                 case IOP13XX_INIT_I2C_0:
 429                         iop13xx_i2c_0_controller.id = i2c_idx++;
 430                         iop13xx_devices[plat_idx++] =
 431                                 &iop13xx_i2c_0_controller;
 432                         break;
 433                 case IOP13XX_INIT_I2C_1:
 434                         iop13xx_i2c_1_controller.id = i2c_idx++;
 435                         iop13xx_devices[plat_idx++] =
 436                                 &iop13xx_i2c_1_controller;
 437                         break;
 438                 case IOP13XX_INIT_I2C_2:
 439                         iop13xx_i2c_2_controller.id = i2c_idx++;
 440                         iop13xx_devices[plat_idx++] =
 441                                 &iop13xx_i2c_2_controller;
 442                         break;
 443                 }
 444         }
 445
 446         /* initialize adma channel ids and capabilities */
 447         adma_idx = 0;
 448         for (i = 0; i < IQ81340_NUM_ADMA; i++) {
 449                 struct iop_adma_platform_data *plat_data;
 450                 if ((init_adma & (1 << i)) && IOP13XX_SETUP_DEBUG)
 451                         printk(KERN_INFO
 452                                 "Adding adma%d to platform device list\n", i);
 453                 switch (init_adma & (1 << i)) {
 454                 case IOP13XX_INIT_ADMA_0:
 455                         iop13xx_adma_0_channel.id = adma_idx++;
 456                         iop13xx_devices[plat_idx++] = &iop13xx_adma_0_channel;
 457                         plat_data = &iop13xx_adma_0_data;
 458                         dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
 459                         dma_cap_set(DMA_XOR, plat_data->cap_mask);
 460                         dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask);
 461                         dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
 462                         break;
 463                 case IOP13XX_INIT_ADMA_1:
 464                         iop13xx_adma_1_channel.id = adma_idx++;
 465                         iop13xx_devices[plat_idx++] = &iop13xx_adma_1_channel;
 466                         plat_data = &iop13xx_adma_1_data;
 467                         dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
 468                         dma_cap_set(DMA_XOR, plat_data->cap_mask);
 469                         dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask);
 470                         dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
 471                         break;
 472                 case IOP13XX_INIT_ADMA_2:
 473                         iop13xx_adma_2_channel.id = adma_idx++;
 474                         iop13xx_devices[plat_idx++] = &iop13xx_adma_2_channel;
 475                         plat_data = &iop13xx_adma_2_data;
 476                         dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
 477                         dma_cap_set(DMA_XOR, plat_data->cap_mask);
 478                         dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask);
 479                         dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
 480                         dma_cap_set(DMA_PQ, plat_data->cap_mask);
 481                         dma_cap_set(DMA_PQ_VAL, plat_data->cap_mask);
 482                         break;
 483                 }
 484         }
 485
 486 #ifdef CONFIG_MTD_PHYSMAP
 487         iq8134x_flash_resource.end = iq8134x_flash_resource.start +
 488                                 iq8134x_probe_flash_size() - 1;
 489         if (iq8134x_flash_resource.end > iq8134x_flash_resource.start)
 490                 iop13xx_devices[plat_idx++] = &iq8134x_flash;
 491         else
 492                 printk(KERN_ERR "%s: Failed to probe flash size\n", __func__);
 493 #endif
 494
 495         platform_add_devices(iop13xx_devices, plat_idx);
 496 }
 497
 498 static int __init iop13xx_init_uart_setup(char *str)
 499 {
 500         if (str) {
 501                 while (*str != '\0') {
 502                         switch(*str) {
 503                         case '0':
 504                                 init_uart |= IOP13XX_INIT_UART_0;
 505                                 break;
 506                         case '1':
 507                                 init_uart |= IOP13XX_INIT_UART_1;
 508                                 break;
 509                         case ',':
 510                         case '=':
 511                                 break;
 512                         default:
 513                                 PRINTK("\"iop13xx_init_uart\" malformed"
 514                                             " at character: \'%c\'", *str);
 515                                 *(str + 1) = '\0';
 516                                 init_uart = IOP13XX_INIT_UART_DEFAULT;
 517                         }
 518                         str++;
 519                 }
 520         }
 521         return 1;
 522 }
 523
 524 static int __init iop13xx_init_i2c_setup(char *str)
 525 {
 526         if (str) {
 527                 while (*str != '\0') {
 528                         switch(*str) {
 529                         case '0':
 530                                 init_i2c |= IOP13XX_INIT_I2C_0;
 531                                 break;
 532                         case '1':
 533                                 init_i2c |= IOP13XX_INIT_I2C_1;
 534                                 break;
 535                         case '2':
 536                                 init_i2c |= IOP13XX_INIT_I2C_2;
 537                                 break;
 538                         case ',':
 539                         case '=':
 540                                 break;
 541                         default:
 542                                 PRINTK("\"iop13xx_init_i2c\" malformed"
 543                                             " at character: \'%c\'", *str);
 544                                 *(str + 1) = '\0';
 545                                 init_i2c = IOP13XX_INIT_I2C_DEFAULT;
 546                         }
 547                         str++;
 548                 }
 549         }
 550         return 1;
 551 }
 552
 553 static int __init iop13xx_init_adma_setup(char *str)
 554 {
 555         if (str)        {
 556                 while (*str != '\0') {
 557                         switch (*str) {
 558                         case '0':
 559                                 init_adma |= IOP13XX_INIT_ADMA_0;
 560                                 break;
 561                         case '1':
 562                                 init_adma |= IOP13XX_INIT_ADMA_1;
 563                                 break;
 564                         case '2':
 565                                 init_adma |= IOP13XX_INIT_ADMA_2;
 566                                 break;
 567                         case ',':
 568                         case '=':
 569                                 break;
 570                         default:
 571                                 PRINTK("\"iop13xx_init_adma\" malformed"
 572                                             " at character: \'%c\'", *str);
 573                                 *(str + 1) = '\0';
 574                                 init_adma = IOP13XX_INIT_ADMA_DEFAULT;
 575                         }
 576                         str++;
 577                 }
 578         }
 579         return 1;
 580 }
 581
 582 __setup("iop13xx_init_adma", iop13xx_init_adma_setup);
 583 __setup("iop13xx_init_uart", iop13xx_init_uart_setup);
 584 __setup("iop13xx_init_i2c", iop13xx_init_i2c_setup);
 585
 586 void iop13xx_restart(enum reboot_mode mode, const char *cmd)
 587 {
 588         /*
 589          * Reset the internal bus (warning both cores are reset)
 590          */
 591         write_wdtcr(IOP_WDTCR_EN_ARM);
 592         write_wdtcr(IOP_WDTCR_EN);
 593         write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
 594         write_wdtcr(0x1000);
 595 }