arch/arm/mach-iop13xx/setup.c

   1 /*
   2  * iop13xx platform Initialization
   3  * Copyright (c) 2005-2006, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  16  * Place - Suite 330, Boston, MA 02111-1307 USA.
  17  *
  18  */
  19
  20 #include <linux/dma-mapping.h>
  21 #include <linux/serial_8250.h>
  22 #include <linux/io.h>
  23 #ifdef CONFIG_MTD_PHYSMAP
  24 #include <linux/mtd/physmap.h>
  25 #endif
  26 #include <asm/mach/map.h>
  27 #include <mach/hardware.h>
  28 #include <asm/irq.h>
  29 #include <asm/hardware/iop_adma.h>
  30 #include <mach/irqs.h>
  31
  32 #define IOP13XX_UART_XTAL 33334000
  33 #define IOP13XX_SETUP_DEBUG 0
  34 #define PRINTK(x...) ((void)(IOP13XX_SETUP_DEBUG && printk(x)))
  35
  36 /* Standard IO mapping for all IOP13XX based systems
  37  */
  38 static struct map_desc iop13xx_std_desc[] __initdata = {
  39         {    /* mem mapped registers */
  40                 .virtual = (unsigned long)IOP13XX_PMMR_VIRT_MEM_BASE,
  41                 .pfn     = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE),
  42                 .length  = IOP13XX_PMMR_SIZE,
  43                 .type    = MT_DEVICE,
  44         },
  45 };
  46
  47 static struct resource iop13xx_uart0_resources[] = {
  48         [0] = {
  49                 .start = IOP13XX_UART0_PHYS,
  50                 .end = IOP13XX_UART0_PHYS + 0x3f,
  51                 .flags = IORESOURCE_MEM,
  52         },
  53         [1] = {
  54                 .start = IRQ_IOP13XX_UART0,
  55                 .end = IRQ_IOP13XX_UART0,
  56                 .flags = IORESOURCE_IRQ
  57         }
  58 };
  59
  60 static struct resource iop13xx_uart1_resources[] = {
  61         [0] = {
  62                 .start = IOP13XX_UART1_PHYS,
  63                 .end = IOP13XX_UART1_PHYS + 0x3f,
  64                 .flags = IORESOURCE_MEM,
  65         },
  66         [1] = {
  67                 .start = IRQ_IOP13XX_UART1,
  68                 .end = IRQ_IOP13XX_UART1,
  69                 .flags = IORESOURCE_IRQ
  70         }
  71 };
  72
  73 static struct plat_serial8250_port iop13xx_uart0_data[] = {
  74         {
  75        .membase     = IOP13XX_UART0_VIRT,
  76        .mapbase     = IOP13XX_UART0_PHYS,
  77        .irq         = IRQ_IOP13XX_UART0,
  78        .uartclk     = IOP13XX_UART_XTAL,
  79        .regshift    = 2,
  80        .iotype      = UPIO_MEM,
  81        .flags       = UPF_SKIP_TEST,
  82         },
  83         {  },
  84 };
  85
  86 static struct plat_serial8250_port iop13xx_uart1_data[] = {
  87         {
  88        .membase     = IOP13XX_UART1_VIRT,
  89        .mapbase     = IOP13XX_UART1_PHYS,
  90        .irq         = IRQ_IOP13XX_UART1,
  91        .uartclk     = IOP13XX_UART_XTAL,
  92        .regshift    = 2,
  93        .iotype      = UPIO_MEM,
  94        .flags       = UPF_SKIP_TEST,
  95         },
  96         {  },
  97 };
  98
  99 /* The ids are fixed up later in iop13xx_platform_init */
 100 static struct platform_device iop13xx_uart0 = {
 101        .name = "serial8250",
 102        .id = 0,
 103        .dev.platform_data = iop13xx_uart0_data,
 104        .num_resources = 2,
 105        .resource = iop13xx_uart0_resources,
 106 };
 107
 108 static struct platform_device iop13xx_uart1 = {
 109        .name = "serial8250",
 110        .id = 0,
 111        .dev.platform_data = iop13xx_uart1_data,
 112        .num_resources = 2,
 113        .resource = iop13xx_uart1_resources
 114 };
 115
 116 static struct resource iop13xx_i2c_0_resources[] = {
 117         [0] = {
 118                 .start = IOP13XX_I2C0_PHYS,
 119                 .end = IOP13XX_I2C0_PHYS + 0x18,
 120                 .flags = IORESOURCE_MEM,
 121         },
 122         [1] = {
 123                 .start = IRQ_IOP13XX_I2C_0,
 124                 .end = IRQ_IOP13XX_I2C_0,
 125                 .flags = IORESOURCE_IRQ
 126         }
 127 };
 128
 129 static struct resource iop13xx_i2c_1_resources[] = {
 130         [0] = {
 131                 .start = IOP13XX_I2C1_PHYS,
 132                 .end = IOP13XX_I2C1_PHYS + 0x18,
 133                 .flags = IORESOURCE_MEM,
 134         },
 135         [1] = {
 136                 .start = IRQ_IOP13XX_I2C_1,
 137                 .end = IRQ_IOP13XX_I2C_1,
 138                 .flags = IORESOURCE_IRQ
 139         }
 140 };
 141
 142 static struct resource iop13xx_i2c_2_resources[] = {
 143         [0] = {
 144                 .start = IOP13XX_I2C2_PHYS,
 145                 .end = IOP13XX_I2C2_PHYS + 0x18,
 146                 .flags = IORESOURCE_MEM,
 147         },
 148         [1] = {
 149                 .start = IRQ_IOP13XX_I2C_2,
 150                 .end = IRQ_IOP13XX_I2C_2,
 151                 .flags = IORESOURCE_IRQ
 152         }
 153 };
 154
 155 /* I2C controllers. The IOP13XX uses the same block as the IOP3xx, so
 156  * we just use the same device name.
 157  */
 158
 159 /* The ids are fixed up later in iop13xx_platform_init */
 160 static struct platform_device iop13xx_i2c_0_controller = {
 161         .name = "IOP3xx-I2C",
 162         .id = 0,
 163         .num_resources = 2,
 164         .resource = iop13xx_i2c_0_resources
 165 };
 166
 167 static struct platform_device iop13xx_i2c_1_controller = {
 168         .name = "IOP3xx-I2C",
 169         .id = 0,
 170         .num_resources = 2,
 171         .resource = iop13xx_i2c_1_resources
 172 };
 173
 174 static struct platform_device iop13xx_i2c_2_controller = {
 175         .name = "IOP3xx-I2C",
 176         .id = 0,
 177         .num_resources = 2,
 178         .resource = iop13xx_i2c_2_resources
 179 };
 180
 181 #ifdef CONFIG_MTD_PHYSMAP
 182 /* PBI Flash Device
 183  */
 184 static struct physmap_flash_data iq8134x_flash_data = {
 185         .width = 2,
 186 };
 187
 188 static struct resource iq8134x_flash_resource = {
 189         .start = IQ81340_FLASHBASE,
 190         .end   = 0,
 191         .flags = IORESOURCE_MEM,
 192 };
 193
 194 static struct platform_device iq8134x_flash = {
 195         .name           = "physmap-flash",
 196         .id             = 0,
 197         .dev            = { .platform_data  = &iq8134x_flash_data, },
 198         .num_resources  = 1,
 199         .resource       = &iq8134x_flash_resource,
 200 };
 201
 202 static unsigned long iq8134x_probe_flash_size(void)
 203 {
 204         uint8_t __iomem *flash_addr = ioremap(IQ81340_FLASHBASE, PAGE_SIZE);
 205         int i;
 206         char query[3];
 207         unsigned long size = 0;
 208         int width = iq8134x_flash_data.width;
 209
 210         if (flash_addr) {
 211                 /* send CFI 'query' command */
 212                 writew(0x98, flash_addr);
 213
 214                 /* check for CFI compliance */
 215                 for (i = 0; i < 3 * width; i += width)
 216                         query[i / width] = readb(flash_addr + (0x10 * width) + i);
 217
 218                 /* read the size */
 219                 if (memcmp(query, "QRY", 3) == 0)
 220                         size = 1 << readb(flash_addr + (0x27 * width));
 221
 222                 /* send CFI 'read array' command */
 223                 writew(0xff, flash_addr);
 224
 225                 iounmap(flash_addr);
 226         }
 227
 228         return size;
 229 }
 230 #endif
 231
 232 /* ADMA Channels */
 233 static struct resource iop13xx_adma_0_resources[] = {
 234         [0] = {
 235                 .start = IOP13XX_ADMA_PHYS_BASE(0),
 236                 .end = IOP13XX_ADMA_UPPER_PA(0),
 237                 .flags = IORESOURCE_MEM,
 238         },
 239         [1] = {
 240                 .start = IRQ_IOP13XX_ADMA0_EOT,
 241                 .end = IRQ_IOP13XX_ADMA0_EOT,
 242                 .flags = IORESOURCE_IRQ
 243         },
 244         [2] = {
 245                 .start = IRQ_IOP13XX_ADMA0_EOC,
 246                 .end = IRQ_IOP13XX_ADMA0_EOC,
 247                 .flags = IORESOURCE_IRQ
 248         },
 249         [3] = {
 250                 .start = IRQ_IOP13XX_ADMA0_ERR,
 251                 .end = IRQ_IOP13XX_ADMA0_ERR,
 252                 .flags = IORESOURCE_IRQ
 253         }
 254 };
 255
 256 static struct resource iop13xx_adma_1_resources[] = {
 257         [0] = {
 258                 .start = IOP13XX_ADMA_PHYS_BASE(1),
 259                 .end = IOP13XX_ADMA_UPPER_PA(1),
 260                 .flags = IORESOURCE_MEM,
 261         },
 262         [1] = {
 263                 .start = IRQ_IOP13XX_ADMA1_EOT,
 264                 .end = IRQ_IOP13XX_ADMA1_EOT,
 265                 .flags = IORESOURCE_IRQ
 266         },
 267         [2] = {
 268                 .start = IRQ_IOP13XX_ADMA1_EOC,
 269                 .end = IRQ_IOP13XX_ADMA1_EOC,
 270                 .flags = IORESOURCE_IRQ
 271         },
 272         [3] = {
 273                 .start = IRQ_IOP13XX_ADMA1_ERR,
 274                 .end = IRQ_IOP13XX_ADMA1_ERR,
 275                 .flags = IORESOURCE_IRQ
 276         }
 277 };
 278
 279 static struct resource iop13xx_adma_2_resources[] = {
 280         [0] = {
 281                 .start = IOP13XX_ADMA_PHYS_BASE(2),
 282                 .end = IOP13XX_ADMA_UPPER_PA(2),
 283                 .flags = IORESOURCE_MEM,
 284         },
 285         [1] = {
 286                 .start = IRQ_IOP13XX_ADMA2_EOT,
 287                 .end = IRQ_IOP13XX_ADMA2_EOT,
 288                 .flags = IORESOURCE_IRQ
 289         },
 290         [2] = {
 291                 .start = IRQ_IOP13XX_ADMA2_EOC,
 292                 .end = IRQ_IOP13XX_ADMA2_EOC,
 293                 .flags = IORESOURCE_IRQ
 294         },
 295         [3] = {
 296                 .start = IRQ_IOP13XX_ADMA2_ERR,
 297                 .end = IRQ_IOP13XX_ADMA2_ERR,
 298                 .flags = IORESOURCE_IRQ
 299         }
 300 };
 301
 302 static u64 iop13xx_adma_dmamask = DMA_BIT_MASK(64);
 303 static struct iop_adma_platform_data iop13xx_adma_0_data = {
 304         .hw_id = 0,
 305         .pool_size = PAGE_SIZE,
 306 };
 307
 308 static struct iop_adma_platform_data iop13xx_adma_1_data = {
 309         .hw_id = 1,
 310         .pool_size = PAGE_SIZE,
 311 };
 312
 313 static struct iop_adma_platform_data iop13xx_adma_2_data = {
 314         .hw_id = 2,
 315         .pool_size = PAGE_SIZE,
 316 };
 317
 318 /* The ids are fixed up later in iop13xx_platform_init */
 319 static struct platform_device iop13xx_adma_0_channel = {
 320         .name = "iop-adma",
 321         .id = 0,
 322         .num_resources = 4,
 323         .resource = iop13xx_adma_0_resources,
 324         .dev = {
 325                 .dma_mask = &iop13xx_adma_dmamask,
 326                 .coherent_dma_mask = DMA_BIT_MASK(64),
 327                 .platform_data = (void *) &iop13xx_adma_0_data,
 328         },
 329 };
 330
 331 static struct platform_device iop13xx_adma_1_channel = {
 332         .name = "iop-adma",
 333         .id = 0,
 334         .num_resources = 4,
 335         .resource = iop13xx_adma_1_resources,
 336         .dev = {
 337                 .dma_mask = &iop13xx_adma_dmamask,
 338                 .coherent_dma_mask = DMA_BIT_MASK(64),
 339                 .platform_data = (void *) &iop13xx_adma_1_data,
 340         },
 341 };
 342
 343 static struct platform_device iop13xx_adma_2_channel = {
 344         .name = "iop-adma",
 345         .id = 0,
 346         .num_resources = 4,
 347         .resource = iop13xx_adma_2_resources,
 348         .dev = {
 349                 .dma_mask = &iop13xx_adma_dmamask,
 350                 .coherent_dma_mask = DMA_BIT_MASK(64),
 351                 .platform_data = (void *) &iop13xx_adma_2_data,
 352         },
 353 };
 354
 355 void __init iop13xx_map_io(void)
 356 {
 357         /* Initialize the Static Page Table maps */
 358         iotable_init(iop13xx_std_desc, ARRAY_SIZE(iop13xx_std_desc));
 359 }
 360
 361 static int init_uart;
 362 static int init_i2c;
 363 static int init_adma;
 364
 365 void __init iop13xx_platform_init(void)
 366 {
 367         int i;
 368         u32 uart_idx, i2c_idx, adma_idx, plat_idx;
 369         struct platform_device *iop13xx_devices[IQ81340_MAX_PLAT_DEVICES];
 370
 371         /* set the bases so we can read the device id */
 372         iop13xx_set_atu_mmr_bases();
 373
 374         memset(iop13xx_devices, 0, sizeof(iop13xx_devices));
 375
 376         if (init_uart == IOP13XX_INIT_UART_DEFAULT) {
 377                 switch (iop13xx_dev_id()) {
 378                 /* enable both uarts on iop341 */
 379                 case 0x3380:
 380                 case 0x3384:
 381                 case 0x3388:
 382                 case 0x338c:
 383                         init_uart |= IOP13XX_INIT_UART_0;
 384                         init_uart |= IOP13XX_INIT_UART_1;
 385                         break;
 386                 /* only enable uart 1 */
 387                 default:
 388                         init_uart |= IOP13XX_INIT_UART_1;
 389                 }
 390         }
 391
 392         if (init_i2c == IOP13XX_INIT_I2C_DEFAULT) {
 393                 switch (iop13xx_dev_id()) {
 394                 /* enable all i2c units on iop341 and iop342 */
 395                 case 0x3380:
 396                 case 0x3384:
 397                 case 0x3388:
 398                 case 0x338c:
 399                 case 0x3382:
 400                 case 0x3386:
 401                 case 0x338a:
 402                 case 0x338e:
 403                         init_i2c |= IOP13XX_INIT_I2C_0;
 404                         init_i2c |= IOP13XX_INIT_I2C_1;
 405                         init_i2c |= IOP13XX_INIT_I2C_2;
 406                         break;
 407                 /* only enable i2c 1 and 2 */
 408                 default:
 409                         init_i2c |= IOP13XX_INIT_I2C_1;
 410                         init_i2c |= IOP13XX_INIT_I2C_2;
 411                 }
 412         }
 413
 414         if (init_adma == IOP13XX_INIT_ADMA_DEFAULT) {
 415                 init_adma |= IOP13XX_INIT_ADMA_0;
 416                 init_adma |= IOP13XX_INIT_ADMA_1;
 417                 init_adma |= IOP13XX_INIT_ADMA_2;
 418         }
 419
 420         plat_idx = 0;
 421         uart_idx = 0;
 422         i2c_idx = 0;
 423
 424         /* uart 1 (if enabled) is ttyS0 */
 425         if (init_uart & IOP13XX_INIT_UART_1) {
 426                 PRINTK("Adding uart1 to platform device list\n");
 427                 iop13xx_uart1.id = uart_idx++;
 428                 iop13xx_devices[plat_idx++] = &iop13xx_uart1;
 429         }
 430         if (init_uart & IOP13XX_INIT_UART_0) {
 431                 PRINTK("Adding uart0 to platform device list\n");
 432                 iop13xx_uart0.id = uart_idx++;
 433                 iop13xx_devices[plat_idx++] = &iop13xx_uart0;
 434         }
 435
 436         for(i = 0; i < IQ81340_NUM_I2C; i++) {
 437                 if ((init_i2c & (1 << i)) && IOP13XX_SETUP_DEBUG)
 438                         printk("Adding i2c%d to platform device list\n", i);
 439                 switch(init_i2c & (1 << i)) {
 440                 case IOP13XX_INIT_I2C_0:
 441                         iop13xx_i2c_0_controller.id = i2c_idx++;
 442                         iop13xx_devices[plat_idx++] =
 443                                 &iop13xx_i2c_0_controller;
 444                         break;
 445                 case IOP13XX_INIT_I2C_1:
 446                         iop13xx_i2c_1_controller.id = i2c_idx++;
 447                         iop13xx_devices[plat_idx++] =
 448                                 &iop13xx_i2c_1_controller;
 449                         break;
 450                 case IOP13XX_INIT_I2C_2:
 451                         iop13xx_i2c_2_controller.id = i2c_idx++;
 452                         iop13xx_devices[plat_idx++] =
 453                                 &iop13xx_i2c_2_controller;
 454                         break;
 455                 }
 456         }
 457
 458         /* initialize adma channel ids and capabilities */
 459         adma_idx = 0;
 460         for (i = 0; i < IQ81340_NUM_ADMA; i++) {
 461                 struct iop_adma_platform_data *plat_data;
 462                 if ((init_adma & (1 << i)) && IOP13XX_SETUP_DEBUG)
 463                         printk(KERN_INFO
 464                                 "Adding adma%d to platform device list\n", i);
 465                 switch (init_adma & (1 << i)) {
 466                 case IOP13XX_INIT_ADMA_0:
 467                         iop13xx_adma_0_channel.id = adma_idx++;
 468                         iop13xx_devices[plat_idx++] = &iop13xx_adma_0_channel;
 469                         plat_data = &iop13xx_adma_0_data;
 470                         dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
 471                         dma_cap_set(DMA_XOR, plat_data->cap_mask);
 472                         dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask);
 473                         dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
 474                         break;
 475                 case IOP13XX_INIT_ADMA_1:
 476                         iop13xx_adma_1_channel.id = adma_idx++;
 477                         iop13xx_devices[plat_idx++] = &iop13xx_adma_1_channel;
 478                         plat_data = &iop13xx_adma_1_data;
 479                         dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
 480                         dma_cap_set(DMA_XOR, plat_data->cap_mask);
 481                         dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask);
 482                         dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
 483                         break;
 484                 case IOP13XX_INIT_ADMA_2:
 485                         iop13xx_adma_2_channel.id = adma_idx++;
 486                         iop13xx_devices[plat_idx++] = &iop13xx_adma_2_channel;
 487                         plat_data = &iop13xx_adma_2_data;
 488                         dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
 489                         dma_cap_set(DMA_XOR, plat_data->cap_mask);
 490                         dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask);
 491                         dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
 492                         dma_cap_set(DMA_PQ, plat_data->cap_mask);
 493                         dma_cap_set(DMA_PQ_VAL, plat_data->cap_mask);
 494                         break;
 495                 }
 496         }
 497
 498 #ifdef CONFIG_MTD_PHYSMAP
 499         iq8134x_flash_resource.end = iq8134x_flash_resource.start +
 500                                 iq8134x_probe_flash_size() - 1;
 501         if (iq8134x_flash_resource.end > iq8134x_flash_resource.start)
 502                 iop13xx_devices[plat_idx++] = &iq8134x_flash;
 503         else
 504                 printk(KERN_ERR "%s: Failed to probe flash size\n", __func__);
 505 #endif
 506
 507         platform_add_devices(iop13xx_devices, plat_idx);
 508 }
 509
 510 static int __init iop13xx_init_uart_setup(char *str)
 511 {
 512         if (str) {
 513                 while (*str != '\0') {
 514                         switch(*str) {
 515                         case '0':
 516                                 init_uart |= IOP13XX_INIT_UART_0;
 517                                 break;
 518                         case '1':
 519                                 init_uart |= IOP13XX_INIT_UART_1;
 520                                 break;
 521                         case ',':
 522                         case '=':
 523                                 break;
 524                         default:
 525                                 PRINTK("\"iop13xx_init_uart\" malformed"
 526                                             " at character: \'%c\'", *str);
 527                                 *(str + 1) = '\0';
 528                                 init_uart = IOP13XX_INIT_UART_DEFAULT;
 529                         }
 530                         str++;
 531                 }
 532         }
 533         return 1;
 534 }
 535
 536 static int __init iop13xx_init_i2c_setup(char *str)
 537 {
 538         if (str) {
 539                 while (*str != '\0') {
 540                         switch(*str) {
 541                         case '0':
 542                                 init_i2c |= IOP13XX_INIT_I2C_0;
 543                                 break;
 544                         case '1':
 545                                 init_i2c |= IOP13XX_INIT_I2C_1;
 546                                 break;
 547                         case '2':
 548                                 init_i2c |= IOP13XX_INIT_I2C_2;
 549                                 break;
 550                         case ',':
 551                         case '=':
 552                                 break;
 553                         default:
 554                                 PRINTK("\"iop13xx_init_i2c\" malformed"
 555                                             " at character: \'%c\'", *str);
 556                                 *(str + 1) = '\0';
 557                                 init_i2c = IOP13XX_INIT_I2C_DEFAULT;
 558                         }
 559                         str++;
 560                 }
 561         }
 562         return 1;
 563 }
 564
 565 static int __init iop13xx_init_adma_setup(char *str)
 566 {
 567         if (str)        {
 568                 while (*str != '\0') {
 569                         switch (*str) {
 570                         case '0':
 571                                 init_adma |= IOP13XX_INIT_ADMA_0;
 572                                 break;
 573                         case '1':
 574                                 init_adma |= IOP13XX_INIT_ADMA_1;
 575                                 break;
 576                         case '2':
 577                                 init_adma |= IOP13XX_INIT_ADMA_2;
 578                                 break;
 579                         case ',':
 580                         case '=':
 581                                 break;
 582                         default:
 583                                 PRINTK("\"iop13xx_init_adma\" malformed"
 584                                             " at character: \'%c\'", *str);
 585                                 *(str + 1) = '\0';
 586                                 init_adma = IOP13XX_INIT_ADMA_DEFAULT;
 587                         }
 588                         str++;
 589                 }
 590         }
 591         return 1;
 592 }
 593
 594 __setup("iop13xx_init_adma", iop13xx_init_adma_setup);
 595 __setup("iop13xx_init_uart", iop13xx_init_uart_setup);
 596 __setup("iop13xx_init_i2c", iop13xx_init_i2c_setup);
 597
 598 void iop13xx_restart(enum reboot_mode mode, const char *cmd)
 599 {
 600         /*
 601          * Reset the internal bus (warning both cores are reset)
 602          */
 603         write_wdtcr(IOP_WDTCR_EN_ARM);
 604         write_wdtcr(IOP_WDTCR_EN);
 605         write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
 606         write_wdtcr(0x1000);
 607 }