arch/arm/mach-iop13xx/pci.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * iop13xx PCI support
   4  * Copyright (c) 2005-2006, Intel Corporation.
   5  */
   6
   7 #include <linux/pci.h>
   8 #include <linux/slab.h>
   9 #include <linux/delay.h>
  10 #include <linux/jiffies.h>
  11 #include <linux/export.h>
  12 #include <asm/irq.h>
  13 #include <mach/hardware.h>
  14 #include <linux/sizes.h>
  15 #include <asm/signal.h>
  16 #include <asm/mach/pci.h>
  17 #include "pci.h"
  18
  19 #define IOP13XX_PCI_DEBUG 0
  20 #define PRINTK(x...) ((void)(IOP13XX_PCI_DEBUG && printk(x)))
  21
  22 u32 iop13xx_atux_pmmr_offset; /* This offset can change based on strapping */
  23 u32 iop13xx_atue_pmmr_offset; /* This offset can change based on strapping */
  24 static struct pci_bus *pci_bus_atux = 0;
  25 static struct pci_bus *pci_bus_atue = 0;
  26 void __iomem *iop13xx_atue_mem_base;
  27 void __iomem *iop13xx_atux_mem_base;
  28 size_t iop13xx_atue_mem_size;
  29 size_t iop13xx_atux_mem_size;
  30
  31 EXPORT_SYMBOL(iop13xx_atue_mem_base);
  32 EXPORT_SYMBOL(iop13xx_atux_mem_base);
  33 EXPORT_SYMBOL(iop13xx_atue_mem_size);
  34 EXPORT_SYMBOL(iop13xx_atux_mem_size);
  35
  36 int init_atu = 0; /* Flag to select which ATU(s) to initialize / disable */
  37 static unsigned long atux_trhfa_timeout = 0; /* Trhfa = RST# high to first
  38                                                  access */
  39
  40 /* Scan the initialized busses and ioremap the requested memory range
  41  */
  42 void iop13xx_map_pci_memory(void)
  43 {
  44         int atu;
  45         struct pci_bus *bus;
  46         struct pci_dev *dev;
  47         resource_size_t end = 0;
  48
  49         for (atu = 0; atu < 2; atu++) {
  50                 bus = atu ? pci_bus_atue : pci_bus_atux;
  51                 if (bus) {
  52                         list_for_each_entry(dev, &bus->devices, bus_list) {
  53                                 int i;
  54                                 int max = 7;
  55
  56                                 if (dev->subordinate)
  57                                         max = DEVICE_COUNT_RESOURCE;
  58
  59                                 for (i = 0; i < max; i++) {
  60                                         struct resource *res = &dev->resource[i];
  61                                         if (res->flags & IORESOURCE_MEM)
  62                                                 end = max(res->end, end);
  63                                 }
  64                         }
  65
  66                         switch(atu) {
  67                         case 0:
  68                                 iop13xx_atux_mem_size =
  69                                         (end - IOP13XX_PCIX_LOWER_MEM_RA) + 1;
  70
  71                                 /* 16MB align the request */
  72                                 if (iop13xx_atux_mem_size & (SZ_16M - 1)) {
  73                                         iop13xx_atux_mem_size &= ~(SZ_16M - 1);
  74                                         iop13xx_atux_mem_size += SZ_16M;
  75                                 }
  76
  77                                 if (end) {
  78                                         iop13xx_atux_mem_base = __arm_ioremap_pfn(
  79                                         __phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA)
  80                                         , 0, iop13xx_atux_mem_size, MT_DEVICE);
  81                                         if (!iop13xx_atux_mem_base) {
  82                                                 printk("%s: atux allocation "
  83                                                        "failed\n", __func__);
  84                                                 BUG();
  85                                         }
  86                                 } else
  87                                         iop13xx_atux_mem_size = 0;
  88                                 PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n",
  89                                 __func__, atu, iop13xx_atux_mem_size,
  90                                 iop13xx_atux_mem_base);
  91                                 break;
  92                         case 1:
  93                                 iop13xx_atue_mem_size =
  94                                         (end - IOP13XX_PCIE_LOWER_MEM_RA) + 1;
  95
  96                                 /* 16MB align the request */
  97                                 if (iop13xx_atue_mem_size & (SZ_16M - 1)) {
  98                                         iop13xx_atue_mem_size &= ~(SZ_16M - 1);
  99                                         iop13xx_atue_mem_size += SZ_16M;
 100                                 }
 101
 102                                 if (end) {
 103                                         iop13xx_atue_mem_base = __arm_ioremap_pfn(
 104                                         __phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA)
 105                                         , 0, iop13xx_atue_mem_size, MT_DEVICE);
 106                                         if (!iop13xx_atue_mem_base) {
 107                                                 printk("%s: atue allocation "
 108                                                        "failed\n", __func__);
 109                                                 BUG();
 110                                         }
 111                                 } else
 112                                         iop13xx_atue_mem_size = 0;
 113                                 PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n",
 114                                 __func__, atu, iop13xx_atue_mem_size,
 115                                 iop13xx_atue_mem_base);
 116                                 break;
 117                         }
 118
 119                         printk("%s: Initialized (%uM @ resource/virtual: %08lx/%p)\n",
 120                         atu ? "ATUE" : "ATUX",
 121                         (atu ? iop13xx_atue_mem_size : iop13xx_atux_mem_size) /
 122                         SZ_1M,
 123                         atu ? IOP13XX_PCIE_LOWER_MEM_RA :
 124                         IOP13XX_PCIX_LOWER_MEM_RA,
 125                         atu ? iop13xx_atue_mem_base :
 126                         iop13xx_atux_mem_base);
 127                         end = 0;
 128                 }
 129
 130         }
 131 }
 132
 133 static int iop13xx_atu_function(int atu)
 134 {
 135         int func = 0;
 136         /* the function number depends on the value of the
 137          * IOP13XX_INTERFACE_SEL_PCIX reset strap
 138          * see C-Spec section 3.17
 139          */
 140         switch(atu) {
 141         case IOP13XX_INIT_ATU_ATUX:
 142                 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
 143                         func = 5;
 144                 else
 145                         func = 0;
 146                 break;
 147         case IOP13XX_INIT_ATU_ATUE:
 148                 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
 149                         func = 0;
 150                 else
 151                         func = 5;
 152                 break;
 153         default:
 154                 BUG();
 155         }
 156
 157         return func;
 158 }
 159
 160 /* iop13xx_atux_cfg_address - format a configuration address for atux
 161  * @bus: Target bus to access
 162  * @devfn: Combined device number and function number
 163  * @where: Desired register's address offset
 164  *
 165  * Convert the parameters to a configuration address formatted
 166  * according the PCI-X 2.0 specification
 167  */
 168 static u32 iop13xx_atux_cfg_address(struct pci_bus *bus, int devfn, int where)
 169 {
 170         struct pci_sys_data *sys = bus->sysdata;
 171         u32 addr;
 172
 173         if (sys->busnr == bus->number)
 174                 addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11);
 175         else
 176                 addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;
 177
 178         addr |= PCI_FUNC(devfn) << 8 | ((where & 0xff) & ~3);
 179         addr |= ((where & 0xf00) >> 8) << 24; /* upper register number */
 180
 181         return addr;
 182 }
 183
 184 /* iop13xx_atue_cfg_address - format a configuration address for atue
 185  * @bus: Target bus to access
 186  * @devfn: Combined device number and function number
 187  * @where: Desired register's address offset
 188  *
 189  * Convert the parameters to an address usable by the ATUE_OCCAR
 190  */
 191 static u32 iop13xx_atue_cfg_address(struct pci_bus *bus, int devfn, int where)
 192 {
 193         struct pci_sys_data *sys = bus->sysdata;
 194         u32 addr;
 195
 196         PRINTK("iop13xx_atue_cfg_address: bus: %d dev: %d func: %d",
 197                 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
 198         addr = ((u32) bus->number)     << IOP13XX_ATUE_OCCAR_BUS_NUM |
 199                    ((u32) PCI_SLOT(devfn)) << IOP13XX_ATUE_OCCAR_DEV_NUM |
 200                    ((u32) PCI_FUNC(devfn)) << IOP13XX_ATUE_OCCAR_FUNC_NUM |
 201                    (where & ~0x3);
 202
 203         if (sys->busnr != bus->number)
 204                 addr |= 1; /* type 1 access */
 205
 206         return addr;
 207 }
 208
 209 /* This routine checks the status of the last configuration cycle.  If an error
 210  * was detected it returns >0, else it returns a 0.  The errors being checked
 211  * are parity, master abort, target abort (master and target).  These types of
 212  * errors occur during a config cycle where there is no device, like during
 213  * the discovery stage.
 214  */
 215 static int iop13xx_atux_pci_status(int clear)
 216 {
 217         unsigned int status;
 218         int err = 0;
 219
 220         /*
 221          * Check the status registers.
 222          */
 223         status = __raw_readw(IOP13XX_ATUX_ATUSR);
 224         if (status & IOP_PCI_STATUS_ERROR)
 225         {
 226                 PRINTK("\t\t\tPCI error: ATUSR %#08x", status);
 227                 if(clear)
 228                         __raw_writew(status & IOP_PCI_STATUS_ERROR,
 229                                 IOP13XX_ATUX_ATUSR);
 230                 err = 1;
 231         }
 232         status = __raw_readl(IOP13XX_ATUX_ATUISR);
 233         if (status & IOP13XX_ATUX_ATUISR_ERROR)
 234         {
 235                 PRINTK("\t\t\tPCI error interrupt:  ATUISR %#08x", status);
 236                 if(clear)
 237                         __raw_writel(status & IOP13XX_ATUX_ATUISR_ERROR,
 238                                 IOP13XX_ATUX_ATUISR);
 239                 err = 1;
 240         }
 241         return err;
 242 }
 243
 244 /* Simply write the address register and read the configuration
 245  * data.  Note that the data dependency on %0 encourages an abort
 246  * to be detected before we return.
 247  */
 248 static u32 iop13xx_atux_read(unsigned long addr)
 249 {
 250         u32 val;
 251
 252         __asm__ __volatile__(
 253                 "str    %1, [%2]\n\t"
 254                 "ldr    %0, [%3]\n\t"
 255                 "mov    %0, %0\n\t"
 256                 : "=r" (val)
 257                 : "r" (addr), "r" (IOP13XX_ATUX_OCCAR), "r" (IOP13XX_ATUX_OCCDR));
 258
 259         return val;
 260 }
 261
 262 /* The read routines must check the error status of the last configuration
 263  * cycle.  If there was an error, the routine returns all hex f's.
 264  */
 265 static int
 266 iop13xx_atux_read_config(struct pci_bus *bus, unsigned int devfn, int where,
 267                 int size, u32 *value)
 268 {
 269         unsigned long addr = iop13xx_atux_cfg_address(bus, devfn, where);
 270         u32 val = iop13xx_atux_read(addr) >> ((where & 3) * 8);
 271
 272         if (iop13xx_atux_pci_status(1) || is_atux_occdr_error()) {
 273                 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3,
 274                         IOP13XX_XBG_BECSR);
 275                 val = 0xffffffff;
 276         }
 277
 278         *value = val;
 279
 280         return PCIBIOS_SUCCESSFUL;
 281 }
 282
 283 static int
 284 iop13xx_atux_write_config(struct pci_bus *bus, unsigned int devfn, int where,
 285                 int size, u32 value)
 286 {
 287         unsigned long addr = iop13xx_atux_cfg_address(bus, devfn, where);
 288         u32 val;
 289
 290         if (size != 4) {
 291                 val = iop13xx_atux_read(addr);
 292                 if (!iop13xx_atux_pci_status(1) == 0)
 293                         return PCIBIOS_SUCCESSFUL;
 294
 295                 where = (where & 3) * 8;
 296
 297                 if (size == 1)
 298                         val &= ~(0xff << where);
 299                 else
 300                         val &= ~(0xffff << where);
 301
 302                 __raw_writel(val | value << where, IOP13XX_ATUX_OCCDR);
 303         } else {
 304                 __raw_writel(addr, IOP13XX_ATUX_OCCAR);
 305                 __raw_writel(value, IOP13XX_ATUX_OCCDR);
 306         }
 307
 308         return PCIBIOS_SUCCESSFUL;
 309 }
 310
 311 static struct pci_ops iop13xx_atux_ops = {
 312         .read   = iop13xx_atux_read_config,
 313         .write  = iop13xx_atux_write_config,
 314 };
 315
 316 /* This routine checks the status of the last configuration cycle.  If an error
 317  * was detected it returns >0, else it returns a 0.  The errors being checked
 318  * are parity, master abort, target abort (master and target).  These types of
 319  * errors occur during a config cycle where there is no device, like during
 320  * the discovery stage.
 321  */
 322 static int iop13xx_atue_pci_status(int clear)
 323 {
 324         unsigned int status;
 325         int err = 0;
 326
 327         /*
 328          * Check the status registers.
 329          */
 330
 331         /* standard pci status register */
 332         status = __raw_readw(IOP13XX_ATUE_ATUSR);
 333         if (status & IOP_PCI_STATUS_ERROR) {
 334                 PRINTK("\t\t\tPCI error: ATUSR %#08x", status);
 335                 if(clear)
 336                         __raw_writew(status & IOP_PCI_STATUS_ERROR,
 337                                 IOP13XX_ATUE_ATUSR);
 338                 err++;
 339         }
 340
 341         /* check the normal status bits in the ATUISR */
 342         status = __raw_readl(IOP13XX_ATUE_ATUISR);
 343         if (status & IOP13XX_ATUE_ATUISR_ERROR) {
 344                 PRINTK("\t\t\tPCI error: ATUISR %#08x", status);
 345                 if (clear)
 346                         __raw_writew(status & IOP13XX_ATUE_ATUISR_ERROR,
 347                                 IOP13XX_ATUE_ATUISR);
 348                 err++;
 349
 350                 /* check the PCI-E status if the ATUISR reports an interface error */
 351                 if (status & IOP13XX_ATUE_STAT_PCI_IFACE_ERR) {
 352                         /* get the unmasked errors */
 353                         status = __raw_readl(IOP13XX_ATUE_PIE_STS) &
 354                                         ~(__raw_readl(IOP13XX_ATUE_PIE_MSK));
 355
 356                         if (status) {
 357                                 PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x",
 358                                         __raw_readl(IOP13XX_ATUE_PIE_STS));
 359                                 err++;
 360                         } else {
 361                                 PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x",
 362                                         __raw_readl(IOP13XX_ATUE_PIE_STS));
 363                                 PRINTK("\t\t\tPCI-E error: ATUE_PIE_MSK %#08x",
 364                                         __raw_readl(IOP13XX_ATUE_PIE_MSK));
 365                                 BUG();
 366                         }
 367
 368                         if(clear)
 369                                 __raw_writel(status, IOP13XX_ATUE_PIE_STS);
 370                 }
 371         }
 372
 373         return err;
 374 }
 375
 376 static int
 377 iop13xx_pcie_map_irq(const struct pci_dev *dev, u8 idsel, u8 pin)
 378 {
 379         WARN_ON(idsel != 0);
 380
 381         switch (pin) {
 382         case 1: return ATUE_INTA;
 383         case 2: return ATUE_INTB;
 384         case 3: return ATUE_INTC;
 385         case 4: return ATUE_INTD;
 386         default: return -1;
 387         }
 388 }
 389
 390 static u32 iop13xx_atue_read(unsigned long addr)
 391 {
 392         u32 val;
 393
 394         __raw_writel(addr, IOP13XX_ATUE_OCCAR);
 395         val = __raw_readl(IOP13XX_ATUE_OCCDR);
 396
 397         rmb();
 398
 399         return val;
 400 }
 401
 402 /* The read routines must check the error status of the last configuration
 403  * cycle.  If there was an error, the routine returns all hex f's.
 404  */
 405 static int
 406 iop13xx_atue_read_config(struct pci_bus *bus, unsigned int devfn, int where,
 407                 int size, u32 *value)
 408 {
 409         u32 val;
 410         unsigned long addr = iop13xx_atue_cfg_address(bus, devfn, where);
 411
 412         /* Hide device numbers > 0 on the local PCI-E bus (Type 0 access) */
 413         if (!PCI_SLOT(devfn) || (addr & 1)) {
 414                 val = iop13xx_atue_read(addr) >> ((where & 3) * 8);
 415                 if( iop13xx_atue_pci_status(1) || is_atue_occdr_error() ) {
 416                         __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3,
 417                                 IOP13XX_XBG_BECSR);
 418                         val = 0xffffffff;
 419                 }
 420
 421                 PRINTK("addr=%#0lx, val=%#010x", addr, val);
 422         } else
 423                 val = 0xffffffff;
 424
 425         *value = val;
 426
 427         return PCIBIOS_SUCCESSFUL;
 428 }
 429
 430 static int
 431 iop13xx_atue_write_config(struct pci_bus *bus, unsigned int devfn, int where,
 432                 int size, u32 value)
 433 {
 434         unsigned long addr = iop13xx_atue_cfg_address(bus, devfn, where);
 435         u32 val;
 436
 437         if (size != 4) {
 438                 val = iop13xx_atue_read(addr);
 439                 if (!iop13xx_atue_pci_status(1) == 0)
 440                         return PCIBIOS_SUCCESSFUL;
 441
 442                 where = (where & 3) * 8;
 443
 444                 if (size == 1)
 445                         val &= ~(0xff << where);
 446                 else
 447                         val &= ~(0xffff << where);
 448
 449                 __raw_writel(val | value << where, IOP13XX_ATUE_OCCDR);
 450         } else {
 451                 __raw_writel(addr, IOP13XX_ATUE_OCCAR);
 452                 __raw_writel(value, IOP13XX_ATUE_OCCDR);
 453         }
 454
 455         return PCIBIOS_SUCCESSFUL;
 456 }
 457
 458 static struct pci_ops iop13xx_atue_ops = {
 459         .read   = iop13xx_atue_read_config,
 460         .write  = iop13xx_atue_write_config,
 461 };
 462
 463 /* When a PCI device does not exist during config cycles, the XScale gets a
 464  * bus error instead of returning 0xffffffff.  We can't rely on the ATU status
 465  * bits to tell us that it was indeed a configuration cycle that caused this
 466  * error especially in the case when the ATUE link is down.  Instead we rely
 467  * on data from the south XSI bridge to validate the abort
 468  */
 469 int
 470 iop13xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
 471 {
 472         PRINTK("Data abort: address = 0x%08lx "
 473                     "fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx",
 474                 addr, fsr, regs->ARM_pc, regs->ARM_lr);
 475
 476         PRINTK("IOP13XX_XBG_BECSR: %#10x", __raw_readl(IOP13XX_XBG_BECSR));
 477         PRINTK("IOP13XX_XBG_BERAR: %#10x", __raw_readl(IOP13XX_XBG_BERAR));
 478         PRINTK("IOP13XX_XBG_BERUAR: %#10x", __raw_readl(IOP13XX_XBG_BERUAR));
 479
 480         /*  If it was an imprecise abort, then we need to correct the
 481          *  return address to be _after_ the instruction.
 482          */
 483         if (fsr & (1 << 10))
 484                 regs->ARM_pc += 4;
 485
 486         if (is_atue_occdr_error() || is_atux_occdr_error())
 487                 return 0;
 488         else
 489                 return 1;
 490 }
 491
 492 /* Scan an IOP13XX PCI bus.  nr selects which ATU we use.
 493  */
 494 int iop13xx_scan_bus(int nr, struct pci_host_bridge *bridge)
 495 {
 496         int which_atu, ret;
 497         struct pci_sys_data *sys = pci_host_bridge_priv(bridge);
 498
 499         switch (init_atu) {
 500         case IOP13XX_INIT_ATU_ATUX:
 501                 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUX;
 502                 break;
 503         case IOP13XX_INIT_ATU_ATUE:
 504                 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUE;
 505                 break;
 506         case (IOP13XX_INIT_ATU_ATUX | IOP13XX_INIT_ATU_ATUE):
 507                 which_atu = nr ? IOP13XX_INIT_ATU_ATUE : IOP13XX_INIT_ATU_ATUX;
 508                 break;
 509         default:
 510                 which_atu = 0;
 511         }
 512
 513         if (!which_atu) {
 514                 BUG();
 515                 return -ENODEV;
 516         }
 517
 518         list_splice_init(&sys->resources, &bridge->windows);
 519         bridge->dev.parent = NULL;
 520         bridge->sysdata = sys;
 521         bridge->busnr = sys->busnr;
 522
 523         switch (which_atu) {
 524         case IOP13XX_INIT_ATU_ATUX:
 525                 if (time_after_eq(jiffies + msecs_to_jiffies(1000),
 526                                   atux_trhfa_timeout))  /* ensure not wrap */
 527                         while(time_before(jiffies, atux_trhfa_timeout))
 528                                 udelay(100);
 529
 530                 bridge->ops = &iop13xx_atux_ops;
 531                 ret = pci_scan_root_bus_bridge(bridge);
 532                 if (!ret)
 533                         pci_bus_atux = bridge->bus;
 534                 break;
 535         case IOP13XX_INIT_ATU_ATUE:
 536                 bridge->ops = &iop13xx_atue_ops;
 537                 ret = pci_scan_root_bus_bridge(bridge);
 538                 if (!ret)
 539                         pci_bus_atue = bridge->bus;
 540                 break;
 541         default:
 542                 ret = -EINVAL;
 543         }
 544
 545         return ret;
 546 }
 547
 548 /* This function is called from iop13xx_pci_init() after assigning valid
 549  * values to iop13xx_atue_pmmr_offset.  This is the location for common
 550  * setup of ATUE for all IOP13XX implementations.
 551  */
 552 void __init iop13xx_atue_setup(void)
 553 {
 554         int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUE);
 555         u32 reg_val;
 556
 557 #ifdef CONFIG_PCI_MSI
 558         /* BAR 0 (inbound msi window) */
 559         __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_MU_MUBAR);
 560         __raw_writel(~(IOP13XX_MU_WINDOW_SIZE - 1), IOP13XX_ATUE_IALR0);
 561         __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_ATUE_IATVR0);
 562         __raw_writel(IOP13XX_MU_BASE_PCI, IOP13XX_ATUE_IABAR0);
 563 #endif
 564
 565         /* BAR 1 (1:1 mapping with Physical RAM) */
 566         /* Set limit and enable */
 567         __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1,
 568                         IOP13XX_ATUE_IALR1);
 569         __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1);
 570
 571         /* Set base at the top of the reserved address space */
 572         __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 |
 573                         PCI_BASE_ADDRESS_MEM_PREFETCH, IOP13XX_ATUE_IABAR1);
 574
 575         /* 1:1 mapping with physical ram
 576          * (leave big endian byte swap disabled)
 577          */
 578          __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1);
 579          __raw_writel(PHYS_OFFSET, IOP13XX_ATUE_IATVR1);
 580
 581         /* Outbound window 1 (PCIX/PCIE memory window) */
 582         /* 32 bit Address Space */
 583         __raw_writel(0x0, IOP13XX_ATUE_OUMWTVR1);
 584         /* PA[35:32] */
 585         __raw_writel(IOP13XX_ATUE_OUMBAR_ENABLE |
 586                         (IOP13XX_PCIE_MEM_PHYS_OFFSET >> 32),
 587                         IOP13XX_ATUE_OUMBAR1);
 588
 589         /* Setup the I/O Bar
 590          * A[35-16] in 31-12
 591          */
 592         __raw_writel(((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000),
 593                 IOP13XX_ATUE_OIOBAR);
 594         __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR);
 595
 596         /* clear startup errors */
 597         iop13xx_atue_pci_status(1);
 598
 599         /* OIOBAR function number
 600          */
 601         reg_val = __raw_readl(IOP13XX_ATUE_OIOBAR);
 602         reg_val &= ~0x7;
 603         reg_val |= func;
 604         __raw_writel(reg_val, IOP13XX_ATUE_OIOBAR);
 605
 606         /* OUMBAR function numbers
 607          */
 608         reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0);
 609         reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
 610                         IOP13XX_ATU_OUMBAR_FUNC_NUM);
 611         reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
 612         __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0);
 613
 614         reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1);
 615         reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
 616                         IOP13XX_ATU_OUMBAR_FUNC_NUM);
 617         reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
 618         __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1);
 619
 620         reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2);
 621         reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
 622                         IOP13XX_ATU_OUMBAR_FUNC_NUM);
 623         reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
 624         __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2);
 625
 626         reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3);
 627         reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
 628                         IOP13XX_ATU_OUMBAR_FUNC_NUM);
 629         reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
 630         __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3);
 631
 632         /* Enable inbound and outbound cycles
 633          */
 634         reg_val = __raw_readw(IOP13XX_ATUE_ATUCMD);
 635         reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
 636                         PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
 637         __raw_writew(reg_val, IOP13XX_ATUE_ATUCMD);
 638
 639         reg_val = __raw_readl(IOP13XX_ATUE_ATUCR);
 640         reg_val |= IOP13XX_ATUE_ATUCR_OUT_EN |
 641                         IOP13XX_ATUE_ATUCR_IVM;
 642         __raw_writel(reg_val, IOP13XX_ATUE_ATUCR);
 643 }
 644
 645 void __init iop13xx_atue_disable(void)
 646 {
 647         u32 reg_val;
 648
 649         __raw_writew(0x0, IOP13XX_ATUE_ATUCMD);
 650         __raw_writel(IOP13XX_ATUE_ATUCR_IVM, IOP13XX_ATUE_ATUCR);
 651
 652         /* wait for cycles to quiesce */
 653         while (__raw_readl(IOP13XX_ATUE_PCSR) & (IOP13XX_ATUE_PCSR_OUT_Q_BUSY |
 654                                              IOP13XX_ATUE_PCSR_IN_Q_BUSY |
 655                                              IOP13XX_ATUE_PCSR_LLRB_BUSY))
 656                 cpu_relax();
 657
 658         /* BAR 0 ( Disabled ) */
 659         __raw_writel(0x0, IOP13XX_ATUE_IAUBAR0);
 660         __raw_writel(0x0, IOP13XX_ATUE_IABAR0);
 661         __raw_writel(0x0, IOP13XX_ATUE_IAUTVR0);
 662         __raw_writel(0x0, IOP13XX_ATUE_IATVR0);
 663         __raw_writel(0x0, IOP13XX_ATUE_IALR0);
 664         reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0);
 665         reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
 666         __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0);
 667
 668         /* BAR 1 ( Disabled ) */
 669         __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1);
 670         __raw_writel(0x0, IOP13XX_ATUE_IABAR1);
 671         __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1);
 672         __raw_writel(0x0, IOP13XX_ATUE_IATVR1);
 673         __raw_writel(0x0, IOP13XX_ATUE_IALR1);
 674         reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1);
 675         reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
 676         __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1);
 677
 678         /* BAR 2 ( Disabled ) */
 679         __raw_writel(0x0, IOP13XX_ATUE_IAUBAR2);
 680         __raw_writel(0x0, IOP13XX_ATUE_IABAR2);
 681         __raw_writel(0x0, IOP13XX_ATUE_IAUTVR2);
 682         __raw_writel(0x0, IOP13XX_ATUE_IATVR2);
 683         __raw_writel(0x0, IOP13XX_ATUE_IALR2);
 684         reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2);
 685         reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
 686         __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2);
 687
 688         /* BAR 3 ( Disabled ) */
 689         reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3);
 690         reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
 691         __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3);
 692
 693         /* Setup the I/O Bar
 694          * A[35-16] in 31-12
 695          */
 696         __raw_writel((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000,
 697                         IOP13XX_ATUE_OIOBAR);
 698         __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR);
 699 }
 700
 701 /* This function is called from iop13xx_pci_init() after assigning valid
 702  * values to iop13xx_atux_pmmr_offset.  This is the location for common
 703  * setup of ATUX for all IOP13XX implementations.
 704  */
 705 void __init iop13xx_atux_setup(void)
 706 {
 707         u32 reg_val;
 708         int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX);
 709
 710         /* Take PCI-X bus out of reset if bootloader hasn't already.
 711          * According to spec, we should wait for 2^25 PCI clocks to meet
 712          * the PCI timing parameter Trhfa (RST# high to first access).
 713          * This is rarely necessary and often ignored.
 714          */
 715         reg_val = __raw_readl(IOP13XX_ATUX_PCSR);
 716         if (reg_val & IOP13XX_ATUX_PCSR_P_RSTOUT) {
 717                 int msec = (reg_val >> IOP13XX_ATUX_PCSR_FREQ_OFFSET) & 0x7;
 718                 msec = 1000 / (8-msec); /* bits 100=133MHz, 111=>33MHz */
 719                 __raw_writel(reg_val & ~IOP13XX_ATUX_PCSR_P_RSTOUT,
 720                                 IOP13XX_ATUX_PCSR);
 721                 atux_trhfa_timeout = jiffies + msecs_to_jiffies(msec);
 722         }
 723         else
 724                 atux_trhfa_timeout = jiffies;
 725
 726 #ifdef CONFIG_PCI_MSI
 727         /* BAR 0 (inbound msi window) */
 728         __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_MU_MUBAR);
 729         __raw_writel(~(IOP13XX_MU_WINDOW_SIZE - 1), IOP13XX_ATUX_IALR0);
 730         __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_ATUX_IATVR0);
 731         __raw_writel(IOP13XX_MU_BASE_PCI, IOP13XX_ATUX_IABAR0);
 732 #endif
 733
 734         /* BAR 1 (1:1 mapping with Physical RAM) */
 735         /* Set limit and enable */
 736         __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1,
 737                         IOP13XX_ATUX_IALR1);
 738         __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1);
 739
 740         /* Set base at the top of the reserved address space */
 741         __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 |
 742                         PCI_BASE_ADDRESS_MEM_PREFETCH, IOP13XX_ATUX_IABAR1);
 743
 744         /* 1:1 mapping with physical ram
 745          * (leave big endian byte swap disabled)
 746          */
 747         __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1);
 748         __raw_writel(PHYS_OFFSET, IOP13XX_ATUX_IATVR1);
 749
 750         /* Outbound window 1 (PCIX/PCIE memory window) */
 751         /* 32 bit Address Space */
 752         __raw_writel(0x0, IOP13XX_ATUX_OUMWTVR1);
 753         /* PA[35:32] */
 754         __raw_writel(IOP13XX_ATUX_OUMBAR_ENABLE |
 755                         IOP13XX_PCIX_MEM_PHYS_OFFSET >> 32,
 756                         IOP13XX_ATUX_OUMBAR1);
 757
 758         /* Setup the I/O Bar
 759          * A[35-16] in 31-12
 760          */
 761         __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000,
 762                 IOP13XX_ATUX_OIOBAR);
 763         __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR);
 764
 765         /* clear startup errors */
 766         iop13xx_atux_pci_status(1);
 767
 768         /* OIOBAR function number
 769          */
 770         reg_val = __raw_readl(IOP13XX_ATUX_OIOBAR);
 771         reg_val &= ~0x7;
 772         reg_val |= func;
 773         __raw_writel(reg_val, IOP13XX_ATUX_OIOBAR);
 774
 775         /* OUMBAR function numbers
 776          */
 777         reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0);
 778         reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
 779                         IOP13XX_ATU_OUMBAR_FUNC_NUM);
 780         reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
 781         __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0);
 782
 783         reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1);
 784         reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
 785                         IOP13XX_ATU_OUMBAR_FUNC_NUM);
 786         reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
 787         __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1);
 788
 789         reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2);
 790         reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
 791                         IOP13XX_ATU_OUMBAR_FUNC_NUM);
 792         reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
 793         __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2);
 794
 795         reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3);
 796         reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
 797                         IOP13XX_ATU_OUMBAR_FUNC_NUM);
 798         reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
 799         __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3);
 800
 801         /* Enable inbound and outbound cycles
 802          */
 803         reg_val = __raw_readw(IOP13XX_ATUX_ATUCMD);
 804         reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
 805                         PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
 806         __raw_writew(reg_val, IOP13XX_ATUX_ATUCMD);
 807
 808         reg_val = __raw_readl(IOP13XX_ATUX_ATUCR);
 809         reg_val |= IOP13XX_ATUX_ATUCR_OUT_EN;
 810         __raw_writel(reg_val, IOP13XX_ATUX_ATUCR);
 811 }
 812
 813 void __init iop13xx_atux_disable(void)
 814 {
 815         u32 reg_val;
 816
 817         __raw_writew(0x0, IOP13XX_ATUX_ATUCMD);
 818         __raw_writel(0x0, IOP13XX_ATUX_ATUCR);
 819
 820         /* wait for cycles to quiesce */
 821         while (__raw_readl(IOP13XX_ATUX_PCSR) & (IOP13XX_ATUX_PCSR_OUT_Q_BUSY |
 822                                      IOP13XX_ATUX_PCSR_IN_Q_BUSY))
 823                 cpu_relax();
 824
 825         /* BAR 0 ( Disabled ) */
 826         __raw_writel(0x0, IOP13XX_ATUX_IAUBAR0);
 827         __raw_writel(0x0, IOP13XX_ATUX_IABAR0);
 828         __raw_writel(0x0, IOP13XX_ATUX_IAUTVR0);
 829         __raw_writel(0x0, IOP13XX_ATUX_IATVR0);
 830         __raw_writel(0x0, IOP13XX_ATUX_IALR0);
 831         reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0);
 832         reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
 833         __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0);
 834
 835         /* BAR 1 ( Disabled ) */
 836         __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1);
 837         __raw_writel(0x0, IOP13XX_ATUX_IABAR1);
 838         __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1);
 839         __raw_writel(0x0, IOP13XX_ATUX_IATVR1);
 840         __raw_writel(0x0, IOP13XX_ATUX_IALR1);
 841         reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1);
 842         reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
 843         __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1);
 844
 845         /* BAR 2 ( Disabled ) */
 846         __raw_writel(0x0, IOP13XX_ATUX_IAUBAR2);
 847         __raw_writel(0x0, IOP13XX_ATUX_IABAR2);
 848         __raw_writel(0x0, IOP13XX_ATUX_IAUTVR2);
 849         __raw_writel(0x0, IOP13XX_ATUX_IATVR2);
 850         __raw_writel(0x0, IOP13XX_ATUX_IALR2);
 851         reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2);
 852         reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
 853         __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2);
 854
 855         /* BAR 3 ( Disabled ) */
 856         __raw_writel(0x0, IOP13XX_ATUX_IAUBAR3);
 857         __raw_writel(0x0, IOP13XX_ATUX_IABAR3);
 858         __raw_writel(0x0, IOP13XX_ATUX_IAUTVR3);
 859         __raw_writel(0x0, IOP13XX_ATUX_IATVR3);
 860         __raw_writel(0x0, IOP13XX_ATUX_IALR3);
 861         reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3);
 862         reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
 863         __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3);
 864
 865         /* Setup the I/O Bar
 866         * A[35-16] in 31-12
 867         */
 868         __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000,
 869                         IOP13XX_ATUX_OIOBAR);
 870         __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR);
 871 }
 872
 873 void __init iop13xx_set_atu_mmr_bases(void)
 874 {
 875         /* Based on ESSR0, determine the ATU X/E offsets */
 876         switch(__raw_readl(IOP13XX_ESSR0) &
 877                 (IOP13XX_CONTROLLER_ONLY | IOP13XX_INTERFACE_SEL_PCIX)) {
 878         /* both asserted */
 879         case 0:
 880                 iop13xx_atux_pmmr_offset = IOP13XX_ATU1_PMMR_OFFSET;
 881                 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
 882                 break;
 883         /* IOP13XX_CONTROLLER_ONLY = deasserted
 884          * IOP13XX_INTERFACE_SEL_PCIX = asserted
 885          */
 886         case IOP13XX_CONTROLLER_ONLY:
 887                 iop13xx_atux_pmmr_offset = IOP13XX_ATU0_PMMR_OFFSET;
 888                 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
 889                 break;
 890         /* IOP13XX_CONTROLLER_ONLY = asserted
 891          * IOP13XX_INTERFACE_SEL_PCIX = deasserted
 892          */
 893         case IOP13XX_INTERFACE_SEL_PCIX:
 894                 iop13xx_atux_pmmr_offset = IOP13XX_ATU1_PMMR_OFFSET;
 895                 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
 896                 break;
 897         /* both deasserted */
 898         case IOP13XX_CONTROLLER_ONLY | IOP13XX_INTERFACE_SEL_PCIX:
 899                 iop13xx_atux_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
 900                 iop13xx_atue_pmmr_offset = IOP13XX_ATU0_PMMR_OFFSET;
 901                 break;
 902         default:
 903                 BUG();
 904         }
 905 }
 906
 907 void __init iop13xx_atu_select(struct hw_pci *plat_pci)
 908 {
 909         int i;
 910
 911         /* set system defaults
 912          * note: if "iop13xx_init_atu=" is specified this autodetect
 913          * sequence will be bypassed
 914          */
 915         if (init_atu == IOP13XX_INIT_ATU_DEFAULT) {
 916                 /* check for single/dual interface */
 917                 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX) {
 918                         /* ATUE must be present check the device id
 919                          * to see if ATUX is present.
 920                          */
 921                         init_atu |= IOP13XX_INIT_ATU_ATUE;
 922                         switch (__raw_readw(IOP13XX_ATUE_DID) & 0xf0) {
 923                         case 0x70:
 924                         case 0x80:
 925                         case 0xc0:
 926                                 init_atu |= IOP13XX_INIT_ATU_ATUX;
 927                                 break;
 928                         }
 929                 } else {
 930                         /* ATUX must be present check the device id
 931                          * to see if ATUE is present.
 932                          */
 933                         init_atu |= IOP13XX_INIT_ATU_ATUX;
 934                         switch (__raw_readw(IOP13XX_ATUX_DID) & 0xf0) {
 935                         case 0x70:
 936                         case 0x80:
 937                         case 0xc0:
 938                                 init_atu |= IOP13XX_INIT_ATU_ATUE;
 939                                 break;
 940                         }
 941                 }
 942
 943                 /* check central resource and root complex capability */
 944                 if (init_atu & IOP13XX_INIT_ATU_ATUX)
 945                         if (!(__raw_readl(IOP13XX_ATUX_PCSR) &
 946                                 IOP13XX_ATUX_PCSR_CENTRAL_RES))
 947                                 init_atu &= ~IOP13XX_INIT_ATU_ATUX;
 948
 949                 if (init_atu & IOP13XX_INIT_ATU_ATUE)
 950                         if (__raw_readl(IOP13XX_ATUE_PCSR) &
 951                                 IOP13XX_ATUE_PCSR_END_POINT)
 952                                 init_atu &= ~IOP13XX_INIT_ATU_ATUE;
 953         }
 954
 955         for (i = 0; i < 2; i++) {
 956                 if((init_atu & (1 << i)) == (1 << i))
 957                         plat_pci->nr_controllers++;
 958         }
 959 }
 960
 961 void __init iop13xx_pci_init(void)
 962 {
 963         /* clear pre-existing south bridge errors */
 964         __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR);
 965
 966         /* Setup the Min Address for PCI memory... */
 967         pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA;
 968
 969         /* if Linux is given control of an ATU
 970          * clear out its prior configuration,
 971          * otherwise do not touch the registers
 972          */
 973         if (init_atu & IOP13XX_INIT_ATU_ATUE) {
 974                 iop13xx_atue_disable();
 975                 iop13xx_atue_setup();
 976         }
 977
 978         if (init_atu & IOP13XX_INIT_ATU_ATUX) {
 979                 iop13xx_atux_disable();
 980                 iop13xx_atux_setup();
 981         }
 982
 983         hook_fault_code(16+6, iop13xx_pci_abort, SIGBUS, 0,
 984                         "imprecise external abort");
 985 }
 986
 987 /* initialize the pci memory space.  handle any combination of
 988  * atue and atux enabled/disabled
 989  */
 990 int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
 991 {
 992         struct resource *res;
 993         int which_atu;
 994         u32 pcixsr, pcsr;
 995
 996         if (nr > 1)
 997                 return 0;
 998
 999         res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1000         if (!res)
1001                 panic("PCI: unable to alloc resources");
1002
1003
1004         /* 'nr' assumptions:
1005          * ATUX is always 0
1006          * ATUE is 1 when ATUX is also enabled
1007          * ATUE is 0 when ATUX is disabled
1008          */
1009         switch(init_atu) {
1010         case IOP13XX_INIT_ATU_ATUX:
1011                 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUX;
1012                 break;
1013         case IOP13XX_INIT_ATU_ATUE:
1014                 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUE;
1015                 break;
1016         case (IOP13XX_INIT_ATU_ATUX | IOP13XX_INIT_ATU_ATUE):
1017                 which_atu = nr ? IOP13XX_INIT_ATU_ATUE : IOP13XX_INIT_ATU_ATUX;
1018                 break;
1019         default:
1020                 which_atu = 0;
1021         }
1022
1023         if (!which_atu) {
1024                 kfree(res);
1025                 return 0;
1026         }
1027
1028         switch(which_atu) {
1029         case IOP13XX_INIT_ATU_ATUX:
1030                 pcixsr = __raw_readl(IOP13XX_ATUX_PCIXSR);
1031                 pcixsr &= ~0xffff;
1032                 pcixsr |= sys->busnr << IOP13XX_ATUX_PCIXSR_BUS_NUM |
1033                           0 << IOP13XX_ATUX_PCIXSR_DEV_NUM |
1034                           iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX)
1035                                   << IOP13XX_ATUX_PCIXSR_FUNC_NUM;
1036                 __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR);
1037
1038                 pci_ioremap_io(0, IOP13XX_PCIX_LOWER_IO_PA);
1039
1040                 res->start = IOP13XX_PCIX_LOWER_MEM_RA;
1041                 res->end   = IOP13XX_PCIX_UPPER_MEM_RA;
1042                 res->name  = "IQ81340 ATUX PCI Memory Space";
1043                 res->flags = IORESOURCE_MEM;
1044                 sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET;
1045                 break;
1046         case IOP13XX_INIT_ATU_ATUE:
1047                 /* Note: the function number field in the PCSR is ro */
1048                 pcsr = __raw_readl(IOP13XX_ATUE_PCSR);
1049                 pcsr &= ~(0xfff8 << 16);
1050                 pcsr |= sys->busnr << IOP13XX_ATUE_PCSR_BUS_NUM |
1051                                 0 << IOP13XX_ATUE_PCSR_DEV_NUM;
1052
1053                 __raw_writel(pcsr, IOP13XX_ATUE_PCSR);
1054
1055                 pci_ioremap_io(SZ_64K, IOP13XX_PCIE_LOWER_IO_PA);
1056
1057                 res->start = IOP13XX_PCIE_LOWER_MEM_RA;
1058                 res->end   = IOP13XX_PCIE_UPPER_MEM_RA;
1059                 res->name  = "IQ81340 ATUE PCI Memory Space";
1060                 res->flags = IORESOURCE_MEM;
1061                 sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET;
1062                 sys->map_irq = iop13xx_pcie_map_irq;
1063                 break;
1064         default:
1065                 kfree(res);
1066                 return 0;
1067         }
1068
1069         request_resource(&iomem_resource, res);
1070
1071         pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
1072
1073         return 1;
1074 }
1075
1076 u16 iop13xx_dev_id(void)
1077 {
1078         if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
1079                 return __raw_readw(IOP13XX_ATUE_DID);
1080         else
1081                 return __raw_readw(IOP13XX_ATUX_DID);
1082 }
1083
1084 static int __init iop13xx_init_atu_setup(char *str)
1085 {
1086         init_atu = IOP13XX_INIT_ATU_NONE;
1087         if (str) {
1088                 while (*str != '\0') {
1089                         switch (*str) {
1090                         case 'x':
1091                         case 'X':
1092                                 init_atu |= IOP13XX_INIT_ATU_ATUX;
1093                                 init_atu &= ~IOP13XX_INIT_ATU_NONE;
1094                                 break;
1095                         case 'e':
1096                         case 'E':
1097                                 init_atu |= IOP13XX_INIT_ATU_ATUE;
1098                                 init_atu &= ~IOP13XX_INIT_ATU_NONE;
1099                                 break;
1100                         case ',':
1101                         case '=':
1102                                 break;
1103                         default:
1104                                 PRINTK("\"iop13xx_init_atu\" malformed at "
1105                                             "character: \'%c\'", *str);
1106                                 *(str + 1) = '\0';
1107                                 init_atu = IOP13XX_INIT_ATU_DEFAULT;
1108                         }
1109                         str++;
1110                 }
1111         }
1112         return 1;
1113 }
1114
1115 __setup("iop13xx_init_atu", iop13xx_init_atu_setup);