arch/arm/mach-integrator/integrator_cp.c

   1 /*
   2  *  linux/arch/arm/mach-integrator/integrator_cp.c
   3  *
   4  *  Copyright (C) 2003 Deep Blue Solutions Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License.
   9  */
  10 #include <linux/types.h>
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/list.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/string.h>
  17 #include <linux/device.h>
  18 #include <linux/amba/bus.h>
  19 #include <linux/amba/kmi.h>
  20 #include <linux/amba/clcd.h>
  21 #include <linux/amba/mmci.h>
  22 #include <linux/io.h>
  23 #include <linux/irqchip/versatile-fpga.h>
  24 #include <linux/gfp.h>
  25 #include <linux/mtd/physmap.h>
  26 #include <linux/of_irq.h>
  27 #include <linux/of_address.h>
  28 #include <linux/of_platform.h>
  29 #include <linux/sys_soc.h>
  30
  31 #include <mach/hardware.h>
  32 #include <mach/platform.h>
  33 #include <asm/setup.h>
  34 #include <asm/mach-types.h>
  35
  36 #include <mach/lm.h>
  37
  38 #include <asm/mach/arch.h>
  39 #include <asm/mach/irq.h>
  40 #include <asm/mach/map.h>
  41 #include <asm/mach/time.h>
  42
  43 #include <plat/clcd.h>
  44 #include <plat/sched_clock.h>
  45
  46 #include "cm.h"
  47 #include "common.h"
  48
  49 /* Base address to the CP controller */
  50 static void __iomem *intcp_con_base;
  51
  52 #define INTCP_PA_FLASH_BASE             0x24000000
  53
  54 #define INTCP_PA_CLCD_BASE              0xc0000000
  55
  56 #define INTCP_FLASHPROG                 0x04
  57 #define CINTEGRATOR_FLASHPROG_FLVPPEN   (1 << 0)
  58 #define CINTEGRATOR_FLASHPROG_FLWREN    (1 << 1)
  59
  60 /*
  61  * Logical      Physical
  62  * f1000000     10000000        Core module registers
  63  * f1300000     13000000        Counter/Timer
  64  * f1400000     14000000        Interrupt controller
  65  * f1600000     16000000        UART 0
  66  * f1700000     17000000        UART 1
  67  * f1a00000     1a000000        Debug LEDs
  68  * fc900000     c9000000        GPIO
  69  * fca00000     ca000000        SIC
  70  */
  71
  72 static struct map_desc intcp_io_desc[] __initdata __maybe_unused = {
  73         {
  74                 .virtual        = IO_ADDRESS(INTEGRATOR_HDR_BASE),
  75                 .pfn            = __phys_to_pfn(INTEGRATOR_HDR_BASE),
  76                 .length         = SZ_4K,
  77                 .type           = MT_DEVICE
  78         }, {
  79                 .virtual        = IO_ADDRESS(INTEGRATOR_CT_BASE),
  80                 .pfn            = __phys_to_pfn(INTEGRATOR_CT_BASE),
  81                 .length         = SZ_4K,
  82                 .type           = MT_DEVICE
  83         }, {
  84                 .virtual        = IO_ADDRESS(INTEGRATOR_IC_BASE),
  85                 .pfn            = __phys_to_pfn(INTEGRATOR_IC_BASE),
  86                 .length         = SZ_4K,
  87                 .type           = MT_DEVICE
  88         }, {
  89                 .virtual        = IO_ADDRESS(INTEGRATOR_UART0_BASE),
  90                 .pfn            = __phys_to_pfn(INTEGRATOR_UART0_BASE),
  91                 .length         = SZ_4K,
  92                 .type           = MT_DEVICE
  93         }, {
  94                 .virtual        = IO_ADDRESS(INTEGRATOR_DBG_BASE),
  95                 .pfn            = __phys_to_pfn(INTEGRATOR_DBG_BASE),
  96                 .length         = SZ_4K,
  97                 .type           = MT_DEVICE
  98         }, {
  99                 .virtual        = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
 100                 .pfn            = __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
 101                 .length         = SZ_4K,
 102                 .type           = MT_DEVICE
 103         }, {
 104                 .virtual        = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
 105                 .pfn            = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
 106                 .length         = SZ_4K,
 107                 .type           = MT_DEVICE
 108         }
 109 };
 110
 111 static void __init intcp_map_io(void)
 112 {
 113         iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
 114 }
 115
 116 /*
 117  * Flash handling.
 118  */
 119 static int intcp_flash_init(struct platform_device *dev)
 120 {
 121         u32 val;
 122
 123         val = readl(intcp_con_base + INTCP_FLASHPROG);
 124         val |= CINTEGRATOR_FLASHPROG_FLWREN;
 125         writel(val, intcp_con_base + INTCP_FLASHPROG);
 126
 127         return 0;
 128 }
 129
 130 static void intcp_flash_exit(struct platform_device *dev)
 131 {
 132         u32 val;
 133
 134         val = readl(intcp_con_base + INTCP_FLASHPROG);
 135         val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
 136         writel(val, intcp_con_base + INTCP_FLASHPROG);
 137 }
 138
 139 static void intcp_flash_set_vpp(struct platform_device *pdev, int on)
 140 {
 141         u32 val;
 142
 143         val = readl(intcp_con_base + INTCP_FLASHPROG);
 144         if (on)
 145                 val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
 146         else
 147                 val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
 148         writel(val, intcp_con_base + INTCP_FLASHPROG);
 149 }
 150
 151 static struct physmap_flash_data intcp_flash_data = {
 152         .width          = 4,
 153         .init           = intcp_flash_init,
 154         .exit           = intcp_flash_exit,
 155         .set_vpp        = intcp_flash_set_vpp,
 156 };
 157
 158 /*
 159  * It seems that the card insertion interrupt remains active after
 160  * we've acknowledged it.  We therefore ignore the interrupt, and
 161  * rely on reading it from the SIC.  This also means that we must
 162  * clear the latched interrupt.
 163  */
 164 static unsigned int mmc_status(struct device *dev)
 165 {
 166         unsigned int status = readl(__io_address(0xca000000 + 4));
 167         writel(8, intcp_con_base + 8);
 168
 169         return status & 8;
 170 }
 171
 172 static struct mmci_platform_data mmc_data = {
 173         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 174         .status         = mmc_status,
 175         .gpio_wp        = -1,
 176         .gpio_cd        = -1,
 177 };
 178
 179 /*
 180  * CLCD support
 181  */
 182 /*
 183  * Ensure VGA is selected.
 184  */
 185 static void cp_clcd_enable(struct clcd_fb *fb)
 186 {
 187         struct fb_var_screeninfo *var = &fb->fb.var;
 188         u32 val = CM_CTRL_STATIC1 | CM_CTRL_STATIC2
 189                         | CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1;
 190
 191         if (var->bits_per_pixel <= 8 ||
 192             (var->bits_per_pixel == 16 && var->green.length == 5))
 193                 /* Pseudocolor, RGB555, BGR555 */
 194                 val |= CM_CTRL_LCDMUXSEL_VGA555_TFT555;
 195         else if (fb->fb.var.bits_per_pixel <= 16)
 196                 /* truecolor RGB565 */
 197                 val |= CM_CTRL_LCDMUXSEL_VGA565_TFT555;
 198         else
 199                 val = 0; /* no idea for this, don't trust the docs */
 200
 201         cm_control(CM_CTRL_LCDMUXSEL_MASK|
 202                    CM_CTRL_LCDEN0|
 203                    CM_CTRL_LCDEN1|
 204                    CM_CTRL_STATIC1|
 205                    CM_CTRL_STATIC2|
 206                    CM_CTRL_STATIC|
 207                    CM_CTRL_n24BITEN, val);
 208 }
 209
 210 static int cp_clcd_setup(struct clcd_fb *fb)
 211 {
 212         fb->panel = versatile_clcd_get_panel("VGA");
 213         if (!fb->panel)
 214                 return -EINVAL;
 215
 216         return versatile_clcd_setup_dma(fb, SZ_1M);
 217 }
 218
 219 static struct clcd_board clcd_data = {
 220         .name           = "Integrator/CP",
 221         .caps           = CLCD_CAP_5551 | CLCD_CAP_RGB565 | CLCD_CAP_888,
 222         .check          = clcdfb_check,
 223         .decode         = clcdfb_decode,
 224         .enable         = cp_clcd_enable,
 225         .setup          = cp_clcd_setup,
 226         .mmap           = versatile_clcd_mmap_dma,
 227         .remove         = versatile_clcd_remove_dma,
 228 };
 229
 230 #define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)
 231
 232 static void __init intcp_init_early(void)
 233 {
 234 #ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK
 235         versatile_sched_clock_init(REFCOUNTER, 24000000);
 236 #endif
 237 }
 238
 239 static const struct of_device_id fpga_irq_of_match[] __initconst = {
 240         { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
 241         { /* Sentinel */ }
 242 };
 243
 244 static void __init intcp_init_irq_of(void)
 245 {
 246         cm_init();
 247         of_irq_init(fpga_irq_of_match);
 248 }
 249
 250 /*
 251  * For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA
 252  * and enforce the bus names since these are used for clock lookups.
 253  */
 254 static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
 255         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
 256                 "rtc", NULL),
 257         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
 258                 "uart0", NULL),
 259         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
 260                 "uart1", NULL),
 261         OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
 262                 "kmi0", NULL),
 263         OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
 264                 "kmi1", NULL),
 265         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_MMC_BASE,
 266                 "mmci", &mmc_data),
 267         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_AACI_BASE,
 268                 "aaci", &mmc_data),
 269         OF_DEV_AUXDATA("arm,primecell", INTCP_PA_CLCD_BASE,
 270                 "clcd", &clcd_data),
 271         OF_DEV_AUXDATA("cfi-flash", INTCP_PA_FLASH_BASE,
 272                 "physmap-flash", &intcp_flash_data),
 273         { /* sentinel */ },
 274 };
 275
 276 static const struct of_device_id intcp_syscon_match[] = {
 277         { .compatible = "arm,integrator-cp-syscon"},
 278         { },
 279 };
 280
 281 static void __init intcp_init_of(void)
 282 {
 283         struct device_node *root;
 284         struct device_node *cpcon;
 285         struct device *parent;
 286         struct soc_device *soc_dev;
 287         struct soc_device_attribute *soc_dev_attr;
 288         u32 intcp_sc_id;
 289         int err;
 290
 291         /* Here we create an SoC device for the root node */
 292         root = of_find_node_by_path("/");
 293         if (!root)
 294                 return;
 295
 296         cpcon = of_find_matching_node(root, intcp_syscon_match);
 297         if (!cpcon)
 298                 return;
 299
 300         intcp_con_base = of_iomap(cpcon, 0);
 301         if (!intcp_con_base)
 302                 return;
 303
 304         intcp_sc_id = readl(intcp_con_base);
 305
 306         soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
 307         if (!soc_dev_attr)
 308                 return;
 309
 310         err = of_property_read_string(root, "compatible",
 311                                       &soc_dev_attr->soc_id);
 312         if (err)
 313                 return;
 314         err = of_property_read_string(root, "model", &soc_dev_attr->machine);
 315         if (err)
 316                 return;
 317         soc_dev_attr->family = "Integrator";
 318         soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
 319                                            'A' + (intcp_sc_id & 0x0f));
 320
 321         soc_dev = soc_device_register(soc_dev_attr);
 322         if (IS_ERR(soc_dev)) {
 323                 kfree(soc_dev_attr->revision);
 324                 kfree(soc_dev_attr);
 325                 return;
 326         }
 327
 328         parent = soc_device_to_device(soc_dev);
 329         integrator_init_sysfs(parent, intcp_sc_id);
 330         of_platform_populate(root, of_default_bus_match_table,
 331                         intcp_auxdata_lookup, parent);
 332 }
 333
 334 static const char * intcp_dt_board_compat[] = {
 335         "arm,integrator-cp",
 336         NULL,
 337 };
 338
 339 DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
 340         .reserve        = integrator_reserve,
 341         .map_io         = intcp_map_io,
 342         .init_early     = intcp_init_early,
 343         .init_irq       = intcp_init_irq_of,
 344         .handle_irq     = fpga_handle_irq,
 345         .init_machine   = intcp_init_of,
 346         .restart        = integrator_restart,
 347         .dt_compat      = intcp_dt_board_compat,
 348 MACHINE_END