arch/arm/mach-integrator/integrator_cp.c

   1 /*
   2  *  linux/arch/arm/mach-integrator/integrator_cp.c
   3  *
   4  *  Copyright (C) 2003 Deep Blue Solutions Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License.
   9  */
  10 #include <linux/types.h>
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/list.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/string.h>
  17 #include <linux/device.h>
  18 #include <linux/amba/bus.h>
  19 #include <linux/amba/kmi.h>
  20 #include <linux/amba/clcd.h>
  21 #include <linux/amba/mmci.h>
  22 #include <linux/io.h>
  23 #include <linux/irqchip/versatile-fpga.h>
  24 #include <linux/gfp.h>
  25 #include <linux/mtd/physmap.h>
  26 #include <linux/of_irq.h>
  27 #include <linux/of_address.h>
  28 #include <linux/of_platform.h>
  29 #include <linux/sys_soc.h>
  30 #include <linux/sched_clock.h>
  31
  32 #include <asm/setup.h>
  33 #include <asm/mach-types.h>
  34 #include <asm/mach/arch.h>
  35 #include <asm/mach/irq.h>
  36 #include <asm/mach/map.h>
  37 #include <asm/mach/time.h>
  38
  39 #include <plat/clcd.h>
  40
  41 #include "hardware.h"
  42 #include "cm.h"
  43 #include "common.h"
  44
  45 /* Base address to the CP controller */
  46 static void __iomem *intcp_con_base;
  47
  48 #define INTCP_PA_FLASH_BASE             0x24000000
  49
  50 #define INTCP_PA_CLCD_BASE              0xc0000000
  51
  52 #define INTCP_FLASHPROG                 0x04
  53 #define CINTEGRATOR_FLASHPROG_FLVPPEN   (1 << 0)
  54 #define CINTEGRATOR_FLASHPROG_FLWREN    (1 << 1)
  55
  56 /*
  57  * Logical      Physical
  58  * f1000000     10000000        Core module registers
  59  * f1300000     13000000        Counter/Timer
  60  * f1400000     14000000        Interrupt controller
  61  * f1600000     16000000        UART 0
  62  * f1700000     17000000        UART 1
  63  * f1a00000     1a000000        Debug LEDs
  64  * fc900000     c9000000        GPIO
  65  * fca00000     ca000000        SIC
  66  */
  67
  68 static struct map_desc intcp_io_desc[] __initdata __maybe_unused = {
  69         {
  70                 .virtual        = IO_ADDRESS(INTEGRATOR_HDR_BASE),
  71                 .pfn            = __phys_to_pfn(INTEGRATOR_HDR_BASE),
  72                 .length         = SZ_4K,
  73                 .type           = MT_DEVICE
  74         }, {
  75                 .virtual        = IO_ADDRESS(INTEGRATOR_CT_BASE),
  76                 .pfn            = __phys_to_pfn(INTEGRATOR_CT_BASE),
  77                 .length         = SZ_4K,
  78                 .type           = MT_DEVICE
  79         }, {
  80                 .virtual        = IO_ADDRESS(INTEGRATOR_IC_BASE),
  81                 .pfn            = __phys_to_pfn(INTEGRATOR_IC_BASE),
  82                 .length         = SZ_4K,
  83                 .type           = MT_DEVICE
  84         }, {
  85                 .virtual        = IO_ADDRESS(INTEGRATOR_UART0_BASE),
  86                 .pfn            = __phys_to_pfn(INTEGRATOR_UART0_BASE),
  87                 .length         = SZ_4K,
  88                 .type           = MT_DEVICE
  89         }, {
  90                 .virtual        = IO_ADDRESS(INTEGRATOR_DBG_BASE),
  91                 .pfn            = __phys_to_pfn(INTEGRATOR_DBG_BASE),
  92                 .length         = SZ_4K,
  93                 .type           = MT_DEVICE
  94         }, {
  95                 .virtual        = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
  96                 .pfn            = __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
  97                 .length         = SZ_4K,
  98                 .type           = MT_DEVICE
  99         }, {
 100                 .virtual        = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
 101                 .pfn            = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
 102                 .length         = SZ_4K,
 103                 .type           = MT_DEVICE
 104         }
 105 };
 106
 107 static void __init intcp_map_io(void)
 108 {
 109         iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
 110 }
 111
 112 /*
 113  * Flash handling.
 114  */
 115 static int intcp_flash_init(struct platform_device *dev)
 116 {
 117         u32 val;
 118
 119         val = readl(intcp_con_base + INTCP_FLASHPROG);
 120         val |= CINTEGRATOR_FLASHPROG_FLWREN;
 121         writel(val, intcp_con_base + INTCP_FLASHPROG);
 122
 123         return 0;
 124 }
 125
 126 static void intcp_flash_exit(struct platform_device *dev)
 127 {
 128         u32 val;
 129
 130         val = readl(intcp_con_base + INTCP_FLASHPROG);
 131         val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
 132         writel(val, intcp_con_base + INTCP_FLASHPROG);
 133 }
 134
 135 static void intcp_flash_set_vpp(struct platform_device *pdev, int on)
 136 {
 137         u32 val;
 138
 139         val = readl(intcp_con_base + INTCP_FLASHPROG);
 140         if (on)
 141                 val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
 142         else
 143                 val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
 144         writel(val, intcp_con_base + INTCP_FLASHPROG);
 145 }
 146
 147 static struct physmap_flash_data intcp_flash_data = {
 148         .width          = 4,
 149         .init           = intcp_flash_init,
 150         .exit           = intcp_flash_exit,
 151         .set_vpp        = intcp_flash_set_vpp,
 152 };
 153
 154 /*
 155  * It seems that the card insertion interrupt remains active after
 156  * we've acknowledged it.  We therefore ignore the interrupt, and
 157  * rely on reading it from the SIC.  This also means that we must
 158  * clear the latched interrupt.
 159  */
 160 static unsigned int mmc_status(struct device *dev)
 161 {
 162         unsigned int status = readl(__io_address(0xca000000 + 4));
 163         writel(8, intcp_con_base + 8);
 164
 165         return status & 8;
 166 }
 167
 168 static struct mmci_platform_data mmc_data = {
 169         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 170         .status         = mmc_status,
 171         .gpio_wp        = -1,
 172         .gpio_cd        = -1,
 173 };
 174
 175 /*
 176  * CLCD support
 177  */
 178 /*
 179  * Ensure VGA is selected.
 180  */
 181 static void cp_clcd_enable(struct clcd_fb *fb)
 182 {
 183         struct fb_var_screeninfo *var = &fb->fb.var;
 184         u32 val = CM_CTRL_STATIC1 | CM_CTRL_STATIC2
 185                         | CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1;
 186
 187         if (var->bits_per_pixel <= 8 ||
 188             (var->bits_per_pixel == 16 && var->green.length == 5))
 189                 /* Pseudocolor, RGB555, BGR555 */
 190                 val |= CM_CTRL_LCDMUXSEL_VGA555_TFT555;
 191         else if (fb->fb.var.bits_per_pixel <= 16)
 192                 /* truecolor RGB565 */
 193                 val |= CM_CTRL_LCDMUXSEL_VGA565_TFT555;
 194         else
 195                 val = 0; /* no idea for this, don't trust the docs */
 196
 197         cm_control(CM_CTRL_LCDMUXSEL_MASK|
 198                    CM_CTRL_LCDEN0|
 199                    CM_CTRL_LCDEN1|
 200                    CM_CTRL_STATIC1|
 201                    CM_CTRL_STATIC2|
 202                    CM_CTRL_STATIC|
 203                    CM_CTRL_n24BITEN, val);
 204 }
 205
 206 static int cp_clcd_setup(struct clcd_fb *fb)
 207 {
 208         fb->panel = versatile_clcd_get_panel("VGA");
 209         if (!fb->panel)
 210                 return -EINVAL;
 211
 212         return versatile_clcd_setup_dma(fb, SZ_1M);
 213 }
 214
 215 static struct clcd_board clcd_data = {
 216         .name           = "Integrator/CP",
 217         .caps           = CLCD_CAP_5551 | CLCD_CAP_RGB565 | CLCD_CAP_888,
 218         .check          = clcdfb_check,
 219         .decode         = clcdfb_decode,
 220         .enable         = cp_clcd_enable,
 221         .setup          = cp_clcd_setup,
 222         .mmap           = versatile_clcd_mmap_dma,
 223         .remove         = versatile_clcd_remove_dma,
 224 };
 225
 226 #define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)
 227
 228 static u64 notrace intcp_read_sched_clock(void)
 229 {
 230         return readl(REFCOUNTER);
 231 }
 232
 233 static void __init intcp_init_early(void)
 234 {
 235         sched_clock_register(intcp_read_sched_clock, 32, 24000000);
 236 }
 237
 238 static const struct of_device_id fpga_irq_of_match[] __initconst = {
 239         { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
 240         { /* Sentinel */ }
 241 };
 242
 243 static void __init intcp_init_irq_of(void)
 244 {
 245         cm_init();
 246         of_irq_init(fpga_irq_of_match);
 247 }
 248
 249 /*
 250  * For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA
 251  * and enforce the bus names since these are used for clock lookups.
 252  */
 253 static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
 254         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
 255                 "rtc", NULL),
 256         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
 257                 "uart0", NULL),
 258         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
 259                 "uart1", NULL),
 260         OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
 261                 "kmi0", NULL),
 262         OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
 263                 "kmi1", NULL),
 264         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_MMC_BASE,
 265                 "mmci", &mmc_data),
 266         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_AACI_BASE,
 267                 "aaci", &mmc_data),
 268         OF_DEV_AUXDATA("arm,primecell", INTCP_PA_CLCD_BASE,
 269                 "clcd", &clcd_data),
 270         OF_DEV_AUXDATA("cfi-flash", INTCP_PA_FLASH_BASE,
 271                 "physmap-flash", &intcp_flash_data),
 272         { /* sentinel */ },
 273 };
 274
 275 static const struct of_device_id intcp_syscon_match[] = {
 276         { .compatible = "arm,integrator-cp-syscon"},
 277         { },
 278 };
 279
 280 static void __init intcp_init_of(void)
 281 {
 282         struct device_node *root;
 283         struct device_node *cpcon;
 284         struct device *parent;
 285         struct soc_device *soc_dev;
 286         struct soc_device_attribute *soc_dev_attr;
 287         u32 intcp_sc_id;
 288         int err;
 289
 290         /* Here we create an SoC device for the root node */
 291         root = of_find_node_by_path("/");
 292         if (!root)
 293                 return;
 294
 295         cpcon = of_find_matching_node(root, intcp_syscon_match);
 296         if (!cpcon)
 297                 return;
 298
 299         intcp_con_base = of_iomap(cpcon, 0);
 300         if (!intcp_con_base)
 301                 return;
 302
 303         intcp_sc_id = readl(intcp_con_base);
 304
 305         soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
 306         if (!soc_dev_attr)
 307                 return;
 308
 309         err = of_property_read_string(root, "compatible",
 310                                       &soc_dev_attr->soc_id);
 311         if (err)
 312                 return;
 313         err = of_property_read_string(root, "model", &soc_dev_attr->machine);
 314         if (err)
 315                 return;
 316         soc_dev_attr->family = "Integrator";
 317         soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
 318                                            'A' + (intcp_sc_id & 0x0f));
 319
 320         soc_dev = soc_device_register(soc_dev_attr);
 321         if (IS_ERR(soc_dev)) {
 322                 kfree(soc_dev_attr->revision);
 323                 kfree(soc_dev_attr);
 324                 return;
 325         }
 326
 327         parent = soc_device_to_device(soc_dev);
 328         integrator_init_sysfs(parent, intcp_sc_id);
 329         of_platform_populate(root, of_default_bus_match_table,
 330                         intcp_auxdata_lookup, parent);
 331 }
 332
 333 static const char * intcp_dt_board_compat[] = {
 334         "arm,integrator-cp",
 335         NULL,
 336 };
 337
 338 DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
 339         .reserve        = integrator_reserve,
 340         .map_io         = intcp_map_io,
 341         .init_early     = intcp_init_early,
 342         .init_irq       = intcp_init_irq_of,
 343         .handle_irq     = fpga_handle_irq,
 344         .init_machine   = intcp_init_of,
 345         .restart        = integrator_restart,
 346         .dt_compat      = intcp_dt_board_compat,
 347 MACHINE_END