arch/arm/mach-imx/mach-mx27ads.c

   1 /*
   2  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   3  *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
   4  *  Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16 #include <linux/gpio/driver.h>
  17 /* Needed for gpio_to_irq() */
  18 #include <linux/gpio.h>
  19 #include <linux/gpio/machine.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/mtd/mtd.h>
  22 #include <linux/mtd/map.h>
  23 #include <linux/mtd/partitions.h>
  24 #include <linux/mtd/physmap.h>
  25 #include <linux/i2c.h>
  26 #include <linux/irq.h>
  27
  28 #include <linux/regulator/fixed.h>
  29 #include <linux/regulator/machine.h>
  30
  31 #include <asm/mach-types.h>
  32 #include <asm/mach/arch.h>
  33 #include <asm/mach/time.h>
  34 #include <asm/mach/map.h>
  35
  36 #include "common.h"
  37 #include "devices-imx27.h"
  38 #include "hardware.h"
  39 #include "iomux-mx27.h"
  40
  41 /*
  42  * Base address of PBC controller, CS4
  43  */
  44 #define PBC_BASE_ADDRESS        0xf4300000
  45 #define PBC_REG_ADDR(offset)    (void __force __iomem *) \
  46                 (PBC_BASE_ADDRESS + (offset))
  47
  48 /* When the PBC address connection is fixed in h/w, defined as 1 */
  49 #define PBC_ADDR_SH             0
  50
  51 /* Offsets for the PBC Controller register */
  52 /*
  53  * PBC Board version register offset
  54  */
  55 #define PBC_VERSION_REG         PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
  56 /*
  57  * PBC Board control register 1 set address.
  58  */
  59 #define PBC_BCTRL1_SET_REG      PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
  60 /*
  61  * PBC Board control register 1 clear address.
  62  */
  63 #define PBC_BCTRL1_CLEAR_REG    PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
  64
  65 /* PBC Board Control Register 1 bit definitions */
  66 #define PBC_BCTRL1_LCDON        0x0800  /* Enable the LCD */
  67
  68 /* to determine the correct external crystal reference */
  69 #define CKIH_27MHZ_BIT_SET      (1 << 3)
  70
  71 static const int mx27ads_pins[] __initconst = {
  72         /* UART0 */
  73         PE12_PF_UART1_TXD,
  74         PE13_PF_UART1_RXD,
  75         PE14_PF_UART1_CTS,
  76         PE15_PF_UART1_RTS,
  77         /* UART1 */
  78         PE3_PF_UART2_CTS,
  79         PE4_PF_UART2_RTS,
  80         PE6_PF_UART2_TXD,
  81         PE7_PF_UART2_RXD,
  82         /* UART2 */
  83         PE8_PF_UART3_TXD,
  84         PE9_PF_UART3_RXD,
  85         PE10_PF_UART3_CTS,
  86         PE11_PF_UART3_RTS,
  87         /* UART3 */
  88         PB26_AF_UART4_RTS,
  89         PB28_AF_UART4_TXD,
  90         PB29_AF_UART4_CTS,
  91         PB31_AF_UART4_RXD,
  92         /* UART4 */
  93         PB18_AF_UART5_TXD,
  94         PB19_AF_UART5_RXD,
  95         PB20_AF_UART5_CTS,
  96         PB21_AF_UART5_RTS,
  97         /* UART5 */
  98         PB10_AF_UART6_TXD,
  99         PB12_AF_UART6_CTS,
 100         PB11_AF_UART6_RXD,
 101         PB13_AF_UART6_RTS,
 102         /* FEC */
 103         PD0_AIN_FEC_TXD0,
 104         PD1_AIN_FEC_TXD1,
 105         PD2_AIN_FEC_TXD2,
 106         PD3_AIN_FEC_TXD3,
 107         PD4_AOUT_FEC_RX_ER,
 108         PD5_AOUT_FEC_RXD1,
 109         PD6_AOUT_FEC_RXD2,
 110         PD7_AOUT_FEC_RXD3,
 111         PD8_AF_FEC_MDIO,
 112         PD9_AIN_FEC_MDC,
 113         PD10_AOUT_FEC_CRS,
 114         PD11_AOUT_FEC_TX_CLK,
 115         PD12_AOUT_FEC_RXD0,
 116         PD13_AOUT_FEC_RX_DV,
 117         PD14_AOUT_FEC_RX_CLK,
 118         PD15_AOUT_FEC_COL,
 119         PD16_AIN_FEC_TX_ER,
 120         PF23_AIN_FEC_TX_EN,
 121         /* I2C2 */
 122         PC5_PF_I2C2_SDA,
 123         PC6_PF_I2C2_SCL,
 124         /* FB */
 125         PA5_PF_LSCLK,
 126         PA6_PF_LD0,
 127         PA7_PF_LD1,
 128         PA8_PF_LD2,
 129         PA9_PF_LD3,
 130         PA10_PF_LD4,
 131         PA11_PF_LD5,
 132         PA12_PF_LD6,
 133         PA13_PF_LD7,
 134         PA14_PF_LD8,
 135         PA15_PF_LD9,
 136         PA16_PF_LD10,
 137         PA17_PF_LD11,
 138         PA18_PF_LD12,
 139         PA19_PF_LD13,
 140         PA20_PF_LD14,
 141         PA21_PF_LD15,
 142         PA22_PF_LD16,
 143         PA23_PF_LD17,
 144         PA24_PF_REV,
 145         PA25_PF_CLS,
 146         PA26_PF_PS,
 147         PA27_PF_SPL_SPR,
 148         PA28_PF_HSYNC,
 149         PA29_PF_VSYNC,
 150         PA30_PF_CONTRAST,
 151         PA31_PF_OE_ACD,
 152         /* OWIRE */
 153         PE16_AF_OWIRE,
 154         /* SDHC1*/
 155         PE18_PF_SD1_D0,
 156         PE19_PF_SD1_D1,
 157         PE20_PF_SD1_D2,
 158         PE21_PF_SD1_D3,
 159         PE22_PF_SD1_CMD,
 160         PE23_PF_SD1_CLK,
 161         /* SDHC2*/
 162         PB4_PF_SD2_D0,
 163         PB5_PF_SD2_D1,
 164         PB6_PF_SD2_D2,
 165         PB7_PF_SD2_D3,
 166         PB8_PF_SD2_CMD,
 167         PB9_PF_SD2_CLK,
 168 };
 169
 170 static const struct mxc_nand_platform_data
 171 mx27ads_nand_board_info __initconst = {
 172         .width = 1,
 173         .hw_ecc = 1,
 174 };
 175
 176 /* ADS's NOR flash */
 177 static struct physmap_flash_data mx27ads_flash_data = {
 178         .width = 2,
 179 };
 180
 181 static struct resource mx27ads_flash_resource = {
 182         .start = 0xc0000000,
 183         .end = 0xc0000000 + 0x02000000 - 1,
 184         .flags = IORESOURCE_MEM,
 185
 186 };
 187
 188 static struct platform_device mx27ads_nor_mtd_device = {
 189         .name = "physmap-flash",
 190         .id = 0,
 191         .dev = {
 192                 .platform_data = &mx27ads_flash_data,
 193         },
 194         .num_resources = 1,
 195         .resource = &mx27ads_flash_resource,
 196 };
 197
 198 static const struct imxi2c_platform_data mx27ads_i2c1_data __initconst = {
 199         .bitrate = 100000,
 200 };
 201
 202 static struct i2c_board_info mx27ads_i2c_devices[] = {
 203 };
 204
 205 static void vgpio_set(struct gpio_chip *chip, unsigned offset, int value)
 206 {
 207         if (value)
 208                 imx_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_SET_REG);
 209         else
 210                 imx_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG);
 211 }
 212
 213 static int vgpio_dir_out(struct gpio_chip *chip, unsigned offset, int value)
 214 {
 215         return 0;
 216 }
 217
 218 #define MX27ADS_LCD_GPIO        (6 * 32)
 219
 220 static struct regulator_consumer_supply mx27ads_lcd_regulator_consumer =
 221         REGULATOR_SUPPLY("lcd", "imx-fb.0");
 222
 223 static struct regulator_init_data mx27ads_lcd_regulator_init_data = {
 224         .constraints    = {
 225                 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
 226 },
 227         .consumer_supplies      = &mx27ads_lcd_regulator_consumer,
 228         .num_consumer_supplies  = 1,
 229 };
 230
 231 static struct fixed_voltage_config mx27ads_lcd_regulator_pdata = {
 232         .supply_name    = "LCD",
 233         .microvolts     = 3300000,
 234         .init_data      = &mx27ads_lcd_regulator_init_data,
 235 };
 236
 237 static struct gpiod_lookup_table mx27ads_lcd_regulator_gpiod_table = {
 238         .dev_id = "reg-fixed-voltage.0", /* Let's hope ID 0 is what we get */
 239         .table = {
 240                 GPIO_LOOKUP("LCD", 0, NULL, GPIO_ACTIVE_HIGH),
 241                 { },
 242         },
 243 };
 244
 245 static void __init mx27ads_regulator_init(void)
 246 {
 247         struct gpio_chip *vchip;
 248
 249         vchip = kzalloc(sizeof(*vchip), GFP_KERNEL);
 250         vchip->owner            = THIS_MODULE;
 251         vchip->label            = "LCD";
 252         vchip->base             = MX27ADS_LCD_GPIO;
 253         vchip->ngpio            = 1;
 254         vchip->direction_output = vgpio_dir_out;
 255         vchip->set              = vgpio_set;
 256         gpiochip_add_data(vchip, NULL);
 257
 258         gpiod_add_lookup_table(&mx27ads_lcd_regulator_gpiod_table);
 259
 260         platform_device_register_data(NULL, "reg-fixed-voltage",
 261                                       PLATFORM_DEVID_AUTO,
 262                                       &mx27ads_lcd_regulator_pdata,
 263                                       sizeof(mx27ads_lcd_regulator_pdata));
 264 }
 265
 266 static struct imx_fb_videomode mx27ads_modes[] = {
 267         {
 268                 .mode = {
 269                         .name           = "Sharp-LQ035Q7",
 270                         .refresh        = 60,
 271                         .xres           = 240,
 272                         .yres           = 320,
 273                         .pixclock       = 188679, /* in ps (5.3MHz) */
 274                         .hsync_len      = 1,
 275                         .left_margin    = 9,
 276                         .right_margin   = 16,
 277                         .vsync_len      = 1,
 278                         .upper_margin   = 7,
 279                         .lower_margin   = 9,
 280                 },
 281                 .bpp            = 16,
 282                 .pcr            = 0xFB008BC0,
 283         },
 284 };
 285
 286 static const struct imx_fb_platform_data mx27ads_fb_data __initconst = {
 287         .mode = mx27ads_modes,
 288         .num_modes = ARRAY_SIZE(mx27ads_modes),
 289
 290         /*
 291          * - HSYNC active high
 292          * - VSYNC active high
 293          * - clk notenabled while idle
 294          * - clock inverted
 295          * - data not inverted
 296          * - data enable low active
 297          * - enable sharp mode
 298          */
 299         .pwmr           = 0x00A903FF,
 300         .lscr1          = 0x00120300,
 301         .dmacr          = 0x00020010,
 302 };
 303
 304 static int mx27ads_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
 305                               void *data)
 306 {
 307         return request_irq(gpio_to_irq(IMX_GPIO_NR(5, 21)), detect_irq,
 308                            IRQF_TRIGGER_RISING, "sdhc1-card-detect", data);
 309 }
 310
 311 static int mx27ads_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
 312                               void *data)
 313 {
 314         return request_irq(gpio_to_irq(IMX_GPIO_NR(2, 7)), detect_irq,
 315                            IRQF_TRIGGER_RISING, "sdhc2-card-detect", data);
 316 }
 317
 318 static void mx27ads_sdhc1_exit(struct device *dev, void *data)
 319 {
 320         free_irq(gpio_to_irq(IMX_GPIO_NR(5, 21)), data);
 321 }
 322
 323 static void mx27ads_sdhc2_exit(struct device *dev, void *data)
 324 {
 325         free_irq(gpio_to_irq(IMX_GPIO_NR(2, 7)), data);
 326 }
 327
 328 static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
 329         .init = mx27ads_sdhc1_init,
 330         .exit = mx27ads_sdhc1_exit,
 331 };
 332
 333 static const struct imxmmc_platform_data sdhc2_pdata __initconst = {
 334         .init = mx27ads_sdhc2_init,
 335         .exit = mx27ads_sdhc2_exit,
 336 };
 337
 338 static struct platform_device *platform_devices[] __initdata = {
 339         &mx27ads_nor_mtd_device,
 340 };
 341
 342 static const struct imxuart_platform_data uart_pdata __initconst = {
 343         .flags = IMXUART_HAVE_RTSCTS,
 344 };
 345
 346 static void __init mx27ads_board_init(void)
 347 {
 348         imx27_soc_init();
 349
 350         mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins),
 351                         "mx27ads");
 352
 353         imx27_add_imx_uart0(&uart_pdata);
 354         imx27_add_imx_uart1(&uart_pdata);
 355         imx27_add_imx_uart2(&uart_pdata);
 356         imx27_add_imx_uart3(&uart_pdata);
 357         imx27_add_imx_uart4(&uart_pdata);
 358         imx27_add_imx_uart5(&uart_pdata);
 359         imx27_add_mxc_nand(&mx27ads_nand_board_info);
 360
 361         /* only the i2c master 1 is used on this CPU card */
 362         i2c_register_board_info(1, mx27ads_i2c_devices,
 363                                 ARRAY_SIZE(mx27ads_i2c_devices));
 364         imx27_add_imx_i2c(1, &mx27ads_i2c1_data);
 365         imx27_add_imx_fb(&mx27ads_fb_data);
 366
 367         imx27_add_fec(NULL);
 368         imx27_add_mxc_w1();
 369 }
 370
 371 static void __init mx27ads_late_init(void)
 372 {
 373         mx27ads_regulator_init();
 374
 375         imx27_add_mxc_mmc(0, &sdhc1_pdata);
 376         imx27_add_mxc_mmc(1, &sdhc2_pdata);
 377
 378         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 379 }
 380
 381 static void __init mx27ads_timer_init(void)
 382 {
 383         unsigned long fref = 26000000;
 384
 385         if ((imx_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0)
 386                 fref = 27000000;
 387
 388         mx27_clocks_init(fref);
 389 }
 390
 391 static struct map_desc mx27ads_io_desc[] __initdata = {
 392         {
 393                 .virtual = PBC_BASE_ADDRESS,
 394                 .pfn = __phys_to_pfn(MX27_CS4_BASE_ADDR),
 395                 .length = SZ_1M,
 396                 .type = MT_DEVICE,
 397         },
 398 };
 399
 400 static void __init mx27ads_map_io(void)
 401 {
 402         mx27_map_io();
 403         iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc));
 404 }
 405
 406 MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
 407         /* maintainer: Freescale Semiconductor, Inc. */
 408         .atag_offset = 0x100,
 409         .map_io = mx27ads_map_io,
 410         .init_early = imx27_init_early,
 411         .init_irq = mx27_init_irq,
 412         .init_time      = mx27ads_timer_init,
 413         .init_machine = mx27ads_board_init,
 414         .init_late      = mx27ads_late_init,
 415         .restart        = mxc_restart,
 416 MACHINE_END