arch/arm/mach-exynos/mct.c

   1 /* linux/arch/arm/mach-exynos4/mct.c
   2  *
   3  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * EXYNOS4 MCT(Multi-Core Timer) support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/sched.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/irq.h>
  16 #include <linux/err.h>
  17 #include <linux/clk.h>
  18 #include <linux/clockchips.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/delay.h>
  21 #include <linux/percpu.h>
  22 #include <linux/of.h>
  23
  24 #include <asm/arch_timer.h>
  25 #include <asm/hardware/gic.h>
  26 #include <asm/localtimer.h>
  27
  28 #include <plat/cpu.h>
  29
  30 #include <mach/map.h>
  31 #include <mach/irqs.h>
  32 #include <mach/regs-mct.h>
  33 #include <asm/mach/time.h>
  34
  35 #define TICK_BASE_CNT   1
  36
  37 enum {
  38         MCT_INT_SPI,
  39         MCT_INT_PPI
  40 };
  41
  42 static unsigned long clk_rate;
  43 static unsigned int mct_int_type;
  44
  45 struct mct_clock_event_device {
  46         struct clock_event_device *evt;
  47         void __iomem *base;
  48         char name[10];
  49 };
  50
  51 static void exynos4_mct_write(unsigned int value, void *addr)
  52 {
  53         void __iomem *stat_addr;
  54         u32 mask;
  55         u32 i;
  56
  57         __raw_writel(value, addr);
  58
  59         if (likely(addr >= EXYNOS4_MCT_L_BASE(0))) {
  60                 u32 base = (u32) addr & EXYNOS4_MCT_L_MASK;
  61                 switch ((u32) addr & ~EXYNOS4_MCT_L_MASK) {
  62                 case (u32) MCT_L_TCON_OFFSET:
  63                         stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
  64                         mask = 1 << 3;          /* L_TCON write status */
  65                         break;
  66                 case (u32) MCT_L_ICNTB_OFFSET:
  67                         stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
  68                         mask = 1 << 1;          /* L_ICNTB write status */
  69                         break;
  70                 case (u32) MCT_L_TCNTB_OFFSET:
  71                         stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
  72                         mask = 1 << 0;          /* L_TCNTB write status */
  73                         break;
  74                 default:
  75                         return;
  76                 }
  77         } else {
  78                 switch ((u32) addr) {
  79                 case (u32) EXYNOS4_MCT_G_TCON:
  80                         stat_addr = EXYNOS4_MCT_G_WSTAT;
  81                         mask = 1 << 16;         /* G_TCON write status */
  82                         break;
  83                 case (u32) EXYNOS4_MCT_G_COMP0_L:
  84                         stat_addr = EXYNOS4_MCT_G_WSTAT;
  85                         mask = 1 << 0;          /* G_COMP0_L write status */
  86                         break;
  87                 case (u32) EXYNOS4_MCT_G_COMP0_U:
  88                         stat_addr = EXYNOS4_MCT_G_WSTAT;
  89                         mask = 1 << 1;          /* G_COMP0_U write status */
  90                         break;
  91                 case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
  92                         stat_addr = EXYNOS4_MCT_G_WSTAT;
  93                         mask = 1 << 2;          /* G_COMP0_ADD_INCR w status */
  94                         break;
  95                 case (u32) EXYNOS4_MCT_G_CNT_L:
  96                         stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
  97                         mask = 1 << 0;          /* G_CNT_L write status */
  98                         break;
  99                 case (u32) EXYNOS4_MCT_G_CNT_U:
 100                         stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
 101                         mask = 1 << 1;          /* G_CNT_U write status */
 102                         break;
 103                 default:
 104                         return;
 105                 }
 106         }
 107
 108         /* Wait maximum 1 ms until written values are applied */
 109         for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
 110                 if (__raw_readl(stat_addr) & mask) {
 111                         __raw_writel(mask, stat_addr);
 112                         return;
 113                 }
 114
 115         panic("MCT hangs after writing %d (addr:0x%08x)\n", value, (u32)addr);
 116 }
 117
 118 /* Clocksource handling */
 119 static void exynos4_mct_frc_start(u32 hi, u32 lo)
 120 {
 121         u32 reg;
 122
 123         exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
 124         exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
 125
 126         reg = __raw_readl(EXYNOS4_MCT_G_TCON);
 127         reg |= MCT_G_TCON_START;
 128         exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
 129 }
 130
 131 static cycle_t exynos4_frc_read(struct clocksource *cs)
 132 {
 133         unsigned int lo, hi;
 134         u32 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
 135
 136         do {
 137                 hi = hi2;
 138                 lo = __raw_readl(EXYNOS4_MCT_G_CNT_L);
 139                 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
 140         } while (hi != hi2);
 141
 142         return ((cycle_t)hi << 32) | lo;
 143 }
 144
 145 static void exynos4_frc_resume(struct clocksource *cs)
 146 {
 147         exynos4_mct_frc_start(0, 0);
 148 }
 149
 150 struct clocksource mct_frc = {
 151         .name           = "mct-frc",
 152         .rating         = 400,
 153         .read           = exynos4_frc_read,
 154         .mask           = CLOCKSOURCE_MASK(64),
 155         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 156         .resume         = exynos4_frc_resume,
 157 };
 158
 159 static void __init exynos4_clocksource_init(void)
 160 {
 161         exynos4_mct_frc_start(0, 0);
 162
 163         if (clocksource_register_hz(&mct_frc, clk_rate))
 164                 panic("%s: can't register clocksource\n", mct_frc.name);
 165 }
 166
 167 static void exynos4_mct_comp0_stop(void)
 168 {
 169         unsigned int tcon;
 170
 171         tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
 172         tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
 173
 174         exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
 175         exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
 176 }
 177
 178 static void exynos4_mct_comp0_start(enum clock_event_mode mode,
 179                                     unsigned long cycles)
 180 {
 181         unsigned int tcon;
 182         cycle_t comp_cycle;
 183
 184         tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
 185
 186         if (mode == CLOCK_EVT_MODE_PERIODIC) {
 187                 tcon |= MCT_G_TCON_COMP0_AUTO_INC;
 188                 exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
 189         }
 190
 191         comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
 192         exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
 193         exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
 194
 195         exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
 196
 197         tcon |= MCT_G_TCON_COMP0_ENABLE;
 198         exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
 199 }
 200
 201 static int exynos4_comp_set_next_event(unsigned long cycles,
 202                                        struct clock_event_device *evt)
 203 {
 204         exynos4_mct_comp0_start(evt->mode, cycles);
 205
 206         return 0;
 207 }
 208
 209 static void exynos4_comp_set_mode(enum clock_event_mode mode,
 210                                   struct clock_event_device *evt)
 211 {
 212         unsigned long cycles_per_jiffy;
 213         exynos4_mct_comp0_stop();
 214
 215         switch (mode) {
 216         case CLOCK_EVT_MODE_PERIODIC:
 217                 cycles_per_jiffy =
 218                         (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
 219                 exynos4_mct_comp0_start(mode, cycles_per_jiffy);
 220                 break;
 221
 222         case CLOCK_EVT_MODE_ONESHOT:
 223         case CLOCK_EVT_MODE_UNUSED:
 224         case CLOCK_EVT_MODE_SHUTDOWN:
 225         case CLOCK_EVT_MODE_RESUME:
 226                 break;
 227         }
 228 }
 229
 230 static struct clock_event_device mct_comp_device = {
 231         .name           = "mct-comp",
 232         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 233         .rating         = 250,
 234         .set_next_event = exynos4_comp_set_next_event,
 235         .set_mode       = exynos4_comp_set_mode,
 236 };
 237
 238 static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
 239 {
 240         struct clock_event_device *evt = dev_id;
 241
 242         exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
 243
 244         evt->event_handler(evt);
 245
 246         return IRQ_HANDLED;
 247 }
 248
 249 static struct irqaction mct_comp_event_irq = {
 250         .name           = "mct_comp_irq",
 251         .flags          = IRQF_TIMER | IRQF_IRQPOLL,
 252         .handler        = exynos4_mct_comp_isr,
 253         .dev_id         = &mct_comp_device,
 254 };
 255
 256 static void exynos4_clockevent_init(void)
 257 {
 258         clockevents_calc_mult_shift(&mct_comp_device, clk_rate, 5);
 259         mct_comp_device.max_delta_ns =
 260                 clockevent_delta2ns(0xffffffff, &mct_comp_device);
 261         mct_comp_device.min_delta_ns =
 262                 clockevent_delta2ns(0xf, &mct_comp_device);
 263         mct_comp_device.cpumask = cpumask_of(0);
 264         clockevents_register_device(&mct_comp_device);
 265
 266         if (soc_is_exynos5250())
 267                 setup_irq(EXYNOS5_IRQ_MCT_G0, &mct_comp_event_irq);
 268         else
 269                 setup_irq(EXYNOS4_IRQ_MCT_G0, &mct_comp_event_irq);
 270 }
 271
 272 #ifdef CONFIG_LOCAL_TIMERS
 273
 274 static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
 275
 276 /* Clock event handling */
 277 static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
 278 {
 279         unsigned long tmp;
 280         unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
 281         void __iomem *addr = mevt->base + MCT_L_TCON_OFFSET;
 282
 283         tmp = __raw_readl(addr);
 284         if (tmp & mask) {
 285                 tmp &= ~mask;
 286                 exynos4_mct_write(tmp, addr);
 287         }
 288 }
 289
 290 static void exynos4_mct_tick_start(unsigned long cycles,
 291                                    struct mct_clock_event_device *mevt)
 292 {
 293         unsigned long tmp;
 294
 295         exynos4_mct_tick_stop(mevt);
 296
 297         tmp = (1 << 31) | cycles;       /* MCT_L_UPDATE_ICNTB */
 298
 299         /* update interrupt count buffer */
 300         exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
 301
 302         /* enable MCT tick interrupt */
 303         exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
 304
 305         tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET);
 306         tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
 307                MCT_L_TCON_INTERVAL_MODE;
 308         exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
 309 }
 310
 311 static int exynos4_tick_set_next_event(unsigned long cycles,
 312                                        struct clock_event_device *evt)
 313 {
 314         struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
 315
 316         exynos4_mct_tick_start(cycles, mevt);
 317
 318         return 0;
 319 }
 320
 321 static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
 322                                          struct clock_event_device *evt)
 323 {
 324         struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
 325         unsigned long cycles_per_jiffy;
 326
 327         exynos4_mct_tick_stop(mevt);
 328
 329         switch (mode) {
 330         case CLOCK_EVT_MODE_PERIODIC:
 331                 cycles_per_jiffy =
 332                         (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
 333                 exynos4_mct_tick_start(cycles_per_jiffy, mevt);
 334                 break;
 335
 336         case CLOCK_EVT_MODE_ONESHOT:
 337         case CLOCK_EVT_MODE_UNUSED:
 338         case CLOCK_EVT_MODE_SHUTDOWN:
 339         case CLOCK_EVT_MODE_RESUME:
 340                 break;
 341         }
 342 }
 343
 344 static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
 345 {
 346         struct clock_event_device *evt = mevt->evt;
 347
 348         /*
 349          * This is for supporting oneshot mode.
 350          * Mct would generate interrupt periodically
 351          * without explicit stopping.
 352          */
 353         if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
 354                 exynos4_mct_tick_stop(mevt);
 355
 356         /* Clear the MCT tick interrupt */
 357         if (__raw_readl(mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
 358                 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
 359                 return 1;
 360         } else {
 361                 return 0;
 362         }
 363 }
 364
 365 static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
 366 {
 367         struct mct_clock_event_device *mevt = dev_id;
 368         struct clock_event_device *evt = mevt->evt;
 369
 370         exynos4_mct_tick_clear(mevt);
 371
 372         evt->event_handler(evt);
 373
 374         return IRQ_HANDLED;
 375 }
 376
 377 static struct irqaction mct_tick0_event_irq = {
 378         .name           = "mct_tick0_irq",
 379         .flags          = IRQF_TIMER | IRQF_NOBALANCING,
 380         .handler        = exynos4_mct_tick_isr,
 381 };
 382
 383 static struct irqaction mct_tick1_event_irq = {
 384         .name           = "mct_tick1_irq",
 385         .flags          = IRQF_TIMER | IRQF_NOBALANCING,
 386         .handler        = exynos4_mct_tick_isr,
 387 };
 388
 389 static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
 390 {
 391         struct mct_clock_event_device *mevt;
 392         unsigned int cpu = smp_processor_id();
 393         int mct_lx_irq;
 394
 395         mevt = this_cpu_ptr(&percpu_mct_tick);
 396         mevt->evt = evt;
 397
 398         mevt->base = EXYNOS4_MCT_L_BASE(cpu);
 399         sprintf(mevt->name, "mct_tick%d", cpu);
 400
 401         evt->name = mevt->name;
 402         evt->cpumask = cpumask_of(cpu);
 403         evt->set_next_event = exynos4_tick_set_next_event;
 404         evt->set_mode = exynos4_tick_set_mode;
 405         evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
 406         evt->rating = 450;
 407
 408         clockevents_calc_mult_shift(evt, clk_rate / (TICK_BASE_CNT + 1), 5);
 409         evt->max_delta_ns =
 410                 clockevent_delta2ns(0x7fffffff, evt);
 411         evt->min_delta_ns =
 412                 clockevent_delta2ns(0xf, evt);
 413
 414         clockevents_register_device(evt);
 415
 416         exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
 417
 418         if (mct_int_type == MCT_INT_SPI) {
 419                 if (cpu == 0) {
 420                         mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L0 :
 421                                                 EXYNOS5_IRQ_MCT_L0;
 422                         mct_tick0_event_irq.dev_id = mevt;
 423                         evt->irq = mct_lx_irq;
 424                         setup_irq(mct_lx_irq, &mct_tick0_event_irq);
 425                 } else {
 426                         mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L1 :
 427                                                 EXYNOS5_IRQ_MCT_L1;
 428                         mct_tick1_event_irq.dev_id = mevt;
 429                         evt->irq = mct_lx_irq;
 430                         setup_irq(mct_lx_irq, &mct_tick1_event_irq);
 431                         irq_set_affinity(mct_lx_irq, cpumask_of(1));
 432                 }
 433         } else {
 434                 enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);
 435         }
 436
 437         return 0;
 438 }
 439
 440 static void exynos4_local_timer_stop(struct clock_event_device *evt)
 441 {
 442         unsigned int cpu = smp_processor_id();
 443         evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
 444         if (mct_int_type == MCT_INT_SPI)
 445                 if (cpu == 0)
 446                         remove_irq(evt->irq, &mct_tick0_event_irq);
 447                 else
 448                         remove_irq(evt->irq, &mct_tick1_event_irq);
 449         else
 450                 disable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER);
 451 }
 452
 453 static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
 454         .setup  = exynos4_local_timer_setup,
 455         .stop   = exynos4_local_timer_stop,
 456 };
 457 #endif /* CONFIG_LOCAL_TIMERS */
 458
 459 static void __init exynos4_timer_resources(void)
 460 {
 461         struct clk *mct_clk;
 462         mct_clk = clk_get(NULL, "xtal");
 463
 464         clk_rate = clk_get_rate(mct_clk);
 465
 466 #ifdef CONFIG_LOCAL_TIMERS
 467         if (mct_int_type == MCT_INT_PPI) {
 468                 int err;
 469
 470                 err = request_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER,
 471                                          exynos4_mct_tick_isr, "MCT",
 472                                          &percpu_mct_tick);
 473                 WARN(err, "MCT: can't request IRQ %d (%d)\n",
 474                      EXYNOS_IRQ_MCT_LOCALTIMER, err);
 475         }
 476
 477         local_timer_register(&exynos4_mct_tick_ops);
 478 #endif /* CONFIG_LOCAL_TIMERS */
 479 }
 480
 481 static void __init exynos_timer_init(void)
 482 {
 483         if (soc_is_exynos5440()) {
 484                 arch_timer_of_register();
 485                 return;
 486         }
 487
 488         if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
 489                 mct_int_type = MCT_INT_SPI;
 490         else
 491                 mct_int_type = MCT_INT_PPI;
 492
 493         exynos4_timer_resources();
 494         exynos4_clocksource_init();
 495         exynos4_clockevent_init();
 496 }
 497
 498 struct sys_timer exynos4_timer = {
 499         .init           = exynos_timer_init,
 500 };