arch/arm/mach-exynos/include/mach/map.h

   1 /* linux/arch/arm/mach-exynos/include/mach/map.h
   2  *
   3  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * EXYNOS4 - Memory map definitions
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #ifndef __ASM_ARCH_MAP_H
  14 #define __ASM_ARCH_MAP_H __FILE__
  15
  16 #include <plat/map-base.h>
  17
  18 /*
  19  * EXYNOS4 UART offset is 0x10000 but the older S5P SoCs are 0x400.
  20  * So need to define it, and here is to avoid redefinition warning.
  21  */
  22 #define S3C_UART_OFFSET                 (0x10000)
  23
  24 #include <plat/map-s5p.h>
  25
  26 #define EXYNOS4_PA_SYSRAM0              0x02025000
  27 #define EXYNOS4_PA_SYSRAM1              0x02020000
  28 #define EXYNOS5_PA_SYSRAM               0x02020000
  29
  30 #define EXYNOS4_PA_FIMC0                0x11800000
  31 #define EXYNOS4_PA_FIMC1                0x11810000
  32 #define EXYNOS4_PA_FIMC2                0x11820000
  33 #define EXYNOS4_PA_FIMC3                0x11830000
  34
  35 #define EXYNOS4_PA_JPEG                 0x11840000
  36
  37 /* x = 0...1 */
  38 #define EXYNOS4_PA_FIMC_LITE(x)         (0x12390000 + ((x) * 0x10000))
  39
  40 #define EXYNOS4_PA_G2D                  0x12800000
  41
  42 #define EXYNOS4_PA_I2S0                 0x03830000
  43 #define EXYNOS4_PA_I2S1                 0xE3100000
  44 #define EXYNOS4_PA_I2S2                 0xE2A00000
  45
  46 #define EXYNOS4_PA_PCM0                 0x03840000
  47 #define EXYNOS4_PA_PCM1                 0x13980000
  48 #define EXYNOS4_PA_PCM2                 0x13990000
  49
  50 #define EXYNOS4_PA_SROM_BANK(x)         (0x04000000 + ((x) * 0x01000000))
  51
  52 #define EXYNOS4_PA_ONENAND              0x0C000000
  53 #define EXYNOS4_PA_ONENAND_DMA          0x0C600000
  54
  55 #define EXYNOS_PA_CHIPID                0x10000000
  56
  57 #define EXYNOS4_PA_SYSCON               0x10010000
  58 #define EXYNOS5_PA_SYSCON               0x10050100
  59
  60 #define EXYNOS4_PA_PMU                  0x10020000
  61 #define EXYNOS5_PA_PMU                  0x10040000
  62
  63 #define EXYNOS4_PA_CMU                  0x10030000
  64 #define EXYNOS5_PA_CMU                  0x10010000
  65
  66 #define EXYNOS4_PA_SYSTIMER             0x10050000
  67 #define EXYNOS5_PA_SYSTIMER             0x101C0000
  68
  69 #define EXYNOS4_PA_WATCHDOG             0x10060000
  70 #define EXYNOS5_PA_WATCHDOG             0x101D0000
  71
  72 #define EXYNOS4_PA_RTC                  0x10070000
  73
  74 #define EXYNOS4_PA_KEYPAD               0x100A0000
  75
  76 #define EXYNOS4_PA_DMC0                 0x10400000
  77 #define EXYNOS4_PA_DMC1                 0x10410000
  78
  79 #define EXYNOS4_PA_COMBINER             0x10440000
  80 #define EXYNOS5_PA_COMBINER             0x10440000
  81
  82 #define EXYNOS4_PA_GIC_CPU              0x10480000
  83 #define EXYNOS4_PA_GIC_DIST             0x10490000
  84 #define EXYNOS5_PA_GIC_CPU              0x10482000
  85 #define EXYNOS5_PA_GIC_DIST             0x10481000
  86
  87 #define EXYNOS4_PA_COREPERI             0x10500000
  88 #define EXYNOS4_PA_TWD                  0x10500600
  89 #define EXYNOS4_PA_L2CC                 0x10502000
  90
  91 #define EXYNOS4_PA_MDMA0                0x10810000
  92 #define EXYNOS4_PA_MDMA1                0x12840000
  93 #define EXYNOS4_PA_PDMA0                0x12680000
  94 #define EXYNOS4_PA_PDMA1                0x12690000
  95 #define EXYNOS5_PA_MDMA0                0x10800000
  96 #define EXYNOS5_PA_MDMA1                0x11C10000
  97 #define EXYNOS5_PA_PDMA0                0x121A0000
  98 #define EXYNOS5_PA_PDMA1                0x121B0000
  99
 100 #define EXYNOS4_PA_SYSMMU_MDMA          0x10A40000
 101 #define EXYNOS4_PA_SYSMMU_2D_ACP        0x10A40000
 102 #define EXYNOS4_PA_SYSMMU_SSS           0x10A50000
 103 #define EXYNOS4_PA_SYSMMU_FIMC0         0x11A20000
 104 #define EXYNOS4_PA_SYSMMU_FIMC1         0x11A30000
 105 #define EXYNOS4_PA_SYSMMU_FIMC2         0x11A40000
 106 #define EXYNOS4_PA_SYSMMU_FIMC3         0x11A50000
 107 #define EXYNOS4_PA_SYSMMU_JPEG          0x11A60000
 108 #define EXYNOS4_PA_SYSMMU_FIMD0         0x11E20000
 109 #define EXYNOS4_PA_SYSMMU_FIMD1         0x12220000
 110 #define EXYNOS4_PA_SYSMMU_FIMC_ISP      0x12260000
 111 #define EXYNOS4_PA_SYSMMU_FIMC_DRC      0x12270000
 112 #define EXYNOS4_PA_SYSMMU_FIMC_FD       0x122A0000
 113 #define EXYNOS4_PA_SYSMMU_ISPCPU        0x122B0000
 114 #define EXYNOS4_PA_SYSMMU_FIMC_LITE0    0x123B0000
 115 #define EXYNOS4_PA_SYSMMU_FIMC_LITE1    0x123C0000
 116 #define EXYNOS4_PA_SYSMMU_PCIe          0x12620000
 117 #define EXYNOS4_PA_SYSMMU_G2D           0x12A20000
 118 #define EXYNOS4_PA_SYSMMU_ROTATOR       0x12A30000
 119 #define EXYNOS4_PA_SYSMMU_MDMA2         0x12A40000
 120 #define EXYNOS4_PA_SYSMMU_TV            0x12E20000
 121 #define EXYNOS4_PA_SYSMMU_MFC_L         0x13620000
 122 #define EXYNOS4_PA_SYSMMU_MFC_R         0x13630000
 123
 124 #define EXYNOS5_PA_SYSMMU_MDMA1         0x10A40000
 125 #define EXYNOS5_PA_SYSMMU_SSS           0x10A50000
 126 #define EXYNOS5_PA_SYSMMU_2D            0x10A60000
 127 #define EXYNOS5_PA_SYSMMU_MFC_L         0x11200000
 128 #define EXYNOS5_PA_SYSMMU_MFC_R         0x11210000
 129 #define EXYNOS5_PA_SYSMMU_ROTATOR       0x11D40000
 130 #define EXYNOS5_PA_SYSMMU_MDMA2         0x11D50000
 131 #define EXYNOS5_PA_SYSMMU_JPEG          0x11F20000
 132 #define EXYNOS5_PA_SYSMMU_IOP           0x12360000
 133 #define EXYNOS5_PA_SYSMMU_RTIC          0x12370000
 134 #define EXYNOS5_PA_SYSMMU_GPS           0x12630000
 135 #define EXYNOS5_PA_SYSMMU_ISP           0x13260000
 136 #define EXYNOS5_PA_SYSMMU_DRC           0x12370000
 137 #define EXYNOS5_PA_SYSMMU_SCALERC       0x13280000
 138 #define EXYNOS5_PA_SYSMMU_SCALERP       0x13290000
 139 #define EXYNOS5_PA_SYSMMU_FD            0x132A0000
 140 #define EXYNOS5_PA_SYSMMU_ISPCPU        0x132B0000
 141 #define EXYNOS5_PA_SYSMMU_ODC           0x132C0000
 142 #define EXYNOS5_PA_SYSMMU_DIS0          0x132D0000
 143 #define EXYNOS5_PA_SYSMMU_DIS1          0x132E0000
 144 #define EXYNOS5_PA_SYSMMU_3DNR          0x132F0000
 145 #define EXYNOS5_PA_SYSMMU_LITE0         0x13C40000
 146 #define EXYNOS5_PA_SYSMMU_LITE1         0x13C50000
 147 #define EXYNOS5_PA_SYSMMU_GSC0          0x13E80000
 148 #define EXYNOS5_PA_SYSMMU_GSC1          0x13E90000
 149 #define EXYNOS5_PA_SYSMMU_GSC2          0x13EA0000
 150 #define EXYNOS5_PA_SYSMMU_GSC3          0x13EB0000
 151 #define EXYNOS5_PA_SYSMMU_FIMD1         0x14640000
 152 #define EXYNOS5_PA_SYSMMU_TV            0x14650000
 153
 154 #define EXYNOS4_PA_SPI0                 0x13920000
 155 #define EXYNOS4_PA_SPI1                 0x13930000
 156 #define EXYNOS4_PA_SPI2                 0x13940000
 157
 158 #define EXYNOS4_PA_GPIO1                0x11400000
 159 #define EXYNOS4_PA_GPIO2                0x11000000
 160 #define EXYNOS4_PA_GPIO3                0x03860000
 161 #define EXYNOS5_PA_GPIO1                0x11400000
 162 #define EXYNOS5_PA_GPIO2                0x13400000
 163 #define EXYNOS5_PA_GPIO3                0x10D10000
 164 #define EXYNOS5_PA_GPIO4                0x03860000
 165
 166 #define EXYNOS4_PA_MIPI_CSIS0           0x11880000
 167 #define EXYNOS4_PA_MIPI_CSIS1           0x11890000
 168
 169 #define EXYNOS4_PA_FIMD0                0x11C00000
 170
 171 #define EXYNOS4_PA_HSMMC(x)             (0x12510000 + ((x) * 0x10000))
 172 #define EXYNOS4_PA_DWMCI                0x12550000
 173
 174 #define EXYNOS4_PA_HSOTG                0x12480000
 175 #define EXYNOS4_PA_USB_HSPHY            0x125B0000
 176
 177 #define EXYNOS4_PA_SATA                 0x12560000
 178 #define EXYNOS4_PA_SATAPHY              0x125D0000
 179 #define EXYNOS4_PA_SATAPHY_CTRL         0x126B0000
 180
 181 #define EXYNOS4_PA_SROMC                0x12570000
 182 #define EXYNOS5_PA_SROMC                0x12250000
 183
 184 #define EXYNOS4_PA_EHCI                 0x12580000
 185 #define EXYNOS4_PA_OHCI                 0x12590000
 186 #define EXYNOS4_PA_HSPHY                0x125B0000
 187 #define EXYNOS4_PA_MFC                  0x13400000
 188
 189 #define EXYNOS4_PA_UART                 0x13800000
 190 #define EXYNOS5_PA_UART                 0x12C00000
 191
 192 #define EXYNOS4_PA_VP                   0x12C00000
 193 #define EXYNOS4_PA_MIXER                0x12C10000
 194 #define EXYNOS4_PA_SDO                  0x12C20000
 195 #define EXYNOS4_PA_HDMI                 0x12D00000
 196 #define EXYNOS4_PA_IIC_HDMIPHY          0x138E0000
 197
 198 #define EXYNOS4_PA_IIC(x)               (0x13860000 + ((x) * 0x10000))
 199 #define EXYNOS5_PA_IIC(x)               (0x12C60000 + ((x) * 0x10000))
 200
 201 #define EXYNOS4_PA_ADC                  0x13910000
 202 #define EXYNOS4_PA_ADC1                 0x13911000
 203
 204 #define EXYNOS4_PA_AC97                 0x139A0000
 205
 206 #define EXYNOS4_PA_SPDIF                0x139B0000
 207
 208 #define EXYNOS4_PA_TIMER                0x139D0000
 209 #define EXYNOS5_PA_TIMER                0x12DD0000
 210
 211 #define EXYNOS4_PA_SDRAM                0x40000000
 212 #define EXYNOS5_PA_SDRAM                0x40000000
 213
 214 /* Compatibiltiy Defines */
 215
 216 #define S3C_PA_HSMMC0                   EXYNOS4_PA_HSMMC(0)
 217 #define S3C_PA_HSMMC1                   EXYNOS4_PA_HSMMC(1)
 218 #define S3C_PA_HSMMC2                   EXYNOS4_PA_HSMMC(2)
 219 #define S3C_PA_HSMMC3                   EXYNOS4_PA_HSMMC(3)
 220 #define S3C_PA_IIC                      EXYNOS4_PA_IIC(0)
 221 #define S3C_PA_IIC1                     EXYNOS4_PA_IIC(1)
 222 #define S3C_PA_IIC2                     EXYNOS4_PA_IIC(2)
 223 #define S3C_PA_IIC3                     EXYNOS4_PA_IIC(3)
 224 #define S3C_PA_IIC4                     EXYNOS4_PA_IIC(4)
 225 #define S3C_PA_IIC5                     EXYNOS4_PA_IIC(5)
 226 #define S3C_PA_IIC6                     EXYNOS4_PA_IIC(6)
 227 #define S3C_PA_IIC7                     EXYNOS4_PA_IIC(7)
 228 #define S3C_PA_RTC                      EXYNOS4_PA_RTC
 229 #define S3C_PA_WDT                      EXYNOS4_PA_WATCHDOG
 230 #define S3C_PA_SPI0                     EXYNOS4_PA_SPI0
 231 #define S3C_PA_SPI1                     EXYNOS4_PA_SPI1
 232 #define S3C_PA_SPI2                     EXYNOS4_PA_SPI2
 233 #define S3C_PA_USB_HSOTG                EXYNOS4_PA_HSOTG
 234
 235 #define S5P_PA_EHCI                     EXYNOS4_PA_EHCI
 236 #define S5P_PA_FIMC0                    EXYNOS4_PA_FIMC0
 237 #define S5P_PA_FIMC1                    EXYNOS4_PA_FIMC1
 238 #define S5P_PA_FIMC2                    EXYNOS4_PA_FIMC2
 239 #define S5P_PA_FIMC3                    EXYNOS4_PA_FIMC3
 240 #define S5P_PA_JPEG                     EXYNOS4_PA_JPEG
 241 #define S5P_PA_G2D                      EXYNOS4_PA_G2D
 242 #define S5P_PA_FIMD0                    EXYNOS4_PA_FIMD0
 243 #define S5P_PA_HDMI                     EXYNOS4_PA_HDMI
 244 #define S5P_PA_IIC_HDMIPHY              EXYNOS4_PA_IIC_HDMIPHY
 245 #define S5P_PA_MFC                      EXYNOS4_PA_MFC
 246 #define S5P_PA_MIPI_CSIS0               EXYNOS4_PA_MIPI_CSIS0
 247 #define S5P_PA_MIPI_CSIS1               EXYNOS4_PA_MIPI_CSIS1
 248 #define S5P_PA_MIXER                    EXYNOS4_PA_MIXER
 249 #define S5P_PA_ONENAND                  EXYNOS4_PA_ONENAND
 250 #define S5P_PA_ONENAND_DMA              EXYNOS4_PA_ONENAND_DMA
 251 #define S5P_PA_SDO                      EXYNOS4_PA_SDO
 252 #define S5P_PA_SDRAM                    EXYNOS4_PA_SDRAM
 253 #define S5P_PA_VP                       EXYNOS4_PA_VP
 254
 255 #define SAMSUNG_PA_ADC                  EXYNOS4_PA_ADC
 256 #define SAMSUNG_PA_ADC1                 EXYNOS4_PA_ADC1
 257 #define SAMSUNG_PA_KEYPAD               EXYNOS4_PA_KEYPAD
 258
 259 /* Compatibility UART */
 260
 261 #define EXYNOS4_PA_UART0                0x13800000
 262 #define EXYNOS4_PA_UART1                0x13810000
 263 #define EXYNOS4_PA_UART2                0x13820000
 264 #define EXYNOS4_PA_UART3                0x13830000
 265 #define EXYNOS4_SZ_UART                 SZ_256
 266
 267 #define EXYNOS5_PA_UART0                0x12C00000
 268 #define EXYNOS5_PA_UART1                0x12C10000
 269 #define EXYNOS5_PA_UART2                0x12C20000
 270 #define EXYNOS5_PA_UART3                0x12C30000
 271 #define EXYNOS5_SZ_UART                 SZ_256
 272
 273 #define S3C_VA_UARTx(x)                 (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
 274
 275 #endif /* __ASM_ARCH_MAP_H */