arch/arm/mach-ep93xx/clock.c

   1 /*
   2  * arch/arm/mach-ep93xx/clock.c
   3  * Clock control for Cirrus EP93xx chips.
   4  *
   5  * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or (at
  10  * your option) any later version.
  11  */
  12
  13 #define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
  14
  15 #include <linux/kernel.h>
  16 #include <linux/clk.h>
  17 #include <linux/err.h>
  18 #include <linux/module.h>
  19 #include <linux/string.h>
  20 #include <linux/io.h>
  21 #include <linux/spinlock.h>
  22
  23 #include <mach/hardware.h>
  24
  25 #include <asm/clkdev.h>
  26 #include <asm/div64.h>
  27
  28
  29 struct clk {
  30         struct clk      *parent;
  31         unsigned long   rate;
  32         int             users;
  33         int             sw_locked;
  34         void __iomem    *enable_reg;
  35         u32             enable_mask;
  36
  37         unsigned long   (*get_rate)(struct clk *clk);
  38         int             (*set_rate)(struct clk *clk, unsigned long rate);
  39 };
  40
  41
  42 static unsigned long get_uart_rate(struct clk *clk);
  43
  44 static int set_keytchclk_rate(struct clk *clk, unsigned long rate);
  45 static int set_div_rate(struct clk *clk, unsigned long rate);
  46 static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate);
  47 static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate);
  48
  49 static struct clk clk_xtali = {
  50         .rate           = EP93XX_EXT_CLK_RATE,
  51 };
  52 static struct clk clk_uart1 = {
  53         .parent         = &clk_xtali,
  54         .sw_locked      = 1,
  55         .enable_reg     = EP93XX_SYSCON_DEVCFG,
  56         .enable_mask    = EP93XX_SYSCON_DEVCFG_U1EN,
  57         .get_rate       = get_uart_rate,
  58 };
  59 static struct clk clk_uart2 = {
  60         .parent         = &clk_xtali,
  61         .sw_locked      = 1,
  62         .enable_reg     = EP93XX_SYSCON_DEVCFG,
  63         .enable_mask    = EP93XX_SYSCON_DEVCFG_U2EN,
  64         .get_rate       = get_uart_rate,
  65 };
  66 static struct clk clk_uart3 = {
  67         .parent         = &clk_xtali,
  68         .sw_locked      = 1,
  69         .enable_reg     = EP93XX_SYSCON_DEVCFG,
  70         .enable_mask    = EP93XX_SYSCON_DEVCFG_U3EN,
  71         .get_rate       = get_uart_rate,
  72 };
  73 static struct clk clk_pll1 = {
  74         .parent         = &clk_xtali,
  75 };
  76 static struct clk clk_f = {
  77         .parent         = &clk_pll1,
  78 };
  79 static struct clk clk_h = {
  80         .parent         = &clk_pll1,
  81 };
  82 static struct clk clk_p = {
  83         .parent         = &clk_pll1,
  84 };
  85 static struct clk clk_pll2 = {
  86         .parent         = &clk_xtali,
  87 };
  88 static struct clk clk_usb_host = {
  89         .parent         = &clk_pll2,
  90         .enable_reg     = EP93XX_SYSCON_PWRCNT,
  91         .enable_mask    = EP93XX_SYSCON_PWRCNT_USH_EN,
  92 };
  93 static struct clk clk_keypad = {
  94         .parent         = &clk_xtali,
  95         .sw_locked      = 1,
  96         .enable_reg     = EP93XX_SYSCON_KEYTCHCLKDIV,
  97         .enable_mask    = EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
  98         .set_rate       = set_keytchclk_rate,
  99 };
 100 static struct clk clk_pwm = {
 101         .parent         = &clk_xtali,
 102         .rate           = EP93XX_EXT_CLK_RATE,
 103 };
 104
 105 static struct clk clk_video = {
 106         .sw_locked      = 1,
 107         .enable_reg     = EP93XX_SYSCON_VIDCLKDIV,
 108         .enable_mask    = EP93XX_SYSCON_CLKDIV_ENABLE,
 109         .set_rate       = set_div_rate,
 110 };
 111
 112 static struct clk clk_i2s_mclk = {
 113         .sw_locked      = 1,
 114         .enable_reg     = EP93XX_SYSCON_I2SCLKDIV,
 115         .enable_mask    = EP93XX_SYSCON_CLKDIV_ENABLE,
 116         .set_rate       = set_div_rate,
 117 };
 118
 119 static struct clk clk_i2s_sclk = {
 120         .sw_locked      = 1,
 121         .parent         = &clk_i2s_mclk,
 122         .enable_reg     = EP93XX_SYSCON_I2SCLKDIV,
 123         .enable_mask    = EP93XX_SYSCON_I2SCLKDIV_SENA,
 124         .set_rate       = set_i2s_sclk_rate,
 125 };
 126
 127 static struct clk clk_i2s_lrclk = {
 128         .sw_locked      = 1,
 129         .parent         = &clk_i2s_sclk,
 130         .enable_reg     = EP93XX_SYSCON_I2SCLKDIV,
 131         .enable_mask    = EP93XX_SYSCON_I2SCLKDIV_SENA,
 132         .set_rate       = set_i2s_lrclk_rate,
 133 };
 134
 135 /* DMA Clocks */
 136 static struct clk clk_m2p0 = {
 137         .parent         = &clk_h,
 138         .enable_reg     = EP93XX_SYSCON_PWRCNT,
 139         .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2P0,
 140 };
 141 static struct clk clk_m2p1 = {
 142         .parent         = &clk_h,
 143         .enable_reg     = EP93XX_SYSCON_PWRCNT,
 144         .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2P1,
 145 };
 146 static struct clk clk_m2p2 = {
 147         .parent         = &clk_h,
 148         .enable_reg     = EP93XX_SYSCON_PWRCNT,
 149         .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2P2,
 150 };
 151 static struct clk clk_m2p3 = {
 152         .parent         = &clk_h,
 153         .enable_reg     = EP93XX_SYSCON_PWRCNT,
 154         .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2P3,
 155 };
 156 static struct clk clk_m2p4 = {
 157         .parent         = &clk_h,
 158         .enable_reg     = EP93XX_SYSCON_PWRCNT,
 159         .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2P4,
 160 };
 161 static struct clk clk_m2p5 = {
 162         .parent         = &clk_h,
 163         .enable_reg     = EP93XX_SYSCON_PWRCNT,
 164         .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2P5,
 165 };
 166 static struct clk clk_m2p6 = {
 167         .parent         = &clk_h,
 168         .enable_reg     = EP93XX_SYSCON_PWRCNT,
 169         .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2P6,
 170 };
 171 static struct clk clk_m2p7 = {
 172         .parent         = &clk_h,
 173         .enable_reg     = EP93XX_SYSCON_PWRCNT,
 174         .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2P7,
 175 };
 176 static struct clk clk_m2p8 = {
 177         .parent         = &clk_h,
 178         .enable_reg     = EP93XX_SYSCON_PWRCNT,
 179         .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2P8,
 180 };
 181 static struct clk clk_m2p9 = {
 182         .parent         = &clk_h,
 183         .enable_reg     = EP93XX_SYSCON_PWRCNT,
 184         .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2P9,
 185 };
 186 static struct clk clk_m2m0 = {
 187         .parent         = &clk_h,
 188         .enable_reg     = EP93XX_SYSCON_PWRCNT,
 189         .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2M0,
 190 };
 191 static struct clk clk_m2m1 = {
 192         .parent         = &clk_h,
 193         .enable_reg     = EP93XX_SYSCON_PWRCNT,
 194         .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2M1,
 195 };
 196
 197 #define INIT_CK(dev,con,ck)                                     \
 198         { .dev_id = dev, .con_id = con, .clk = ck }
 199
 200 static struct clk_lookup clocks[] = {
 201         INIT_CK(NULL,                   "xtali",        &clk_xtali),
 202         INIT_CK("apb:uart1",            NULL,           &clk_uart1),
 203         INIT_CK("apb:uart2",            NULL,           &clk_uart2),
 204         INIT_CK("apb:uart3",            NULL,           &clk_uart3),
 205         INIT_CK(NULL,                   "pll1",         &clk_pll1),
 206         INIT_CK(NULL,                   "fclk",         &clk_f),
 207         INIT_CK(NULL,                   "hclk",         &clk_h),
 208         INIT_CK(NULL,                   "pclk",         &clk_p),
 209         INIT_CK(NULL,                   "pll2",         &clk_pll2),
 210         INIT_CK("ep93xx-ohci",          NULL,           &clk_usb_host),
 211         INIT_CK("ep93xx-keypad",        NULL,           &clk_keypad),
 212         INIT_CK("ep93xx-fb",            NULL,           &clk_video),
 213         INIT_CK("ep93xx-i2s",           "mclk",         &clk_i2s_mclk),
 214         INIT_CK("ep93xx-i2s",           "sclk",         &clk_i2s_sclk),
 215         INIT_CK("ep93xx-i2s",           "lrclk",        &clk_i2s_lrclk),
 216         INIT_CK(NULL,                   "pwm_clk",      &clk_pwm),
 217         INIT_CK(NULL,                   "m2p0",         &clk_m2p0),
 218         INIT_CK(NULL,                   "m2p1",         &clk_m2p1),
 219         INIT_CK(NULL,                   "m2p2",         &clk_m2p2),
 220         INIT_CK(NULL,                   "m2p3",         &clk_m2p3),
 221         INIT_CK(NULL,                   "m2p4",         &clk_m2p4),
 222         INIT_CK(NULL,                   "m2p5",         &clk_m2p5),
 223         INIT_CK(NULL,                   "m2p6",         &clk_m2p6),
 224         INIT_CK(NULL,                   "m2p7",         &clk_m2p7),
 225         INIT_CK(NULL,                   "m2p8",         &clk_m2p8),
 226         INIT_CK(NULL,                   "m2p9",         &clk_m2p9),
 227         INIT_CK(NULL,                   "m2m0",         &clk_m2m0),
 228         INIT_CK(NULL,                   "m2m1",         &clk_m2m1),
 229 };
 230
 231 static DEFINE_SPINLOCK(clk_lock);
 232
 233 static void __clk_enable(struct clk *clk)
 234 {
 235         if (!clk->users++) {
 236                 if (clk->parent)
 237                         __clk_enable(clk->parent);
 238
 239                 if (clk->enable_reg) {
 240                         u32 v;
 241
 242                         v = __raw_readl(clk->enable_reg);
 243                         v |= clk->enable_mask;
 244                         if (clk->sw_locked)
 245                                 ep93xx_syscon_swlocked_write(v, clk->enable_reg);
 246                         else
 247                                 __raw_writel(v, clk->enable_reg);
 248                 }
 249         }
 250 }
 251
 252 int clk_enable(struct clk *clk)
 253 {
 254         unsigned long flags;
 255
 256         if (!clk)
 257                 return -EINVAL;
 258
 259         spin_lock_irqsave(&clk_lock, flags);
 260         __clk_enable(clk);
 261         spin_unlock_irqrestore(&clk_lock, flags);
 262
 263         return 0;
 264 }
 265 EXPORT_SYMBOL(clk_enable);
 266
 267 static void __clk_disable(struct clk *clk)
 268 {
 269         if (!--clk->users) {
 270                 if (clk->enable_reg) {
 271                         u32 v;
 272
 273                         v = __raw_readl(clk->enable_reg);
 274                         v &= ~clk->enable_mask;
 275                         if (clk->sw_locked)
 276                                 ep93xx_syscon_swlocked_write(v, clk->enable_reg);
 277                         else
 278                                 __raw_writel(v, clk->enable_reg);
 279                 }
 280
 281                 if (clk->parent)
 282                         __clk_disable(clk->parent);
 283         }
 284 }
 285
 286 void clk_disable(struct clk *clk)
 287 {
 288         unsigned long flags;
 289
 290         if (!clk)
 291                 return;
 292
 293         spin_lock_irqsave(&clk_lock, flags);
 294         __clk_disable(clk);
 295         spin_unlock_irqrestore(&clk_lock, flags);
 296 }
 297 EXPORT_SYMBOL(clk_disable);
 298
 299 static unsigned long get_uart_rate(struct clk *clk)
 300 {
 301         unsigned long rate = clk_get_rate(clk->parent);
 302         u32 value;
 303
 304         value = __raw_readl(EP93XX_SYSCON_PWRCNT);
 305         if (value & EP93XX_SYSCON_PWRCNT_UARTBAUD)
 306                 return rate;
 307         else
 308                 return rate / 2;
 309 }
 310
 311 unsigned long clk_get_rate(struct clk *clk)
 312 {
 313         if (clk->get_rate)
 314                 return clk->get_rate(clk);
 315
 316         return clk->rate;
 317 }
 318 EXPORT_SYMBOL(clk_get_rate);
 319
 320 static int set_keytchclk_rate(struct clk *clk, unsigned long rate)
 321 {
 322         u32 val;
 323         u32 div_bit;
 324
 325         val = __raw_readl(clk->enable_reg);
 326
 327         /*
 328          * The Key Matrix and ADC clocks are configured using the same
 329          * System Controller register.  The clock used will be either
 330          * 1/4 or 1/16 the external clock rate depending on the
 331          * EP93XX_SYSCON_KEYTCHCLKDIV_KDIV/EP93XX_SYSCON_KEYTCHCLKDIV_ADIV
 332          * bit being set or cleared.
 333          */
 334         div_bit = clk->enable_mask >> 15;
 335
 336         if (rate == EP93XX_KEYTCHCLK_DIV4)
 337                 val |= div_bit;
 338         else if (rate == EP93XX_KEYTCHCLK_DIV16)
 339                 val &= ~div_bit;
 340         else
 341                 return -EINVAL;
 342
 343         ep93xx_syscon_swlocked_write(val, clk->enable_reg);
 344         clk->rate = rate;
 345         return 0;
 346 }
 347
 348 static int calc_clk_div(struct clk *clk, unsigned long rate,
 349                         int *psel, int *esel, int *pdiv, int *div)
 350 {
 351         struct clk *mclk;
 352         unsigned long max_rate, actual_rate, mclk_rate, rate_err = -1;
 353         int i, found = 0, __div = 0, __pdiv = 0;
 354
 355         /* Don't exceed the maximum rate */
 356         max_rate = max(max(clk_pll1.rate / 4, clk_pll2.rate / 4),
 357                        clk_xtali.rate / 4);
 358         rate = min(rate, max_rate);
 359
 360         /*
 361          * Try the two pll's and the external clock
 362          * Because the valid predividers are 2, 2.5 and 3, we multiply
 363          * all the clocks by 2 to avoid floating point math.
 364          *
 365          * This is based on the algorithm in the ep93xx raster guide:
 366          * http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf
 367          *
 368          */
 369         for (i = 0; i < 3; i++) {
 370                 if (i == 0)
 371                         mclk = &clk_xtali;
 372                 else if (i == 1)
 373                         mclk = &clk_pll1;
 374                 else
 375                         mclk = &clk_pll2;
 376                 mclk_rate = mclk->rate * 2;
 377
 378                 /* Try each predivider value */
 379                 for (__pdiv = 4; __pdiv <= 6; __pdiv++) {
 380                         __div = mclk_rate / (rate * __pdiv);
 381                         if (__div < 2 || __div > 127)
 382                                 continue;
 383
 384                         actual_rate = mclk_rate / (__pdiv * __div);
 385
 386                         if (!found || abs(actual_rate - rate) < rate_err) {
 387                                 *pdiv = __pdiv - 3;
 388                                 *div = __div;
 389                                 *psel = (i == 2);
 390                                 *esel = (i != 0);
 391                                 clk->parent = mclk;
 392                                 clk->rate = actual_rate;
 393                                 rate_err = abs(actual_rate - rate);
 394                                 found = 1;
 395                         }
 396                 }
 397         }
 398
 399         if (!found)
 400                 return -EINVAL;
 401
 402         return 0;
 403 }
 404
 405 static int set_div_rate(struct clk *clk, unsigned long rate)
 406 {
 407         int err, psel = 0, esel = 0, pdiv = 0, div = 0;
 408         u32 val;
 409
 410         err = calc_clk_div(clk, rate, &psel, &esel, &pdiv, &div);
 411         if (err)
 412                 return err;
 413
 414         /* Clear the esel, psel, pdiv and div bits */
 415         val = __raw_readl(clk->enable_reg);
 416         val &= ~0x7fff;
 417
 418         /* Set the new esel, psel, pdiv and div bits for the new clock rate */
 419         val |= (esel ? EP93XX_SYSCON_CLKDIV_ESEL : 0) |
 420                 (psel ? EP93XX_SYSCON_CLKDIV_PSEL : 0) |
 421                 (pdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | div;
 422         ep93xx_syscon_swlocked_write(val, clk->enable_reg);
 423         return 0;
 424 }
 425
 426 static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate)
 427 {
 428         unsigned val = __raw_readl(clk->enable_reg);
 429
 430         if (rate == clk_i2s_mclk.rate / 2)
 431                 ep93xx_syscon_swlocked_write(val & ~EP93XX_I2SCLKDIV_SDIV,
 432                                              clk->enable_reg);
 433         else if (rate == clk_i2s_mclk.rate / 4)
 434                 ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_SDIV,
 435                                              clk->enable_reg);
 436         else
 437                 return -EINVAL;
 438
 439         clk_i2s_sclk.rate = rate;
 440         return 0;
 441 }
 442
 443 static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate)
 444 {
 445         unsigned val = __raw_readl(clk->enable_reg) &
 446                 ~EP93XX_I2SCLKDIV_LRDIV_MASK;
 447
 448         if (rate == clk_i2s_sclk.rate / 32)
 449                 ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV32,
 450                                              clk->enable_reg);
 451         else if (rate == clk_i2s_sclk.rate / 64)
 452                 ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV64,
 453                                              clk->enable_reg);
 454         else if (rate == clk_i2s_sclk.rate / 128)
 455                 ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV128,
 456                                              clk->enable_reg);
 457         else
 458                 return -EINVAL;
 459
 460         clk_i2s_lrclk.rate = rate;
 461         return 0;
 462 }
 463
 464 int clk_set_rate(struct clk *clk, unsigned long rate)
 465 {
 466         if (clk->set_rate)
 467                 return clk->set_rate(clk, rate);
 468
 469         return -EINVAL;
 470 }
 471 EXPORT_SYMBOL(clk_set_rate);
 472
 473
 474 static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
 475 static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
 476 static char pclk_divisors[] = { 1, 2, 4, 8 };
 477
 478 /*
 479  * PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS
 480  */
 481 static unsigned long calc_pll_rate(u32 config_word)
 482 {
 483         unsigned long long rate;
 484         int i;
 485
 486         rate = clk_xtali.rate;
 487         rate *= ((config_word >> 11) & 0x1f) + 1;               /* X1FBD */
 488         rate *= ((config_word >> 5) & 0x3f) + 1;                /* X2FBD */
 489         do_div(rate, (config_word & 0x1f) + 1);                 /* X2IPD */
 490         for (i = 0; i < ((config_word >> 16) & 3); i++)         /* PS */
 491                 rate >>= 1;
 492
 493         return (unsigned long)rate;
 494 }
 495
 496 static void __init ep93xx_dma_clock_init(void)
 497 {
 498         clk_m2p0.rate = clk_h.rate;
 499         clk_m2p1.rate = clk_h.rate;
 500         clk_m2p2.rate = clk_h.rate;
 501         clk_m2p3.rate = clk_h.rate;
 502         clk_m2p4.rate = clk_h.rate;
 503         clk_m2p5.rate = clk_h.rate;
 504         clk_m2p6.rate = clk_h.rate;
 505         clk_m2p7.rate = clk_h.rate;
 506         clk_m2p8.rate = clk_h.rate;
 507         clk_m2p9.rate = clk_h.rate;
 508         clk_m2m0.rate = clk_h.rate;
 509         clk_m2m1.rate = clk_h.rate;
 510 }
 511
 512 static int __init ep93xx_clock_init(void)
 513 {
 514         u32 value;
 515
 516         /* Determine the bootloader configured pll1 rate */
 517         value = __raw_readl(EP93XX_SYSCON_CLKSET1);
 518         if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1))
 519                 clk_pll1.rate = clk_xtali.rate;
 520         else
 521                 clk_pll1.rate = calc_pll_rate(value);
 522
 523         /* Initialize the pll1 derived clocks */
 524         clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7];
 525         clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7];
 526         clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3];
 527         ep93xx_dma_clock_init();
 528
 529         /* Determine the bootloader configured pll2 rate */
 530         value = __raw_readl(EP93XX_SYSCON_CLKSET2);
 531         if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2))
 532                 clk_pll2.rate = clk_xtali.rate;
 533         else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN)
 534                 clk_pll2.rate = calc_pll_rate(value);
 535         else
 536                 clk_pll2.rate = 0;
 537
 538         /* Initialize the pll2 derived clocks */
 539         clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1);
 540
 541         pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n",
 542                 clk_pll1.rate / 1000000, clk_pll2.rate / 1000000);
 543         pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",
 544                 clk_f.rate / 1000000, clk_h.rate / 1000000,
 545                 clk_p.rate / 1000000);
 546
 547         clkdev_add_table(clocks, ARRAY_SIZE(clocks));
 548         return 0;
 549 }
 550 arch_initcall(ep93xx_clock_init);