Merge tag 'v3.8-rc1' into staging/for_v3.9
[sfrench/cifs-2.6.git] / arch / arm / mach-davinci / dm644x.c
1 /*
2  * TI DaVinci DM644x chip specific setup
3  *
4  * Author: Kevin Hilman, Deep Root Systems, LLC
5  *
6  * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7  * the terms of the GNU General Public License version 2. This program
8  * is licensed "as is" without any warranty of any kind, whether express
9  * or implied.
10  */
11 #include <linux/init.h>
12 #include <linux/clk.h>
13 #include <linux/serial_8250.h>
14 #include <linux/platform_device.h>
15
16 #include <asm/mach/map.h>
17
18 #include <mach/cputype.h>
19 #include <mach/edma.h>
20 #include <mach/irqs.h>
21 #include <mach/psc.h>
22 #include <mach/mux.h>
23 #include <mach/time.h>
24 #include <mach/serial.h>
25 #include <mach/common.h>
26 #include <mach/gpio-davinci.h>
27
28 #include "davinci.h"
29 #include "clock.h"
30 #include "mux.h"
31 #include "asp.h"
32
33 /*
34  * Device specific clocks
35  */
36 #define DM644X_REF_FREQ         27000000
37
38 #define DM644X_EMAC_BASE                0x01c80000
39 #define DM644X_EMAC_MDIO_BASE           (DM644X_EMAC_BASE + 0x4000)
40 #define DM644X_EMAC_CNTRL_OFFSET        0x0000
41 #define DM644X_EMAC_CNTRL_MOD_OFFSET    0x1000
42 #define DM644X_EMAC_CNTRL_RAM_OFFSET    0x2000
43 #define DM644X_EMAC_CNTRL_RAM_SIZE      0x2000
44
45 static struct pll_data pll1_data = {
46         .num       = 1,
47         .phys_base = DAVINCI_PLL1_BASE,
48 };
49
50 static struct pll_data pll2_data = {
51         .num       = 2,
52         .phys_base = DAVINCI_PLL2_BASE,
53 };
54
55 static struct clk ref_clk = {
56         .name = "ref_clk",
57         .rate = DM644X_REF_FREQ,
58 };
59
60 static struct clk pll1_clk = {
61         .name = "pll1",
62         .parent = &ref_clk,
63         .pll_data = &pll1_data,
64         .flags = CLK_PLL,
65 };
66
67 static struct clk pll1_sysclk1 = {
68         .name = "pll1_sysclk1",
69         .parent = &pll1_clk,
70         .flags = CLK_PLL,
71         .div_reg = PLLDIV1,
72 };
73
74 static struct clk pll1_sysclk2 = {
75         .name = "pll1_sysclk2",
76         .parent = &pll1_clk,
77         .flags = CLK_PLL,
78         .div_reg = PLLDIV2,
79 };
80
81 static struct clk pll1_sysclk3 = {
82         .name = "pll1_sysclk3",
83         .parent = &pll1_clk,
84         .flags = CLK_PLL,
85         .div_reg = PLLDIV3,
86 };
87
88 static struct clk pll1_sysclk5 = {
89         .name = "pll1_sysclk5",
90         .parent = &pll1_clk,
91         .flags = CLK_PLL,
92         .div_reg = PLLDIV5,
93 };
94
95 static struct clk pll1_aux_clk = {
96         .name = "pll1_aux_clk",
97         .parent = &pll1_clk,
98         .flags = CLK_PLL | PRE_PLL,
99 };
100
101 static struct clk pll1_sysclkbp = {
102         .name = "pll1_sysclkbp",
103         .parent = &pll1_clk,
104         .flags = CLK_PLL | PRE_PLL,
105         .div_reg = BPDIV
106 };
107
108 static struct clk pll2_clk = {
109         .name = "pll2",
110         .parent = &ref_clk,
111         .pll_data = &pll2_data,
112         .flags = CLK_PLL,
113 };
114
115 static struct clk pll2_sysclk1 = {
116         .name = "pll2_sysclk1",
117         .parent = &pll2_clk,
118         .flags = CLK_PLL,
119         .div_reg = PLLDIV1,
120 };
121
122 static struct clk pll2_sysclk2 = {
123         .name = "pll2_sysclk2",
124         .parent = &pll2_clk,
125         .flags = CLK_PLL,
126         .div_reg = PLLDIV2,
127 };
128
129 static struct clk pll2_sysclkbp = {
130         .name = "pll2_sysclkbp",
131         .parent = &pll2_clk,
132         .flags = CLK_PLL | PRE_PLL,
133         .div_reg = BPDIV
134 };
135
136 static struct clk dsp_clk = {
137         .name = "dsp",
138         .parent = &pll1_sysclk1,
139         .lpsc = DAVINCI_LPSC_GEM,
140         .domain = DAVINCI_GPSC_DSPDOMAIN,
141         .usecount = 1,                  /* REVISIT how to disable? */
142 };
143
144 static struct clk arm_clk = {
145         .name = "arm",
146         .parent = &pll1_sysclk2,
147         .lpsc = DAVINCI_LPSC_ARM,
148         .flags = ALWAYS_ENABLED,
149 };
150
151 static struct clk vicp_clk = {
152         .name = "vicp",
153         .parent = &pll1_sysclk2,
154         .lpsc = DAVINCI_LPSC_IMCOP,
155         .domain = DAVINCI_GPSC_DSPDOMAIN,
156         .usecount = 1,                  /* REVISIT how to disable? */
157 };
158
159 static struct clk vpss_master_clk = {
160         .name = "vpss_master",
161         .parent = &pll1_sysclk3,
162         .lpsc = DAVINCI_LPSC_VPSSMSTR,
163         .flags = CLK_PSC,
164 };
165
166 static struct clk vpss_slave_clk = {
167         .name = "vpss_slave",
168         .parent = &pll1_sysclk3,
169         .lpsc = DAVINCI_LPSC_VPSSSLV,
170 };
171
172 static struct clk uart0_clk = {
173         .name = "uart0",
174         .parent = &pll1_aux_clk,
175         .lpsc = DAVINCI_LPSC_UART0,
176 };
177
178 static struct clk uart1_clk = {
179         .name = "uart1",
180         .parent = &pll1_aux_clk,
181         .lpsc = DAVINCI_LPSC_UART1,
182 };
183
184 static struct clk uart2_clk = {
185         .name = "uart2",
186         .parent = &pll1_aux_clk,
187         .lpsc = DAVINCI_LPSC_UART2,
188 };
189
190 static struct clk emac_clk = {
191         .name = "emac",
192         .parent = &pll1_sysclk5,
193         .lpsc = DAVINCI_LPSC_EMAC_WRAPPER,
194 };
195
196 static struct clk i2c_clk = {
197         .name = "i2c",
198         .parent = &pll1_aux_clk,
199         .lpsc = DAVINCI_LPSC_I2C,
200 };
201
202 static struct clk ide_clk = {
203         .name = "ide",
204         .parent = &pll1_sysclk5,
205         .lpsc = DAVINCI_LPSC_ATA,
206 };
207
208 static struct clk asp_clk = {
209         .name = "asp0",
210         .parent = &pll1_sysclk5,
211         .lpsc = DAVINCI_LPSC_McBSP,
212 };
213
214 static struct clk mmcsd_clk = {
215         .name = "mmcsd",
216         .parent = &pll1_sysclk5,
217         .lpsc = DAVINCI_LPSC_MMC_SD,
218 };
219
220 static struct clk spi_clk = {
221         .name = "spi",
222         .parent = &pll1_sysclk5,
223         .lpsc = DAVINCI_LPSC_SPI,
224 };
225
226 static struct clk gpio_clk = {
227         .name = "gpio",
228         .parent = &pll1_sysclk5,
229         .lpsc = DAVINCI_LPSC_GPIO,
230 };
231
232 static struct clk usb_clk = {
233         .name = "usb",
234         .parent = &pll1_sysclk5,
235         .lpsc = DAVINCI_LPSC_USB,
236 };
237
238 static struct clk vlynq_clk = {
239         .name = "vlynq",
240         .parent = &pll1_sysclk5,
241         .lpsc = DAVINCI_LPSC_VLYNQ,
242 };
243
244 static struct clk aemif_clk = {
245         .name = "aemif",
246         .parent = &pll1_sysclk5,
247         .lpsc = DAVINCI_LPSC_AEMIF,
248 };
249
250 static struct clk pwm0_clk = {
251         .name = "pwm0",
252         .parent = &pll1_aux_clk,
253         .lpsc = DAVINCI_LPSC_PWM0,
254 };
255
256 static struct clk pwm1_clk = {
257         .name = "pwm1",
258         .parent = &pll1_aux_clk,
259         .lpsc = DAVINCI_LPSC_PWM1,
260 };
261
262 static struct clk pwm2_clk = {
263         .name = "pwm2",
264         .parent = &pll1_aux_clk,
265         .lpsc = DAVINCI_LPSC_PWM2,
266 };
267
268 static struct clk timer0_clk = {
269         .name = "timer0",
270         .parent = &pll1_aux_clk,
271         .lpsc = DAVINCI_LPSC_TIMER0,
272 };
273
274 static struct clk timer1_clk = {
275         .name = "timer1",
276         .parent = &pll1_aux_clk,
277         .lpsc = DAVINCI_LPSC_TIMER1,
278 };
279
280 static struct clk timer2_clk = {
281         .name = "timer2",
282         .parent = &pll1_aux_clk,
283         .lpsc = DAVINCI_LPSC_TIMER2,
284         .usecount = 1,              /* REVISIT: why can't this be disabled? */
285 };
286
287 static struct clk_lookup dm644x_clks[] = {
288         CLK(NULL, "ref", &ref_clk),
289         CLK(NULL, "pll1", &pll1_clk),
290         CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
291         CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
292         CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
293         CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
294         CLK(NULL, "pll1_aux", &pll1_aux_clk),
295         CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
296         CLK(NULL, "pll2", &pll2_clk),
297         CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
298         CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
299         CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
300         CLK(NULL, "dsp", &dsp_clk),
301         CLK(NULL, "arm", &arm_clk),
302         CLK(NULL, "vicp", &vicp_clk),
303         CLK(NULL, "vpss_master", &vpss_master_clk),
304         CLK(NULL, "vpss_slave", &vpss_slave_clk),
305         CLK(NULL, "arm", &arm_clk),
306         CLK(NULL, "uart0", &uart0_clk),
307         CLK(NULL, "uart1", &uart1_clk),
308         CLK(NULL, "uart2", &uart2_clk),
309         CLK("davinci_emac.1", NULL, &emac_clk),
310         CLK("i2c_davinci.1", NULL, &i2c_clk),
311         CLK("palm_bk3710", NULL, &ide_clk),
312         CLK("davinci-mcbsp", NULL, &asp_clk),
313         CLK("davinci_mmc.0", NULL, &mmcsd_clk),
314         CLK(NULL, "spi", &spi_clk),
315         CLK(NULL, "gpio", &gpio_clk),
316         CLK(NULL, "usb", &usb_clk),
317         CLK(NULL, "vlynq", &vlynq_clk),
318         CLK(NULL, "aemif", &aemif_clk),
319         CLK(NULL, "pwm0", &pwm0_clk),
320         CLK(NULL, "pwm1", &pwm1_clk),
321         CLK(NULL, "pwm2", &pwm2_clk),
322         CLK(NULL, "timer0", &timer0_clk),
323         CLK(NULL, "timer1", &timer1_clk),
324         CLK("watchdog", NULL, &timer2_clk),
325         CLK(NULL, NULL, NULL),
326 };
327
328 static struct emac_platform_data dm644x_emac_pdata = {
329         .ctrl_reg_offset        = DM644X_EMAC_CNTRL_OFFSET,
330         .ctrl_mod_reg_offset    = DM644X_EMAC_CNTRL_MOD_OFFSET,
331         .ctrl_ram_offset        = DM644X_EMAC_CNTRL_RAM_OFFSET,
332         .ctrl_ram_size          = DM644X_EMAC_CNTRL_RAM_SIZE,
333         .version                = EMAC_VERSION_1,
334 };
335
336 static struct resource dm644x_emac_resources[] = {
337         {
338                 .start  = DM644X_EMAC_BASE,
339                 .end    = DM644X_EMAC_BASE + SZ_16K - 1,
340                 .flags  = IORESOURCE_MEM,
341         },
342         {
343                 .start = IRQ_EMACINT,
344                 .end   = IRQ_EMACINT,
345                 .flags = IORESOURCE_IRQ,
346         },
347 };
348
349 static struct platform_device dm644x_emac_device = {
350        .name            = "davinci_emac",
351        .id              = 1,
352        .dev = {
353                .platform_data   = &dm644x_emac_pdata,
354        },
355        .num_resources   = ARRAY_SIZE(dm644x_emac_resources),
356        .resource        = dm644x_emac_resources,
357 };
358
359 static struct resource dm644x_mdio_resources[] = {
360         {
361                 .start  = DM644X_EMAC_MDIO_BASE,
362                 .end    = DM644X_EMAC_MDIO_BASE + SZ_4K - 1,
363                 .flags  = IORESOURCE_MEM,
364         },
365 };
366
367 static struct platform_device dm644x_mdio_device = {
368         .name           = "davinci_mdio",
369         .id             = 0,
370         .num_resources  = ARRAY_SIZE(dm644x_mdio_resources),
371         .resource       = dm644x_mdio_resources,
372 };
373
374 /*
375  * Device specific mux setup
376  *
377  *      soc     description     mux  mode   mode  mux    dbg
378  *                              reg  offset mask  mode
379  */
380 static const struct mux_config dm644x_pins[] = {
381 #ifdef CONFIG_DAVINCI_MUX
382 MUX_CFG(DM644X, HDIREN,         0,   16,    1,    1,     true)
383 MUX_CFG(DM644X, ATAEN,          0,   17,    1,    1,     true)
384 MUX_CFG(DM644X, ATAEN_DISABLE,  0,   17,    1,    0,     true)
385
386 MUX_CFG(DM644X, HPIEN_DISABLE,  0,   29,    1,    0,     true)
387
388 MUX_CFG(DM644X, AEAW,           0,   0,     31,   31,    true)
389 MUX_CFG(DM644X, AEAW0,          0,   0,     1,    0,     true)
390 MUX_CFG(DM644X, AEAW1,          0,   1,     1,    0,     true)
391 MUX_CFG(DM644X, AEAW2,          0,   2,     1,    0,     true)
392 MUX_CFG(DM644X, AEAW3,          0,   3,     1,    0,     true)
393 MUX_CFG(DM644X, AEAW4,          0,   4,     1,    0,     true)
394
395 MUX_CFG(DM644X, MSTK,           1,   9,     1,    0,     false)
396
397 MUX_CFG(DM644X, I2C,            1,   7,     1,    1,     false)
398
399 MUX_CFG(DM644X, MCBSP,          1,   10,    1,    1,     false)
400
401 MUX_CFG(DM644X, UART1,          1,   1,     1,    1,     true)
402 MUX_CFG(DM644X, UART2,          1,   2,     1,    1,     true)
403
404 MUX_CFG(DM644X, PWM0,           1,   4,     1,    1,     false)
405
406 MUX_CFG(DM644X, PWM1,           1,   5,     1,    1,     false)
407
408 MUX_CFG(DM644X, PWM2,           1,   6,     1,    1,     false)
409
410 MUX_CFG(DM644X, VLYNQEN,        0,   15,    1,    1,     false)
411 MUX_CFG(DM644X, VLSCREN,        0,   14,    1,    1,     false)
412 MUX_CFG(DM644X, VLYNQWD,        0,   12,    3,    3,     false)
413
414 MUX_CFG(DM644X, EMACEN,         0,   31,    1,    1,     true)
415
416 MUX_CFG(DM644X, GPIO3V,         0,   31,    1,    0,     true)
417
418 MUX_CFG(DM644X, GPIO0,          0,   24,    1,    0,     true)
419 MUX_CFG(DM644X, GPIO3,          0,   25,    1,    0,     false)
420 MUX_CFG(DM644X, GPIO43_44,      1,   7,     1,    0,     false)
421 MUX_CFG(DM644X, GPIO46_47,      0,   22,    1,    0,     true)
422
423 MUX_CFG(DM644X, RGB666,         0,   22,    1,    1,     true)
424
425 MUX_CFG(DM644X, LOEEN,          0,   24,    1,    1,     true)
426 MUX_CFG(DM644X, LFLDEN,         0,   25,    1,    1,     false)
427 #endif
428 };
429
430 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
431 static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
432         [IRQ_VDINT0]            = 2,
433         [IRQ_VDINT1]            = 6,
434         [IRQ_VDINT2]            = 6,
435         [IRQ_HISTINT]           = 6,
436         [IRQ_H3AINT]            = 6,
437         [IRQ_PRVUINT]           = 6,
438         [IRQ_RSZINT]            = 6,
439         [7]                     = 7,
440         [IRQ_VENCINT]           = 6,
441         [IRQ_ASQINT]            = 6,
442         [IRQ_IMXINT]            = 6,
443         [IRQ_VLCDINT]           = 6,
444         [IRQ_USBINT]            = 4,
445         [IRQ_EMACINT]           = 4,
446         [14]                    = 7,
447         [15]                    = 7,
448         [IRQ_CCINT0]            = 5,    /* dma */
449         [IRQ_CCERRINT]          = 5,    /* dma */
450         [IRQ_TCERRINT0]         = 5,    /* dma */
451         [IRQ_TCERRINT]          = 5,    /* dma */
452         [IRQ_PSCIN]             = 7,
453         [21]                    = 7,
454         [IRQ_IDE]               = 4,
455         [23]                    = 7,
456         [IRQ_MBXINT]            = 7,
457         [IRQ_MBRINT]            = 7,
458         [IRQ_MMCINT]            = 7,
459         [IRQ_SDIOINT]           = 7,
460         [28]                    = 7,
461         [IRQ_DDRINT]            = 7,
462         [IRQ_AEMIFINT]          = 7,
463         [IRQ_VLQINT]            = 4,
464         [IRQ_TINT0_TINT12]      = 2,    /* clockevent */
465         [IRQ_TINT0_TINT34]      = 2,    /* clocksource */
466         [IRQ_TINT1_TINT12]      = 7,    /* DSP timer */
467         [IRQ_TINT1_TINT34]      = 7,    /* system tick */
468         [IRQ_PWMINT0]           = 7,
469         [IRQ_PWMINT1]           = 7,
470         [IRQ_PWMINT2]           = 7,
471         [IRQ_I2C]               = 3,
472         [IRQ_UARTINT0]          = 3,
473         [IRQ_UARTINT1]          = 3,
474         [IRQ_UARTINT2]          = 3,
475         [IRQ_SPINT0]            = 3,
476         [IRQ_SPINT1]            = 3,
477         [45]                    = 7,
478         [IRQ_DSP2ARM0]          = 4,
479         [IRQ_DSP2ARM1]          = 4,
480         [IRQ_GPIO0]             = 7,
481         [IRQ_GPIO1]             = 7,
482         [IRQ_GPIO2]             = 7,
483         [IRQ_GPIO3]             = 7,
484         [IRQ_GPIO4]             = 7,
485         [IRQ_GPIO5]             = 7,
486         [IRQ_GPIO6]             = 7,
487         [IRQ_GPIO7]             = 7,
488         [IRQ_GPIOBNK0]          = 7,
489         [IRQ_GPIOBNK1]          = 7,
490         [IRQ_GPIOBNK2]          = 7,
491         [IRQ_GPIOBNK3]          = 7,
492         [IRQ_GPIOBNK4]          = 7,
493         [IRQ_COMMTX]            = 7,
494         [IRQ_COMMRX]            = 7,
495         [IRQ_EMUINT]            = 7,
496 };
497
498 /*----------------------------------------------------------------------*/
499
500 static const s8
501 queue_tc_mapping[][2] = {
502         /* {event queue no, TC no} */
503         {0, 0},
504         {1, 1},
505         {-1, -1},
506 };
507
508 static const s8
509 queue_priority_mapping[][2] = {
510         /* {event queue no, Priority} */
511         {0, 3},
512         {1, 7},
513         {-1, -1},
514 };
515
516 static struct edma_soc_info edma_cc0_info = {
517         .n_channel              = 64,
518         .n_region               = 4,
519         .n_slot                 = 128,
520         .n_tc                   = 2,
521         .n_cc                   = 1,
522         .queue_tc_mapping       = queue_tc_mapping,
523         .queue_priority_mapping = queue_priority_mapping,
524         .default_queue          = EVENTQ_1,
525 };
526
527 static struct edma_soc_info *dm644x_edma_info[EDMA_MAX_CC] = {
528         &edma_cc0_info,
529 };
530
531 static struct resource edma_resources[] = {
532         {
533                 .name   = "edma_cc0",
534                 .start  = 0x01c00000,
535                 .end    = 0x01c00000 + SZ_64K - 1,
536                 .flags  = IORESOURCE_MEM,
537         },
538         {
539                 .name   = "edma_tc0",
540                 .start  = 0x01c10000,
541                 .end    = 0x01c10000 + SZ_1K - 1,
542                 .flags  = IORESOURCE_MEM,
543         },
544         {
545                 .name   = "edma_tc1",
546                 .start  = 0x01c10400,
547                 .end    = 0x01c10400 + SZ_1K - 1,
548                 .flags  = IORESOURCE_MEM,
549         },
550         {
551                 .name   = "edma0",
552                 .start  = IRQ_CCINT0,
553                 .flags  = IORESOURCE_IRQ,
554         },
555         {
556                 .name   = "edma0_err",
557                 .start  = IRQ_CCERRINT,
558                 .flags  = IORESOURCE_IRQ,
559         },
560         /* not using TC*_ERR */
561 };
562
563 static struct platform_device dm644x_edma_device = {
564         .name                   = "edma",
565         .id                     = 0,
566         .dev.platform_data      = dm644x_edma_info,
567         .num_resources          = ARRAY_SIZE(edma_resources),
568         .resource               = edma_resources,
569 };
570
571 /* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */
572 static struct resource dm644x_asp_resources[] = {
573         {
574                 .start  = DAVINCI_ASP0_BASE,
575                 .end    = DAVINCI_ASP0_BASE + SZ_8K - 1,
576                 .flags  = IORESOURCE_MEM,
577         },
578         {
579                 .start  = DAVINCI_DMA_ASP0_TX,
580                 .end    = DAVINCI_DMA_ASP0_TX,
581                 .flags  = IORESOURCE_DMA,
582         },
583         {
584                 .start  = DAVINCI_DMA_ASP0_RX,
585                 .end    = DAVINCI_DMA_ASP0_RX,
586                 .flags  = IORESOURCE_DMA,
587         },
588 };
589
590 static struct platform_device dm644x_asp_device = {
591         .name           = "davinci-mcbsp",
592         .id             = -1,
593         .num_resources  = ARRAY_SIZE(dm644x_asp_resources),
594         .resource       = dm644x_asp_resources,
595 };
596
597 #define DM644X_VPSS_BASE        0x01c73400
598
599 static struct resource dm644x_vpss_resources[] = {
600         {
601                 /* VPSS Base address */
602                 .name           = "vpss",
603                 .start          = DM644X_VPSS_BASE,
604                 .end            = DM644X_VPSS_BASE + 0xff,
605                 .flags          = IORESOURCE_MEM,
606         },
607 };
608
609 static struct platform_device dm644x_vpss_device = {
610         .name                   = "vpss",
611         .id                     = -1,
612         .dev.platform_data      = "dm644x_vpss",
613         .num_resources          = ARRAY_SIZE(dm644x_vpss_resources),
614         .resource               = dm644x_vpss_resources,
615 };
616
617 static struct resource dm644x_vpfe_resources[] = {
618         {
619                 .start          = IRQ_VDINT0,
620                 .end            = IRQ_VDINT0,
621                 .flags          = IORESOURCE_IRQ,
622         },
623         {
624                 .start          = IRQ_VDINT1,
625                 .end            = IRQ_VDINT1,
626                 .flags          = IORESOURCE_IRQ,
627         },
628 };
629
630 static u64 dm644x_video_dma_mask = DMA_BIT_MASK(32);
631 static struct resource dm644x_ccdc_resource[] = {
632         /* CCDC Base address */
633         {
634                 .start          = 0x01c70400,
635                 .end            = 0x01c70400 + 0xff,
636                 .flags          = IORESOURCE_MEM,
637         },
638 };
639
640 static struct platform_device dm644x_ccdc_dev = {
641         .name           = "dm644x_ccdc",
642         .id             = -1,
643         .num_resources  = ARRAY_SIZE(dm644x_ccdc_resource),
644         .resource       = dm644x_ccdc_resource,
645         .dev = {
646                 .dma_mask               = &dm644x_video_dma_mask,
647                 .coherent_dma_mask      = DMA_BIT_MASK(32),
648         },
649 };
650
651 static struct platform_device dm644x_vpfe_dev = {
652         .name           = CAPTURE_DRV_NAME,
653         .id             = -1,
654         .num_resources  = ARRAY_SIZE(dm644x_vpfe_resources),
655         .resource       = dm644x_vpfe_resources,
656         .dev = {
657                 .dma_mask               = &dm644x_video_dma_mask,
658                 .coherent_dma_mask      = DMA_BIT_MASK(32),
659         },
660 };
661
662 #define DM644X_OSD_BASE         0x01c72600
663
664 static struct resource dm644x_osd_resources[] = {
665         {
666                 .start  = DM644X_OSD_BASE,
667                 .end    = DM644X_OSD_BASE + 0x1ff,
668                 .flags  = IORESOURCE_MEM,
669         },
670 };
671
672 static struct platform_device dm644x_osd_dev = {
673         .name           = DM644X_VPBE_OSD_SUBDEV_NAME,
674         .id             = -1,
675         .num_resources  = ARRAY_SIZE(dm644x_osd_resources),
676         .resource       = dm644x_osd_resources,
677         .dev            = {
678                 .dma_mask               = &dm644x_video_dma_mask,
679                 .coherent_dma_mask      = DMA_BIT_MASK(32),
680         },
681 };
682
683 #define DM644X_VENC_BASE                0x01c72400
684
685 static struct resource dm644x_venc_resources[] = {
686         {
687                 .start  = DM644X_VENC_BASE,
688                 .end    = DM644X_VENC_BASE + 0x17f,
689                 .flags  = IORESOURCE_MEM,
690         },
691 };
692
693 #define DM644X_VPSS_MUXSEL_PLL2_MODE          BIT(0)
694 #define DM644X_VPSS_MUXSEL_VPBECLK_MODE       BIT(1)
695 #define DM644X_VPSS_VENCLKEN                  BIT(3)
696 #define DM644X_VPSS_DACCLKEN                  BIT(4)
697
698 static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,
699                                    unsigned int pclock)
700 {
701         int ret = 0;
702         u32 v = DM644X_VPSS_VENCLKEN;
703
704         switch (type) {
705         case VPBE_ENC_STD:
706                 v |= DM644X_VPSS_DACCLKEN;
707                 writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
708                 break;
709         case VPBE_ENC_CUSTOM_TIMINGS:
710                 if (pclock <= 27000000) {
711                         v |= DM644X_VPSS_DACCLKEN;
712                         writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
713                 } else {
714                         /*
715                          * For HD, use external clock source since
716                          * HD requires higher clock rate
717                          */
718                         v |= DM644X_VPSS_MUXSEL_VPBECLK_MODE;
719                         writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
720                 }
721                 break;
722         default:
723                 ret  = -EINVAL;
724         }
725
726         return ret;
727 }
728
729 static struct resource dm644x_v4l2_disp_resources[] = {
730         {
731                 .start  = IRQ_VENCINT,
732                 .end    = IRQ_VENCINT,
733                 .flags  = IORESOURCE_IRQ,
734         },
735 };
736
737 static struct platform_device dm644x_vpbe_display = {
738         .name           = "vpbe-v4l2",
739         .id             = -1,
740         .num_resources  = ARRAY_SIZE(dm644x_v4l2_disp_resources),
741         .resource       = dm644x_v4l2_disp_resources,
742         .dev            = {
743                 .dma_mask               = &dm644x_video_dma_mask,
744                 .coherent_dma_mask      = DMA_BIT_MASK(32),
745         },
746 };
747
748 static struct venc_platform_data dm644x_venc_pdata = {
749         .setup_clock    = dm644x_venc_setup_clock,
750 };
751
752 static struct platform_device dm644x_venc_dev = {
753         .name           = DM644X_VPBE_VENC_SUBDEV_NAME,
754         .id             = -1,
755         .num_resources  = ARRAY_SIZE(dm644x_venc_resources),
756         .resource       = dm644x_venc_resources,
757         .dev            = {
758                 .dma_mask               = &dm644x_video_dma_mask,
759                 .coherent_dma_mask      = DMA_BIT_MASK(32),
760                 .platform_data          = &dm644x_venc_pdata,
761         },
762 };
763
764 static struct platform_device dm644x_vpbe_dev = {
765         .name           = "vpbe_controller",
766         .id             = -1,
767         .dev            = {
768                 .dma_mask               = &dm644x_video_dma_mask,
769                 .coherent_dma_mask      = DMA_BIT_MASK(32),
770         },
771 };
772
773 /*----------------------------------------------------------------------*/
774
775 static struct map_desc dm644x_io_desc[] = {
776         {
777                 .virtual        = IO_VIRT,
778                 .pfn            = __phys_to_pfn(IO_PHYS),
779                 .length         = IO_SIZE,
780                 .type           = MT_DEVICE
781         },
782 };
783
784 /* Contents of JTAG ID register used to identify exact cpu type */
785 static struct davinci_id dm644x_ids[] = {
786         {
787                 .variant        = 0x0,
788                 .part_no        = 0xb700,
789                 .manufacturer   = 0x017,
790                 .cpu_id         = DAVINCI_CPU_ID_DM6446,
791                 .name           = "dm6446",
792         },
793         {
794                 .variant        = 0x1,
795                 .part_no        = 0xb700,
796                 .manufacturer   = 0x017,
797                 .cpu_id         = DAVINCI_CPU_ID_DM6446,
798                 .name           = "dm6446a",
799         },
800 };
801
802 static u32 dm644x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
803
804 /*
805  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
806  * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
807  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
808  * T1_TOP: Timer 1, top   :  <unused>
809  */
810 static struct davinci_timer_info dm644x_timer_info = {
811         .timers         = davinci_timer_instance,
812         .clockevent_id  = T0_BOT,
813         .clocksource_id = T0_TOP,
814 };
815
816 static struct plat_serial8250_port dm644x_serial_platform_data[] = {
817         {
818                 .mapbase        = DAVINCI_UART0_BASE,
819                 .irq            = IRQ_UARTINT0,
820                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
821                                   UPF_IOREMAP,
822                 .iotype         = UPIO_MEM,
823                 .regshift       = 2,
824         },
825         {
826                 .mapbase        = DAVINCI_UART1_BASE,
827                 .irq            = IRQ_UARTINT1,
828                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
829                                   UPF_IOREMAP,
830                 .iotype         = UPIO_MEM,
831                 .regshift       = 2,
832         },
833         {
834                 .mapbase        = DAVINCI_UART2_BASE,
835                 .irq            = IRQ_UARTINT2,
836                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
837                                   UPF_IOREMAP,
838                 .iotype         = UPIO_MEM,
839                 .regshift       = 2,
840         },
841         {
842                 .flags          = 0
843         },
844 };
845
846 static struct platform_device dm644x_serial_device = {
847         .name                   = "serial8250",
848         .id                     = PLAT8250_DEV_PLATFORM,
849         .dev                    = {
850                 .platform_data  = dm644x_serial_platform_data,
851         },
852 };
853
854 static struct davinci_soc_info davinci_soc_info_dm644x = {
855         .io_desc                = dm644x_io_desc,
856         .io_desc_num            = ARRAY_SIZE(dm644x_io_desc),
857         .jtag_id_reg            = 0x01c40028,
858         .ids                    = dm644x_ids,
859         .ids_num                = ARRAY_SIZE(dm644x_ids),
860         .cpu_clks               = dm644x_clks,
861         .psc_bases              = dm644x_psc_bases,
862         .psc_bases_num          = ARRAY_SIZE(dm644x_psc_bases),
863         .pinmux_base            = DAVINCI_SYSTEM_MODULE_BASE,
864         .pinmux_pins            = dm644x_pins,
865         .pinmux_pins_num        = ARRAY_SIZE(dm644x_pins),
866         .intc_base              = DAVINCI_ARM_INTC_BASE,
867         .intc_type              = DAVINCI_INTC_TYPE_AINTC,
868         .intc_irq_prios         = dm644x_default_priorities,
869         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
870         .timer_info             = &dm644x_timer_info,
871         .gpio_type              = GPIO_TYPE_DAVINCI,
872         .gpio_base              = DAVINCI_GPIO_BASE,
873         .gpio_num               = 71,
874         .gpio_irq               = IRQ_GPIOBNK0,
875         .serial_dev             = &dm644x_serial_device,
876         .emac_pdata             = &dm644x_emac_pdata,
877         .sram_dma               = 0x00008000,
878         .sram_len               = SZ_16K,
879 };
880
881 void __init dm644x_init_asp(struct snd_platform_data *pdata)
882 {
883         davinci_cfg_reg(DM644X_MCBSP);
884         dm644x_asp_device.dev.platform_data = pdata;
885         platform_device_register(&dm644x_asp_device);
886 }
887
888 void __init dm644x_init(void)
889 {
890         davinci_common_init(&davinci_soc_info_dm644x);
891         davinci_map_sysmod();
892 }
893
894 int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
895                                 struct vpbe_config *vpbe_cfg)
896 {
897         if (vpfe_cfg || vpbe_cfg)
898                 platform_device_register(&dm644x_vpss_device);
899
900         if (vpfe_cfg) {
901                 dm644x_vpfe_dev.dev.platform_data = vpfe_cfg;
902                 platform_device_register(&dm644x_ccdc_dev);
903                 platform_device_register(&dm644x_vpfe_dev);
904                 /* Add ccdc clock aliases */
905                 clk_add_alias("master", dm644x_ccdc_dev.name,
906                               "vpss_master", NULL);
907                 clk_add_alias("slave", dm644x_ccdc_dev.name,
908                               "vpss_slave", NULL);
909         }
910
911         if (vpbe_cfg) {
912                 dm644x_vpbe_dev.dev.platform_data = vpbe_cfg;
913                 platform_device_register(&dm644x_osd_dev);
914                 platform_device_register(&dm644x_venc_dev);
915                 platform_device_register(&dm644x_vpbe_dev);
916                 platform_device_register(&dm644x_vpbe_display);
917         }
918
919         return 0;
920 }
921
922 static int __init dm644x_init_devices(void)
923 {
924         if (!cpu_is_davinci_dm644x())
925                 return 0;
926
927         platform_device_register(&dm644x_edma_device);
928
929         platform_device_register(&dm644x_mdio_device);
930         platform_device_register(&dm644x_emac_device);
931         clk_add_alias(NULL, dev_name(&dm644x_mdio_device.dev),
932                       NULL, &dm644x_emac_device.dev);
933
934         return 0;
935 }
936 postcore_initcall(dm644x_init_devices);