arch/arm/mach-davinci/dm365.c

   1 /*
   2  * TI DaVinci DM365 chip specific setup
   3  *
   4  * Copyright (C) 2009 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #include <linux/init.h>
  16 #include <linux/clk.h>
  17 #include <linux/serial_8250.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/platform_data/edma.h>
  22
  23 #include <asm/mach/map.h>
  24
  25 #include <mach/cputype.h>
  26 #include <mach/psc.h>
  27 #include <mach/mux.h>
  28 #include <mach/irqs.h>
  29 #include <mach/time.h>
  30 #include <mach/serial.h>
  31 #include <mach/common.h>
  32 #include <linux/platform_data/keyscan-davinci.h>
  33 #include <linux/platform_data/spi-davinci.h>
  34 #include <mach/gpio-davinci.h>
  35
  36 #include "davinci.h"
  37 #include "clock.h"
  38 #include "mux.h"
  39 #include "asp.h"
  40
  41 #define DM365_REF_FREQ          24000000        /* 24 MHz on the DM365 EVM */
  42 #define DM365_RTC_BASE                  0x01c69000
  43 #define DM365_KEYSCAN_BASE              0x01c69400
  44 #define DM365_OSD_BASE                  0x01c71c00
  45 #define DM365_VENC_BASE                 0x01c71e00
  46 #define DAVINCI_DM365_VC_BASE           0x01d0c000
  47 #define DAVINCI_DMA_VC_TX               2
  48 #define DAVINCI_DMA_VC_RX               3
  49 #define DM365_EMAC_BASE                 0x01d07000
  50 #define DM365_EMAC_MDIO_BASE            (DM365_EMAC_BASE + 0x4000)
  51 #define DM365_EMAC_CNTRL_OFFSET         0x0000
  52 #define DM365_EMAC_CNTRL_MOD_OFFSET     0x3000
  53 #define DM365_EMAC_CNTRL_RAM_OFFSET     0x1000
  54 #define DM365_EMAC_CNTRL_RAM_SIZE       0x2000
  55
  56 static struct pll_data pll1_data = {
  57         .num            = 1,
  58         .phys_base      = DAVINCI_PLL1_BASE,
  59         .flags          = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
  60 };
  61
  62 static struct pll_data pll2_data = {
  63         .num            = 2,
  64         .phys_base      = DAVINCI_PLL2_BASE,
  65         .flags          = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
  66 };
  67
  68 static struct clk ref_clk = {
  69         .name           = "ref_clk",
  70         .rate           = DM365_REF_FREQ,
  71 };
  72
  73 static struct clk pll1_clk = {
  74         .name           = "pll1",
  75         .parent         = &ref_clk,
  76         .flags          = CLK_PLL,
  77         .pll_data       = &pll1_data,
  78 };
  79
  80 static struct clk pll1_aux_clk = {
  81         .name           = "pll1_aux_clk",
  82         .parent         = &pll1_clk,
  83         .flags          = CLK_PLL | PRE_PLL,
  84 };
  85
  86 static struct clk pll1_sysclkbp = {
  87         .name           = "pll1_sysclkbp",
  88         .parent         = &pll1_clk,
  89         .flags          = CLK_PLL | PRE_PLL,
  90         .div_reg        = BPDIV
  91 };
  92
  93 static struct clk clkout0_clk = {
  94         .name           = "clkout0",
  95         .parent         = &pll1_clk,
  96         .flags          = CLK_PLL | PRE_PLL,
  97 };
  98
  99 static struct clk pll1_sysclk1 = {
 100         .name           = "pll1_sysclk1",
 101         .parent         = &pll1_clk,
 102         .flags          = CLK_PLL,
 103         .div_reg        = PLLDIV1,
 104 };
 105
 106 static struct clk pll1_sysclk2 = {
 107         .name           = "pll1_sysclk2",
 108         .parent         = &pll1_clk,
 109         .flags          = CLK_PLL,
 110         .div_reg        = PLLDIV2,
 111 };
 112
 113 static struct clk pll1_sysclk3 = {
 114         .name           = "pll1_sysclk3",
 115         .parent         = &pll1_clk,
 116         .flags          = CLK_PLL,
 117         .div_reg        = PLLDIV3,
 118 };
 119
 120 static struct clk pll1_sysclk4 = {
 121         .name           = "pll1_sysclk4",
 122         .parent         = &pll1_clk,
 123         .flags          = CLK_PLL,
 124         .div_reg        = PLLDIV4,
 125 };
 126
 127 static struct clk pll1_sysclk5 = {
 128         .name           = "pll1_sysclk5",
 129         .parent         = &pll1_clk,
 130         .flags          = CLK_PLL,
 131         .div_reg        = PLLDIV5,
 132 };
 133
 134 static struct clk pll1_sysclk6 = {
 135         .name           = "pll1_sysclk6",
 136         .parent         = &pll1_clk,
 137         .flags          = CLK_PLL,
 138         .div_reg        = PLLDIV6,
 139 };
 140
 141 static struct clk pll1_sysclk7 = {
 142         .name           = "pll1_sysclk7",
 143         .parent         = &pll1_clk,
 144         .flags          = CLK_PLL,
 145         .div_reg        = PLLDIV7,
 146 };
 147
 148 static struct clk pll1_sysclk8 = {
 149         .name           = "pll1_sysclk8",
 150         .parent         = &pll1_clk,
 151         .flags          = CLK_PLL,
 152         .div_reg        = PLLDIV8,
 153 };
 154
 155 static struct clk pll1_sysclk9 = {
 156         .name           = "pll1_sysclk9",
 157         .parent         = &pll1_clk,
 158         .flags          = CLK_PLL,
 159         .div_reg        = PLLDIV9,
 160 };
 161
 162 static struct clk pll2_clk = {
 163         .name           = "pll2",
 164         .parent         = &ref_clk,
 165         .flags          = CLK_PLL,
 166         .pll_data       = &pll2_data,
 167 };
 168
 169 static struct clk pll2_aux_clk = {
 170         .name           = "pll2_aux_clk",
 171         .parent         = &pll2_clk,
 172         .flags          = CLK_PLL | PRE_PLL,
 173 };
 174
 175 static struct clk clkout1_clk = {
 176         .name           = "clkout1",
 177         .parent         = &pll2_clk,
 178         .flags          = CLK_PLL | PRE_PLL,
 179 };
 180
 181 static struct clk pll2_sysclk1 = {
 182         .name           = "pll2_sysclk1",
 183         .parent         = &pll2_clk,
 184         .flags          = CLK_PLL,
 185         .div_reg        = PLLDIV1,
 186 };
 187
 188 static struct clk pll2_sysclk2 = {
 189         .name           = "pll2_sysclk2",
 190         .parent         = &pll2_clk,
 191         .flags          = CLK_PLL,
 192         .div_reg        = PLLDIV2,
 193 };
 194
 195 static struct clk pll2_sysclk3 = {
 196         .name           = "pll2_sysclk3",
 197         .parent         = &pll2_clk,
 198         .flags          = CLK_PLL,
 199         .div_reg        = PLLDIV3,
 200 };
 201
 202 static struct clk pll2_sysclk4 = {
 203         .name           = "pll2_sysclk4",
 204         .parent         = &pll2_clk,
 205         .flags          = CLK_PLL,
 206         .div_reg        = PLLDIV4,
 207 };
 208
 209 static struct clk pll2_sysclk5 = {
 210         .name           = "pll2_sysclk5",
 211         .parent         = &pll2_clk,
 212         .flags          = CLK_PLL,
 213         .div_reg        = PLLDIV5,
 214 };
 215
 216 static struct clk pll2_sysclk6 = {
 217         .name           = "pll2_sysclk6",
 218         .parent         = &pll2_clk,
 219         .flags          = CLK_PLL,
 220         .div_reg        = PLLDIV6,
 221 };
 222
 223 static struct clk pll2_sysclk7 = {
 224         .name           = "pll2_sysclk7",
 225         .parent         = &pll2_clk,
 226         .flags          = CLK_PLL,
 227         .div_reg        = PLLDIV7,
 228 };
 229
 230 static struct clk pll2_sysclk8 = {
 231         .name           = "pll2_sysclk8",
 232         .parent         = &pll2_clk,
 233         .flags          = CLK_PLL,
 234         .div_reg        = PLLDIV8,
 235 };
 236
 237 static struct clk pll2_sysclk9 = {
 238         .name           = "pll2_sysclk9",
 239         .parent         = &pll2_clk,
 240         .flags          = CLK_PLL,
 241         .div_reg        = PLLDIV9,
 242 };
 243
 244 static struct clk vpss_dac_clk = {
 245         .name           = "vpss_dac",
 246         .parent         = &pll1_sysclk3,
 247         .lpsc           = DM365_LPSC_DAC_CLK,
 248 };
 249
 250 static struct clk vpss_master_clk = {
 251         .name           = "vpss_master",
 252         .parent         = &pll1_sysclk5,
 253         .lpsc           = DM365_LPSC_VPSSMSTR,
 254         .flags          = CLK_PSC,
 255 };
 256
 257 static struct clk vpss_slave_clk = {
 258         .name           = "vpss_slave",
 259         .parent         = &pll1_sysclk5,
 260         .lpsc           = DAVINCI_LPSC_VPSSSLV,
 261 };
 262
 263 static struct clk arm_clk = {
 264         .name           = "arm_clk",
 265         .parent         = &pll2_sysclk2,
 266         .lpsc           = DAVINCI_LPSC_ARM,
 267         .flags          = ALWAYS_ENABLED,
 268 };
 269
 270 static struct clk uart0_clk = {
 271         .name           = "uart0",
 272         .parent         = &pll1_aux_clk,
 273         .lpsc           = DAVINCI_LPSC_UART0,
 274 };
 275
 276 static struct clk uart1_clk = {
 277         .name           = "uart1",
 278         .parent         = &pll1_sysclk4,
 279         .lpsc           = DAVINCI_LPSC_UART1,
 280 };
 281
 282 static struct clk i2c_clk = {
 283         .name           = "i2c",
 284         .parent         = &pll1_aux_clk,
 285         .lpsc           = DAVINCI_LPSC_I2C,
 286 };
 287
 288 static struct clk mmcsd0_clk = {
 289         .name           = "mmcsd0",
 290         .parent         = &pll1_sysclk8,
 291         .lpsc           = DAVINCI_LPSC_MMC_SD,
 292 };
 293
 294 static struct clk mmcsd1_clk = {
 295         .name           = "mmcsd1",
 296         .parent         = &pll1_sysclk4,
 297         .lpsc           = DM365_LPSC_MMC_SD1,
 298 };
 299
 300 static struct clk spi0_clk = {
 301         .name           = "spi0",
 302         .parent         = &pll1_sysclk4,
 303         .lpsc           = DAVINCI_LPSC_SPI,
 304 };
 305
 306 static struct clk spi1_clk = {
 307         .name           = "spi1",
 308         .parent         = &pll1_sysclk4,
 309         .lpsc           = DM365_LPSC_SPI1,
 310 };
 311
 312 static struct clk spi2_clk = {
 313         .name           = "spi2",
 314         .parent         = &pll1_sysclk4,
 315         .lpsc           = DM365_LPSC_SPI2,
 316 };
 317
 318 static struct clk spi3_clk = {
 319         .name           = "spi3",
 320         .parent         = &pll1_sysclk4,
 321         .lpsc           = DM365_LPSC_SPI3,
 322 };
 323
 324 static struct clk spi4_clk = {
 325         .name           = "spi4",
 326         .parent         = &pll1_aux_clk,
 327         .lpsc           = DM365_LPSC_SPI4,
 328 };
 329
 330 static struct clk gpio_clk = {
 331         .name           = "gpio",
 332         .parent         = &pll1_sysclk4,
 333         .lpsc           = DAVINCI_LPSC_GPIO,
 334 };
 335
 336 static struct clk aemif_clk = {
 337         .name           = "aemif",
 338         .parent         = &pll1_sysclk4,
 339         .lpsc           = DAVINCI_LPSC_AEMIF,
 340 };
 341
 342 static struct clk pwm0_clk = {
 343         .name           = "pwm0",
 344         .parent         = &pll1_aux_clk,
 345         .lpsc           = DAVINCI_LPSC_PWM0,
 346 };
 347
 348 static struct clk pwm1_clk = {
 349         .name           = "pwm1",
 350         .parent         = &pll1_aux_clk,
 351         .lpsc           = DAVINCI_LPSC_PWM1,
 352 };
 353
 354 static struct clk pwm2_clk = {
 355         .name           = "pwm2",
 356         .parent         = &pll1_aux_clk,
 357         .lpsc           = DAVINCI_LPSC_PWM2,
 358 };
 359
 360 static struct clk pwm3_clk = {
 361         .name           = "pwm3",
 362         .parent         = &ref_clk,
 363         .lpsc           = DM365_LPSC_PWM3,
 364 };
 365
 366 static struct clk timer0_clk = {
 367         .name           = "timer0",
 368         .parent         = &pll1_aux_clk,
 369         .lpsc           = DAVINCI_LPSC_TIMER0,
 370 };
 371
 372 static struct clk timer1_clk = {
 373         .name           = "timer1",
 374         .parent         = &pll1_aux_clk,
 375         .lpsc           = DAVINCI_LPSC_TIMER1,
 376 };
 377
 378 static struct clk timer2_clk = {
 379         .name           = "timer2",
 380         .parent         = &pll1_aux_clk,
 381         .lpsc           = DAVINCI_LPSC_TIMER2,
 382         .usecount       = 1,
 383 };
 384
 385 static struct clk timer3_clk = {
 386         .name           = "timer3",
 387         .parent         = &pll1_aux_clk,
 388         .lpsc           = DM365_LPSC_TIMER3,
 389 };
 390
 391 static struct clk usb_clk = {
 392         .name           = "usb",
 393         .parent         = &pll1_aux_clk,
 394         .lpsc           = DAVINCI_LPSC_USB,
 395 };
 396
 397 static struct clk emac_clk = {
 398         .name           = "emac",
 399         .parent         = &pll1_sysclk4,
 400         .lpsc           = DM365_LPSC_EMAC,
 401 };
 402
 403 static struct clk voicecodec_clk = {
 404         .name           = "voice_codec",
 405         .parent         = &pll2_sysclk4,
 406         .lpsc           = DM365_LPSC_VOICE_CODEC,
 407 };
 408
 409 static struct clk asp0_clk = {
 410         .name           = "asp0",
 411         .parent         = &pll1_sysclk4,
 412         .lpsc           = DM365_LPSC_McBSP1,
 413 };
 414
 415 static struct clk rto_clk = {
 416         .name           = "rto",
 417         .parent         = &pll1_sysclk4,
 418         .lpsc           = DM365_LPSC_RTO,
 419 };
 420
 421 static struct clk mjcp_clk = {
 422         .name           = "mjcp",
 423         .parent         = &pll1_sysclk3,
 424         .lpsc           = DM365_LPSC_MJCP,
 425 };
 426
 427 static struct clk_lookup dm365_clks[] = {
 428         CLK(NULL, "ref", &ref_clk),
 429         CLK(NULL, "pll1", &pll1_clk),
 430         CLK(NULL, "pll1_aux", &pll1_aux_clk),
 431         CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
 432         CLK(NULL, "clkout0", &clkout0_clk),
 433         CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
 434         CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
 435         CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
 436         CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
 437         CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
 438         CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
 439         CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
 440         CLK(NULL, "pll1_sysclk8", &pll1_sysclk8),
 441         CLK(NULL, "pll1_sysclk9", &pll1_sysclk9),
 442         CLK(NULL, "pll2", &pll2_clk),
 443         CLK(NULL, "pll2_aux", &pll2_aux_clk),
 444         CLK(NULL, "clkout1", &clkout1_clk),
 445         CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
 446         CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
 447         CLK(NULL, "pll2_sysclk3", &pll2_sysclk3),
 448         CLK(NULL, "pll2_sysclk4", &pll2_sysclk4),
 449         CLK(NULL, "pll2_sysclk5", &pll2_sysclk5),
 450         CLK(NULL, "pll2_sysclk6", &pll2_sysclk6),
 451         CLK(NULL, "pll2_sysclk7", &pll2_sysclk7),
 452         CLK(NULL, "pll2_sysclk8", &pll2_sysclk8),
 453         CLK(NULL, "pll2_sysclk9", &pll2_sysclk9),
 454         CLK(NULL, "vpss_dac", &vpss_dac_clk),
 455         CLK("vpss", "master", &vpss_master_clk),
 456         CLK("vpss", "slave", &vpss_slave_clk),
 457         CLK(NULL, "arm", &arm_clk),
 458         CLK(NULL, "uart0", &uart0_clk),
 459         CLK(NULL, "uart1", &uart1_clk),
 460         CLK("i2c_davinci.1", NULL, &i2c_clk),
 461         CLK("da830-mmc.0", NULL, &mmcsd0_clk),
 462         CLK("da830-mmc.1", NULL, &mmcsd1_clk),
 463         CLK("spi_davinci.0", NULL, &spi0_clk),
 464         CLK("spi_davinci.1", NULL, &spi1_clk),
 465         CLK("spi_davinci.2", NULL, &spi2_clk),
 466         CLK("spi_davinci.3", NULL, &spi3_clk),
 467         CLK("spi_davinci.4", NULL, &spi4_clk),
 468         CLK(NULL, "gpio", &gpio_clk),
 469         CLK(NULL, "aemif", &aemif_clk),
 470         CLK(NULL, "pwm0", &pwm0_clk),
 471         CLK(NULL, "pwm1", &pwm1_clk),
 472         CLK(NULL, "pwm2", &pwm2_clk),
 473         CLK(NULL, "pwm3", &pwm3_clk),
 474         CLK(NULL, "timer0", &timer0_clk),
 475         CLK(NULL, "timer1", &timer1_clk),
 476         CLK("watchdog", NULL, &timer2_clk),
 477         CLK(NULL, "timer3", &timer3_clk),
 478         CLK(NULL, "usb", &usb_clk),
 479         CLK("davinci_emac.1", NULL, &emac_clk),
 480         CLK("davinci_voicecodec", NULL, &voicecodec_clk),
 481         CLK("davinci-mcbsp", NULL, &asp0_clk),
 482         CLK(NULL, "rto", &rto_clk),
 483         CLK(NULL, "mjcp", &mjcp_clk),
 484         CLK(NULL, NULL, NULL),
 485 };
 486
 487 /*----------------------------------------------------------------------*/
 488
 489 #define INTMUX          0x18
 490 #define EVTMUX          0x1c
 491
 492
 493 static const struct mux_config dm365_pins[] = {
 494 #ifdef CONFIG_DAVINCI_MUX
 495 MUX_CFG(DM365,  MMCSD0,         0,   24,     1,   0,     false)
 496
 497 MUX_CFG(DM365,  SD1_CLK,        0,   16,    3,    1,     false)
 498 MUX_CFG(DM365,  SD1_CMD,        4,   30,    3,    1,     false)
 499 MUX_CFG(DM365,  SD1_DATA3,      4,   28,    3,    1,     false)
 500 MUX_CFG(DM365,  SD1_DATA2,      4,   26,    3,    1,     false)
 501 MUX_CFG(DM365,  SD1_DATA1,      4,   24,    3,    1,     false)
 502 MUX_CFG(DM365,  SD1_DATA0,      4,   22,    3,    1,     false)
 503
 504 MUX_CFG(DM365,  I2C_SDA,        3,   23,    3,    2,     false)
 505 MUX_CFG(DM365,  I2C_SCL,        3,   21,    3,    2,     false)
 506
 507 MUX_CFG(DM365,  AEMIF_AR_A14,   2,   0,     3,    1,     false)
 508 MUX_CFG(DM365,  AEMIF_AR_BA0,   2,   0,     3,    2,     false)
 509 MUX_CFG(DM365,  AEMIF_A3,       2,   2,     3,    1,     false)
 510 MUX_CFG(DM365,  AEMIF_A7,       2,   4,     3,    1,     false)
 511 MUX_CFG(DM365,  AEMIF_D15_8,    2,   6,     1,    1,     false)
 512 MUX_CFG(DM365,  AEMIF_CE0,      2,   7,     1,    0,     false)
 513 MUX_CFG(DM365,  AEMIF_CE1,      2,   8,     1,    0,     false)
 514 MUX_CFG(DM365,  AEMIF_WE_OE,    2,   9,     1,    0,     false)
 515
 516 MUX_CFG(DM365,  MCBSP0_BDX,     0,   23,    1,    1,     false)
 517 MUX_CFG(DM365,  MCBSP0_X,       0,   22,    1,    1,     false)
 518 MUX_CFG(DM365,  MCBSP0_BFSX,    0,   21,    1,    1,     false)
 519 MUX_CFG(DM365,  MCBSP0_BDR,     0,   20,    1,    1,     false)
 520 MUX_CFG(DM365,  MCBSP0_R,       0,   19,    1,    1,     false)
 521 MUX_CFG(DM365,  MCBSP0_BFSR,    0,   18,    1,    1,     false)
 522
 523 MUX_CFG(DM365,  SPI0_SCLK,      3,   28,    1,    1,     false)
 524 MUX_CFG(DM365,  SPI0_SDI,       3,   26,    3,    1,     false)
 525 MUX_CFG(DM365,  SPI0_SDO,       3,   25,    1,    1,     false)
 526 MUX_CFG(DM365,  SPI0_SDENA0,    3,   29,    3,    1,     false)
 527 MUX_CFG(DM365,  SPI0_SDENA1,    3,   26,    3,    2,     false)
 528
 529 MUX_CFG(DM365,  UART0_RXD,      3,   20,    1,    1,     false)
 530 MUX_CFG(DM365,  UART0_TXD,      3,   19,    1,    1,     false)
 531 MUX_CFG(DM365,  UART1_RXD,      3,   17,    3,    2,     false)
 532 MUX_CFG(DM365,  UART1_TXD,      3,   15,    3,    2,     false)
 533 MUX_CFG(DM365,  UART1_RTS,      3,   23,    3,    1,     false)
 534 MUX_CFG(DM365,  UART1_CTS,      3,   21,    3,    1,     false)
 535
 536 MUX_CFG(DM365,  EMAC_TX_EN,     3,   17,    3,    1,     false)
 537 MUX_CFG(DM365,  EMAC_TX_CLK,    3,   15,    3,    1,     false)
 538 MUX_CFG(DM365,  EMAC_COL,       3,   14,    1,    1,     false)
 539 MUX_CFG(DM365,  EMAC_TXD3,      3,   13,    1,    1,     false)
 540 MUX_CFG(DM365,  EMAC_TXD2,      3,   12,    1,    1,     false)
 541 MUX_CFG(DM365,  EMAC_TXD1,      3,   11,    1,    1,     false)
 542 MUX_CFG(DM365,  EMAC_TXD0,      3,   10,    1,    1,     false)
 543 MUX_CFG(DM365,  EMAC_RXD3,      3,   9,     1,    1,     false)
 544 MUX_CFG(DM365,  EMAC_RXD2,      3,   8,     1,    1,     false)
 545 MUX_CFG(DM365,  EMAC_RXD1,      3,   7,     1,    1,     false)
 546 MUX_CFG(DM365,  EMAC_RXD0,      3,   6,     1,    1,     false)
 547 MUX_CFG(DM365,  EMAC_RX_CLK,    3,   5,     1,    1,     false)
 548 MUX_CFG(DM365,  EMAC_RX_DV,     3,   4,     1,    1,     false)
 549 MUX_CFG(DM365,  EMAC_RX_ER,     3,   3,     1,    1,     false)
 550 MUX_CFG(DM365,  EMAC_CRS,       3,   2,     1,    1,     false)
 551 MUX_CFG(DM365,  EMAC_MDIO,      3,   1,     1,    1,     false)
 552 MUX_CFG(DM365,  EMAC_MDCLK,     3,   0,     1,    1,     false)
 553
 554 MUX_CFG(DM365,  KEYSCAN,        2,   0,     0x3f, 0x3f,  false)
 555
 556 MUX_CFG(DM365,  PWM0,           1,   0,     3,    2,     false)
 557 MUX_CFG(DM365,  PWM0_G23,       3,   26,    3,    3,     false)
 558 MUX_CFG(DM365,  PWM1,           1,   2,     3,    2,     false)
 559 MUX_CFG(DM365,  PWM1_G25,       3,   29,    3,    2,     false)
 560 MUX_CFG(DM365,  PWM2_G87,       1,   10,    3,    2,     false)
 561 MUX_CFG(DM365,  PWM2_G88,       1,   8,     3,    2,     false)
 562 MUX_CFG(DM365,  PWM2_G89,       1,   6,     3,    2,     false)
 563 MUX_CFG(DM365,  PWM2_G90,       1,   4,     3,    2,     false)
 564 MUX_CFG(DM365,  PWM3_G80,       1,   20,    3,    3,     false)
 565 MUX_CFG(DM365,  PWM3_G81,       1,   18,    3,    3,     false)
 566 MUX_CFG(DM365,  PWM3_G85,       1,   14,    3,    2,     false)
 567 MUX_CFG(DM365,  PWM3_G86,       1,   12,    3,    2,     false)
 568
 569 MUX_CFG(DM365,  SPI1_SCLK,      4,   2,     3,    1,     false)
 570 MUX_CFG(DM365,  SPI1_SDI,       3,   31,    1,    1,     false)
 571 MUX_CFG(DM365,  SPI1_SDO,       4,   0,     3,    1,     false)
 572 MUX_CFG(DM365,  SPI1_SDENA0,    4,   4,     3,    1,     false)
 573 MUX_CFG(DM365,  SPI1_SDENA1,    4,   0,     3,    2,     false)
 574
 575 MUX_CFG(DM365,  SPI2_SCLK,      4,   10,    3,    1,     false)
 576 MUX_CFG(DM365,  SPI2_SDI,       4,   6,     3,    1,     false)
 577 MUX_CFG(DM365,  SPI2_SDO,       4,   8,     3,    1,     false)
 578 MUX_CFG(DM365,  SPI2_SDENA0,    4,   12,    3,    1,     false)
 579 MUX_CFG(DM365,  SPI2_SDENA1,    4,   8,     3,    2,     false)
 580
 581 MUX_CFG(DM365,  SPI3_SCLK,      0,   0,     3,    2,     false)
 582 MUX_CFG(DM365,  SPI3_SDI,       0,   2,     3,    2,     false)
 583 MUX_CFG(DM365,  SPI3_SDO,       0,   6,     3,    2,     false)
 584 MUX_CFG(DM365,  SPI3_SDENA0,    0,   4,     3,    2,     false)
 585 MUX_CFG(DM365,  SPI3_SDENA1,    0,   6,     3,    3,     false)
 586
 587 MUX_CFG(DM365,  SPI4_SCLK,      4,   18,    3,    1,     false)
 588 MUX_CFG(DM365,  SPI4_SDI,       4,   14,    3,    1,     false)
 589 MUX_CFG(DM365,  SPI4_SDO,       4,   16,    3,    1,     false)
 590 MUX_CFG(DM365,  SPI4_SDENA0,    4,   20,    3,    1,     false)
 591 MUX_CFG(DM365,  SPI4_SDENA1,    4,   16,    3,    2,     false)
 592
 593 MUX_CFG(DM365,  CLKOUT0,        4,   20,    3,    3,     false)
 594 MUX_CFG(DM365,  CLKOUT1,        4,   16,    3,    3,     false)
 595 MUX_CFG(DM365,  CLKOUT2,        4,   8,     3,    3,     false)
 596
 597 MUX_CFG(DM365,  GPIO20,         3,   21,    3,    0,     false)
 598 MUX_CFG(DM365,  GPIO30,         4,   6,     3,    0,     false)
 599 MUX_CFG(DM365,  GPIO31,         4,   8,     3,    0,     false)
 600 MUX_CFG(DM365,  GPIO32,         4,   10,    3,    0,     false)
 601 MUX_CFG(DM365,  GPIO33,         4,   12,    3,    0,     false)
 602 MUX_CFG(DM365,  GPIO40,         4,   26,    3,    0,     false)
 603 MUX_CFG(DM365,  GPIO64_57,      2,   6,     1,    0,     false)
 604
 605 MUX_CFG(DM365,  VOUT_FIELD,     1,   18,    3,    1,     false)
 606 MUX_CFG(DM365,  VOUT_FIELD_G81, 1,   18,    3,    0,     false)
 607 MUX_CFG(DM365,  VOUT_HVSYNC,    1,   16,    1,    0,     false)
 608 MUX_CFG(DM365,  VOUT_COUTL_EN,  1,   0,     0xff, 0x55,  false)
 609 MUX_CFG(DM365,  VOUT_COUTH_EN,  1,   8,     0xff, 0x55,  false)
 610 MUX_CFG(DM365,  VIN_CAM_WEN,    0,   14,    3,    0,     false)
 611 MUX_CFG(DM365,  VIN_CAM_VD,     0,   13,    1,    0,     false)
 612 MUX_CFG(DM365,  VIN_CAM_HD,     0,   12,    1,    0,     false)
 613 MUX_CFG(DM365,  VIN_YIN4_7_EN,  0,   0,     0xff, 0,     false)
 614 MUX_CFG(DM365,  VIN_YIN0_3_EN,  0,   8,     0xf,  0,     false)
 615
 616 INT_CFG(DM365,  INT_EDMA_CC,         2,     1,    1,     false)
 617 INT_CFG(DM365,  INT_EDMA_TC0_ERR,    3,     1,    1,     false)
 618 INT_CFG(DM365,  INT_EDMA_TC1_ERR,    4,     1,    1,     false)
 619 INT_CFG(DM365,  INT_EDMA_TC2_ERR,    22,    1,    1,     false)
 620 INT_CFG(DM365,  INT_EDMA_TC3_ERR,    23,    1,    1,     false)
 621 INT_CFG(DM365,  INT_PRTCSS,          10,    1,    1,     false)
 622 INT_CFG(DM365,  INT_EMAC_RXTHRESH,   14,    1,    1,     false)
 623 INT_CFG(DM365,  INT_EMAC_RXPULSE,    15,    1,    1,     false)
 624 INT_CFG(DM365,  INT_EMAC_TXPULSE,    16,    1,    1,     false)
 625 INT_CFG(DM365,  INT_EMAC_MISCPULSE,  17,    1,    1,     false)
 626 INT_CFG(DM365,  INT_IMX0_ENABLE,     0,     1,    0,     false)
 627 INT_CFG(DM365,  INT_IMX0_DISABLE,    0,     1,    1,     false)
 628 INT_CFG(DM365,  INT_HDVICP_ENABLE,   0,     1,    1,     false)
 629 INT_CFG(DM365,  INT_HDVICP_DISABLE,  0,     1,    0,     false)
 630 INT_CFG(DM365,  INT_IMX1_ENABLE,     24,    1,    1,     false)
 631 INT_CFG(DM365,  INT_IMX1_DISABLE,    24,    1,    0,     false)
 632 INT_CFG(DM365,  INT_NSF_ENABLE,      25,    1,    1,     false)
 633 INT_CFG(DM365,  INT_NSF_DISABLE,     25,    1,    0,     false)
 634
 635 EVT_CFG(DM365,  EVT2_ASP_TX,         0,     1,    0,     false)
 636 EVT_CFG(DM365,  EVT3_ASP_RX,         1,     1,    0,     false)
 637 EVT_CFG(DM365,  EVT2_VC_TX,          0,     1,    1,     false)
 638 EVT_CFG(DM365,  EVT3_VC_RX,          1,     1,    1,     false)
 639 #endif
 640 };
 641
 642 static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
 643
 644 static struct davinci_spi_platform_data dm365_spi0_pdata = {
 645         .version        = SPI_VERSION_1,
 646         .num_chipselect = 2,
 647         .dma_event_q    = EVENTQ_3,
 648 };
 649
 650 static struct resource dm365_spi0_resources[] = {
 651         {
 652                 .start = 0x01c66000,
 653                 .end   = 0x01c667ff,
 654                 .flags = IORESOURCE_MEM,
 655         },
 656         {
 657                 .start = IRQ_DM365_SPIINT0_0,
 658                 .flags = IORESOURCE_IRQ,
 659         },
 660         {
 661                 .start = 17,
 662                 .flags = IORESOURCE_DMA,
 663         },
 664         {
 665                 .start = 16,
 666                 .flags = IORESOURCE_DMA,
 667         },
 668 };
 669
 670 static struct platform_device dm365_spi0_device = {
 671         .name = "spi_davinci",
 672         .id = 0,
 673         .dev = {
 674                 .dma_mask = &dm365_spi0_dma_mask,
 675                 .coherent_dma_mask = DMA_BIT_MASK(32),
 676                 .platform_data = &dm365_spi0_pdata,
 677         },
 678         .num_resources = ARRAY_SIZE(dm365_spi0_resources),
 679         .resource = dm365_spi0_resources,
 680 };
 681
 682 void __init dm365_init_spi0(unsigned chipselect_mask,
 683                 const struct spi_board_info *info, unsigned len)
 684 {
 685         davinci_cfg_reg(DM365_SPI0_SCLK);
 686         davinci_cfg_reg(DM365_SPI0_SDI);
 687         davinci_cfg_reg(DM365_SPI0_SDO);
 688
 689         /* not all slaves will be wired up */
 690         if (chipselect_mask & BIT(0))
 691                 davinci_cfg_reg(DM365_SPI0_SDENA0);
 692         if (chipselect_mask & BIT(1))
 693                 davinci_cfg_reg(DM365_SPI0_SDENA1);
 694
 695         spi_register_board_info(info, len);
 696
 697         platform_device_register(&dm365_spi0_device);
 698 }
 699
 700 static struct emac_platform_data dm365_emac_pdata = {
 701         .ctrl_reg_offset        = DM365_EMAC_CNTRL_OFFSET,
 702         .ctrl_mod_reg_offset    = DM365_EMAC_CNTRL_MOD_OFFSET,
 703         .ctrl_ram_offset        = DM365_EMAC_CNTRL_RAM_OFFSET,
 704         .ctrl_ram_size          = DM365_EMAC_CNTRL_RAM_SIZE,
 705         .version                = EMAC_VERSION_2,
 706 };
 707
 708 static struct resource dm365_emac_resources[] = {
 709         {
 710                 .start  = DM365_EMAC_BASE,
 711                 .end    = DM365_EMAC_BASE + SZ_16K - 1,
 712                 .flags  = IORESOURCE_MEM,
 713         },
 714         {
 715                 .start  = IRQ_DM365_EMAC_RXTHRESH,
 716                 .end    = IRQ_DM365_EMAC_RXTHRESH,
 717                 .flags  = IORESOURCE_IRQ,
 718         },
 719         {
 720                 .start  = IRQ_DM365_EMAC_RXPULSE,
 721                 .end    = IRQ_DM365_EMAC_RXPULSE,
 722                 .flags  = IORESOURCE_IRQ,
 723         },
 724         {
 725                 .start  = IRQ_DM365_EMAC_TXPULSE,
 726                 .end    = IRQ_DM365_EMAC_TXPULSE,
 727                 .flags  = IORESOURCE_IRQ,
 728         },
 729         {
 730                 .start  = IRQ_DM365_EMAC_MISCPULSE,
 731                 .end    = IRQ_DM365_EMAC_MISCPULSE,
 732                 .flags  = IORESOURCE_IRQ,
 733         },
 734 };
 735
 736 static struct platform_device dm365_emac_device = {
 737         .name           = "davinci_emac",
 738         .id             = 1,
 739         .dev = {
 740                 .platform_data  = &dm365_emac_pdata,
 741         },
 742         .num_resources  = ARRAY_SIZE(dm365_emac_resources),
 743         .resource       = dm365_emac_resources,
 744 };
 745
 746 static struct resource dm365_mdio_resources[] = {
 747         {
 748                 .start  = DM365_EMAC_MDIO_BASE,
 749                 .end    = DM365_EMAC_MDIO_BASE + SZ_4K - 1,
 750                 .flags  = IORESOURCE_MEM,
 751         },
 752 };
 753
 754 static struct platform_device dm365_mdio_device = {
 755         .name           = "davinci_mdio",
 756         .id             = 0,
 757         .num_resources  = ARRAY_SIZE(dm365_mdio_resources),
 758         .resource       = dm365_mdio_resources,
 759 };
 760
 761 static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 762         [IRQ_VDINT0]                    = 2,
 763         [IRQ_VDINT1]                    = 6,
 764         [IRQ_VDINT2]                    = 6,
 765         [IRQ_HISTINT]                   = 6,
 766         [IRQ_H3AINT]                    = 6,
 767         [IRQ_PRVUINT]                   = 6,
 768         [IRQ_RSZINT]                    = 6,
 769         [IRQ_DM365_INSFINT]             = 7,
 770         [IRQ_VENCINT]                   = 6,
 771         [IRQ_ASQINT]                    = 6,
 772         [IRQ_IMXINT]                    = 6,
 773         [IRQ_DM365_IMCOPINT]            = 4,
 774         [IRQ_USBINT]                    = 4,
 775         [IRQ_DM365_RTOINT]              = 7,
 776         [IRQ_DM365_TINT5]               = 7,
 777         [IRQ_DM365_TINT6]               = 5,
 778         [IRQ_CCINT0]                    = 5,
 779         [IRQ_CCERRINT]                  = 5,
 780         [IRQ_TCERRINT0]                 = 5,
 781         [IRQ_TCERRINT]                  = 7,
 782         [IRQ_PSCIN]                     = 4,
 783         [IRQ_DM365_SPINT2_1]            = 7,
 784         [IRQ_DM365_TINT7]               = 7,
 785         [IRQ_DM365_SDIOINT0]            = 7,
 786         [IRQ_MBXINT]                    = 7,
 787         [IRQ_MBRINT]                    = 7,
 788         [IRQ_MMCINT]                    = 7,
 789         [IRQ_DM365_MMCINT1]             = 7,
 790         [IRQ_DM365_PWMINT3]             = 7,
 791         [IRQ_AEMIFINT]                  = 2,
 792         [IRQ_DM365_SDIOINT1]            = 2,
 793         [IRQ_TINT0_TINT12]              = 7,
 794         [IRQ_TINT0_TINT34]              = 7,
 795         [IRQ_TINT1_TINT12]              = 7,
 796         [IRQ_TINT1_TINT34]              = 7,
 797         [IRQ_PWMINT0]                   = 7,
 798         [IRQ_PWMINT1]                   = 3,
 799         [IRQ_PWMINT2]                   = 3,
 800         [IRQ_I2C]                       = 3,
 801         [IRQ_UARTINT0]                  = 3,
 802         [IRQ_UARTINT1]                  = 3,
 803         [IRQ_DM365_RTCINT]              = 3,
 804         [IRQ_DM365_SPIINT0_0]           = 3,
 805         [IRQ_DM365_SPIINT3_0]           = 3,
 806         [IRQ_DM365_GPIO0]               = 3,
 807         [IRQ_DM365_GPIO1]               = 7,
 808         [IRQ_DM365_GPIO2]               = 4,
 809         [IRQ_DM365_GPIO3]               = 4,
 810         [IRQ_DM365_GPIO4]               = 7,
 811         [IRQ_DM365_GPIO5]               = 7,
 812         [IRQ_DM365_GPIO6]               = 7,
 813         [IRQ_DM365_GPIO7]               = 7,
 814         [IRQ_DM365_EMAC_RXTHRESH]       = 7,
 815         [IRQ_DM365_EMAC_RXPULSE]        = 7,
 816         [IRQ_DM365_EMAC_TXPULSE]        = 7,
 817         [IRQ_DM365_EMAC_MISCPULSE]      = 7,
 818         [IRQ_DM365_GPIO12]              = 7,
 819         [IRQ_DM365_GPIO13]              = 7,
 820         [IRQ_DM365_GPIO14]              = 7,
 821         [IRQ_DM365_GPIO15]              = 7,
 822         [IRQ_DM365_KEYINT]              = 7,
 823         [IRQ_DM365_TCERRINT2]           = 7,
 824         [IRQ_DM365_TCERRINT3]           = 7,
 825         [IRQ_DM365_EMUINT]              = 7,
 826 };
 827
 828 /* Four Transfer Controllers on DM365 */
 829 static s8
 830 dm365_queue_tc_mapping[][2] = {
 831         /* {event queue no, TC no} */
 832         {0, 0},
 833         {1, 1},
 834         {2, 2},
 835         {3, 3},
 836         {-1, -1},
 837 };
 838
 839 static s8
 840 dm365_queue_priority_mapping[][2] = {
 841         /* {event queue no, Priority} */
 842         {0, 7},
 843         {1, 7},
 844         {2, 7},
 845         {3, 0},
 846         {-1, -1},
 847 };
 848
 849 static struct edma_soc_info edma_cc0_info = {
 850         .n_channel              = 64,
 851         .n_region               = 4,
 852         .n_slot                 = 256,
 853         .n_tc                   = 4,
 854         .n_cc                   = 1,
 855         .queue_tc_mapping       = dm365_queue_tc_mapping,
 856         .queue_priority_mapping = dm365_queue_priority_mapping,
 857         .default_queue          = EVENTQ_3,
 858 };
 859
 860 static struct edma_soc_info *dm365_edma_info[EDMA_MAX_CC] = {
 861         &edma_cc0_info,
 862 };
 863
 864 static struct resource edma_resources[] = {
 865         {
 866                 .name   = "edma_cc0",
 867                 .start  = 0x01c00000,
 868                 .end    = 0x01c00000 + SZ_64K - 1,
 869                 .flags  = IORESOURCE_MEM,
 870         },
 871         {
 872                 .name   = "edma_tc0",
 873                 .start  = 0x01c10000,
 874                 .end    = 0x01c10000 + SZ_1K - 1,
 875                 .flags  = IORESOURCE_MEM,
 876         },
 877         {
 878                 .name   = "edma_tc1",
 879                 .start  = 0x01c10400,
 880                 .end    = 0x01c10400 + SZ_1K - 1,
 881                 .flags  = IORESOURCE_MEM,
 882         },
 883         {
 884                 .name   = "edma_tc2",
 885                 .start  = 0x01c10800,
 886                 .end    = 0x01c10800 + SZ_1K - 1,
 887                 .flags  = IORESOURCE_MEM,
 888         },
 889         {
 890                 .name   = "edma_tc3",
 891                 .start  = 0x01c10c00,
 892                 .end    = 0x01c10c00 + SZ_1K - 1,
 893                 .flags  = IORESOURCE_MEM,
 894         },
 895         {
 896                 .name   = "edma0",
 897                 .start  = IRQ_CCINT0,
 898                 .flags  = IORESOURCE_IRQ,
 899         },
 900         {
 901                 .name   = "edma0_err",
 902                 .start  = IRQ_CCERRINT,
 903                 .flags  = IORESOURCE_IRQ,
 904         },
 905         /* not using TC*_ERR */
 906 };
 907
 908 static struct platform_device dm365_edma_device = {
 909         .name                   = "edma",
 910         .id                     = 0,
 911         .dev.platform_data      = dm365_edma_info,
 912         .num_resources          = ARRAY_SIZE(edma_resources),
 913         .resource               = edma_resources,
 914 };
 915
 916 static struct resource dm365_asp_resources[] = {
 917         {
 918                 .start  = DAVINCI_DM365_ASP0_BASE,
 919                 .end    = DAVINCI_DM365_ASP0_BASE + SZ_8K - 1,
 920                 .flags  = IORESOURCE_MEM,
 921         },
 922         {
 923                 .start  = DAVINCI_DMA_ASP0_TX,
 924                 .end    = DAVINCI_DMA_ASP0_TX,
 925                 .flags  = IORESOURCE_DMA,
 926         },
 927         {
 928                 .start  = DAVINCI_DMA_ASP0_RX,
 929                 .end    = DAVINCI_DMA_ASP0_RX,
 930                 .flags  = IORESOURCE_DMA,
 931         },
 932 };
 933
 934 static struct platform_device dm365_asp_device = {
 935         .name           = "davinci-mcbsp",
 936         .id             = -1,
 937         .num_resources  = ARRAY_SIZE(dm365_asp_resources),
 938         .resource       = dm365_asp_resources,
 939 };
 940
 941 static struct resource dm365_vc_resources[] = {
 942         {
 943                 .start  = DAVINCI_DM365_VC_BASE,
 944                 .end    = DAVINCI_DM365_VC_BASE + SZ_1K - 1,
 945                 .flags  = IORESOURCE_MEM,
 946         },
 947         {
 948                 .start  = DAVINCI_DMA_VC_TX,
 949                 .end    = DAVINCI_DMA_VC_TX,
 950                 .flags  = IORESOURCE_DMA,
 951         },
 952         {
 953                 .start  = DAVINCI_DMA_VC_RX,
 954                 .end    = DAVINCI_DMA_VC_RX,
 955                 .flags  = IORESOURCE_DMA,
 956         },
 957 };
 958
 959 static struct platform_device dm365_vc_device = {
 960         .name           = "davinci_voicecodec",
 961         .id             = -1,
 962         .num_resources  = ARRAY_SIZE(dm365_vc_resources),
 963         .resource       = dm365_vc_resources,
 964 };
 965
 966 static struct resource dm365_rtc_resources[] = {
 967         {
 968                 .start = DM365_RTC_BASE,
 969                 .end = DM365_RTC_BASE + SZ_1K - 1,
 970                 .flags = IORESOURCE_MEM,
 971         },
 972         {
 973                 .start = IRQ_DM365_RTCINT,
 974                 .flags = IORESOURCE_IRQ,
 975         },
 976 };
 977
 978 static struct platform_device dm365_rtc_device = {
 979         .name = "rtc_davinci",
 980         .id = 0,
 981         .num_resources = ARRAY_SIZE(dm365_rtc_resources),
 982         .resource = dm365_rtc_resources,
 983 };
 984
 985 static struct map_desc dm365_io_desc[] = {
 986         {
 987                 .virtual        = IO_VIRT,
 988                 .pfn            = __phys_to_pfn(IO_PHYS),
 989                 .length         = IO_SIZE,
 990                 .type           = MT_DEVICE
 991         },
 992 };
 993
 994 static struct resource dm365_ks_resources[] = {
 995         {
 996                 /* registers */
 997                 .start = DM365_KEYSCAN_BASE,
 998                 .end = DM365_KEYSCAN_BASE + SZ_1K - 1,
 999                 .flags = IORESOURCE_MEM,
1000         },
1001         {
1002                 /* interrupt */
1003                 .start = IRQ_DM365_KEYINT,
1004                 .end = IRQ_DM365_KEYINT,
1005                 .flags = IORESOURCE_IRQ,
1006         },
1007 };
1008
1009 static struct platform_device dm365_ks_device = {
1010         .name           = "davinci_keyscan",
1011         .id             = 0,
1012         .num_resources  = ARRAY_SIZE(dm365_ks_resources),
1013         .resource       = dm365_ks_resources,
1014 };
1015
1016 /* Contents of JTAG ID register used to identify exact cpu type */
1017 static struct davinci_id dm365_ids[] = {
1018         {
1019                 .variant        = 0x0,
1020                 .part_no        = 0xb83e,
1021                 .manufacturer   = 0x017,
1022                 .cpu_id         = DAVINCI_CPU_ID_DM365,
1023                 .name           = "dm365_rev1.1",
1024         },
1025         {
1026                 .variant        = 0x8,
1027                 .part_no        = 0xb83e,
1028                 .manufacturer   = 0x017,
1029                 .cpu_id         = DAVINCI_CPU_ID_DM365,
1030                 .name           = "dm365_rev1.2",
1031         },
1032 };
1033
1034 static u32 dm365_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
1035
1036 static struct davinci_timer_info dm365_timer_info = {
1037         .timers         = davinci_timer_instance,
1038         .clockevent_id  = T0_BOT,
1039         .clocksource_id = T0_TOP,
1040 };
1041
1042 #define DM365_UART1_BASE        (IO_PHYS + 0x106000)
1043
1044 static struct plat_serial8250_port dm365_serial_platform_data[] = {
1045         {
1046                 .mapbase        = DAVINCI_UART0_BASE,
1047                 .irq            = IRQ_UARTINT0,
1048                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
1049                                   UPF_IOREMAP,
1050                 .iotype         = UPIO_MEM,
1051                 .regshift       = 2,
1052         },
1053         {
1054                 .mapbase        = DM365_UART1_BASE,
1055                 .irq            = IRQ_UARTINT1,
1056                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
1057                                   UPF_IOREMAP,
1058                 .iotype         = UPIO_MEM,
1059                 .regshift       = 2,
1060         },
1061         {
1062                 .flags          = 0
1063         },
1064 };
1065
1066 static struct platform_device dm365_serial_device = {
1067         .name                   = "serial8250",
1068         .id                     = PLAT8250_DEV_PLATFORM,
1069         .dev                    = {
1070                 .platform_data  = dm365_serial_platform_data,
1071         },
1072 };
1073
1074 static struct davinci_soc_info davinci_soc_info_dm365 = {
1075         .io_desc                = dm365_io_desc,
1076         .io_desc_num            = ARRAY_SIZE(dm365_io_desc),
1077         .jtag_id_reg            = 0x01c40028,
1078         .ids                    = dm365_ids,
1079         .ids_num                = ARRAY_SIZE(dm365_ids),
1080         .cpu_clks               = dm365_clks,
1081         .psc_bases              = dm365_psc_bases,
1082         .psc_bases_num          = ARRAY_SIZE(dm365_psc_bases),
1083         .pinmux_base            = DAVINCI_SYSTEM_MODULE_BASE,
1084         .pinmux_pins            = dm365_pins,
1085         .pinmux_pins_num        = ARRAY_SIZE(dm365_pins),
1086         .intc_base              = DAVINCI_ARM_INTC_BASE,
1087         .intc_type              = DAVINCI_INTC_TYPE_AINTC,
1088         .intc_irq_prios         = dm365_default_priorities,
1089         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
1090         .timer_info             = &dm365_timer_info,
1091         .gpio_type              = GPIO_TYPE_DAVINCI,
1092         .gpio_base              = DAVINCI_GPIO_BASE,
1093         .gpio_num               = 104,
1094         .gpio_irq               = IRQ_DM365_GPIO0,
1095         .gpio_unbanked          = 8,    /* really 16 ... skip muxed GPIOs */
1096         .serial_dev             = &dm365_serial_device,
1097         .emac_pdata             = &dm365_emac_pdata,
1098         .sram_dma               = 0x00010000,
1099         .sram_len               = SZ_32K,
1100 };
1101
1102 void __init dm365_init_asp(struct snd_platform_data *pdata)
1103 {
1104         davinci_cfg_reg(DM365_MCBSP0_BDX);
1105         davinci_cfg_reg(DM365_MCBSP0_X);
1106         davinci_cfg_reg(DM365_MCBSP0_BFSX);
1107         davinci_cfg_reg(DM365_MCBSP0_BDR);
1108         davinci_cfg_reg(DM365_MCBSP0_R);
1109         davinci_cfg_reg(DM365_MCBSP0_BFSR);
1110         davinci_cfg_reg(DM365_EVT2_ASP_TX);
1111         davinci_cfg_reg(DM365_EVT3_ASP_RX);
1112         dm365_asp_device.dev.platform_data = pdata;
1113         platform_device_register(&dm365_asp_device);
1114 }
1115
1116 void __init dm365_init_vc(struct snd_platform_data *pdata)
1117 {
1118         davinci_cfg_reg(DM365_EVT2_VC_TX);
1119         davinci_cfg_reg(DM365_EVT3_VC_RX);
1120         dm365_vc_device.dev.platform_data = pdata;
1121         platform_device_register(&dm365_vc_device);
1122 }
1123
1124 void __init dm365_init_ks(struct davinci_ks_platform_data *pdata)
1125 {
1126         dm365_ks_device.dev.platform_data = pdata;
1127         platform_device_register(&dm365_ks_device);
1128 }
1129
1130 void __init dm365_init_rtc(void)
1131 {
1132         davinci_cfg_reg(DM365_INT_PRTCSS);
1133         platform_device_register(&dm365_rtc_device);
1134 }
1135
1136 void __init dm365_init(void)
1137 {
1138         davinci_common_init(&davinci_soc_info_dm365);
1139         davinci_map_sysmod();
1140 }
1141
1142 static struct resource dm365_vpss_resources[] = {
1143         {
1144                 /* VPSS ISP5 Base address */
1145                 .name           = "isp5",
1146                 .start          = 0x01c70000,
1147                 .end            = 0x01c70000 + 0xff,
1148                 .flags          = IORESOURCE_MEM,
1149         },
1150         {
1151                 /* VPSS CLK Base address */
1152                 .name           = "vpss",
1153                 .start          = 0x01c70200,
1154                 .end            = 0x01c70200 + 0xff,
1155                 .flags          = IORESOURCE_MEM,
1156         },
1157 };
1158
1159 static struct platform_device dm365_vpss_device = {
1160        .name                   = "vpss",
1161        .id                     = -1,
1162        .dev.platform_data      = "dm365_vpss",
1163        .num_resources          = ARRAY_SIZE(dm365_vpss_resources),
1164        .resource               = dm365_vpss_resources,
1165 };
1166
1167 static struct resource vpfe_resources[] = {
1168         {
1169                 .start          = IRQ_VDINT0,
1170                 .end            = IRQ_VDINT0,
1171                 .flags          = IORESOURCE_IRQ,
1172         },
1173         {
1174                 .start          = IRQ_VDINT1,
1175                 .end            = IRQ_VDINT1,
1176                 .flags          = IORESOURCE_IRQ,
1177         },
1178 };
1179
1180 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
1181 static struct platform_device vpfe_capture_dev = {
1182         .name           = CAPTURE_DRV_NAME,
1183         .id             = -1,
1184         .num_resources  = ARRAY_SIZE(vpfe_resources),
1185         .resource       = vpfe_resources,
1186         .dev = {
1187                 .dma_mask               = &vpfe_capture_dma_mask,
1188                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1189         },
1190 };
1191
1192 static void dm365_isif_setup_pinmux(void)
1193 {
1194         davinci_cfg_reg(DM365_VIN_CAM_WEN);
1195         davinci_cfg_reg(DM365_VIN_CAM_VD);
1196         davinci_cfg_reg(DM365_VIN_CAM_HD);
1197         davinci_cfg_reg(DM365_VIN_YIN4_7_EN);
1198         davinci_cfg_reg(DM365_VIN_YIN0_3_EN);
1199 }
1200
1201 static struct resource isif_resource[] = {
1202         /* ISIF Base address */
1203         {
1204                 .start          = 0x01c71000,
1205                 .end            = 0x01c71000 + 0x1ff,
1206                 .flags          = IORESOURCE_MEM,
1207         },
1208         /* ISIF Linearization table 0 */
1209         {
1210                 .start          = 0x1C7C000,
1211                 .end            = 0x1C7C000 + 0x2ff,
1212                 .flags          = IORESOURCE_MEM,
1213         },
1214         /* ISIF Linearization table 1 */
1215         {
1216                 .start          = 0x1C7C400,
1217                 .end            = 0x1C7C400 + 0x2ff,
1218                 .flags          = IORESOURCE_MEM,
1219         },
1220 };
1221 static struct platform_device dm365_isif_dev = {
1222         .name           = "isif",
1223         .id             = -1,
1224         .num_resources  = ARRAY_SIZE(isif_resource),
1225         .resource       = isif_resource,
1226         .dev = {
1227                 .dma_mask               = &vpfe_capture_dma_mask,
1228                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1229                 .platform_data          = dm365_isif_setup_pinmux,
1230         },
1231 };
1232
1233 static struct resource dm365_osd_resources[] = {
1234         {
1235                 .start = DM365_OSD_BASE,
1236                 .end   = DM365_OSD_BASE + 0xff,
1237                 .flags = IORESOURCE_MEM,
1238         },
1239 };
1240
1241 static u64 dm365_video_dma_mask = DMA_BIT_MASK(32);
1242
1243 static struct platform_device dm365_osd_dev = {
1244         .name           = DM365_VPBE_OSD_SUBDEV_NAME,
1245         .id             = -1,
1246         .num_resources  = ARRAY_SIZE(dm365_osd_resources),
1247         .resource       = dm365_osd_resources,
1248         .dev            = {
1249                 .dma_mask               = &dm365_video_dma_mask,
1250                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1251         },
1252 };
1253
1254 static struct resource dm365_venc_resources[] = {
1255         {
1256                 .start = IRQ_VENCINT,
1257                 .end   = IRQ_VENCINT,
1258                 .flags = IORESOURCE_IRQ,
1259         },
1260         /* venc registers io space */
1261         {
1262                 .start = DM365_VENC_BASE,
1263                 .end   = DM365_VENC_BASE + 0x177,
1264                 .flags = IORESOURCE_MEM,
1265         },
1266         /* vdaccfg registers io space */
1267         {
1268                 .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
1269                 .end   = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
1270                 .flags = IORESOURCE_MEM,
1271         },
1272 };
1273
1274 static struct resource dm365_v4l2_disp_resources[] = {
1275         {
1276                 .start = IRQ_VENCINT,
1277                 .end   = IRQ_VENCINT,
1278                 .flags = IORESOURCE_IRQ,
1279         },
1280         /* venc registers io space */
1281         {
1282                 .start = DM365_VENC_BASE,
1283                 .end   = DM365_VENC_BASE + 0x177,
1284                 .flags = IORESOURCE_MEM,
1285         },
1286 };
1287
1288 static int dm365_vpbe_setup_pinmux(enum v4l2_mbus_pixelcode if_type,
1289                             int field)
1290 {
1291         switch (if_type) {
1292         case V4L2_MBUS_FMT_SGRBG8_1X8:
1293                 davinci_cfg_reg(DM365_VOUT_FIELD_G81);
1294                 davinci_cfg_reg(DM365_VOUT_COUTL_EN);
1295                 davinci_cfg_reg(DM365_VOUT_COUTH_EN);
1296                 break;
1297         case V4L2_MBUS_FMT_YUYV10_1X20:
1298                 if (field)
1299                         davinci_cfg_reg(DM365_VOUT_FIELD);
1300                 else
1301                         davinci_cfg_reg(DM365_VOUT_FIELD_G81);
1302                 davinci_cfg_reg(DM365_VOUT_COUTL_EN);
1303                 davinci_cfg_reg(DM365_VOUT_COUTH_EN);
1304                 break;
1305         default:
1306                 return -EINVAL;
1307         }
1308
1309         return 0;
1310 }
1311
1312 static int dm365_venc_setup_clock(enum vpbe_enc_timings_type type,
1313                                   unsigned int pclock)
1314 {
1315         void __iomem *vpss_clkctl_reg;
1316         u32 val;
1317
1318         vpss_clkctl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
1319
1320         switch (type) {
1321         case VPBE_ENC_STD:
1322                 val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
1323                 break;
1324         case VPBE_ENC_DV_TIMINGS:
1325                 if (pclock <= 27000000) {
1326                         val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
1327                 } else {
1328                         /* set sysclk4 to output 74.25 MHz from pll1 */
1329                         val = VPSS_PLLC2SYSCLK5_ENABLE | VPSS_DACCLKEN_ENABLE |
1330                               VPSS_VENCCLKEN_ENABLE;
1331                 }
1332                 break;
1333         default:
1334                 return -EINVAL;
1335         }
1336         writel(val, vpss_clkctl_reg);
1337
1338         return 0;
1339 }
1340
1341 static struct platform_device dm365_vpbe_display = {
1342         .name           = "vpbe-v4l2",
1343         .id             = -1,
1344         .num_resources  = ARRAY_SIZE(dm365_v4l2_disp_resources),
1345         .resource       = dm365_v4l2_disp_resources,
1346         .dev            = {
1347                 .dma_mask               = &dm365_video_dma_mask,
1348                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1349         },
1350 };
1351
1352 static struct venc_platform_data dm365_venc_pdata = {
1353         .setup_pinmux   = dm365_vpbe_setup_pinmux,
1354         .setup_clock    = dm365_venc_setup_clock,
1355 };
1356
1357 static struct platform_device dm365_venc_dev = {
1358         .name           = DM365_VPBE_VENC_SUBDEV_NAME,
1359         .id             = -1,
1360         .num_resources  = ARRAY_SIZE(dm365_venc_resources),
1361         .resource       = dm365_venc_resources,
1362         .dev            = {
1363                 .dma_mask               = &dm365_video_dma_mask,
1364                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1365                 .platform_data          = (void *)&dm365_venc_pdata,
1366         },
1367 };
1368
1369 static struct platform_device dm365_vpbe_dev = {
1370         .name           = "vpbe_controller",
1371         .id             = -1,
1372         .dev            = {
1373                 .dma_mask               = &dm365_video_dma_mask,
1374                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1375         },
1376 };
1377
1378 int __init dm365_init_video(struct vpfe_config *vpfe_cfg,
1379                                 struct vpbe_config *vpbe_cfg)
1380 {
1381         if (vpfe_cfg || vpbe_cfg)
1382                 platform_device_register(&dm365_vpss_device);
1383
1384         if (vpfe_cfg) {
1385                 vpfe_capture_dev.dev.platform_data = vpfe_cfg;
1386                 platform_device_register(&dm365_isif_dev);
1387                 platform_device_register(&vpfe_capture_dev);
1388         }
1389         if (vpbe_cfg) {
1390                 dm365_vpbe_dev.dev.platform_data = vpbe_cfg;
1391                 platform_device_register(&dm365_osd_dev);
1392                 platform_device_register(&dm365_venc_dev);
1393                 platform_device_register(&dm365_vpbe_dev);
1394                 platform_device_register(&dm365_vpbe_display);
1395         }
1396
1397         return 0;
1398 }
1399
1400 static int __init dm365_init_devices(void)
1401 {
1402         if (!cpu_is_davinci_dm365())
1403                 return 0;
1404
1405         davinci_cfg_reg(DM365_INT_EDMA_CC);
1406         platform_device_register(&dm365_edma_device);
1407
1408         platform_device_register(&dm365_mdio_device);
1409         platform_device_register(&dm365_emac_device);
1410         clk_add_alias(NULL, dev_name(&dm365_mdio_device.dev),
1411                       NULL, &dm365_emac_device.dev);
1412
1413         return 0;
1414 }
1415 postcore_initcall(dm365_init_devices);