arch/arm/mach-davinci/dm355.c

   1 /*
   2  * TI DaVinci DM355 chip specific setup
   3  *
   4  * Author: Kevin Hilman, Deep Root Systems, LLC
   5  *
   6  * 2007 (c) Deep Root Systems, LLC. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11 #include <linux/init.h>
  12 #include <linux/clk.h>
  13 #include <linux/serial_8250.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/gpio.h>
  17
  18 #include <linux/spi/spi.h>
  19
  20 #include <asm/mach/map.h>
  21
  22 #include <mach/dm355.h>
  23 #include <mach/cputype.h>
  24 #include <mach/edma.h>
  25 #include <mach/psc.h>
  26 #include <mach/mux.h>
  27 #include <mach/irqs.h>
  28 #include <mach/time.h>
  29 #include <mach/serial.h>
  30 #include <mach/common.h>
  31 #include <mach/asp.h>
  32
  33 #include "clock.h"
  34 #include "mux.h"
  35
  36 #define DM355_UART2_BASE        (IO_PHYS + 0x206000)
  37
  38 /*
  39  * Device specific clocks
  40  */
  41 #define DM355_REF_FREQ          24000000        /* 24 or 36 MHz */
  42
  43 static struct pll_data pll1_data = {
  44         .num       = 1,
  45         .phys_base = DAVINCI_PLL1_BASE,
  46         .flags     = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
  47 };
  48
  49 static struct pll_data pll2_data = {
  50         .num       = 2,
  51         .phys_base = DAVINCI_PLL2_BASE,
  52         .flags     = PLL_HAS_PREDIV,
  53 };
  54
  55 static struct clk ref_clk = {
  56         .name = "ref_clk",
  57         /* FIXME -- crystal rate is board-specific */
  58         .rate = DM355_REF_FREQ,
  59 };
  60
  61 static struct clk pll1_clk = {
  62         .name = "pll1",
  63         .parent = &ref_clk,
  64         .flags = CLK_PLL,
  65         .pll_data = &pll1_data,
  66 };
  67
  68 static struct clk pll1_aux_clk = {
  69         .name = "pll1_aux_clk",
  70         .parent = &pll1_clk,
  71         .flags = CLK_PLL | PRE_PLL,
  72 };
  73
  74 static struct clk pll1_sysclk1 = {
  75         .name = "pll1_sysclk1",
  76         .parent = &pll1_clk,
  77         .flags = CLK_PLL,
  78         .div_reg = PLLDIV1,
  79 };
  80
  81 static struct clk pll1_sysclk2 = {
  82         .name = "pll1_sysclk2",
  83         .parent = &pll1_clk,
  84         .flags = CLK_PLL,
  85         .div_reg = PLLDIV2,
  86 };
  87
  88 static struct clk pll1_sysclk3 = {
  89         .name = "pll1_sysclk3",
  90         .parent = &pll1_clk,
  91         .flags = CLK_PLL,
  92         .div_reg = PLLDIV3,
  93 };
  94
  95 static struct clk pll1_sysclk4 = {
  96         .name = "pll1_sysclk4",
  97         .parent = &pll1_clk,
  98         .flags = CLK_PLL,
  99         .div_reg = PLLDIV4,
 100 };
 101
 102 static struct clk pll1_sysclkbp = {
 103         .name = "pll1_sysclkbp",
 104         .parent = &pll1_clk,
 105         .flags = CLK_PLL | PRE_PLL,
 106         .div_reg = BPDIV
 107 };
 108
 109 static struct clk vpss_dac_clk = {
 110         .name = "vpss_dac",
 111         .parent = &pll1_sysclk3,
 112         .lpsc = DM355_LPSC_VPSS_DAC,
 113 };
 114
 115 static struct clk vpss_master_clk = {
 116         .name = "vpss_master",
 117         .parent = &pll1_sysclk4,
 118         .lpsc = DAVINCI_LPSC_VPSSMSTR,
 119         .flags = CLK_PSC,
 120 };
 121
 122 static struct clk vpss_slave_clk = {
 123         .name = "vpss_slave",
 124         .parent = &pll1_sysclk4,
 125         .lpsc = DAVINCI_LPSC_VPSSSLV,
 126 };
 127
 128
 129 static struct clk clkout1_clk = {
 130         .name = "clkout1",
 131         .parent = &pll1_aux_clk,
 132         /* NOTE:  clkout1 can be externally gated by muxing GPIO-18 */
 133 };
 134
 135 static struct clk clkout2_clk = {
 136         .name = "clkout2",
 137         .parent = &pll1_sysclkbp,
 138 };
 139
 140 static struct clk pll2_clk = {
 141         .name = "pll2",
 142         .parent = &ref_clk,
 143         .flags = CLK_PLL,
 144         .pll_data = &pll2_data,
 145 };
 146
 147 static struct clk pll2_sysclk1 = {
 148         .name = "pll2_sysclk1",
 149         .parent = &pll2_clk,
 150         .flags = CLK_PLL,
 151         .div_reg = PLLDIV1,
 152 };
 153
 154 static struct clk pll2_sysclkbp = {
 155         .name = "pll2_sysclkbp",
 156         .parent = &pll2_clk,
 157         .flags = CLK_PLL | PRE_PLL,
 158         .div_reg = BPDIV
 159 };
 160
 161 static struct clk clkout3_clk = {
 162         .name = "clkout3",
 163         .parent = &pll2_sysclkbp,
 164         /* NOTE:  clkout3 can be externally gated by muxing GPIO-16 */
 165 };
 166
 167 static struct clk arm_clk = {
 168         .name = "arm_clk",
 169         .parent = &pll1_sysclk1,
 170         .lpsc = DAVINCI_LPSC_ARM,
 171         .flags = ALWAYS_ENABLED,
 172 };
 173
 174 /*
 175  * NOT LISTED below, and not touched by Linux
 176  *   - in SyncReset state by default
 177  *      .lpsc = DAVINCI_LPSC_TPCC,
 178  *      .lpsc = DAVINCI_LPSC_TPTC0,
 179  *      .lpsc = DAVINCI_LPSC_TPTC1,
 180  *      .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
 181  *      .lpsc = DAVINCI_LPSC_MEMSTICK,
 182  *   - in Enabled state by default
 183  *      .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
 184  *      .lpsc = DAVINCI_LPSC_SCR2,      // "bus"
 185  *      .lpsc = DAVINCI_LPSC_SCR3,      // "bus"
 186  *      .lpsc = DAVINCI_LPSC_SCR4,      // "bus"
 187  *      .lpsc = DAVINCI_LPSC_CROSSBAR,  // "emulation"
 188  *      .lpsc = DAVINCI_LPSC_CFG27,     // "test"
 189  *      .lpsc = DAVINCI_LPSC_CFG3,      // "test"
 190  *      .lpsc = DAVINCI_LPSC_CFG5,      // "test"
 191  */
 192
 193 static struct clk mjcp_clk = {
 194         .name = "mjcp",
 195         .parent = &pll1_sysclk1,
 196         .lpsc = DAVINCI_LPSC_IMCOP,
 197 };
 198
 199 static struct clk uart0_clk = {
 200         .name = "uart0",
 201         .parent = &pll1_aux_clk,
 202         .lpsc = DAVINCI_LPSC_UART0,
 203 };
 204
 205 static struct clk uart1_clk = {
 206         .name = "uart1",
 207         .parent = &pll1_aux_clk,
 208         .lpsc = DAVINCI_LPSC_UART1,
 209 };
 210
 211 static struct clk uart2_clk = {
 212         .name = "uart2",
 213         .parent = &pll1_sysclk2,
 214         .lpsc = DAVINCI_LPSC_UART2,
 215 };
 216
 217 static struct clk i2c_clk = {
 218         .name = "i2c",
 219         .parent = &pll1_aux_clk,
 220         .lpsc = DAVINCI_LPSC_I2C,
 221 };
 222
 223 static struct clk asp0_clk = {
 224         .name = "asp0",
 225         .parent = &pll1_sysclk2,
 226         .lpsc = DAVINCI_LPSC_McBSP,
 227 };
 228
 229 static struct clk asp1_clk = {
 230         .name = "asp1",
 231         .parent = &pll1_sysclk2,
 232         .lpsc = DM355_LPSC_McBSP1,
 233 };
 234
 235 static struct clk mmcsd0_clk = {
 236         .name = "mmcsd0",
 237         .parent = &pll1_sysclk2,
 238         .lpsc = DAVINCI_LPSC_MMC_SD,
 239 };
 240
 241 static struct clk mmcsd1_clk = {
 242         .name = "mmcsd1",
 243         .parent = &pll1_sysclk2,
 244         .lpsc = DM355_LPSC_MMC_SD1,
 245 };
 246
 247 static struct clk spi0_clk = {
 248         .name = "spi0",
 249         .parent = &pll1_sysclk2,
 250         .lpsc = DAVINCI_LPSC_SPI,
 251 };
 252
 253 static struct clk spi1_clk = {
 254         .name = "spi1",
 255         .parent = &pll1_sysclk2,
 256         .lpsc = DM355_LPSC_SPI1,
 257 };
 258
 259 static struct clk spi2_clk = {
 260         .name = "spi2",
 261         .parent = &pll1_sysclk2,
 262         .lpsc = DM355_LPSC_SPI2,
 263 };
 264
 265 static struct clk gpio_clk = {
 266         .name = "gpio",
 267         .parent = &pll1_sysclk2,
 268         .lpsc = DAVINCI_LPSC_GPIO,
 269 };
 270
 271 static struct clk aemif_clk = {
 272         .name = "aemif",
 273         .parent = &pll1_sysclk2,
 274         .lpsc = DAVINCI_LPSC_AEMIF,
 275 };
 276
 277 static struct clk pwm0_clk = {
 278         .name = "pwm0",
 279         .parent = &pll1_aux_clk,
 280         .lpsc = DAVINCI_LPSC_PWM0,
 281 };
 282
 283 static struct clk pwm1_clk = {
 284         .name = "pwm1",
 285         .parent = &pll1_aux_clk,
 286         .lpsc = DAVINCI_LPSC_PWM1,
 287 };
 288
 289 static struct clk pwm2_clk = {
 290         .name = "pwm2",
 291         .parent = &pll1_aux_clk,
 292         .lpsc = DAVINCI_LPSC_PWM2,
 293 };
 294
 295 static struct clk pwm3_clk = {
 296         .name = "pwm3",
 297         .parent = &pll1_aux_clk,
 298         .lpsc = DM355_LPSC_PWM3,
 299 };
 300
 301 static struct clk timer0_clk = {
 302         .name = "timer0",
 303         .parent = &pll1_aux_clk,
 304         .lpsc = DAVINCI_LPSC_TIMER0,
 305 };
 306
 307 static struct clk timer1_clk = {
 308         .name = "timer1",
 309         .parent = &pll1_aux_clk,
 310         .lpsc = DAVINCI_LPSC_TIMER1,
 311 };
 312
 313 static struct clk timer2_clk = {
 314         .name = "timer2",
 315         .parent = &pll1_aux_clk,
 316         .lpsc = DAVINCI_LPSC_TIMER2,
 317         .usecount = 1,              /* REVISIT: why cant' this be disabled? */
 318 };
 319
 320 static struct clk timer3_clk = {
 321         .name = "timer3",
 322         .parent = &pll1_aux_clk,
 323         .lpsc = DM355_LPSC_TIMER3,
 324 };
 325
 326 static struct clk rto_clk = {
 327         .name = "rto",
 328         .parent = &pll1_aux_clk,
 329         .lpsc = DM355_LPSC_RTO,
 330 };
 331
 332 static struct clk usb_clk = {
 333         .name = "usb",
 334         .parent = &pll1_sysclk2,
 335         .lpsc = DAVINCI_LPSC_USB,
 336 };
 337
 338 static struct davinci_clk dm355_clks[] = {
 339         CLK(NULL, "ref", &ref_clk),
 340         CLK(NULL, "pll1", &pll1_clk),
 341         CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
 342         CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
 343         CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
 344         CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
 345         CLK(NULL, "pll1_aux", &pll1_aux_clk),
 346         CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
 347         CLK(NULL, "vpss_dac", &vpss_dac_clk),
 348         CLK(NULL, "vpss_master", &vpss_master_clk),
 349         CLK(NULL, "vpss_slave", &vpss_slave_clk),
 350         CLK(NULL, "clkout1", &clkout1_clk),
 351         CLK(NULL, "clkout2", &clkout2_clk),
 352         CLK(NULL, "pll2", &pll2_clk),
 353         CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
 354         CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
 355         CLK(NULL, "clkout3", &clkout3_clk),
 356         CLK(NULL, "arm", &arm_clk),
 357         CLK(NULL, "mjcp", &mjcp_clk),
 358         CLK(NULL, "uart0", &uart0_clk),
 359         CLK(NULL, "uart1", &uart1_clk),
 360         CLK(NULL, "uart2", &uart2_clk),
 361         CLK("i2c_davinci.1", NULL, &i2c_clk),
 362         CLK("davinci-asp.0", NULL, &asp0_clk),
 363         CLK("davinci-asp.1", NULL, &asp1_clk),
 364         CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
 365         CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
 366         CLK(NULL, "spi0", &spi0_clk),
 367         CLK(NULL, "spi1", &spi1_clk),
 368         CLK(NULL, "spi2", &spi2_clk),
 369         CLK(NULL, "gpio", &gpio_clk),
 370         CLK(NULL, "aemif", &aemif_clk),
 371         CLK(NULL, "pwm0", &pwm0_clk),
 372         CLK(NULL, "pwm1", &pwm1_clk),
 373         CLK(NULL, "pwm2", &pwm2_clk),
 374         CLK(NULL, "pwm3", &pwm3_clk),
 375         CLK(NULL, "timer0", &timer0_clk),
 376         CLK(NULL, "timer1", &timer1_clk),
 377         CLK("watchdog", NULL, &timer2_clk),
 378         CLK(NULL, "timer3", &timer3_clk),
 379         CLK(NULL, "rto", &rto_clk),
 380         CLK(NULL, "usb", &usb_clk),
 381         CLK(NULL, NULL, NULL),
 382 };
 383
 384 /*----------------------------------------------------------------------*/
 385
 386 static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
 387
 388 static struct resource dm355_spi0_resources[] = {
 389         {
 390                 .start = 0x01c66000,
 391                 .end   = 0x01c667ff,
 392                 .flags = IORESOURCE_MEM,
 393         },
 394         {
 395                 .start = IRQ_DM355_SPINT0_1,
 396                 .flags = IORESOURCE_IRQ,
 397         },
 398         /* Not yet used, so not included:
 399          * IORESOURCE_IRQ:
 400          *  - IRQ_DM355_SPINT0_0
 401          * IORESOURCE_DMA:
 402          *  - DAVINCI_DMA_SPI_SPIX
 403          *  - DAVINCI_DMA_SPI_SPIR
 404          */
 405 };
 406
 407 static struct platform_device dm355_spi0_device = {
 408         .name = "spi_davinci",
 409         .id = 0,
 410         .dev = {
 411                 .dma_mask = &dm355_spi0_dma_mask,
 412                 .coherent_dma_mask = DMA_BIT_MASK(32),
 413         },
 414         .num_resources = ARRAY_SIZE(dm355_spi0_resources),
 415         .resource = dm355_spi0_resources,
 416 };
 417
 418 void __init dm355_init_spi0(unsigned chipselect_mask,
 419                 struct spi_board_info *info, unsigned len)
 420 {
 421         /* for now, assume we need MISO */
 422         davinci_cfg_reg(DM355_SPI0_SDI);
 423
 424         /* not all slaves will be wired up */
 425         if (chipselect_mask & BIT(0))
 426                 davinci_cfg_reg(DM355_SPI0_SDENA0);
 427         if (chipselect_mask & BIT(1))
 428                 davinci_cfg_reg(DM355_SPI0_SDENA1);
 429
 430         spi_register_board_info(info, len);
 431
 432         platform_device_register(&dm355_spi0_device);
 433 }
 434
 435 /*----------------------------------------------------------------------*/
 436
 437 #define PINMUX0         0x00
 438 #define PINMUX1         0x04
 439 #define PINMUX2         0x08
 440 #define PINMUX3         0x0c
 441 #define PINMUX4         0x10
 442 #define INTMUX          0x18
 443 #define EVTMUX          0x1c
 444
 445 /*
 446  * Device specific mux setup
 447  *
 448  *      soc     description     mux  mode   mode  mux    dbg
 449  *                              reg  offset mask  mode
 450  */
 451 static const struct mux_config dm355_pins[] = {
 452 #ifdef CONFIG_DAVINCI_MUX
 453 MUX_CFG(DM355,  MMCSD0,         4,   2,     1,    0,     false)
 454
 455 MUX_CFG(DM355,  SD1_CLK,        3,   6,     1,    1,     false)
 456 MUX_CFG(DM355,  SD1_CMD,        3,   7,     1,    1,     false)
 457 MUX_CFG(DM355,  SD1_DATA3,      3,   8,     3,    1,     false)
 458 MUX_CFG(DM355,  SD1_DATA2,      3,   10,    3,    1,     false)
 459 MUX_CFG(DM355,  SD1_DATA1,      3,   12,    3,    1,     false)
 460 MUX_CFG(DM355,  SD1_DATA0,      3,   14,    3,    1,     false)
 461
 462 MUX_CFG(DM355,  I2C_SDA,        3,   19,    1,    1,     false)
 463 MUX_CFG(DM355,  I2C_SCL,        3,   20,    1,    1,     false)
 464
 465 MUX_CFG(DM355,  MCBSP0_BDX,     3,   0,     1,    1,     false)
 466 MUX_CFG(DM355,  MCBSP0_X,       3,   1,     1,    1,     false)
 467 MUX_CFG(DM355,  MCBSP0_BFSX,    3,   2,     1,    1,     false)
 468 MUX_CFG(DM355,  MCBSP0_BDR,     3,   3,     1,    1,     false)
 469 MUX_CFG(DM355,  MCBSP0_R,       3,   4,     1,    1,     false)
 470 MUX_CFG(DM355,  MCBSP0_BFSR,    3,   5,     1,    1,     false)
 471
 472 MUX_CFG(DM355,  SPI0_SDI,       4,   1,     1,    0,     false)
 473 MUX_CFG(DM355,  SPI0_SDENA0,    4,   0,     1,    0,     false)
 474 MUX_CFG(DM355,  SPI0_SDENA1,    3,   28,    1,    1,     false)
 475
 476 INT_CFG(DM355,  INT_EDMA_CC,          2,    1,    1,     false)
 477 INT_CFG(DM355,  INT_EDMA_TC0_ERR,     3,    1,    1,     false)
 478 INT_CFG(DM355,  INT_EDMA_TC1_ERR,     4,    1,    1,     false)
 479
 480 EVT_CFG(DM355,  EVT8_ASP1_TX,         0,    1,    0,     false)
 481 EVT_CFG(DM355,  EVT9_ASP1_RX,         1,    1,    0,     false)
 482 EVT_CFG(DM355,  EVT26_MMC0_RX,        2,    1,    0,     false)
 483
 484 MUX_CFG(DM355,  VOUT_FIELD,     1,   18,    3,    1,     false)
 485 MUX_CFG(DM355,  VOUT_FIELD_G70, 1,   18,    3,    0,     false)
 486 MUX_CFG(DM355,  VOUT_HVSYNC,    1,   16,    1,    0,     false)
 487 MUX_CFG(DM355,  VOUT_COUTL_EN,  1,   0,     0xff, 0x55,  false)
 488 MUX_CFG(DM355,  VOUT_COUTH_EN,  1,   8,     0xff, 0x55,  false)
 489
 490 MUX_CFG(DM355,  VIN_PCLK,       0,   14,    1,    1,     false)
 491 MUX_CFG(DM355,  VIN_CAM_WEN,    0,   13,    1,    1,     false)
 492 MUX_CFG(DM355,  VIN_CAM_VD,     0,   12,    1,    1,     false)
 493 MUX_CFG(DM355,  VIN_CAM_HD,     0,   11,    1,    1,     false)
 494 MUX_CFG(DM355,  VIN_YIN_EN,     0,   10,    1,    1,     false)
 495 MUX_CFG(DM355,  VIN_CINL_EN,    0,   0,   0xff, 0x55,    false)
 496 MUX_CFG(DM355,  VIN_CINH_EN,    0,   8,     3,    3,     false)
 497 #endif
 498 };
 499
 500 static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 501         [IRQ_DM355_CCDC_VDINT0]         = 2,
 502         [IRQ_DM355_CCDC_VDINT1]         = 6,
 503         [IRQ_DM355_CCDC_VDINT2]         = 6,
 504         [IRQ_DM355_IPIPE_HST]           = 6,
 505         [IRQ_DM355_H3AINT]              = 6,
 506         [IRQ_DM355_IPIPE_SDR]           = 6,
 507         [IRQ_DM355_IPIPEIFINT]          = 6,
 508         [IRQ_DM355_OSDINT]              = 7,
 509         [IRQ_DM355_VENCINT]             = 6,
 510         [IRQ_ASQINT]                    = 6,
 511         [IRQ_IMXINT]                    = 6,
 512         [IRQ_USBINT]                    = 4,
 513         [IRQ_DM355_RTOINT]              = 4,
 514         [IRQ_DM355_UARTINT2]            = 7,
 515         [IRQ_DM355_TINT6]               = 7,
 516         [IRQ_CCINT0]                    = 5,    /* dma */
 517         [IRQ_CCERRINT]                  = 5,    /* dma */
 518         [IRQ_TCERRINT0]                 = 5,    /* dma */
 519         [IRQ_TCERRINT]                  = 5,    /* dma */
 520         [IRQ_DM355_SPINT2_1]            = 7,
 521         [IRQ_DM355_TINT7]               = 4,
 522         [IRQ_DM355_SDIOINT0]            = 7,
 523         [IRQ_MBXINT]                    = 7,
 524         [IRQ_MBRINT]                    = 7,
 525         [IRQ_MMCINT]                    = 7,
 526         [IRQ_DM355_MMCINT1]             = 7,
 527         [IRQ_DM355_PWMINT3]             = 7,
 528         [IRQ_DDRINT]                    = 7,
 529         [IRQ_AEMIFINT]                  = 7,
 530         [IRQ_DM355_SDIOINT1]            = 4,
 531         [IRQ_TINT0_TINT12]              = 2,    /* clockevent */
 532         [IRQ_TINT0_TINT34]              = 2,    /* clocksource */
 533         [IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
 534         [IRQ_TINT1_TINT34]              = 7,    /* system tick */
 535         [IRQ_PWMINT0]                   = 7,
 536         [IRQ_PWMINT1]                   = 7,
 537         [IRQ_PWMINT2]                   = 7,
 538         [IRQ_I2C]                       = 3,
 539         [IRQ_UARTINT0]                  = 3,
 540         [IRQ_UARTINT1]                  = 3,
 541         [IRQ_DM355_SPINT0_0]            = 3,
 542         [IRQ_DM355_SPINT0_1]            = 3,
 543         [IRQ_DM355_GPIO0]               = 3,
 544         [IRQ_DM355_GPIO1]               = 7,
 545         [IRQ_DM355_GPIO2]               = 4,
 546         [IRQ_DM355_GPIO3]               = 4,
 547         [IRQ_DM355_GPIO4]               = 7,
 548         [IRQ_DM355_GPIO5]               = 7,
 549         [IRQ_DM355_GPIO6]               = 7,
 550         [IRQ_DM355_GPIO7]               = 7,
 551         [IRQ_DM355_GPIO8]               = 7,
 552         [IRQ_DM355_GPIO9]               = 7,
 553         [IRQ_DM355_GPIOBNK0]            = 7,
 554         [IRQ_DM355_GPIOBNK1]            = 7,
 555         [IRQ_DM355_GPIOBNK2]            = 7,
 556         [IRQ_DM355_GPIOBNK3]            = 7,
 557         [IRQ_DM355_GPIOBNK4]            = 7,
 558         [IRQ_DM355_GPIOBNK5]            = 7,
 559         [IRQ_DM355_GPIOBNK6]            = 7,
 560         [IRQ_COMMTX]                    = 7,
 561         [IRQ_COMMRX]                    = 7,
 562         [IRQ_EMUINT]                    = 7,
 563 };
 564
 565 /*----------------------------------------------------------------------*/
 566
 567 static const s8 dma_chan_dm355_no_event[] = {
 568         12, 13, 24, 56, 57,
 569         58, 59, 60, 61, 62,
 570         63,
 571         -1
 572 };
 573
 574 static const s8
 575 queue_tc_mapping[][2] = {
 576         /* {event queue no, TC no} */
 577         {0, 0},
 578         {1, 1},
 579         {-1, -1},
 580 };
 581
 582 static const s8
 583 queue_priority_mapping[][2] = {
 584         /* {event queue no, Priority} */
 585         {0, 3},
 586         {1, 7},
 587         {-1, -1},
 588 };
 589
 590 static struct edma_soc_info dm355_edma_info[] = {
 591         {
 592                 .n_channel              = 64,
 593                 .n_region               = 4,
 594                 .n_slot                 = 128,
 595                 .n_tc                   = 2,
 596                 .n_cc                   = 1,
 597                 .noevent                = dma_chan_dm355_no_event,
 598                 .queue_tc_mapping       = queue_tc_mapping,
 599                 .queue_priority_mapping = queue_priority_mapping,
 600         },
 601 };
 602
 603 static struct resource edma_resources[] = {
 604         {
 605                 .name   = "edma_cc0",
 606                 .start  = 0x01c00000,
 607                 .end    = 0x01c00000 + SZ_64K - 1,
 608                 .flags  = IORESOURCE_MEM,
 609         },
 610         {
 611                 .name   = "edma_tc0",
 612                 .start  = 0x01c10000,
 613                 .end    = 0x01c10000 + SZ_1K - 1,
 614                 .flags  = IORESOURCE_MEM,
 615         },
 616         {
 617                 .name   = "edma_tc1",
 618                 .start  = 0x01c10400,
 619                 .end    = 0x01c10400 + SZ_1K - 1,
 620                 .flags  = IORESOURCE_MEM,
 621         },
 622         {
 623                 .name   = "edma0",
 624                 .start  = IRQ_CCINT0,
 625                 .flags  = IORESOURCE_IRQ,
 626         },
 627         {
 628                 .name   = "edma0_err",
 629                 .start  = IRQ_CCERRINT,
 630                 .flags  = IORESOURCE_IRQ,
 631         },
 632         /* not using (or muxing) TC*_ERR */
 633 };
 634
 635 static struct platform_device dm355_edma_device = {
 636         .name                   = "edma",
 637         .id                     = 0,
 638         .dev.platform_data      = dm355_edma_info,
 639         .num_resources          = ARRAY_SIZE(edma_resources),
 640         .resource               = edma_resources,
 641 };
 642
 643 static struct resource dm355_asp1_resources[] = {
 644         {
 645                 .start  = DAVINCI_ASP1_BASE,
 646                 .end    = DAVINCI_ASP1_BASE + SZ_8K - 1,
 647                 .flags  = IORESOURCE_MEM,
 648         },
 649         {
 650                 .start  = DAVINCI_DMA_ASP1_TX,
 651                 .end    = DAVINCI_DMA_ASP1_TX,
 652                 .flags  = IORESOURCE_DMA,
 653         },
 654         {
 655                 .start  = DAVINCI_DMA_ASP1_RX,
 656                 .end    = DAVINCI_DMA_ASP1_RX,
 657                 .flags  = IORESOURCE_DMA,
 658         },
 659 };
 660
 661 static struct platform_device dm355_asp1_device = {
 662         .name           = "davinci-asp",
 663         .id             = 1,
 664         .num_resources  = ARRAY_SIZE(dm355_asp1_resources),
 665         .resource       = dm355_asp1_resources,
 666 };
 667
 668 static struct resource dm355_vpss_resources[] = {
 669         {
 670                 /* VPSS BL Base address */
 671                 .name           = "vpss",
 672                 .start          = 0x01c70800,
 673                 .end            = 0x01c70800 + 0xff,
 674                 .flags          = IORESOURCE_MEM,
 675         },
 676         {
 677                 /* VPSS CLK Base address */
 678                 .name           = "vpss",
 679                 .start          = 0x01c70000,
 680                 .end            = 0x01c70000 + 0xf,
 681                 .flags          = IORESOURCE_MEM,
 682         },
 683 };
 684
 685 static struct platform_device dm355_vpss_device = {
 686         .name                   = "vpss",
 687         .id                     = -1,
 688         .dev.platform_data      = "dm355_vpss",
 689         .num_resources          = ARRAY_SIZE(dm355_vpss_resources),
 690         .resource               = dm355_vpss_resources,
 691 };
 692
 693 static struct resource vpfe_resources[] = {
 694         {
 695                 .start          = IRQ_VDINT0,
 696                 .end            = IRQ_VDINT0,
 697                 .flags          = IORESOURCE_IRQ,
 698         },
 699         {
 700                 .start          = IRQ_VDINT1,
 701                 .end            = IRQ_VDINT1,
 702                 .flags          = IORESOURCE_IRQ,
 703         },
 704         /* CCDC Base address */
 705         {
 706                 .flags          = IORESOURCE_MEM,
 707                 .start          = 0x01c70600,
 708                 .end            = 0x01c70600 + 0x1ff,
 709         },
 710 };
 711
 712 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
 713 static struct platform_device vpfe_capture_dev = {
 714         .name           = CAPTURE_DRV_NAME,
 715         .id             = -1,
 716         .num_resources  = ARRAY_SIZE(vpfe_resources),
 717         .resource       = vpfe_resources,
 718         .dev = {
 719                 .dma_mask               = &vpfe_capture_dma_mask,
 720                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 721         },
 722 };
 723
 724 void dm355_set_vpfe_config(struct vpfe_config *cfg)
 725 {
 726         vpfe_capture_dev.dev.platform_data = cfg;
 727 }
 728
 729 /*----------------------------------------------------------------------*/
 730
 731 static struct map_desc dm355_io_desc[] = {
 732         {
 733                 .virtual        = IO_VIRT,
 734                 .pfn            = __phys_to_pfn(IO_PHYS),
 735                 .length         = IO_SIZE,
 736                 .type           = MT_DEVICE
 737         },
 738         {
 739                 .virtual        = SRAM_VIRT,
 740                 .pfn            = __phys_to_pfn(0x00010000),
 741                 .length         = SZ_32K,
 742                 /* MT_MEMORY_NONCACHED requires supersection alignment */
 743                 .type           = MT_DEVICE,
 744         },
 745 };
 746
 747 /* Contents of JTAG ID register used to identify exact cpu type */
 748 static struct davinci_id dm355_ids[] = {
 749         {
 750                 .variant        = 0x0,
 751                 .part_no        = 0xb73b,
 752                 .manufacturer   = 0x00f,
 753                 .cpu_id         = DAVINCI_CPU_ID_DM355,
 754                 .name           = "dm355",
 755         },
 756 };
 757
 758 static void __iomem *dm355_psc_bases[] = {
 759         IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
 760 };
 761
 762 /*
 763  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
 764  * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
 765  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
 766  * T1_TOP: Timer 1, top   :  <unused>
 767  */
 768 struct davinci_timer_info dm355_timer_info = {
 769         .timers         = davinci_timer_instance,
 770         .clockevent_id  = T0_BOT,
 771         .clocksource_id = T0_TOP,
 772 };
 773
 774 static struct plat_serial8250_port dm355_serial_platform_data[] = {
 775         {
 776                 .mapbase        = DAVINCI_UART0_BASE,
 777                 .irq            = IRQ_UARTINT0,
 778                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 779                                   UPF_IOREMAP,
 780                 .iotype         = UPIO_MEM,
 781                 .regshift       = 2,
 782         },
 783         {
 784                 .mapbase        = DAVINCI_UART1_BASE,
 785                 .irq            = IRQ_UARTINT1,
 786                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 787                                   UPF_IOREMAP,
 788                 .iotype         = UPIO_MEM,
 789                 .regshift       = 2,
 790         },
 791         {
 792                 .mapbase        = DM355_UART2_BASE,
 793                 .irq            = IRQ_DM355_UARTINT2,
 794                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 795                                   UPF_IOREMAP,
 796                 .iotype         = UPIO_MEM,
 797                 .regshift       = 2,
 798         },
 799         {
 800                 .flags          = 0
 801         },
 802 };
 803
 804 static struct platform_device dm355_serial_device = {
 805         .name                   = "serial8250",
 806         .id                     = PLAT8250_DEV_PLATFORM,
 807         .dev                    = {
 808                 .platform_data  = dm355_serial_platform_data,
 809         },
 810 };
 811
 812 static struct davinci_soc_info davinci_soc_info_dm355 = {
 813         .io_desc                = dm355_io_desc,
 814         .io_desc_num            = ARRAY_SIZE(dm355_io_desc),
 815         .jtag_id_base           = IO_ADDRESS(0x01c40028),
 816         .ids                    = dm355_ids,
 817         .ids_num                = ARRAY_SIZE(dm355_ids),
 818         .cpu_clks               = dm355_clks,
 819         .psc_bases              = dm355_psc_bases,
 820         .psc_bases_num          = ARRAY_SIZE(dm355_psc_bases),
 821         .pinmux_base            = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
 822         .pinmux_pins            = dm355_pins,
 823         .pinmux_pins_num        = ARRAY_SIZE(dm355_pins),
 824         .intc_base              = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
 825         .intc_type              = DAVINCI_INTC_TYPE_AINTC,
 826         .intc_irq_prios         = dm355_default_priorities,
 827         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
 828         .timer_info             = &dm355_timer_info,
 829         .gpio_base              = IO_ADDRESS(DAVINCI_GPIO_BASE),
 830         .gpio_num               = 104,
 831         .gpio_irq               = IRQ_DM355_GPIOBNK0,
 832         .serial_dev             = &dm355_serial_device,
 833         .sram_dma               = 0x00010000,
 834         .sram_len               = SZ_32K,
 835 };
 836
 837 void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata)
 838 {
 839         /* we don't use ASP1 IRQs, or we'd need to mux them ... */
 840         if (evt_enable & ASP1_TX_EVT_EN)
 841                 davinci_cfg_reg(DM355_EVT8_ASP1_TX);
 842
 843         if (evt_enable & ASP1_RX_EVT_EN)
 844                 davinci_cfg_reg(DM355_EVT9_ASP1_RX);
 845
 846         dm355_asp1_device.dev.platform_data = pdata;
 847         platform_device_register(&dm355_asp1_device);
 848 }
 849
 850 void __init dm355_init(void)
 851 {
 852         davinci_common_init(&davinci_soc_info_dm355);
 853 }
 854
 855 static int __init dm355_init_devices(void)
 856 {
 857         if (!cpu_is_davinci_dm355())
 858                 return 0;
 859
 860         davinci_cfg_reg(DM355_INT_EDMA_CC);
 861         platform_device_register(&dm355_edma_device);
 862         platform_device_register(&dm355_vpss_device);
 863         /*
 864          * setup Mux configuration for vpfe input and register
 865          * vpfe capture platform device
 866          */
 867         davinci_cfg_reg(DM355_VIN_PCLK);
 868         davinci_cfg_reg(DM355_VIN_CAM_WEN);
 869         davinci_cfg_reg(DM355_VIN_CAM_VD);
 870         davinci_cfg_reg(DM355_VIN_CAM_HD);
 871         davinci_cfg_reg(DM355_VIN_YIN_EN);
 872         davinci_cfg_reg(DM355_VIN_CINL_EN);
 873         davinci_cfg_reg(DM355_VIN_CINH_EN);
 874         platform_device_register(&vpfe_capture_dev);
 875
 876         return 0;
 877 }
 878 postcore_initcall(dm355_init_devices);