arch/arm/mach-davinci/devices-da8xx.c

   1 /*
   2  * DA8XX/OMAP L1XX platform device data
   3  *
   4  * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
   5  * Derived from code that was:
   6  *      Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13 #include <linux/init.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/serial_8250.h>
  17
  18 #include <mach/cputype.h>
  19 #include <mach/common.h>
  20 #include <mach/time.h>
  21 #include <mach/da8xx.h>
  22 #include <mach/cpuidle.h>
  23
  24 #include "clock.h"
  25
  26 #define DA8XX_TPCC_BASE                 0x01c00000
  27 #define DA850_TPCC1_BASE                0x01e30000
  28 #define DA8XX_TPTC0_BASE                0x01c08000
  29 #define DA8XX_TPTC1_BASE                0x01c08400
  30 #define DA850_TPTC2_BASE                0x01e38000
  31 #define DA8XX_WDOG_BASE                 0x01c21000 /* DA8XX_TIMER64P1_BASE */
  32 #define DA8XX_I2C0_BASE                 0x01c22000
  33 #define DA8XX_RTC_BASE                  0x01C23000
  34 #define DA8XX_EMAC_CPPI_PORT_BASE       0x01e20000
  35 #define DA8XX_EMAC_CPGMACSS_BASE        0x01e22000
  36 #define DA8XX_EMAC_CPGMAC_BASE          0x01e23000
  37 #define DA8XX_EMAC_MDIO_BASE            0x01e24000
  38 #define DA8XX_GPIO_BASE                 0x01e26000
  39 #define DA8XX_I2C1_BASE                 0x01e28000
  40
  41 #define DA8XX_EMAC_CTRL_REG_OFFSET      0x3000
  42 #define DA8XX_EMAC_MOD_REG_OFFSET       0x2000
  43 #define DA8XX_EMAC_RAM_OFFSET           0x0000
  44 #define DA8XX_MDIO_REG_OFFSET           0x4000
  45 #define DA8XX_EMAC_CTRL_RAM_SIZE        SZ_8K
  46
  47 void __iomem *da8xx_syscfg0_base;
  48 void __iomem *da8xx_syscfg1_base;
  49
  50 static struct plat_serial8250_port da8xx_serial_pdata[] = {
  51         {
  52                 .mapbase        = DA8XX_UART0_BASE,
  53                 .irq            = IRQ_DA8XX_UARTINT0,
  54                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
  55                                         UPF_IOREMAP,
  56                 .iotype         = UPIO_MEM,
  57                 .regshift       = 2,
  58         },
  59         {
  60                 .mapbase        = DA8XX_UART1_BASE,
  61                 .irq            = IRQ_DA8XX_UARTINT1,
  62                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
  63                                         UPF_IOREMAP,
  64                 .iotype         = UPIO_MEM,
  65                 .regshift       = 2,
  66         },
  67         {
  68                 .mapbase        = DA8XX_UART2_BASE,
  69                 .irq            = IRQ_DA8XX_UARTINT2,
  70                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
  71                                         UPF_IOREMAP,
  72                 .iotype         = UPIO_MEM,
  73                 .regshift       = 2,
  74         },
  75         {
  76                 .flags  = 0,
  77         },
  78 };
  79
  80 struct platform_device da8xx_serial_device = {
  81         .name   = "serial8250",
  82         .id     = PLAT8250_DEV_PLATFORM,
  83         .dev    = {
  84                 .platform_data  = da8xx_serial_pdata,
  85         },
  86 };
  87
  88 static const s8 da8xx_queue_tc_mapping[][2] = {
  89         /* {event queue no, TC no} */
  90         {0, 0},
  91         {1, 1},
  92         {-1, -1}
  93 };
  94
  95 static const s8 da8xx_queue_priority_mapping[][2] = {
  96         /* {event queue no, Priority} */
  97         {0, 3},
  98         {1, 7},
  99         {-1, -1}
 100 };
 101
 102 static const s8 da850_queue_tc_mapping[][2] = {
 103         /* {event queue no, TC no} */
 104         {0, 0},
 105         {-1, -1}
 106 };
 107
 108 static const s8 da850_queue_priority_mapping[][2] = {
 109         /* {event queue no, Priority} */
 110         {0, 3},
 111         {-1, -1}
 112 };
 113
 114 static struct edma_soc_info da830_edma_cc0_info = {
 115         .n_channel              = 32,
 116         .n_region               = 4,
 117         .n_slot                 = 128,
 118         .n_tc                   = 2,
 119         .n_cc                   = 1,
 120         .queue_tc_mapping       = da8xx_queue_tc_mapping,
 121         .queue_priority_mapping = da8xx_queue_priority_mapping,
 122 };
 123
 124 static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = {
 125         &da830_edma_cc0_info,
 126 };
 127
 128 static struct edma_soc_info da850_edma_cc_info[] = {
 129         {
 130                 .n_channel              = 32,
 131                 .n_region               = 4,
 132                 .n_slot                 = 128,
 133                 .n_tc                   = 2,
 134                 .n_cc                   = 1,
 135                 .queue_tc_mapping       = da8xx_queue_tc_mapping,
 136                 .queue_priority_mapping = da8xx_queue_priority_mapping,
 137         },
 138         {
 139                 .n_channel              = 32,
 140                 .n_region               = 4,
 141                 .n_slot                 = 128,
 142                 .n_tc                   = 1,
 143                 .n_cc                   = 1,
 144                 .queue_tc_mapping       = da850_queue_tc_mapping,
 145                 .queue_priority_mapping = da850_queue_priority_mapping,
 146         },
 147 };
 148
 149 static struct edma_soc_info *da850_edma_info[EDMA_MAX_CC] = {
 150         &da850_edma_cc_info[0],
 151         &da850_edma_cc_info[1],
 152 };
 153
 154 static struct resource da830_edma_resources[] = {
 155         {
 156                 .name   = "edma_cc0",
 157                 .start  = DA8XX_TPCC_BASE,
 158                 .end    = DA8XX_TPCC_BASE + SZ_32K - 1,
 159                 .flags  = IORESOURCE_MEM,
 160         },
 161         {
 162                 .name   = "edma_tc0",
 163                 .start  = DA8XX_TPTC0_BASE,
 164                 .end    = DA8XX_TPTC0_BASE + SZ_1K - 1,
 165                 .flags  = IORESOURCE_MEM,
 166         },
 167         {
 168                 .name   = "edma_tc1",
 169                 .start  = DA8XX_TPTC1_BASE,
 170                 .end    = DA8XX_TPTC1_BASE + SZ_1K - 1,
 171                 .flags  = IORESOURCE_MEM,
 172         },
 173         {
 174                 .name   = "edma0",
 175                 .start  = IRQ_DA8XX_CCINT0,
 176                 .flags  = IORESOURCE_IRQ,
 177         },
 178         {
 179                 .name   = "edma0_err",
 180                 .start  = IRQ_DA8XX_CCERRINT,
 181                 .flags  = IORESOURCE_IRQ,
 182         },
 183 };
 184
 185 static struct resource da850_edma_resources[] = {
 186         {
 187                 .name   = "edma_cc0",
 188                 .start  = DA8XX_TPCC_BASE,
 189                 .end    = DA8XX_TPCC_BASE + SZ_32K - 1,
 190                 .flags  = IORESOURCE_MEM,
 191         },
 192         {
 193                 .name   = "edma_tc0",
 194                 .start  = DA8XX_TPTC0_BASE,
 195                 .end    = DA8XX_TPTC0_BASE + SZ_1K - 1,
 196                 .flags  = IORESOURCE_MEM,
 197         },
 198         {
 199                 .name   = "edma_tc1",
 200                 .start  = DA8XX_TPTC1_BASE,
 201                 .end    = DA8XX_TPTC1_BASE + SZ_1K - 1,
 202                 .flags  = IORESOURCE_MEM,
 203         },
 204         {
 205                 .name   = "edma_cc1",
 206                 .start  = DA850_TPCC1_BASE,
 207                 .end    = DA850_TPCC1_BASE + SZ_32K - 1,
 208                 .flags  = IORESOURCE_MEM,
 209         },
 210         {
 211                 .name   = "edma_tc2",
 212                 .start  = DA850_TPTC2_BASE,
 213                 .end    = DA850_TPTC2_BASE + SZ_1K - 1,
 214                 .flags  = IORESOURCE_MEM,
 215         },
 216         {
 217                 .name   = "edma0",
 218                 .start  = IRQ_DA8XX_CCINT0,
 219                 .flags  = IORESOURCE_IRQ,
 220         },
 221         {
 222                 .name   = "edma0_err",
 223                 .start  = IRQ_DA8XX_CCERRINT,
 224                 .flags  = IORESOURCE_IRQ,
 225         },
 226         {
 227                 .name   = "edma1",
 228                 .start  = IRQ_DA850_CCINT1,
 229                 .flags  = IORESOURCE_IRQ,
 230         },
 231         {
 232                 .name   = "edma1_err",
 233                 .start  = IRQ_DA850_CCERRINT1,
 234                 .flags  = IORESOURCE_IRQ,
 235         },
 236 };
 237
 238 static struct platform_device da830_edma_device = {
 239         .name           = "edma",
 240         .id             = -1,
 241         .dev = {
 242                 .platform_data = da830_edma_info,
 243         },
 244         .num_resources  = ARRAY_SIZE(da830_edma_resources),
 245         .resource       = da830_edma_resources,
 246 };
 247
 248 static struct platform_device da850_edma_device = {
 249         .name           = "edma",
 250         .id             = -1,
 251         .dev = {
 252                 .platform_data = da850_edma_info,
 253         },
 254         .num_resources  = ARRAY_SIZE(da850_edma_resources),
 255         .resource       = da850_edma_resources,
 256 };
 257
 258 int __init da830_register_edma(struct edma_rsv_info *rsv)
 259 {
 260         da830_edma_cc0_info.rsv = rsv;
 261
 262         return platform_device_register(&da830_edma_device);
 263 }
 264
 265 int __init da850_register_edma(struct edma_rsv_info *rsv[2])
 266 {
 267         if (rsv) {
 268                 da850_edma_cc_info[0].rsv = rsv[0];
 269                 da850_edma_cc_info[1].rsv = rsv[1];
 270         }
 271
 272         return platform_device_register(&da850_edma_device);
 273 }
 274
 275 static struct resource da8xx_i2c_resources0[] = {
 276         {
 277                 .start  = DA8XX_I2C0_BASE,
 278                 .end    = DA8XX_I2C0_BASE + SZ_4K - 1,
 279                 .flags  = IORESOURCE_MEM,
 280         },
 281         {
 282                 .start  = IRQ_DA8XX_I2CINT0,
 283                 .end    = IRQ_DA8XX_I2CINT0,
 284                 .flags  = IORESOURCE_IRQ,
 285         },
 286 };
 287
 288 static struct platform_device da8xx_i2c_device0 = {
 289         .name           = "i2c_davinci",
 290         .id             = 1,
 291         .num_resources  = ARRAY_SIZE(da8xx_i2c_resources0),
 292         .resource       = da8xx_i2c_resources0,
 293 };
 294
 295 static struct resource da8xx_i2c_resources1[] = {
 296         {
 297                 .start  = DA8XX_I2C1_BASE,
 298                 .end    = DA8XX_I2C1_BASE + SZ_4K - 1,
 299                 .flags  = IORESOURCE_MEM,
 300         },
 301         {
 302                 .start  = IRQ_DA8XX_I2CINT1,
 303                 .end    = IRQ_DA8XX_I2CINT1,
 304                 .flags  = IORESOURCE_IRQ,
 305         },
 306 };
 307
 308 static struct platform_device da8xx_i2c_device1 = {
 309         .name           = "i2c_davinci",
 310         .id             = 2,
 311         .num_resources  = ARRAY_SIZE(da8xx_i2c_resources1),
 312         .resource       = da8xx_i2c_resources1,
 313 };
 314
 315 int __init da8xx_register_i2c(int instance,
 316                 struct davinci_i2c_platform_data *pdata)
 317 {
 318         struct platform_device *pdev;
 319
 320         if (instance == 0)
 321                 pdev = &da8xx_i2c_device0;
 322         else if (instance == 1)
 323                 pdev = &da8xx_i2c_device1;
 324         else
 325                 return -EINVAL;
 326
 327         pdev->dev.platform_data = pdata;
 328         return platform_device_register(pdev);
 329 }
 330
 331 static struct resource da8xx_watchdog_resources[] = {
 332         {
 333                 .start  = DA8XX_WDOG_BASE,
 334                 .end    = DA8XX_WDOG_BASE + SZ_4K - 1,
 335                 .flags  = IORESOURCE_MEM,
 336         },
 337 };
 338
 339 struct platform_device da8xx_wdt_device = {
 340         .name           = "watchdog",
 341         .id             = -1,
 342         .num_resources  = ARRAY_SIZE(da8xx_watchdog_resources),
 343         .resource       = da8xx_watchdog_resources,
 344 };
 345
 346 int __init da8xx_register_watchdog(void)
 347 {
 348         return platform_device_register(&da8xx_wdt_device);
 349 }
 350
 351 static struct resource da8xx_emac_resources[] = {
 352         {
 353                 .start  = DA8XX_EMAC_CPPI_PORT_BASE,
 354                 .end    = DA8XX_EMAC_CPPI_PORT_BASE + 0x5000 - 1,
 355                 .flags  = IORESOURCE_MEM,
 356         },
 357         {
 358                 .start  = IRQ_DA8XX_C0_RX_THRESH_PULSE,
 359                 .end    = IRQ_DA8XX_C0_RX_THRESH_PULSE,
 360                 .flags  = IORESOURCE_IRQ,
 361         },
 362         {
 363                 .start  = IRQ_DA8XX_C0_RX_PULSE,
 364                 .end    = IRQ_DA8XX_C0_RX_PULSE,
 365                 .flags  = IORESOURCE_IRQ,
 366         },
 367         {
 368                 .start  = IRQ_DA8XX_C0_TX_PULSE,
 369                 .end    = IRQ_DA8XX_C0_TX_PULSE,
 370                 .flags  = IORESOURCE_IRQ,
 371         },
 372         {
 373                 .start  = IRQ_DA8XX_C0_MISC_PULSE,
 374                 .end    = IRQ_DA8XX_C0_MISC_PULSE,
 375                 .flags  = IORESOURCE_IRQ,
 376         },
 377 };
 378
 379 struct emac_platform_data da8xx_emac_pdata = {
 380         .ctrl_reg_offset        = DA8XX_EMAC_CTRL_REG_OFFSET,
 381         .ctrl_mod_reg_offset    = DA8XX_EMAC_MOD_REG_OFFSET,
 382         .ctrl_ram_offset        = DA8XX_EMAC_RAM_OFFSET,
 383         .mdio_reg_offset        = DA8XX_MDIO_REG_OFFSET,
 384         .ctrl_ram_size          = DA8XX_EMAC_CTRL_RAM_SIZE,
 385         .version                = EMAC_VERSION_2,
 386 };
 387
 388 static struct platform_device da8xx_emac_device = {
 389         .name           = "davinci_emac",
 390         .id             = 1,
 391         .dev = {
 392                 .platform_data  = &da8xx_emac_pdata,
 393         },
 394         .num_resources  = ARRAY_SIZE(da8xx_emac_resources),
 395         .resource       = da8xx_emac_resources,
 396 };
 397
 398 int __init da8xx_register_emac(void)
 399 {
 400         return platform_device_register(&da8xx_emac_device);
 401 }
 402
 403 static struct resource da830_mcasp1_resources[] = {
 404         {
 405                 .name   = "mcasp1",
 406                 .start  = DAVINCI_DA830_MCASP1_REG_BASE,
 407                 .end    = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
 408                 .flags  = IORESOURCE_MEM,
 409         },
 410         /* TX event */
 411         {
 412                 .start  = DAVINCI_DA830_DMA_MCASP1_AXEVT,
 413                 .end    = DAVINCI_DA830_DMA_MCASP1_AXEVT,
 414                 .flags  = IORESOURCE_DMA,
 415         },
 416         /* RX event */
 417         {
 418                 .start  = DAVINCI_DA830_DMA_MCASP1_AREVT,
 419                 .end    = DAVINCI_DA830_DMA_MCASP1_AREVT,
 420                 .flags  = IORESOURCE_DMA,
 421         },
 422 };
 423
 424 static struct platform_device da830_mcasp1_device = {
 425         .name           = "davinci-mcasp",
 426         .id             = 1,
 427         .num_resources  = ARRAY_SIZE(da830_mcasp1_resources),
 428         .resource       = da830_mcasp1_resources,
 429 };
 430
 431 static struct resource da850_mcasp_resources[] = {
 432         {
 433                 .name   = "mcasp",
 434                 .start  = DAVINCI_DA8XX_MCASP0_REG_BASE,
 435                 .end    = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
 436                 .flags  = IORESOURCE_MEM,
 437         },
 438         /* TX event */
 439         {
 440                 .start  = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
 441                 .end    = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
 442                 .flags  = IORESOURCE_DMA,
 443         },
 444         /* RX event */
 445         {
 446                 .start  = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
 447                 .end    = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
 448                 .flags  = IORESOURCE_DMA,
 449         },
 450 };
 451
 452 static struct platform_device da850_mcasp_device = {
 453         .name           = "davinci-mcasp",
 454         .id             = 0,
 455         .num_resources  = ARRAY_SIZE(da850_mcasp_resources),
 456         .resource       = da850_mcasp_resources,
 457 };
 458
 459 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
 460 {
 461         /* DA830/OMAP-L137 has 3 instances of McASP */
 462         if (cpu_is_davinci_da830() && id == 1) {
 463                 da830_mcasp1_device.dev.platform_data = pdata;
 464                 platform_device_register(&da830_mcasp1_device);
 465         } else if (cpu_is_davinci_da850()) {
 466                 da850_mcasp_device.dev.platform_data = pdata;
 467                 platform_device_register(&da850_mcasp_device);
 468         }
 469 }
 470
 471 static const struct display_panel disp_panel = {
 472         QVGA,
 473         16,
 474         16,
 475         COLOR_ACTIVE,
 476 };
 477
 478 static struct lcd_ctrl_config lcd_cfg = {
 479         &disp_panel,
 480         .ac_bias                = 255,
 481         .ac_bias_intrpt         = 0,
 482         .dma_burst_sz           = 16,
 483         .bpp                    = 16,
 484         .fdd                    = 255,
 485         .tft_alt_mode           = 0,
 486         .stn_565_mode           = 0,
 487         .mono_8bit_mode         = 0,
 488         .invert_line_clock      = 1,
 489         .invert_frm_clock       = 1,
 490         .sync_edge              = 0,
 491         .sync_ctrl              = 1,
 492         .raster_order           = 0,
 493 };
 494
 495 struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
 496         .manu_name              = "sharp",
 497         .controller_data        = &lcd_cfg,
 498         .type                   = "Sharp_LCD035Q3DG01",
 499 };
 500
 501 struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
 502         .manu_name              = "sharp",
 503         .controller_data        = &lcd_cfg,
 504         .type                   = "Sharp_LK043T1DG01",
 505 };
 506
 507 static struct resource da8xx_lcdc_resources[] = {
 508         [0] = { /* registers */
 509                 .start  = DA8XX_LCD_CNTRL_BASE,
 510                 .end    = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
 511                 .flags  = IORESOURCE_MEM,
 512         },
 513         [1] = { /* interrupt */
 514                 .start  = IRQ_DA8XX_LCDINT,
 515                 .end    = IRQ_DA8XX_LCDINT,
 516                 .flags  = IORESOURCE_IRQ,
 517         },
 518 };
 519
 520 static struct platform_device da8xx_lcdc_device = {
 521         .name           = "da8xx_lcdc",
 522         .id             = 0,
 523         .num_resources  = ARRAY_SIZE(da8xx_lcdc_resources),
 524         .resource       = da8xx_lcdc_resources,
 525 };
 526
 527 int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
 528 {
 529         da8xx_lcdc_device.dev.platform_data = pdata;
 530         return platform_device_register(&da8xx_lcdc_device);
 531 }
 532
 533 static struct resource da8xx_mmcsd0_resources[] = {
 534         {               /* registers */
 535                 .start  = DA8XX_MMCSD0_BASE,
 536                 .end    = DA8XX_MMCSD0_BASE + SZ_4K - 1,
 537                 .flags  = IORESOURCE_MEM,
 538         },
 539         {               /* interrupt */
 540                 .start  = IRQ_DA8XX_MMCSDINT0,
 541                 .end    = IRQ_DA8XX_MMCSDINT0,
 542                 .flags  = IORESOURCE_IRQ,
 543         },
 544         {               /* DMA RX */
 545                 .start  = EDMA_CTLR_CHAN(0, 16),
 546                 .end    = EDMA_CTLR_CHAN(0, 16),
 547                 .flags  = IORESOURCE_DMA,
 548         },
 549         {               /* DMA TX */
 550                 .start  = EDMA_CTLR_CHAN(0, 17),
 551                 .end    = EDMA_CTLR_CHAN(0, 17),
 552                 .flags  = IORESOURCE_DMA,
 553         },
 554 };
 555
 556 static struct platform_device da8xx_mmcsd0_device = {
 557         .name           = "davinci_mmc",
 558         .id             = 0,
 559         .num_resources  = ARRAY_SIZE(da8xx_mmcsd0_resources),
 560         .resource       = da8xx_mmcsd0_resources,
 561 };
 562
 563 int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
 564 {
 565         da8xx_mmcsd0_device.dev.platform_data = config;
 566         return platform_device_register(&da8xx_mmcsd0_device);
 567 }
 568
 569 static struct resource da8xx_rtc_resources[] = {
 570         {
 571                 .start          = DA8XX_RTC_BASE,
 572                 .end            = DA8XX_RTC_BASE + SZ_4K - 1,
 573                 .flags          = IORESOURCE_MEM,
 574         },
 575         { /* timer irq */
 576                 .start          = IRQ_DA8XX_RTC,
 577                 .end            = IRQ_DA8XX_RTC,
 578                 .flags          = IORESOURCE_IRQ,
 579         },
 580         { /* alarm irq */
 581                 .start          = IRQ_DA8XX_RTC,
 582                 .end            = IRQ_DA8XX_RTC,
 583                 .flags          = IORESOURCE_IRQ,
 584         },
 585 };
 586
 587 static struct platform_device da8xx_rtc_device = {
 588         .name           = "omap_rtc",
 589         .id             = -1,
 590         .num_resources  = ARRAY_SIZE(da8xx_rtc_resources),
 591         .resource       = da8xx_rtc_resources,
 592 };
 593
 594 int da8xx_register_rtc(void)
 595 {
 596         int ret;
 597         void __iomem *base;
 598
 599         base = ioremap(DA8XX_RTC_BASE, SZ_4K);
 600         if (WARN_ON(!base))
 601                 return -ENOMEM;
 602
 603         /* Unlock the rtc's registers */
 604         __raw_writel(0x83e70b13, base + 0x6c);
 605         __raw_writel(0x95a4f1e0, base + 0x70);
 606
 607         iounmap(base);
 608
 609         ret = platform_device_register(&da8xx_rtc_device);
 610         if (!ret)
 611                 /* Atleast on DA850, RTC is a wakeup source */
 612                 device_init_wakeup(&da8xx_rtc_device.dev, true);
 613
 614         return ret;
 615 }
 616
 617 static void __iomem *da8xx_ddr2_ctlr_base;
 618 void __iomem * __init da8xx_get_mem_ctlr(void)
 619 {
 620         if (da8xx_ddr2_ctlr_base)
 621                 return da8xx_ddr2_ctlr_base;
 622
 623         da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
 624         if (!da8xx_ddr2_ctlr_base)
 625                 pr_warning("%s: Unable to map DDR2 controller", __func__);
 626
 627         return da8xx_ddr2_ctlr_base;
 628 }
 629
 630 static struct resource da8xx_cpuidle_resources[] = {
 631         {
 632                 .start          = DA8XX_DDR2_CTL_BASE,
 633                 .end            = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
 634                 .flags          = IORESOURCE_MEM,
 635         },
 636 };
 637
 638 /* DA8XX devices support DDR2 power down */
 639 static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
 640         .ddr2_pdown     = 1,
 641 };
 642
 643
 644 static struct platform_device da8xx_cpuidle_device = {
 645         .name                   = "cpuidle-davinci",
 646         .num_resources          = ARRAY_SIZE(da8xx_cpuidle_resources),
 647         .resource               = da8xx_cpuidle_resources,
 648         .dev = {
 649                 .platform_data  = &da8xx_cpuidle_pdata,
 650         },
 651 };
 652
 653 int __init da8xx_register_cpuidle(void)
 654 {
 655         da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
 656
 657         return platform_device_register(&da8xx_cpuidle_device);
 658 }