arch/arm/mach-davinci/board-mityomapl138.c

   1 /*
   2  * Critical Link MityOMAP-L138 SoM
   3  *
   4  * Copyright (C) 2010 Critical Link LLC - http://www.criticallink.com
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2. This program is licensed "as is" without any warranty of
   8  * any kind, whether express or implied.
   9  */
  10
  11 #define pr_fmt(fmt) "MityOMAPL138: " fmt
  12
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/console.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/mtd/partitions.h>
  18 #include <linux/regulator/machine.h>
  19 #include <linux/i2c.h>
  20 #include <linux/platform_data/at24.h>
  21 #include <linux/etherdevice.h>
  22 #include <linux/spi/spi.h>
  23 #include <linux/spi/flash.h>
  24
  25 #include <asm/io.h>
  26 #include <asm/mach-types.h>
  27 #include <asm/mach/arch.h>
  28 #include <mach/common.h>
  29 #include "cp_intc.h"
  30 #include <mach/da8xx.h>
  31 #include <linux/platform_data/mtd-davinci.h>
  32 #include <linux/platform_data/mtd-davinci-aemif.h>
  33 #include <linux/platform_data/ti-aemif.h>
  34 #include <mach/mux.h>
  35 #include <linux/platform_data/spi-davinci.h>
  36
  37 #define MITYOMAPL138_PHY_ID             ""
  38
  39 #define FACTORY_CONFIG_MAGIC    0x012C0138
  40 #define FACTORY_CONFIG_VERSION  0x00010001
  41
  42 /* Data Held in On-Board I2C device */
  43 struct factory_config {
  44         u32     magic;
  45         u32     version;
  46         u8      mac[6];
  47         u32     fpga_type;
  48         u32     spare;
  49         u32     serialnumber;
  50         char    partnum[32];
  51 };
  52
  53 static struct factory_config factory_config;
  54
  55 #ifdef CONFIG_CPU_FREQ
  56 struct part_no_info {
  57         const char      *part_no;       /* part number string of interest */
  58         int             max_freq;       /* khz */
  59 };
  60
  61 static struct part_no_info mityomapl138_pn_info[] = {
  62         {
  63                 .part_no        = "L138-C",
  64                 .max_freq       = 300000,
  65         },
  66         {
  67                 .part_no        = "L138-D",
  68                 .max_freq       = 375000,
  69         },
  70         {
  71                 .part_no        = "L138-F",
  72                 .max_freq       = 456000,
  73         },
  74         {
  75                 .part_no        = "1808-C",
  76                 .max_freq       = 300000,
  77         },
  78         {
  79                 .part_no        = "1808-D",
  80                 .max_freq       = 375000,
  81         },
  82         {
  83                 .part_no        = "1808-F",
  84                 .max_freq       = 456000,
  85         },
  86         {
  87                 .part_no        = "1810-D",
  88                 .max_freq       = 375000,
  89         },
  90 };
  91
  92 static void mityomapl138_cpufreq_init(const char *partnum)
  93 {
  94         int i, ret;
  95
  96         for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
  97                 /*
  98                  * the part number has additional characters beyond what is
  99                  * stored in the table.  This information is not needed for
 100                  * determining the speed grade, and would require several
 101                  * more table entries.  Only check the first N characters
 102                  * for a match.
 103                  */
 104                 if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
 105                              strlen(mityomapl138_pn_info[i].part_no))) {
 106                         da850_max_speed = mityomapl138_pn_info[i].max_freq;
 107                         break;
 108                 }
 109         }
 110
 111         ret = da850_register_cpufreq("pll0_sysclk3");
 112         if (ret)
 113                 pr_warn("cpufreq registration failed: %d\n", ret);
 114 }
 115 #else
 116 static void mityomapl138_cpufreq_init(const char *partnum) { }
 117 #endif
 118
 119 static void read_factory_config(struct nvmem_device *nvmem, void *context)
 120 {
 121         int ret;
 122         const char *partnum = NULL;
 123         struct davinci_soc_info *soc_info = &davinci_soc_info;
 124
 125         if (!IS_BUILTIN(CONFIG_NVMEM)) {
 126                 pr_warn("Factory Config not available without CONFIG_NVMEM\n");
 127                 goto bad_config;
 128         }
 129
 130         ret = nvmem_device_read(nvmem, 0, sizeof(factory_config),
 131                                 &factory_config);
 132         if (ret != sizeof(struct factory_config)) {
 133                 pr_warn("Read Factory Config Failed: %d\n", ret);
 134                 goto bad_config;
 135         }
 136
 137         if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
 138                 pr_warn("Factory Config Magic Wrong (%X)\n",
 139                         factory_config.magic);
 140                 goto bad_config;
 141         }
 142
 143         if (factory_config.version != FACTORY_CONFIG_VERSION) {
 144                 pr_warn("Factory Config Version Wrong (%X)\n",
 145                         factory_config.version);
 146                 goto bad_config;
 147         }
 148
 149         pr_info("Found MAC = %pM\n", factory_config.mac);
 150         if (is_valid_ether_addr(factory_config.mac))
 151                 memcpy(soc_info->emac_pdata->mac_addr,
 152                         factory_config.mac, ETH_ALEN);
 153         else
 154                 pr_warn("Invalid MAC found in factory config block\n");
 155
 156         partnum = factory_config.partnum;
 157         pr_info("Part Number = %s\n", partnum);
 158
 159 bad_config:
 160         /* default maximum speed is valid for all platforms */
 161         mityomapl138_cpufreq_init(partnum);
 162 }
 163
 164 static struct at24_platform_data mityomapl138_fd_chip = {
 165         .byte_len       = 256,
 166         .page_size      = 8,
 167         .flags          = AT24_FLAG_READONLY | AT24_FLAG_IRUGO,
 168         .setup          = read_factory_config,
 169         .context        = NULL,
 170 };
 171
 172 static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
 173         .bus_freq       = 100,  /* kHz */
 174         .bus_delay      = 0,    /* usec */
 175 };
 176
 177 /* TPS65023 voltage regulator support */
 178 /* 1.2V Core */
 179 static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = {
 180         {
 181                 .supply = "cvdd",
 182         },
 183 };
 184
 185 /* 1.8V */
 186 static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = {
 187         {
 188                 .supply = "usb0_vdda18",
 189         },
 190         {
 191                 .supply = "usb1_vdda18",
 192         },
 193         {
 194                 .supply = "ddr_dvdd18",
 195         },
 196         {
 197                 .supply = "sata_vddr",
 198         },
 199 };
 200
 201 /* 1.2V */
 202 static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = {
 203         {
 204                 .supply = "sata_vdd",
 205         },
 206         {
 207                 .supply = "usb_cvdd",
 208         },
 209         {
 210                 .supply = "pll0_vdda",
 211         },
 212         {
 213                 .supply = "pll1_vdda",
 214         },
 215 };
 216
 217 /* 1.8V Aux LDO, not used */
 218 static struct regulator_consumer_supply tps65023_ldo1_consumers[] = {
 219         {
 220                 .supply = "1.8v_aux",
 221         },
 222 };
 223
 224 /* FPGA VCC Aux (2.5 or 3.3) LDO */
 225 static struct regulator_consumer_supply tps65023_ldo2_consumers[] = {
 226         {
 227                 .supply = "vccaux",
 228         },
 229 };
 230
 231 static struct regulator_init_data tps65023_regulator_data[] = {
 232         /* dcdc1 */
 233         {
 234                 .constraints = {
 235                         .min_uV = 1150000,
 236                         .max_uV = 1350000,
 237                         .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
 238                                           REGULATOR_CHANGE_STATUS,
 239                         .boot_on = 1,
 240                 },
 241                 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers),
 242                 .consumer_supplies = tps65023_dcdc1_consumers,
 243         },
 244         /* dcdc2 */
 245         {
 246                 .constraints = {
 247                         .min_uV = 1800000,
 248                         .max_uV = 1800000,
 249                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
 250                         .boot_on = 1,
 251                 },
 252                 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers),
 253                 .consumer_supplies = tps65023_dcdc2_consumers,
 254         },
 255         /* dcdc3 */
 256         {
 257                 .constraints = {
 258                         .min_uV = 1200000,
 259                         .max_uV = 1200000,
 260                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
 261                         .boot_on = 1,
 262                 },
 263                 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers),
 264                 .consumer_supplies = tps65023_dcdc3_consumers,
 265         },
 266         /* ldo1 */
 267         {
 268                 .constraints = {
 269                         .min_uV = 1800000,
 270                         .max_uV = 1800000,
 271                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
 272                         .boot_on = 1,
 273                 },
 274                 .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers),
 275                 .consumer_supplies = tps65023_ldo1_consumers,
 276         },
 277         /* ldo2 */
 278         {
 279                 .constraints = {
 280                         .min_uV = 2500000,
 281                         .max_uV = 3300000,
 282                         .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
 283                                           REGULATOR_CHANGE_STATUS,
 284                         .boot_on = 1,
 285                 },
 286                 .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers),
 287                 .consumer_supplies = tps65023_ldo2_consumers,
 288         },
 289 };
 290
 291 static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
 292         {
 293                 I2C_BOARD_INFO("tps65023", 0x48),
 294                 .platform_data = &tps65023_regulator_data[0],
 295         },
 296         {
 297                 I2C_BOARD_INFO("24c02", 0x50),
 298                 .platform_data = &mityomapl138_fd_chip,
 299         },
 300 };
 301
 302 static int __init pmic_tps65023_init(void)
 303 {
 304         return i2c_register_board_info(1, mityomap_tps65023_info,
 305                                         ARRAY_SIZE(mityomap_tps65023_info));
 306 }
 307
 308 /*
 309  * SPI Devices:
 310  *      SPI1_CS0: 8M Flash ST-M25P64-VME6G
 311  */
 312 static struct mtd_partition spi_flash_partitions[] = {
 313         [0] = {
 314                 .name           = "ubl",
 315                 .offset         = 0,
 316                 .size           = SZ_64K,
 317                 .mask_flags     = MTD_WRITEABLE,
 318         },
 319         [1] = {
 320                 .name           = "u-boot",
 321                 .offset         = MTDPART_OFS_APPEND,
 322                 .size           = SZ_512K,
 323                 .mask_flags     = MTD_WRITEABLE,
 324         },
 325         [2] = {
 326                 .name           = "u-boot-env",
 327                 .offset         = MTDPART_OFS_APPEND,
 328                 .size           = SZ_64K,
 329                 .mask_flags     = MTD_WRITEABLE,
 330         },
 331         [3] = {
 332                 .name           = "periph-config",
 333                 .offset         = MTDPART_OFS_APPEND,
 334                 .size           = SZ_64K,
 335                 .mask_flags     = MTD_WRITEABLE,
 336         },
 337         [4] = {
 338                 .name           = "reserved",
 339                 .offset         = MTDPART_OFS_APPEND,
 340                 .size           = SZ_256K + SZ_64K,
 341         },
 342         [5] = {
 343                 .name           = "kernel",
 344                 .offset         = MTDPART_OFS_APPEND,
 345                 .size           = SZ_2M + SZ_1M,
 346         },
 347         [6] = {
 348                 .name           = "fpga",
 349                 .offset         = MTDPART_OFS_APPEND,
 350                 .size           = SZ_2M,
 351         },
 352         [7] = {
 353                 .name           = "spare",
 354                 .offset         = MTDPART_OFS_APPEND,
 355                 .size           = MTDPART_SIZ_FULL,
 356         },
 357 };
 358
 359 static struct flash_platform_data mityomapl138_spi_flash_data = {
 360         .name           = "m25p80",
 361         .parts          = spi_flash_partitions,
 362         .nr_parts       = ARRAY_SIZE(spi_flash_partitions),
 363         .type           = "m24p64",
 364 };
 365
 366 static struct davinci_spi_config spi_eprom_config = {
 367         .io_type        = SPI_IO_TYPE_DMA,
 368         .c2tdelay       = 8,
 369         .t2cdelay       = 8,
 370 };
 371
 372 static struct spi_board_info mityomapl138_spi_flash_info[] = {
 373         {
 374                 .modalias               = "m25p80",
 375                 .platform_data          = &mityomapl138_spi_flash_data,
 376                 .controller_data        = &spi_eprom_config,
 377                 .mode                   = SPI_MODE_0,
 378                 .max_speed_hz           = 30000000,
 379                 .bus_num                = 1,
 380                 .chip_select            = 0,
 381         },
 382 };
 383
 384 /*
 385  * MityDSP-L138 includes a 256 MByte large-page NAND flash
 386  * (128K blocks).
 387  */
 388 static struct mtd_partition mityomapl138_nandflash_partition[] = {
 389         {
 390                 .name           = "rootfs",
 391                 .offset         = 0,
 392                 .size           = SZ_128M,
 393                 .mask_flags     = 0, /* MTD_WRITEABLE, */
 394         },
 395         {
 396                 .name           = "homefs",
 397                 .offset         = MTDPART_OFS_APPEND,
 398                 .size           = MTDPART_SIZ_FULL,
 399                 .mask_flags     = 0,
 400         },
 401 };
 402
 403 static struct davinci_nand_pdata mityomapl138_nandflash_data = {
 404         .core_chipsel   = 1,
 405         .parts          = mityomapl138_nandflash_partition,
 406         .nr_parts       = ARRAY_SIZE(mityomapl138_nandflash_partition),
 407         .ecc_mode       = NAND_ECC_HW,
 408         .bbt_options    = NAND_BBT_USE_FLASH,
 409         .options        = NAND_BUSWIDTH_16,
 410         .ecc_bits       = 1, /* 4 bit mode is not supported with 16 bit NAND */
 411 };
 412
 413 static struct resource mityomapl138_nandflash_resource[] = {
 414         {
 415                 .start  = DA8XX_AEMIF_CS3_BASE,
 416                 .end    = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
 417                 .flags  = IORESOURCE_MEM,
 418         },
 419         {
 420                 .start  = DA8XX_AEMIF_CTL_BASE,
 421                 .end    = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
 422                 .flags  = IORESOURCE_MEM,
 423         },
 424 };
 425
 426 static struct platform_device mityomapl138_aemif_devices[] = {
 427         {
 428                 .name           = "davinci_nand",
 429                 .id             = 1,
 430                 .dev            = {
 431                         .platform_data  = &mityomapl138_nandflash_data,
 432                 },
 433                 .num_resources  = ARRAY_SIZE(mityomapl138_nandflash_resource),
 434                 .resource       = mityomapl138_nandflash_resource,
 435         },
 436 };
 437
 438 static struct resource mityomapl138_aemif_resources[] = {
 439         {
 440                 .start  = DA8XX_AEMIF_CTL_BASE,
 441                 .end    = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
 442                 .flags  = IORESOURCE_MEM,
 443         },
 444 };
 445
 446 static struct aemif_abus_data mityomapl138_aemif_abus_data[] = {
 447         {
 448                 .cs     = 1,
 449         },
 450 };
 451
 452 static struct aemif_platform_data mityomapl138_aemif_pdata = {
 453         .abus_data              = mityomapl138_aemif_abus_data,
 454         .num_abus_data          = ARRAY_SIZE(mityomapl138_aemif_abus_data),
 455         .sub_devices            = mityomapl138_aemif_devices,
 456         .num_sub_devices        = ARRAY_SIZE(mityomapl138_aemif_devices),
 457 };
 458
 459 static struct platform_device mityomapl138_aemif_device = {
 460         .name           = "ti-aemif",
 461         .id             = -1,
 462         .dev = {
 463                 .platform_data  = &mityomapl138_aemif_pdata,
 464         },
 465         .resource       = mityomapl138_aemif_resources,
 466         .num_resources  = ARRAY_SIZE(mityomapl138_aemif_resources),
 467 };
 468
 469 static void __init mityomapl138_setup_nand(void)
 470 {
 471         if (platform_device_register(&mityomapl138_aemif_device))
 472                 pr_warn("%s: Cannot register AEMIF device\n", __func__);
 473 }
 474
 475 static const short mityomap_mii_pins[] = {
 476         DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
 477         DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
 478         DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
 479         DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
 480         DA850_MDIO_D,
 481         -1
 482 };
 483
 484 static const short mityomap_rmii_pins[] = {
 485         DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
 486         DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
 487         DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
 488         DA850_MDIO_D,
 489         -1
 490 };
 491
 492 static void __init mityomapl138_config_emac(void)
 493 {
 494         void __iomem *cfg_chip3_base;
 495         int ret;
 496         u32 val;
 497         struct davinci_soc_info *soc_info = &davinci_soc_info;
 498
 499         soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */
 500
 501         cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
 502         val = __raw_readl(cfg_chip3_base);
 503
 504         if (soc_info->emac_pdata->rmii_en) {
 505                 val |= BIT(8);
 506                 ret = davinci_cfg_reg_list(mityomap_rmii_pins);
 507                 pr_info("RMII PHY configured\n");
 508         } else {
 509                 val &= ~BIT(8);
 510                 ret = davinci_cfg_reg_list(mityomap_mii_pins);
 511                 pr_info("MII PHY configured\n");
 512         }
 513
 514         if (ret) {
 515                 pr_warn("mii/rmii mux setup failed: %d\n", ret);
 516                 return;
 517         }
 518
 519         /* configure the CFGCHIP3 register for RMII or MII */
 520         __raw_writel(val, cfg_chip3_base);
 521
 522         soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID;
 523
 524         ret = da8xx_register_emac();
 525         if (ret)
 526                 pr_warn("emac registration failed: %d\n", ret);
 527 }
 528
 529 static void __init mityomapl138_init(void)
 530 {
 531         int ret;
 532
 533         da850_register_clocks();
 534
 535         /* for now, no special EDMA channels are reserved */
 536         ret = da850_register_edma(NULL);
 537         if (ret)
 538                 pr_warn("edma registration failed: %d\n", ret);
 539
 540         ret = da8xx_register_watchdog();
 541         if (ret)
 542                 pr_warn("watchdog registration failed: %d\n", ret);
 543
 544         davinci_serial_init(da8xx_serial_device);
 545
 546         ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
 547         if (ret)
 548                 pr_warn("i2c0 registration failed: %d\n", ret);
 549
 550         ret = pmic_tps65023_init();
 551         if (ret)
 552                 pr_warn("TPS65023 PMIC init failed: %d\n", ret);
 553
 554         mityomapl138_setup_nand();
 555
 556         ret = spi_register_board_info(mityomapl138_spi_flash_info,
 557                                       ARRAY_SIZE(mityomapl138_spi_flash_info));
 558         if (ret)
 559                 pr_warn("spi info registration failed: %d\n", ret);
 560
 561         ret = da8xx_register_spi_bus(1,
 562                                      ARRAY_SIZE(mityomapl138_spi_flash_info));
 563         if (ret)
 564                 pr_warn("spi 1 registration failed: %d\n", ret);
 565
 566         mityomapl138_config_emac();
 567
 568         ret = da8xx_register_rtc();
 569         if (ret)
 570                 pr_warn("rtc setup failed: %d\n", ret);
 571
 572         ret = da8xx_register_cpuidle();
 573         if (ret)
 574                 pr_warn("cpuidle registration failed: %d\n", ret);
 575
 576         davinci_pm_init();
 577 }
 578
 579 #ifdef CONFIG_SERIAL_8250_CONSOLE
 580 static int __init mityomapl138_console_init(void)
 581 {
 582         if (!machine_is_mityomapl138())
 583                 return 0;
 584
 585         return add_preferred_console("ttyS", 1, "115200");
 586 }
 587 console_initcall(mityomapl138_console_init);
 588 #endif
 589
 590 static void __init mityomapl138_map_io(void)
 591 {
 592         da850_init();
 593 }
 594
 595 MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
 596         .atag_offset    = 0x100,
 597         .map_io         = mityomapl138_map_io,
 598         .init_irq       = cp_intc_init,
 599         .init_time      = da850_init_time,
 600         .init_machine   = mityomapl138_init,
 601         .init_late      = davinci_init_late,
 602         .dma_zone_size  = SZ_128M,
 603 MACHINE_END